1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 Broadcom 4 */ 5 6 /** 7 * DOC: VC4 plane module 8 * 9 * Each DRM plane is a layer of pixels being scanned out by the HVS. 10 * 11 * At atomic modeset check time, we compute the HVS display element 12 * state that would be necessary for displaying the plane (giving us a 13 * chance to figure out if a plane configuration is invalid), then at 14 * atomic flush time the CRTC will ask us to write our element state 15 * into the region of the HVS that it has allocated for us. 16 */ 17 18 #include <drm/drm_atomic.h> 19 #include <drm/drm_atomic_helper.h> 20 #include <drm/drm_atomic_uapi.h> 21 #include <drm/drm_blend.h> 22 #include <drm/drm_drv.h> 23 #include <drm/drm_fb_dma_helper.h> 24 #include <drm/drm_fourcc.h> 25 #include <drm/drm_framebuffer.h> 26 #include <drm/drm_gem_atomic_helper.h> 27 28 #include "uapi/drm/vc4_drm.h" 29 30 #include "vc4_drv.h" 31 #include "vc4_regs.h" 32 33 static const struct hvs_format { 34 u32 drm; /* DRM_FORMAT_* */ 35 u32 hvs; /* HVS_FORMAT_* */ 36 u32 pixel_order; 37 u32 pixel_order_hvs5; 38 bool hvs5_only; 39 } hvs_formats[] = { 40 { 41 .drm = DRM_FORMAT_XRGB8888, 42 .hvs = HVS_PIXEL_FORMAT_RGBA8888, 43 .pixel_order = HVS_PIXEL_ORDER_ABGR, 44 .pixel_order_hvs5 = HVS_PIXEL_ORDER_ARGB, 45 }, 46 { 47 .drm = DRM_FORMAT_ARGB8888, 48 .hvs = HVS_PIXEL_FORMAT_RGBA8888, 49 .pixel_order = HVS_PIXEL_ORDER_ABGR, 50 .pixel_order_hvs5 = HVS_PIXEL_ORDER_ARGB, 51 }, 52 { 53 .drm = DRM_FORMAT_ABGR8888, 54 .hvs = HVS_PIXEL_FORMAT_RGBA8888, 55 .pixel_order = HVS_PIXEL_ORDER_ARGB, 56 .pixel_order_hvs5 = HVS_PIXEL_ORDER_ABGR, 57 }, 58 { 59 .drm = DRM_FORMAT_XBGR8888, 60 .hvs = HVS_PIXEL_FORMAT_RGBA8888, 61 .pixel_order = HVS_PIXEL_ORDER_ARGB, 62 .pixel_order_hvs5 = HVS_PIXEL_ORDER_ABGR, 63 }, 64 { 65 .drm = DRM_FORMAT_RGB565, 66 .hvs = HVS_PIXEL_FORMAT_RGB565, 67 .pixel_order = HVS_PIXEL_ORDER_XRGB, 68 }, 69 { 70 .drm = DRM_FORMAT_BGR565, 71 .hvs = HVS_PIXEL_FORMAT_RGB565, 72 .pixel_order = HVS_PIXEL_ORDER_XBGR, 73 }, 74 { 75 .drm = DRM_FORMAT_ARGB1555, 76 .hvs = HVS_PIXEL_FORMAT_RGBA5551, 77 .pixel_order = HVS_PIXEL_ORDER_ABGR, 78 }, 79 { 80 .drm = DRM_FORMAT_XRGB1555, 81 .hvs = HVS_PIXEL_FORMAT_RGBA5551, 82 .pixel_order = HVS_PIXEL_ORDER_ABGR, 83 }, 84 { 85 .drm = DRM_FORMAT_RGB888, 86 .hvs = HVS_PIXEL_FORMAT_RGB888, 87 .pixel_order = HVS_PIXEL_ORDER_XRGB, 88 }, 89 { 90 .drm = DRM_FORMAT_BGR888, 91 .hvs = HVS_PIXEL_FORMAT_RGB888, 92 .pixel_order = HVS_PIXEL_ORDER_XBGR, 93 }, 94 { 95 .drm = DRM_FORMAT_YUV422, 96 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE, 97 .pixel_order = HVS_PIXEL_ORDER_XYCBCR, 98 }, 99 { 100 .drm = DRM_FORMAT_YVU422, 101 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE, 102 .pixel_order = HVS_PIXEL_ORDER_XYCRCB, 103 }, 104 { 105 .drm = DRM_FORMAT_YUV420, 106 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE, 107 .pixel_order = HVS_PIXEL_ORDER_XYCBCR, 108 }, 109 { 110 .drm = DRM_FORMAT_YVU420, 111 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE, 112 .pixel_order = HVS_PIXEL_ORDER_XYCRCB, 113 }, 114 { 115 .drm = DRM_FORMAT_NV12, 116 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE, 117 .pixel_order = HVS_PIXEL_ORDER_XYCBCR, 118 }, 119 { 120 .drm = DRM_FORMAT_NV21, 121 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE, 122 .pixel_order = HVS_PIXEL_ORDER_XYCRCB, 123 }, 124 { 125 .drm = DRM_FORMAT_NV16, 126 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_2PLANE, 127 .pixel_order = HVS_PIXEL_ORDER_XYCBCR, 128 }, 129 { 130 .drm = DRM_FORMAT_NV61, 131 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_2PLANE, 132 .pixel_order = HVS_PIXEL_ORDER_XYCRCB, 133 }, 134 { 135 .drm = DRM_FORMAT_P030, 136 .hvs = HVS_PIXEL_FORMAT_YCBCR_10BIT, 137 .pixel_order = HVS_PIXEL_ORDER_XYCBCR, 138 .hvs5_only = true, 139 }, 140 }; 141 142 static const struct hvs_format *vc4_get_hvs_format(u32 drm_format) 143 { 144 unsigned i; 145 146 for (i = 0; i < ARRAY_SIZE(hvs_formats); i++) { 147 if (hvs_formats[i].drm == drm_format) 148 return &hvs_formats[i]; 149 } 150 151 return NULL; 152 } 153 154 static enum vc4_scaling_mode vc4_get_scaling_mode(u32 src, u32 dst) 155 { 156 if (dst == src) 157 return VC4_SCALING_NONE; 158 if (3 * dst >= 2 * src) 159 return VC4_SCALING_PPF; 160 else 161 return VC4_SCALING_TPZ; 162 } 163 164 static bool plane_enabled(struct drm_plane_state *state) 165 { 166 return state->fb && !WARN_ON(!state->crtc); 167 } 168 169 static struct drm_plane_state *vc4_plane_duplicate_state(struct drm_plane *plane) 170 { 171 struct vc4_plane_state *vc4_state; 172 173 if (WARN_ON(!plane->state)) 174 return NULL; 175 176 vc4_state = kmemdup(plane->state, sizeof(*vc4_state), GFP_KERNEL); 177 if (!vc4_state) 178 return NULL; 179 180 memset(&vc4_state->lbm, 0, sizeof(vc4_state->lbm)); 181 vc4_state->dlist_initialized = 0; 182 183 __drm_atomic_helper_plane_duplicate_state(plane, &vc4_state->base); 184 185 if (vc4_state->dlist) { 186 vc4_state->dlist = kmemdup(vc4_state->dlist, 187 vc4_state->dlist_count * 4, 188 GFP_KERNEL); 189 if (!vc4_state->dlist) { 190 kfree(vc4_state); 191 return NULL; 192 } 193 vc4_state->dlist_size = vc4_state->dlist_count; 194 } 195 196 return &vc4_state->base; 197 } 198 199 static void vc4_plane_destroy_state(struct drm_plane *plane, 200 struct drm_plane_state *state) 201 { 202 struct vc4_dev *vc4 = to_vc4_dev(plane->dev); 203 struct vc4_plane_state *vc4_state = to_vc4_plane_state(state); 204 205 if (drm_mm_node_allocated(&vc4_state->lbm)) { 206 unsigned long irqflags; 207 208 spin_lock_irqsave(&vc4->hvs->mm_lock, irqflags); 209 drm_mm_remove_node(&vc4_state->lbm); 210 spin_unlock_irqrestore(&vc4->hvs->mm_lock, irqflags); 211 } 212 213 kfree(vc4_state->dlist); 214 __drm_atomic_helper_plane_destroy_state(&vc4_state->base); 215 kfree(state); 216 } 217 218 /* Called during init to allocate the plane's atomic state. */ 219 static void vc4_plane_reset(struct drm_plane *plane) 220 { 221 struct vc4_plane_state *vc4_state; 222 223 WARN_ON(plane->state); 224 225 vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL); 226 if (!vc4_state) 227 return; 228 229 __drm_atomic_helper_plane_reset(plane, &vc4_state->base); 230 } 231 232 static void vc4_dlist_counter_increment(struct vc4_plane_state *vc4_state) 233 { 234 if (vc4_state->dlist_count == vc4_state->dlist_size) { 235 u32 new_size = max(4u, vc4_state->dlist_count * 2); 236 u32 *new_dlist = kmalloc_array(new_size, 4, GFP_KERNEL); 237 238 if (!new_dlist) 239 return; 240 memcpy(new_dlist, vc4_state->dlist, vc4_state->dlist_count * 4); 241 242 kfree(vc4_state->dlist); 243 vc4_state->dlist = new_dlist; 244 vc4_state->dlist_size = new_size; 245 } 246 247 vc4_state->dlist_count++; 248 } 249 250 static void vc4_dlist_write(struct vc4_plane_state *vc4_state, u32 val) 251 { 252 unsigned int idx = vc4_state->dlist_count; 253 254 vc4_dlist_counter_increment(vc4_state); 255 vc4_state->dlist[idx] = val; 256 } 257 258 /* Returns the scl0/scl1 field based on whether the dimensions need to 259 * be up/down/non-scaled. 260 * 261 * This is a replication of a table from the spec. 262 */ 263 static u32 vc4_get_scl_field(struct drm_plane_state *state, int plane) 264 { 265 struct vc4_plane_state *vc4_state = to_vc4_plane_state(state); 266 267 switch (vc4_state->x_scaling[plane] << 2 | vc4_state->y_scaling[plane]) { 268 case VC4_SCALING_PPF << 2 | VC4_SCALING_PPF: 269 return SCALER_CTL0_SCL_H_PPF_V_PPF; 270 case VC4_SCALING_TPZ << 2 | VC4_SCALING_PPF: 271 return SCALER_CTL0_SCL_H_TPZ_V_PPF; 272 case VC4_SCALING_PPF << 2 | VC4_SCALING_TPZ: 273 return SCALER_CTL0_SCL_H_PPF_V_TPZ; 274 case VC4_SCALING_TPZ << 2 | VC4_SCALING_TPZ: 275 return SCALER_CTL0_SCL_H_TPZ_V_TPZ; 276 case VC4_SCALING_PPF << 2 | VC4_SCALING_NONE: 277 return SCALER_CTL0_SCL_H_PPF_V_NONE; 278 case VC4_SCALING_NONE << 2 | VC4_SCALING_PPF: 279 return SCALER_CTL0_SCL_H_NONE_V_PPF; 280 case VC4_SCALING_NONE << 2 | VC4_SCALING_TPZ: 281 return SCALER_CTL0_SCL_H_NONE_V_TPZ; 282 case VC4_SCALING_TPZ << 2 | VC4_SCALING_NONE: 283 return SCALER_CTL0_SCL_H_TPZ_V_NONE; 284 default: 285 case VC4_SCALING_NONE << 2 | VC4_SCALING_NONE: 286 /* The unity case is independently handled by 287 * SCALER_CTL0_UNITY. 288 */ 289 return 0; 290 } 291 } 292 293 static int vc4_plane_margins_adj(struct drm_plane_state *pstate) 294 { 295 struct vc4_plane_state *vc4_pstate = to_vc4_plane_state(pstate); 296 unsigned int left, right, top, bottom, adjhdisplay, adjvdisplay; 297 struct drm_crtc_state *crtc_state; 298 299 crtc_state = drm_atomic_get_new_crtc_state(pstate->state, 300 pstate->crtc); 301 302 vc4_crtc_get_margins(crtc_state, &left, &right, &top, &bottom); 303 if (!left && !right && !top && !bottom) 304 return 0; 305 306 if (left + right >= crtc_state->mode.hdisplay || 307 top + bottom >= crtc_state->mode.vdisplay) 308 return -EINVAL; 309 310 adjhdisplay = crtc_state->mode.hdisplay - (left + right); 311 vc4_pstate->crtc_x = DIV_ROUND_CLOSEST(vc4_pstate->crtc_x * 312 adjhdisplay, 313 crtc_state->mode.hdisplay); 314 vc4_pstate->crtc_x += left; 315 if (vc4_pstate->crtc_x > crtc_state->mode.hdisplay - right) 316 vc4_pstate->crtc_x = crtc_state->mode.hdisplay - right; 317 318 adjvdisplay = crtc_state->mode.vdisplay - (top + bottom); 319 vc4_pstate->crtc_y = DIV_ROUND_CLOSEST(vc4_pstate->crtc_y * 320 adjvdisplay, 321 crtc_state->mode.vdisplay); 322 vc4_pstate->crtc_y += top; 323 if (vc4_pstate->crtc_y > crtc_state->mode.vdisplay - bottom) 324 vc4_pstate->crtc_y = crtc_state->mode.vdisplay - bottom; 325 326 vc4_pstate->crtc_w = DIV_ROUND_CLOSEST(vc4_pstate->crtc_w * 327 adjhdisplay, 328 crtc_state->mode.hdisplay); 329 vc4_pstate->crtc_h = DIV_ROUND_CLOSEST(vc4_pstate->crtc_h * 330 adjvdisplay, 331 crtc_state->mode.vdisplay); 332 333 if (!vc4_pstate->crtc_w || !vc4_pstate->crtc_h) 334 return -EINVAL; 335 336 return 0; 337 } 338 339 static int vc4_plane_setup_clipping_and_scaling(struct drm_plane_state *state) 340 { 341 struct vc4_plane_state *vc4_state = to_vc4_plane_state(state); 342 struct drm_framebuffer *fb = state->fb; 343 struct drm_gem_dma_object *bo = drm_fb_dma_get_gem_obj(fb, 0); 344 int num_planes = fb->format->num_planes; 345 struct drm_crtc_state *crtc_state; 346 u32 h_subsample = fb->format->hsub; 347 u32 v_subsample = fb->format->vsub; 348 int i, ret; 349 350 crtc_state = drm_atomic_get_existing_crtc_state(state->state, 351 state->crtc); 352 if (!crtc_state) { 353 DRM_DEBUG_KMS("Invalid crtc state\n"); 354 return -EINVAL; 355 } 356 357 ret = drm_atomic_helper_check_plane_state(state, crtc_state, 1, 358 INT_MAX, true, true); 359 if (ret) 360 return ret; 361 362 for (i = 0; i < num_planes; i++) 363 vc4_state->offsets[i] = bo->dma_addr + fb->offsets[i]; 364 365 /* 366 * We don't support subpixel source positioning for scaling, 367 * but fractional coordinates can be generated by clipping 368 * so just round for now 369 */ 370 vc4_state->src_x = DIV_ROUND_CLOSEST(state->src.x1, 1 << 16); 371 vc4_state->src_y = DIV_ROUND_CLOSEST(state->src.y1, 1 << 16); 372 vc4_state->src_w[0] = DIV_ROUND_CLOSEST(state->src.x2, 1 << 16) - vc4_state->src_x; 373 vc4_state->src_h[0] = DIV_ROUND_CLOSEST(state->src.y2, 1 << 16) - vc4_state->src_y; 374 375 vc4_state->crtc_x = state->dst.x1; 376 vc4_state->crtc_y = state->dst.y1; 377 vc4_state->crtc_w = state->dst.x2 - state->dst.x1; 378 vc4_state->crtc_h = state->dst.y2 - state->dst.y1; 379 380 ret = vc4_plane_margins_adj(state); 381 if (ret) 382 return ret; 383 384 vc4_state->x_scaling[0] = vc4_get_scaling_mode(vc4_state->src_w[0], 385 vc4_state->crtc_w); 386 vc4_state->y_scaling[0] = vc4_get_scaling_mode(vc4_state->src_h[0], 387 vc4_state->crtc_h); 388 389 vc4_state->is_unity = (vc4_state->x_scaling[0] == VC4_SCALING_NONE && 390 vc4_state->y_scaling[0] == VC4_SCALING_NONE); 391 392 if (num_planes > 1) { 393 vc4_state->is_yuv = true; 394 395 vc4_state->src_w[1] = vc4_state->src_w[0] / h_subsample; 396 vc4_state->src_h[1] = vc4_state->src_h[0] / v_subsample; 397 398 vc4_state->x_scaling[1] = 399 vc4_get_scaling_mode(vc4_state->src_w[1], 400 vc4_state->crtc_w); 401 vc4_state->y_scaling[1] = 402 vc4_get_scaling_mode(vc4_state->src_h[1], 403 vc4_state->crtc_h); 404 405 /* YUV conversion requires that horizontal scaling be enabled 406 * on the UV plane even if vc4_get_scaling_mode() returned 407 * VC4_SCALING_NONE (which can happen when the down-scaling 408 * ratio is 0.5). Let's force it to VC4_SCALING_PPF in this 409 * case. 410 */ 411 if (vc4_state->x_scaling[1] == VC4_SCALING_NONE) 412 vc4_state->x_scaling[1] = VC4_SCALING_PPF; 413 } else { 414 vc4_state->is_yuv = false; 415 vc4_state->x_scaling[1] = VC4_SCALING_NONE; 416 vc4_state->y_scaling[1] = VC4_SCALING_NONE; 417 } 418 419 return 0; 420 } 421 422 static void vc4_write_tpz(struct vc4_plane_state *vc4_state, u32 src, u32 dst) 423 { 424 u32 scale, recip; 425 426 scale = (1 << 16) * src / dst; 427 428 /* The specs note that while the reciprocal would be defined 429 * as (1<<32)/scale, ~0 is close enough. 430 */ 431 recip = ~0 / scale; 432 433 vc4_dlist_write(vc4_state, 434 VC4_SET_FIELD(scale, SCALER_TPZ0_SCALE) | 435 VC4_SET_FIELD(0, SCALER_TPZ0_IPHASE)); 436 vc4_dlist_write(vc4_state, 437 VC4_SET_FIELD(recip, SCALER_TPZ1_RECIP)); 438 } 439 440 static void vc4_write_ppf(struct vc4_plane_state *vc4_state, u32 src, u32 dst) 441 { 442 u32 scale = (1 << 16) * src / dst; 443 444 vc4_dlist_write(vc4_state, 445 SCALER_PPF_AGC | 446 VC4_SET_FIELD(scale, SCALER_PPF_SCALE) | 447 VC4_SET_FIELD(0, SCALER_PPF_IPHASE)); 448 } 449 450 static u32 vc4_lbm_size(struct drm_plane_state *state) 451 { 452 struct vc4_plane_state *vc4_state = to_vc4_plane_state(state); 453 struct vc4_dev *vc4 = to_vc4_dev(state->plane->dev); 454 u32 pix_per_line; 455 u32 lbm; 456 457 /* LBM is not needed when there's no vertical scaling. */ 458 if (vc4_state->y_scaling[0] == VC4_SCALING_NONE && 459 vc4_state->y_scaling[1] == VC4_SCALING_NONE) 460 return 0; 461 462 /* 463 * This can be further optimized in the RGB/YUV444 case if the PPF 464 * decimation factor is between 0.5 and 1.0 by using crtc_w. 465 * 466 * It's not an issue though, since in that case since src_w[0] is going 467 * to be greater than or equal to crtc_w. 468 */ 469 if (vc4_state->x_scaling[0] == VC4_SCALING_TPZ) 470 pix_per_line = vc4_state->crtc_w; 471 else 472 pix_per_line = vc4_state->src_w[0]; 473 474 if (!vc4_state->is_yuv) { 475 if (vc4_state->y_scaling[0] == VC4_SCALING_TPZ) 476 lbm = pix_per_line * 8; 477 else { 478 /* In special cases, this multiplier might be 12. */ 479 lbm = pix_per_line * 16; 480 } 481 } else { 482 /* There are cases for this going down to a multiplier 483 * of 2, but according to the firmware source, the 484 * table in the docs is somewhat wrong. 485 */ 486 lbm = pix_per_line * 16; 487 } 488 489 /* Align it to 64 or 128 (hvs5) bytes */ 490 lbm = roundup(lbm, vc4->is_vc5 ? 128 : 64); 491 492 /* Each "word" of the LBM memory contains 2 or 4 (hvs5) pixels */ 493 lbm /= vc4->is_vc5 ? 4 : 2; 494 495 return lbm; 496 } 497 498 static void vc4_write_scaling_parameters(struct drm_plane_state *state, 499 int channel) 500 { 501 struct vc4_plane_state *vc4_state = to_vc4_plane_state(state); 502 503 /* Ch0 H-PPF Word 0: Scaling Parameters */ 504 if (vc4_state->x_scaling[channel] == VC4_SCALING_PPF) { 505 vc4_write_ppf(vc4_state, 506 vc4_state->src_w[channel], vc4_state->crtc_w); 507 } 508 509 /* Ch0 V-PPF Words 0-1: Scaling Parameters, Context */ 510 if (vc4_state->y_scaling[channel] == VC4_SCALING_PPF) { 511 vc4_write_ppf(vc4_state, 512 vc4_state->src_h[channel], vc4_state->crtc_h); 513 vc4_dlist_write(vc4_state, 0xc0c0c0c0); 514 } 515 516 /* Ch0 H-TPZ Words 0-1: Scaling Parameters, Recip */ 517 if (vc4_state->x_scaling[channel] == VC4_SCALING_TPZ) { 518 vc4_write_tpz(vc4_state, 519 vc4_state->src_w[channel], vc4_state->crtc_w); 520 } 521 522 /* Ch0 V-TPZ Words 0-2: Scaling Parameters, Recip, Context */ 523 if (vc4_state->y_scaling[channel] == VC4_SCALING_TPZ) { 524 vc4_write_tpz(vc4_state, 525 vc4_state->src_h[channel], vc4_state->crtc_h); 526 vc4_dlist_write(vc4_state, 0xc0c0c0c0); 527 } 528 } 529 530 static void vc4_plane_calc_load(struct drm_plane_state *state) 531 { 532 unsigned int hvs_load_shift, vrefresh, i; 533 struct drm_framebuffer *fb = state->fb; 534 struct vc4_plane_state *vc4_state; 535 struct drm_crtc_state *crtc_state; 536 unsigned int vscale_factor; 537 538 vc4_state = to_vc4_plane_state(state); 539 crtc_state = drm_atomic_get_existing_crtc_state(state->state, 540 state->crtc); 541 vrefresh = drm_mode_vrefresh(&crtc_state->adjusted_mode); 542 543 /* The HVS is able to process 2 pixels/cycle when scaling the source, 544 * 4 pixels/cycle otherwise. 545 * Alpha blending step seems to be pipelined and it's always operating 546 * at 4 pixels/cycle, so the limiting aspect here seems to be the 547 * scaler block. 548 * HVS load is expressed in clk-cycles/sec (AKA Hz). 549 */ 550 if (vc4_state->x_scaling[0] != VC4_SCALING_NONE || 551 vc4_state->x_scaling[1] != VC4_SCALING_NONE || 552 vc4_state->y_scaling[0] != VC4_SCALING_NONE || 553 vc4_state->y_scaling[1] != VC4_SCALING_NONE) 554 hvs_load_shift = 1; 555 else 556 hvs_load_shift = 2; 557 558 vc4_state->membus_load = 0; 559 vc4_state->hvs_load = 0; 560 for (i = 0; i < fb->format->num_planes; i++) { 561 /* Even if the bandwidth/plane required for a single frame is 562 * 563 * vc4_state->src_w[i] * vc4_state->src_h[i] * cpp * vrefresh 564 * 565 * when downscaling, we have to read more pixels per line in 566 * the time frame reserved for a single line, so the bandwidth 567 * demand can be punctually higher. To account for that, we 568 * calculate the down-scaling factor and multiply the plane 569 * load by this number. We're likely over-estimating the read 570 * demand, but that's better than under-estimating it. 571 */ 572 vscale_factor = DIV_ROUND_UP(vc4_state->src_h[i], 573 vc4_state->crtc_h); 574 vc4_state->membus_load += vc4_state->src_w[i] * 575 vc4_state->src_h[i] * vscale_factor * 576 fb->format->cpp[i]; 577 vc4_state->hvs_load += vc4_state->crtc_h * vc4_state->crtc_w; 578 } 579 580 vc4_state->hvs_load *= vrefresh; 581 vc4_state->hvs_load >>= hvs_load_shift; 582 vc4_state->membus_load *= vrefresh; 583 } 584 585 static int vc4_plane_allocate_lbm(struct drm_plane_state *state) 586 { 587 struct vc4_dev *vc4 = to_vc4_dev(state->plane->dev); 588 struct vc4_plane_state *vc4_state = to_vc4_plane_state(state); 589 unsigned long irqflags; 590 u32 lbm_size; 591 592 lbm_size = vc4_lbm_size(state); 593 if (!lbm_size) 594 return 0; 595 596 if (WARN_ON(!vc4_state->lbm_offset)) 597 return -EINVAL; 598 599 /* Allocate the LBM memory that the HVS will use for temporary 600 * storage due to our scaling/format conversion. 601 */ 602 if (!drm_mm_node_allocated(&vc4_state->lbm)) { 603 int ret; 604 605 spin_lock_irqsave(&vc4->hvs->mm_lock, irqflags); 606 ret = drm_mm_insert_node_generic(&vc4->hvs->lbm_mm, 607 &vc4_state->lbm, 608 lbm_size, 609 vc4->is_vc5 ? 64 : 32, 610 0, 0); 611 spin_unlock_irqrestore(&vc4->hvs->mm_lock, irqflags); 612 613 if (ret) 614 return ret; 615 } else { 616 WARN_ON_ONCE(lbm_size != vc4_state->lbm.size); 617 } 618 619 vc4_state->dlist[vc4_state->lbm_offset] = vc4_state->lbm.start; 620 621 return 0; 622 } 623 624 /* 625 * The colorspace conversion matrices are held in 3 entries in the dlist. 626 * Create an array of them, with entries for each full and limited mode, and 627 * each supported colorspace. 628 */ 629 static const u32 colorspace_coeffs[2][DRM_COLOR_ENCODING_MAX][3] = { 630 { 631 /* Limited range */ 632 { 633 /* BT601 */ 634 SCALER_CSC0_ITR_R_601_5, 635 SCALER_CSC1_ITR_R_601_5, 636 SCALER_CSC2_ITR_R_601_5, 637 }, { 638 /* BT709 */ 639 SCALER_CSC0_ITR_R_709_3, 640 SCALER_CSC1_ITR_R_709_3, 641 SCALER_CSC2_ITR_R_709_3, 642 }, { 643 /* BT2020 */ 644 SCALER_CSC0_ITR_R_2020, 645 SCALER_CSC1_ITR_R_2020, 646 SCALER_CSC2_ITR_R_2020, 647 } 648 }, { 649 /* Full range */ 650 { 651 /* JFIF */ 652 SCALER_CSC0_JPEG_JFIF, 653 SCALER_CSC1_JPEG_JFIF, 654 SCALER_CSC2_JPEG_JFIF, 655 }, { 656 /* BT709 */ 657 SCALER_CSC0_ITR_R_709_3_FR, 658 SCALER_CSC1_ITR_R_709_3_FR, 659 SCALER_CSC2_ITR_R_709_3_FR, 660 }, { 661 /* BT2020 */ 662 SCALER_CSC0_ITR_R_2020_FR, 663 SCALER_CSC1_ITR_R_2020_FR, 664 SCALER_CSC2_ITR_R_2020_FR, 665 } 666 } 667 }; 668 669 static u32 vc4_hvs4_get_alpha_blend_mode(struct drm_plane_state *state) 670 { 671 if (!state->fb->format->has_alpha) 672 return VC4_SET_FIELD(SCALER_POS2_ALPHA_MODE_FIXED, 673 SCALER_POS2_ALPHA_MODE); 674 675 switch (state->pixel_blend_mode) { 676 case DRM_MODE_BLEND_PIXEL_NONE: 677 return VC4_SET_FIELD(SCALER_POS2_ALPHA_MODE_FIXED, 678 SCALER_POS2_ALPHA_MODE); 679 default: 680 case DRM_MODE_BLEND_PREMULTI: 681 return VC4_SET_FIELD(SCALER_POS2_ALPHA_MODE_PIPELINE, 682 SCALER_POS2_ALPHA_MODE) | 683 SCALER_POS2_ALPHA_PREMULT; 684 case DRM_MODE_BLEND_COVERAGE: 685 return VC4_SET_FIELD(SCALER_POS2_ALPHA_MODE_PIPELINE, 686 SCALER_POS2_ALPHA_MODE); 687 } 688 } 689 690 static u32 vc4_hvs5_get_alpha_blend_mode(struct drm_plane_state *state) 691 { 692 if (!state->fb->format->has_alpha) 693 return VC4_SET_FIELD(SCALER5_CTL2_ALPHA_MODE_FIXED, 694 SCALER5_CTL2_ALPHA_MODE); 695 696 switch (state->pixel_blend_mode) { 697 case DRM_MODE_BLEND_PIXEL_NONE: 698 return VC4_SET_FIELD(SCALER5_CTL2_ALPHA_MODE_FIXED, 699 SCALER5_CTL2_ALPHA_MODE); 700 default: 701 case DRM_MODE_BLEND_PREMULTI: 702 return VC4_SET_FIELD(SCALER5_CTL2_ALPHA_MODE_PIPELINE, 703 SCALER5_CTL2_ALPHA_MODE) | 704 SCALER5_CTL2_ALPHA_PREMULT; 705 case DRM_MODE_BLEND_COVERAGE: 706 return VC4_SET_FIELD(SCALER5_CTL2_ALPHA_MODE_PIPELINE, 707 SCALER5_CTL2_ALPHA_MODE); 708 } 709 } 710 711 /* Writes out a full display list for an active plane to the plane's 712 * private dlist state. 713 */ 714 static int vc4_plane_mode_set(struct drm_plane *plane, 715 struct drm_plane_state *state) 716 { 717 struct vc4_dev *vc4 = to_vc4_dev(plane->dev); 718 struct vc4_plane_state *vc4_state = to_vc4_plane_state(state); 719 struct drm_framebuffer *fb = state->fb; 720 u32 ctl0_offset = vc4_state->dlist_count; 721 const struct hvs_format *format = vc4_get_hvs_format(fb->format->format); 722 u64 base_format_mod = fourcc_mod_broadcom_mod(fb->modifier); 723 int num_planes = fb->format->num_planes; 724 u32 h_subsample = fb->format->hsub; 725 u32 v_subsample = fb->format->vsub; 726 bool mix_plane_alpha; 727 bool covers_screen; 728 u32 scl0, scl1, pitch0; 729 u32 tiling, src_y; 730 u32 hvs_format = format->hvs; 731 unsigned int rotation; 732 int ret, i; 733 734 if (vc4_state->dlist_initialized) 735 return 0; 736 737 ret = vc4_plane_setup_clipping_and_scaling(state); 738 if (ret) 739 return ret; 740 741 /* SCL1 is used for Cb/Cr scaling of planar formats. For RGB 742 * and 4:4:4, scl1 should be set to scl0 so both channels of 743 * the scaler do the same thing. For YUV, the Y plane needs 744 * to be put in channel 1 and Cb/Cr in channel 0, so we swap 745 * the scl fields here. 746 */ 747 if (num_planes == 1) { 748 scl0 = vc4_get_scl_field(state, 0); 749 scl1 = scl0; 750 } else { 751 scl0 = vc4_get_scl_field(state, 1); 752 scl1 = vc4_get_scl_field(state, 0); 753 } 754 755 rotation = drm_rotation_simplify(state->rotation, 756 DRM_MODE_ROTATE_0 | 757 DRM_MODE_REFLECT_X | 758 DRM_MODE_REFLECT_Y); 759 760 /* We must point to the last line when Y reflection is enabled. */ 761 src_y = vc4_state->src_y; 762 if (rotation & DRM_MODE_REFLECT_Y) 763 src_y += vc4_state->src_h[0] - 1; 764 765 switch (base_format_mod) { 766 case DRM_FORMAT_MOD_LINEAR: 767 tiling = SCALER_CTL0_TILING_LINEAR; 768 pitch0 = VC4_SET_FIELD(fb->pitches[0], SCALER_SRC_PITCH); 769 770 /* Adjust the base pointer to the first pixel to be scanned 771 * out. 772 */ 773 for (i = 0; i < num_planes; i++) { 774 vc4_state->offsets[i] += src_y / 775 (i ? v_subsample : 1) * 776 fb->pitches[i]; 777 778 vc4_state->offsets[i] += vc4_state->src_x / 779 (i ? h_subsample : 1) * 780 fb->format->cpp[i]; 781 } 782 783 break; 784 785 case DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED: { 786 u32 tile_size_shift = 12; /* T tiles are 4kb */ 787 /* Whole-tile offsets, mostly for setting the pitch. */ 788 u32 tile_w_shift = fb->format->cpp[0] == 2 ? 6 : 5; 789 u32 tile_h_shift = 5; /* 16 and 32bpp are 32 pixels high */ 790 u32 tile_w_mask = (1 << tile_w_shift) - 1; 791 /* The height mask on 32-bit-per-pixel tiles is 63, i.e. twice 792 * the height (in pixels) of a 4k tile. 793 */ 794 u32 tile_h_mask = (2 << tile_h_shift) - 1; 795 /* For T-tiled, the FB pitch is "how many bytes from one row to 796 * the next, such that 797 * 798 * pitch * tile_h == tile_size * tiles_per_row 799 */ 800 u32 tiles_w = fb->pitches[0] >> (tile_size_shift - tile_h_shift); 801 u32 tiles_l = vc4_state->src_x >> tile_w_shift; 802 u32 tiles_r = tiles_w - tiles_l; 803 u32 tiles_t = src_y >> tile_h_shift; 804 /* Intra-tile offsets, which modify the base address (the 805 * SCALER_PITCH0_TILE_Y_OFFSET tells HVS how to walk from that 806 * base address). 807 */ 808 u32 tile_y = (src_y >> 4) & 1; 809 u32 subtile_y = (src_y >> 2) & 3; 810 u32 utile_y = src_y & 3; 811 u32 x_off = vc4_state->src_x & tile_w_mask; 812 u32 y_off = src_y & tile_h_mask; 813 814 /* When Y reflection is requested we must set the 815 * SCALER_PITCH0_TILE_LINE_DIR flag to tell HVS that all lines 816 * after the initial one should be fetched in descending order, 817 * which makes sense since we start from the last line and go 818 * backward. 819 * Don't know why we need y_off = max_y_off - y_off, but it's 820 * definitely required (I guess it's also related to the "going 821 * backward" situation). 822 */ 823 if (rotation & DRM_MODE_REFLECT_Y) { 824 y_off = tile_h_mask - y_off; 825 pitch0 = SCALER_PITCH0_TILE_LINE_DIR; 826 } else { 827 pitch0 = 0; 828 } 829 830 tiling = SCALER_CTL0_TILING_256B_OR_T; 831 pitch0 |= (VC4_SET_FIELD(x_off, SCALER_PITCH0_SINK_PIX) | 832 VC4_SET_FIELD(y_off, SCALER_PITCH0_TILE_Y_OFFSET) | 833 VC4_SET_FIELD(tiles_l, SCALER_PITCH0_TILE_WIDTH_L) | 834 VC4_SET_FIELD(tiles_r, SCALER_PITCH0_TILE_WIDTH_R)); 835 vc4_state->offsets[0] += tiles_t * (tiles_w << tile_size_shift); 836 vc4_state->offsets[0] += subtile_y << 8; 837 vc4_state->offsets[0] += utile_y << 4; 838 839 /* Rows of tiles alternate left-to-right and right-to-left. */ 840 if (tiles_t & 1) { 841 pitch0 |= SCALER_PITCH0_TILE_INITIAL_LINE_DIR; 842 vc4_state->offsets[0] += (tiles_w - tiles_l) << 843 tile_size_shift; 844 vc4_state->offsets[0] -= (1 + !tile_y) << 10; 845 } else { 846 vc4_state->offsets[0] += tiles_l << tile_size_shift; 847 vc4_state->offsets[0] += tile_y << 10; 848 } 849 850 break; 851 } 852 853 case DRM_FORMAT_MOD_BROADCOM_SAND64: 854 case DRM_FORMAT_MOD_BROADCOM_SAND128: 855 case DRM_FORMAT_MOD_BROADCOM_SAND256: { 856 uint32_t param = fourcc_mod_broadcom_param(fb->modifier); 857 858 if (param > SCALER_TILE_HEIGHT_MASK) { 859 DRM_DEBUG_KMS("SAND height too large (%d)\n", 860 param); 861 return -EINVAL; 862 } 863 864 if (fb->format->format == DRM_FORMAT_P030) { 865 hvs_format = HVS_PIXEL_FORMAT_YCBCR_10BIT; 866 tiling = SCALER_CTL0_TILING_128B; 867 } else { 868 hvs_format = HVS_PIXEL_FORMAT_H264; 869 870 switch (base_format_mod) { 871 case DRM_FORMAT_MOD_BROADCOM_SAND64: 872 tiling = SCALER_CTL0_TILING_64B; 873 break; 874 case DRM_FORMAT_MOD_BROADCOM_SAND128: 875 tiling = SCALER_CTL0_TILING_128B; 876 break; 877 case DRM_FORMAT_MOD_BROADCOM_SAND256: 878 tiling = SCALER_CTL0_TILING_256B_OR_T; 879 break; 880 default: 881 return -EINVAL; 882 } 883 } 884 885 /* Adjust the base pointer to the first pixel to be scanned 886 * out. 887 * 888 * For P030, y_ptr [31:4] is the 128bit word for the start pixel 889 * y_ptr [3:0] is the pixel (0-11) contained within that 128bit 890 * word that should be taken as the first pixel. 891 * Ditto uv_ptr [31:4] vs [3:0], however [3:0] contains the 892 * element within the 128bit word, eg for pixel 3 the value 893 * should be 6. 894 */ 895 for (i = 0; i < num_planes; i++) { 896 u32 tile_w, tile, x_off, pix_per_tile; 897 898 if (fb->format->format == DRM_FORMAT_P030) { 899 /* 900 * Spec says: bits [31:4] of the given address 901 * should point to the 128-bit word containing 902 * the desired starting pixel, and bits[3:0] 903 * should be between 0 and 11, indicating which 904 * of the 12-pixels in that 128-bit word is the 905 * first pixel to be used 906 */ 907 u32 remaining_pixels = vc4_state->src_x % 96; 908 u32 aligned = remaining_pixels / 12; 909 u32 last_bits = remaining_pixels % 12; 910 911 x_off = aligned * 16 + last_bits; 912 tile_w = 128; 913 pix_per_tile = 96; 914 } else { 915 switch (base_format_mod) { 916 case DRM_FORMAT_MOD_BROADCOM_SAND64: 917 tile_w = 64; 918 break; 919 case DRM_FORMAT_MOD_BROADCOM_SAND128: 920 tile_w = 128; 921 break; 922 case DRM_FORMAT_MOD_BROADCOM_SAND256: 923 tile_w = 256; 924 break; 925 default: 926 return -EINVAL; 927 } 928 pix_per_tile = tile_w / fb->format->cpp[0]; 929 x_off = (vc4_state->src_x % pix_per_tile) / 930 (i ? h_subsample : 1) * 931 fb->format->cpp[i]; 932 } 933 934 tile = vc4_state->src_x / pix_per_tile; 935 936 vc4_state->offsets[i] += param * tile_w * tile; 937 vc4_state->offsets[i] += src_y / 938 (i ? v_subsample : 1) * 939 tile_w; 940 vc4_state->offsets[i] += x_off & ~(i ? 1 : 0); 941 } 942 943 pitch0 = VC4_SET_FIELD(param, SCALER_TILE_HEIGHT); 944 break; 945 } 946 947 default: 948 DRM_DEBUG_KMS("Unsupported FB tiling flag 0x%16llx", 949 (long long)fb->modifier); 950 return -EINVAL; 951 } 952 953 /* Don't waste cycles mixing with plane alpha if the set alpha 954 * is opaque or there is no per-pixel alpha information. 955 * In any case we use the alpha property value as the fixed alpha. 956 */ 957 mix_plane_alpha = state->alpha != DRM_BLEND_ALPHA_OPAQUE && 958 fb->format->has_alpha; 959 960 if (!vc4->is_vc5) { 961 /* Control word */ 962 vc4_dlist_write(vc4_state, 963 SCALER_CTL0_VALID | 964 (rotation & DRM_MODE_REFLECT_X ? SCALER_CTL0_HFLIP : 0) | 965 (rotation & DRM_MODE_REFLECT_Y ? SCALER_CTL0_VFLIP : 0) | 966 VC4_SET_FIELD(SCALER_CTL0_RGBA_EXPAND_ROUND, SCALER_CTL0_RGBA_EXPAND) | 967 (format->pixel_order << SCALER_CTL0_ORDER_SHIFT) | 968 (hvs_format << SCALER_CTL0_PIXEL_FORMAT_SHIFT) | 969 VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) | 970 (vc4_state->is_unity ? SCALER_CTL0_UNITY : 0) | 971 VC4_SET_FIELD(scl0, SCALER_CTL0_SCL0) | 972 VC4_SET_FIELD(scl1, SCALER_CTL0_SCL1)); 973 974 /* Position Word 0: Image Positions and Alpha Value */ 975 vc4_state->pos0_offset = vc4_state->dlist_count; 976 vc4_dlist_write(vc4_state, 977 VC4_SET_FIELD(state->alpha >> 8, SCALER_POS0_FIXED_ALPHA) | 978 VC4_SET_FIELD(vc4_state->crtc_x, SCALER_POS0_START_X) | 979 VC4_SET_FIELD(vc4_state->crtc_y, SCALER_POS0_START_Y)); 980 981 /* Position Word 1: Scaled Image Dimensions. */ 982 if (!vc4_state->is_unity) { 983 vc4_dlist_write(vc4_state, 984 VC4_SET_FIELD(vc4_state->crtc_w, 985 SCALER_POS1_SCL_WIDTH) | 986 VC4_SET_FIELD(vc4_state->crtc_h, 987 SCALER_POS1_SCL_HEIGHT)); 988 } 989 990 /* Position Word 2: Source Image Size, Alpha */ 991 vc4_state->pos2_offset = vc4_state->dlist_count; 992 vc4_dlist_write(vc4_state, 993 (mix_plane_alpha ? SCALER_POS2_ALPHA_MIX : 0) | 994 vc4_hvs4_get_alpha_blend_mode(state) | 995 VC4_SET_FIELD(vc4_state->src_w[0], 996 SCALER_POS2_WIDTH) | 997 VC4_SET_FIELD(vc4_state->src_h[0], 998 SCALER_POS2_HEIGHT)); 999 1000 /* Position Word 3: Context. Written by the HVS. */ 1001 vc4_dlist_write(vc4_state, 0xc0c0c0c0); 1002 1003 } else { 1004 u32 hvs_pixel_order = format->pixel_order; 1005 1006 if (format->pixel_order_hvs5) 1007 hvs_pixel_order = format->pixel_order_hvs5; 1008 1009 /* Control word */ 1010 vc4_dlist_write(vc4_state, 1011 SCALER_CTL0_VALID | 1012 (hvs_pixel_order << SCALER_CTL0_ORDER_SHIFT) | 1013 (hvs_format << SCALER_CTL0_PIXEL_FORMAT_SHIFT) | 1014 VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) | 1015 (vc4_state->is_unity ? 1016 SCALER5_CTL0_UNITY : 0) | 1017 VC4_SET_FIELD(scl0, SCALER_CTL0_SCL0) | 1018 VC4_SET_FIELD(scl1, SCALER_CTL0_SCL1) | 1019 SCALER5_CTL0_ALPHA_EXPAND | 1020 SCALER5_CTL0_RGB_EXPAND); 1021 1022 /* Position Word 0: Image Positions and Alpha Value */ 1023 vc4_state->pos0_offset = vc4_state->dlist_count; 1024 vc4_dlist_write(vc4_state, 1025 (rotation & DRM_MODE_REFLECT_Y ? 1026 SCALER5_POS0_VFLIP : 0) | 1027 VC4_SET_FIELD(vc4_state->crtc_x, 1028 SCALER_POS0_START_X) | 1029 (rotation & DRM_MODE_REFLECT_X ? 1030 SCALER5_POS0_HFLIP : 0) | 1031 VC4_SET_FIELD(vc4_state->crtc_y, 1032 SCALER5_POS0_START_Y) 1033 ); 1034 1035 /* Control Word 2 */ 1036 vc4_dlist_write(vc4_state, 1037 VC4_SET_FIELD(state->alpha >> 4, 1038 SCALER5_CTL2_ALPHA) | 1039 vc4_hvs5_get_alpha_blend_mode(state) | 1040 (mix_plane_alpha ? 1041 SCALER5_CTL2_ALPHA_MIX : 0) 1042 ); 1043 1044 /* Position Word 1: Scaled Image Dimensions. */ 1045 if (!vc4_state->is_unity) { 1046 vc4_dlist_write(vc4_state, 1047 VC4_SET_FIELD(vc4_state->crtc_w, 1048 SCALER5_POS1_SCL_WIDTH) | 1049 VC4_SET_FIELD(vc4_state->crtc_h, 1050 SCALER5_POS1_SCL_HEIGHT)); 1051 } 1052 1053 /* Position Word 2: Source Image Size */ 1054 vc4_state->pos2_offset = vc4_state->dlist_count; 1055 vc4_dlist_write(vc4_state, 1056 VC4_SET_FIELD(vc4_state->src_w[0], 1057 SCALER5_POS2_WIDTH) | 1058 VC4_SET_FIELD(vc4_state->src_h[0], 1059 SCALER5_POS2_HEIGHT)); 1060 1061 /* Position Word 3: Context. Written by the HVS. */ 1062 vc4_dlist_write(vc4_state, 0xc0c0c0c0); 1063 } 1064 1065 1066 /* Pointer Word 0/1/2: RGB / Y / Cb / Cr Pointers 1067 * 1068 * The pointers may be any byte address. 1069 */ 1070 vc4_state->ptr0_offset = vc4_state->dlist_count; 1071 for (i = 0; i < num_planes; i++) 1072 vc4_dlist_write(vc4_state, vc4_state->offsets[i]); 1073 1074 /* Pointer Context Word 0/1/2: Written by the HVS */ 1075 for (i = 0; i < num_planes; i++) 1076 vc4_dlist_write(vc4_state, 0xc0c0c0c0); 1077 1078 /* Pitch word 0 */ 1079 vc4_dlist_write(vc4_state, pitch0); 1080 1081 /* Pitch word 1/2 */ 1082 for (i = 1; i < num_planes; i++) { 1083 if (hvs_format != HVS_PIXEL_FORMAT_H264 && 1084 hvs_format != HVS_PIXEL_FORMAT_YCBCR_10BIT) { 1085 vc4_dlist_write(vc4_state, 1086 VC4_SET_FIELD(fb->pitches[i], 1087 SCALER_SRC_PITCH)); 1088 } else { 1089 vc4_dlist_write(vc4_state, pitch0); 1090 } 1091 } 1092 1093 /* Colorspace conversion words */ 1094 if (vc4_state->is_yuv) { 1095 enum drm_color_encoding color_encoding = state->color_encoding; 1096 enum drm_color_range color_range = state->color_range; 1097 const u32 *ccm; 1098 1099 if (color_encoding >= DRM_COLOR_ENCODING_MAX) 1100 color_encoding = DRM_COLOR_YCBCR_BT601; 1101 if (color_range >= DRM_COLOR_RANGE_MAX) 1102 color_range = DRM_COLOR_YCBCR_LIMITED_RANGE; 1103 1104 ccm = colorspace_coeffs[color_range][color_encoding]; 1105 1106 vc4_dlist_write(vc4_state, ccm[0]); 1107 vc4_dlist_write(vc4_state, ccm[1]); 1108 vc4_dlist_write(vc4_state, ccm[2]); 1109 } 1110 1111 vc4_state->lbm_offset = 0; 1112 1113 if (vc4_state->x_scaling[0] != VC4_SCALING_NONE || 1114 vc4_state->x_scaling[1] != VC4_SCALING_NONE || 1115 vc4_state->y_scaling[0] != VC4_SCALING_NONE || 1116 vc4_state->y_scaling[1] != VC4_SCALING_NONE) { 1117 /* Reserve a slot for the LBM Base Address. The real value will 1118 * be set when calling vc4_plane_allocate_lbm(). 1119 */ 1120 if (vc4_state->y_scaling[0] != VC4_SCALING_NONE || 1121 vc4_state->y_scaling[1] != VC4_SCALING_NONE) { 1122 vc4_state->lbm_offset = vc4_state->dlist_count; 1123 vc4_dlist_counter_increment(vc4_state); 1124 } 1125 1126 if (num_planes > 1) { 1127 /* Emit Cb/Cr as channel 0 and Y as channel 1128 * 1. This matches how we set up scl0/scl1 1129 * above. 1130 */ 1131 vc4_write_scaling_parameters(state, 1); 1132 } 1133 vc4_write_scaling_parameters(state, 0); 1134 1135 /* If any PPF setup was done, then all the kernel 1136 * pointers get uploaded. 1137 */ 1138 if (vc4_state->x_scaling[0] == VC4_SCALING_PPF || 1139 vc4_state->y_scaling[0] == VC4_SCALING_PPF || 1140 vc4_state->x_scaling[1] == VC4_SCALING_PPF || 1141 vc4_state->y_scaling[1] == VC4_SCALING_PPF) { 1142 u32 kernel = VC4_SET_FIELD(vc4->hvs->mitchell_netravali_filter.start, 1143 SCALER_PPF_KERNEL_OFFSET); 1144 1145 /* HPPF plane 0 */ 1146 vc4_dlist_write(vc4_state, kernel); 1147 /* VPPF plane 0 */ 1148 vc4_dlist_write(vc4_state, kernel); 1149 /* HPPF plane 1 */ 1150 vc4_dlist_write(vc4_state, kernel); 1151 /* VPPF plane 1 */ 1152 vc4_dlist_write(vc4_state, kernel); 1153 } 1154 } 1155 1156 vc4_state->dlist[ctl0_offset] |= 1157 VC4_SET_FIELD(vc4_state->dlist_count, SCALER_CTL0_SIZE); 1158 1159 /* crtc_* are already clipped coordinates. */ 1160 covers_screen = vc4_state->crtc_x == 0 && vc4_state->crtc_y == 0 && 1161 vc4_state->crtc_w == state->crtc->mode.hdisplay && 1162 vc4_state->crtc_h == state->crtc->mode.vdisplay; 1163 /* Background fill might be necessary when the plane has per-pixel 1164 * alpha content or a non-opaque plane alpha and could blend from the 1165 * background or does not cover the entire screen. 1166 */ 1167 vc4_state->needs_bg_fill = fb->format->has_alpha || !covers_screen || 1168 state->alpha != DRM_BLEND_ALPHA_OPAQUE; 1169 1170 /* Flag the dlist as initialized to avoid checking it twice in case 1171 * the async update check already called vc4_plane_mode_set() and 1172 * decided to fallback to sync update because async update was not 1173 * possible. 1174 */ 1175 vc4_state->dlist_initialized = 1; 1176 1177 vc4_plane_calc_load(state); 1178 1179 return 0; 1180 } 1181 1182 /* If a modeset involves changing the setup of a plane, the atomic 1183 * infrastructure will call this to validate a proposed plane setup. 1184 * However, if a plane isn't getting updated, this (and the 1185 * corresponding vc4_plane_atomic_update) won't get called. Thus, we 1186 * compute the dlist here and have all active plane dlists get updated 1187 * in the CRTC's flush. 1188 */ 1189 static int vc4_plane_atomic_check(struct drm_plane *plane, 1190 struct drm_atomic_state *state) 1191 { 1192 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 1193 plane); 1194 struct vc4_plane_state *vc4_state = to_vc4_plane_state(new_plane_state); 1195 int ret; 1196 1197 vc4_state->dlist_count = 0; 1198 1199 if (!plane_enabled(new_plane_state)) 1200 return 0; 1201 1202 ret = vc4_plane_mode_set(plane, new_plane_state); 1203 if (ret) 1204 return ret; 1205 1206 return vc4_plane_allocate_lbm(new_plane_state); 1207 } 1208 1209 static void vc4_plane_atomic_update(struct drm_plane *plane, 1210 struct drm_atomic_state *state) 1211 { 1212 /* No contents here. Since we don't know where in the CRTC's 1213 * dlist we should be stored, our dlist is uploaded to the 1214 * hardware with vc4_plane_write_dlist() at CRTC atomic_flush 1215 * time. 1216 */ 1217 } 1218 1219 u32 vc4_plane_write_dlist(struct drm_plane *plane, u32 __iomem *dlist) 1220 { 1221 struct vc4_plane_state *vc4_state = to_vc4_plane_state(plane->state); 1222 int i; 1223 int idx; 1224 1225 if (!drm_dev_enter(plane->dev, &idx)) 1226 goto out; 1227 1228 vc4_state->hw_dlist = dlist; 1229 1230 /* Can't memcpy_toio() because it needs to be 32-bit writes. */ 1231 for (i = 0; i < vc4_state->dlist_count; i++) 1232 writel(vc4_state->dlist[i], &dlist[i]); 1233 1234 drm_dev_exit(idx); 1235 1236 out: 1237 return vc4_state->dlist_count; 1238 } 1239 1240 u32 vc4_plane_dlist_size(const struct drm_plane_state *state) 1241 { 1242 const struct vc4_plane_state *vc4_state = 1243 container_of(state, typeof(*vc4_state), base); 1244 1245 return vc4_state->dlist_count; 1246 } 1247 1248 /* Updates the plane to immediately (well, once the FIFO needs 1249 * refilling) scan out from at a new framebuffer. 1250 */ 1251 void vc4_plane_async_set_fb(struct drm_plane *plane, struct drm_framebuffer *fb) 1252 { 1253 struct vc4_plane_state *vc4_state = to_vc4_plane_state(plane->state); 1254 struct drm_gem_dma_object *bo = drm_fb_dma_get_gem_obj(fb, 0); 1255 uint32_t addr; 1256 int idx; 1257 1258 if (!drm_dev_enter(plane->dev, &idx)) 1259 return; 1260 1261 /* We're skipping the address adjustment for negative origin, 1262 * because this is only called on the primary plane. 1263 */ 1264 WARN_ON_ONCE(plane->state->crtc_x < 0 || plane->state->crtc_y < 0); 1265 addr = bo->dma_addr + fb->offsets[0]; 1266 1267 /* Write the new address into the hardware immediately. The 1268 * scanout will start from this address as soon as the FIFO 1269 * needs to refill with pixels. 1270 */ 1271 writel(addr, &vc4_state->hw_dlist[vc4_state->ptr0_offset]); 1272 1273 /* Also update the CPU-side dlist copy, so that any later 1274 * atomic updates that don't do a new modeset on our plane 1275 * also use our updated address. 1276 */ 1277 vc4_state->dlist[vc4_state->ptr0_offset] = addr; 1278 1279 drm_dev_exit(idx); 1280 } 1281 1282 static void vc4_plane_atomic_async_update(struct drm_plane *plane, 1283 struct drm_atomic_state *state) 1284 { 1285 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 1286 plane); 1287 struct vc4_plane_state *vc4_state, *new_vc4_state; 1288 int idx; 1289 1290 if (!drm_dev_enter(plane->dev, &idx)) 1291 return; 1292 1293 swap(plane->state->fb, new_plane_state->fb); 1294 plane->state->crtc_x = new_plane_state->crtc_x; 1295 plane->state->crtc_y = new_plane_state->crtc_y; 1296 plane->state->crtc_w = new_plane_state->crtc_w; 1297 plane->state->crtc_h = new_plane_state->crtc_h; 1298 plane->state->src_x = new_plane_state->src_x; 1299 plane->state->src_y = new_plane_state->src_y; 1300 plane->state->src_w = new_plane_state->src_w; 1301 plane->state->src_h = new_plane_state->src_h; 1302 plane->state->alpha = new_plane_state->alpha; 1303 plane->state->pixel_blend_mode = new_plane_state->pixel_blend_mode; 1304 plane->state->rotation = new_plane_state->rotation; 1305 plane->state->zpos = new_plane_state->zpos; 1306 plane->state->normalized_zpos = new_plane_state->normalized_zpos; 1307 plane->state->color_encoding = new_plane_state->color_encoding; 1308 plane->state->color_range = new_plane_state->color_range; 1309 plane->state->src = new_plane_state->src; 1310 plane->state->dst = new_plane_state->dst; 1311 plane->state->visible = new_plane_state->visible; 1312 1313 new_vc4_state = to_vc4_plane_state(new_plane_state); 1314 vc4_state = to_vc4_plane_state(plane->state); 1315 1316 vc4_state->crtc_x = new_vc4_state->crtc_x; 1317 vc4_state->crtc_y = new_vc4_state->crtc_y; 1318 vc4_state->crtc_h = new_vc4_state->crtc_h; 1319 vc4_state->crtc_w = new_vc4_state->crtc_w; 1320 vc4_state->src_x = new_vc4_state->src_x; 1321 vc4_state->src_y = new_vc4_state->src_y; 1322 memcpy(vc4_state->src_w, new_vc4_state->src_w, 1323 sizeof(vc4_state->src_w)); 1324 memcpy(vc4_state->src_h, new_vc4_state->src_h, 1325 sizeof(vc4_state->src_h)); 1326 memcpy(vc4_state->x_scaling, new_vc4_state->x_scaling, 1327 sizeof(vc4_state->x_scaling)); 1328 memcpy(vc4_state->y_scaling, new_vc4_state->y_scaling, 1329 sizeof(vc4_state->y_scaling)); 1330 vc4_state->is_unity = new_vc4_state->is_unity; 1331 vc4_state->is_yuv = new_vc4_state->is_yuv; 1332 memcpy(vc4_state->offsets, new_vc4_state->offsets, 1333 sizeof(vc4_state->offsets)); 1334 vc4_state->needs_bg_fill = new_vc4_state->needs_bg_fill; 1335 1336 /* Update the current vc4_state pos0, pos2 and ptr0 dlist entries. */ 1337 vc4_state->dlist[vc4_state->pos0_offset] = 1338 new_vc4_state->dlist[vc4_state->pos0_offset]; 1339 vc4_state->dlist[vc4_state->pos2_offset] = 1340 new_vc4_state->dlist[vc4_state->pos2_offset]; 1341 vc4_state->dlist[vc4_state->ptr0_offset] = 1342 new_vc4_state->dlist[vc4_state->ptr0_offset]; 1343 1344 /* Note that we can't just call vc4_plane_write_dlist() 1345 * because that would smash the context data that the HVS is 1346 * currently using. 1347 */ 1348 writel(vc4_state->dlist[vc4_state->pos0_offset], 1349 &vc4_state->hw_dlist[vc4_state->pos0_offset]); 1350 writel(vc4_state->dlist[vc4_state->pos2_offset], 1351 &vc4_state->hw_dlist[vc4_state->pos2_offset]); 1352 writel(vc4_state->dlist[vc4_state->ptr0_offset], 1353 &vc4_state->hw_dlist[vc4_state->ptr0_offset]); 1354 1355 drm_dev_exit(idx); 1356 } 1357 1358 static int vc4_plane_atomic_async_check(struct drm_plane *plane, 1359 struct drm_atomic_state *state) 1360 { 1361 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 1362 plane); 1363 struct vc4_plane_state *old_vc4_state, *new_vc4_state; 1364 int ret; 1365 u32 i; 1366 1367 ret = vc4_plane_mode_set(plane, new_plane_state); 1368 if (ret) 1369 return ret; 1370 1371 old_vc4_state = to_vc4_plane_state(plane->state); 1372 new_vc4_state = to_vc4_plane_state(new_plane_state); 1373 1374 if (!new_vc4_state->hw_dlist) 1375 return -EINVAL; 1376 1377 if (old_vc4_state->dlist_count != new_vc4_state->dlist_count || 1378 old_vc4_state->pos0_offset != new_vc4_state->pos0_offset || 1379 old_vc4_state->pos2_offset != new_vc4_state->pos2_offset || 1380 old_vc4_state->ptr0_offset != new_vc4_state->ptr0_offset || 1381 vc4_lbm_size(plane->state) != vc4_lbm_size(new_plane_state)) 1382 return -EINVAL; 1383 1384 /* Only pos0, pos2 and ptr0 DWORDS can be updated in an async update 1385 * if anything else has changed, fallback to a sync update. 1386 */ 1387 for (i = 0; i < new_vc4_state->dlist_count; i++) { 1388 if (i == new_vc4_state->pos0_offset || 1389 i == new_vc4_state->pos2_offset || 1390 i == new_vc4_state->ptr0_offset || 1391 (new_vc4_state->lbm_offset && 1392 i == new_vc4_state->lbm_offset)) 1393 continue; 1394 1395 if (new_vc4_state->dlist[i] != old_vc4_state->dlist[i]) 1396 return -EINVAL; 1397 } 1398 1399 return 0; 1400 } 1401 1402 static int vc4_prepare_fb(struct drm_plane *plane, 1403 struct drm_plane_state *state) 1404 { 1405 struct vc4_bo *bo; 1406 1407 if (!state->fb) 1408 return 0; 1409 1410 bo = to_vc4_bo(&drm_fb_dma_get_gem_obj(state->fb, 0)->base); 1411 1412 drm_gem_plane_helper_prepare_fb(plane, state); 1413 1414 if (plane->state->fb == state->fb) 1415 return 0; 1416 1417 return vc4_bo_inc_usecnt(bo); 1418 } 1419 1420 static void vc4_cleanup_fb(struct drm_plane *plane, 1421 struct drm_plane_state *state) 1422 { 1423 struct vc4_bo *bo; 1424 1425 if (plane->state->fb == state->fb || !state->fb) 1426 return; 1427 1428 bo = to_vc4_bo(&drm_fb_dma_get_gem_obj(state->fb, 0)->base); 1429 vc4_bo_dec_usecnt(bo); 1430 } 1431 1432 static const struct drm_plane_helper_funcs vc4_plane_helper_funcs = { 1433 .atomic_check = vc4_plane_atomic_check, 1434 .atomic_update = vc4_plane_atomic_update, 1435 .prepare_fb = vc4_prepare_fb, 1436 .cleanup_fb = vc4_cleanup_fb, 1437 .atomic_async_check = vc4_plane_atomic_async_check, 1438 .atomic_async_update = vc4_plane_atomic_async_update, 1439 }; 1440 1441 static const struct drm_plane_helper_funcs vc5_plane_helper_funcs = { 1442 .atomic_check = vc4_plane_atomic_check, 1443 .atomic_update = vc4_plane_atomic_update, 1444 .atomic_async_check = vc4_plane_atomic_async_check, 1445 .atomic_async_update = vc4_plane_atomic_async_update, 1446 }; 1447 1448 static bool vc4_format_mod_supported(struct drm_plane *plane, 1449 uint32_t format, 1450 uint64_t modifier) 1451 { 1452 /* Support T_TILING for RGB formats only. */ 1453 switch (format) { 1454 case DRM_FORMAT_XRGB8888: 1455 case DRM_FORMAT_ARGB8888: 1456 case DRM_FORMAT_ABGR8888: 1457 case DRM_FORMAT_XBGR8888: 1458 case DRM_FORMAT_RGB565: 1459 case DRM_FORMAT_BGR565: 1460 case DRM_FORMAT_ARGB1555: 1461 case DRM_FORMAT_XRGB1555: 1462 switch (fourcc_mod_broadcom_mod(modifier)) { 1463 case DRM_FORMAT_MOD_LINEAR: 1464 case DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED: 1465 return true; 1466 default: 1467 return false; 1468 } 1469 case DRM_FORMAT_NV12: 1470 case DRM_FORMAT_NV21: 1471 switch (fourcc_mod_broadcom_mod(modifier)) { 1472 case DRM_FORMAT_MOD_LINEAR: 1473 case DRM_FORMAT_MOD_BROADCOM_SAND64: 1474 case DRM_FORMAT_MOD_BROADCOM_SAND128: 1475 case DRM_FORMAT_MOD_BROADCOM_SAND256: 1476 return true; 1477 default: 1478 return false; 1479 } 1480 case DRM_FORMAT_P030: 1481 switch (fourcc_mod_broadcom_mod(modifier)) { 1482 case DRM_FORMAT_MOD_BROADCOM_SAND128: 1483 return true; 1484 default: 1485 return false; 1486 } 1487 case DRM_FORMAT_RGBX1010102: 1488 case DRM_FORMAT_BGRX1010102: 1489 case DRM_FORMAT_RGBA1010102: 1490 case DRM_FORMAT_BGRA1010102: 1491 case DRM_FORMAT_YUV422: 1492 case DRM_FORMAT_YVU422: 1493 case DRM_FORMAT_YUV420: 1494 case DRM_FORMAT_YVU420: 1495 case DRM_FORMAT_NV16: 1496 case DRM_FORMAT_NV61: 1497 default: 1498 return (modifier == DRM_FORMAT_MOD_LINEAR); 1499 } 1500 } 1501 1502 static const struct drm_plane_funcs vc4_plane_funcs = { 1503 .update_plane = drm_atomic_helper_update_plane, 1504 .disable_plane = drm_atomic_helper_disable_plane, 1505 .reset = vc4_plane_reset, 1506 .atomic_duplicate_state = vc4_plane_duplicate_state, 1507 .atomic_destroy_state = vc4_plane_destroy_state, 1508 .format_mod_supported = vc4_format_mod_supported, 1509 }; 1510 1511 struct drm_plane *vc4_plane_init(struct drm_device *dev, 1512 enum drm_plane_type type, 1513 uint32_t possible_crtcs) 1514 { 1515 struct vc4_dev *vc4 = to_vc4_dev(dev); 1516 struct drm_plane *plane; 1517 struct vc4_plane *vc4_plane; 1518 u32 formats[ARRAY_SIZE(hvs_formats)]; 1519 int num_formats = 0; 1520 unsigned i; 1521 static const uint64_t modifiers[] = { 1522 DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED, 1523 DRM_FORMAT_MOD_BROADCOM_SAND128, 1524 DRM_FORMAT_MOD_BROADCOM_SAND64, 1525 DRM_FORMAT_MOD_BROADCOM_SAND256, 1526 DRM_FORMAT_MOD_LINEAR, 1527 DRM_FORMAT_MOD_INVALID 1528 }; 1529 1530 for (i = 0; i < ARRAY_SIZE(hvs_formats); i++) { 1531 if (!hvs_formats[i].hvs5_only || vc4->is_vc5) { 1532 formats[num_formats] = hvs_formats[i].drm; 1533 num_formats++; 1534 } 1535 } 1536 1537 vc4_plane = drmm_universal_plane_alloc(dev, struct vc4_plane, base, 1538 possible_crtcs, 1539 &vc4_plane_funcs, 1540 formats, num_formats, 1541 modifiers, type, NULL); 1542 if (IS_ERR(vc4_plane)) 1543 return ERR_CAST(vc4_plane); 1544 plane = &vc4_plane->base; 1545 1546 if (vc4->is_vc5) 1547 drm_plane_helper_add(plane, &vc5_plane_helper_funcs); 1548 else 1549 drm_plane_helper_add(plane, &vc4_plane_helper_funcs); 1550 1551 drm_plane_create_alpha_property(plane); 1552 drm_plane_create_blend_mode_property(plane, 1553 BIT(DRM_MODE_BLEND_PIXEL_NONE) | 1554 BIT(DRM_MODE_BLEND_PREMULTI) | 1555 BIT(DRM_MODE_BLEND_COVERAGE)); 1556 drm_plane_create_rotation_property(plane, DRM_MODE_ROTATE_0, 1557 DRM_MODE_ROTATE_0 | 1558 DRM_MODE_ROTATE_180 | 1559 DRM_MODE_REFLECT_X | 1560 DRM_MODE_REFLECT_Y); 1561 1562 drm_plane_create_color_properties(plane, 1563 BIT(DRM_COLOR_YCBCR_BT601) | 1564 BIT(DRM_COLOR_YCBCR_BT709) | 1565 BIT(DRM_COLOR_YCBCR_BT2020), 1566 BIT(DRM_COLOR_YCBCR_LIMITED_RANGE) | 1567 BIT(DRM_COLOR_YCBCR_FULL_RANGE), 1568 DRM_COLOR_YCBCR_BT709, 1569 DRM_COLOR_YCBCR_LIMITED_RANGE); 1570 1571 return plane; 1572 } 1573 1574 int vc4_plane_create_additional_planes(struct drm_device *drm) 1575 { 1576 struct drm_plane *cursor_plane; 1577 struct drm_crtc *crtc; 1578 unsigned int i; 1579 1580 /* Set up some arbitrary number of planes. We're not limited 1581 * by a set number of physical registers, just the space in 1582 * the HVS (16k) and how small an plane can be (28 bytes). 1583 * However, each plane we set up takes up some memory, and 1584 * increases the cost of looping over planes, which atomic 1585 * modesetting does quite a bit. As a result, we pick a 1586 * modest number of planes to expose, that should hopefully 1587 * still cover any sane usecase. 1588 */ 1589 for (i = 0; i < 16; i++) { 1590 struct drm_plane *plane = 1591 vc4_plane_init(drm, DRM_PLANE_TYPE_OVERLAY, 1592 GENMASK(drm->mode_config.num_crtc - 1, 0)); 1593 1594 if (IS_ERR(plane)) 1595 continue; 1596 } 1597 1598 drm_for_each_crtc(crtc, drm) { 1599 /* Set up the legacy cursor after overlay initialization, 1600 * since we overlay planes on the CRTC in the order they were 1601 * initialized. 1602 */ 1603 cursor_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_CURSOR, 1604 drm_crtc_mask(crtc)); 1605 if (!IS_ERR(cursor_plane)) { 1606 crtc->cursor = cursor_plane; 1607 } 1608 } 1609 1610 return 0; 1611 } 1612