1 /* 2 * Copyright (C) 2015 Broadcom 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 /** 10 * DOC: VC4 plane module 11 * 12 * Each DRM plane is a layer of pixels being scanned out by the HVS. 13 * 14 * At atomic modeset check time, we compute the HVS display element 15 * state that would be necessary for displaying the plane (giving us a 16 * chance to figure out if a plane configuration is invalid), then at 17 * atomic flush time the CRTC will ask us to write our element state 18 * into the region of the HVS that it has allocated for us. 19 */ 20 21 #include <drm/drm_atomic.h> 22 #include <drm/drm_atomic_helper.h> 23 #include <drm/drm_fb_cma_helper.h> 24 #include <drm/drm_plane_helper.h> 25 26 #include "uapi/drm/vc4_drm.h" 27 #include "vc4_drv.h" 28 #include "vc4_regs.h" 29 30 static const struct hvs_format { 31 u32 drm; /* DRM_FORMAT_* */ 32 u32 hvs; /* HVS_FORMAT_* */ 33 u32 pixel_order; 34 } hvs_formats[] = { 35 { 36 .drm = DRM_FORMAT_XRGB8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888, 37 .pixel_order = HVS_PIXEL_ORDER_ABGR, 38 }, 39 { 40 .drm = DRM_FORMAT_ARGB8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888, 41 .pixel_order = HVS_PIXEL_ORDER_ABGR, 42 }, 43 { 44 .drm = DRM_FORMAT_ABGR8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888, 45 .pixel_order = HVS_PIXEL_ORDER_ARGB, 46 }, 47 { 48 .drm = DRM_FORMAT_XBGR8888, .hvs = HVS_PIXEL_FORMAT_RGBA8888, 49 .pixel_order = HVS_PIXEL_ORDER_ARGB, 50 }, 51 { 52 .drm = DRM_FORMAT_RGB565, .hvs = HVS_PIXEL_FORMAT_RGB565, 53 .pixel_order = HVS_PIXEL_ORDER_XRGB, 54 }, 55 { 56 .drm = DRM_FORMAT_BGR565, .hvs = HVS_PIXEL_FORMAT_RGB565, 57 .pixel_order = HVS_PIXEL_ORDER_XBGR, 58 }, 59 { 60 .drm = DRM_FORMAT_ARGB1555, .hvs = HVS_PIXEL_FORMAT_RGBA5551, 61 .pixel_order = HVS_PIXEL_ORDER_ABGR, 62 }, 63 { 64 .drm = DRM_FORMAT_XRGB1555, .hvs = HVS_PIXEL_FORMAT_RGBA5551, 65 .pixel_order = HVS_PIXEL_ORDER_ABGR, 66 }, 67 { 68 .drm = DRM_FORMAT_RGB888, .hvs = HVS_PIXEL_FORMAT_RGB888, 69 .pixel_order = HVS_PIXEL_ORDER_XRGB, 70 }, 71 { 72 .drm = DRM_FORMAT_BGR888, .hvs = HVS_PIXEL_FORMAT_RGB888, 73 .pixel_order = HVS_PIXEL_ORDER_XBGR, 74 }, 75 { 76 .drm = DRM_FORMAT_YUV422, 77 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE, 78 .pixel_order = HVS_PIXEL_ORDER_XYCBCR, 79 }, 80 { 81 .drm = DRM_FORMAT_YVU422, 82 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_3PLANE, 83 .pixel_order = HVS_PIXEL_ORDER_XYCRCB, 84 }, 85 { 86 .drm = DRM_FORMAT_YUV420, 87 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE, 88 .pixel_order = HVS_PIXEL_ORDER_XYCBCR, 89 }, 90 { 91 .drm = DRM_FORMAT_YVU420, 92 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE, 93 .pixel_order = HVS_PIXEL_ORDER_XYCRCB, 94 }, 95 { 96 .drm = DRM_FORMAT_NV12, 97 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE, 98 .pixel_order = HVS_PIXEL_ORDER_XYCBCR, 99 }, 100 { 101 .drm = DRM_FORMAT_NV21, 102 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE, 103 .pixel_order = HVS_PIXEL_ORDER_XYCRCB, 104 }, 105 { 106 .drm = DRM_FORMAT_NV16, 107 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_2PLANE, 108 .pixel_order = HVS_PIXEL_ORDER_XYCBCR, 109 }, 110 { 111 .drm = DRM_FORMAT_NV61, 112 .hvs = HVS_PIXEL_FORMAT_YCBCR_YUV422_2PLANE, 113 .pixel_order = HVS_PIXEL_ORDER_XYCRCB, 114 }, 115 }; 116 117 static const struct hvs_format *vc4_get_hvs_format(u32 drm_format) 118 { 119 unsigned i; 120 121 for (i = 0; i < ARRAY_SIZE(hvs_formats); i++) { 122 if (hvs_formats[i].drm == drm_format) 123 return &hvs_formats[i]; 124 } 125 126 return NULL; 127 } 128 129 static enum vc4_scaling_mode vc4_get_scaling_mode(u32 src, u32 dst) 130 { 131 if (dst > src) 132 return VC4_SCALING_PPF; 133 else if (dst < src) 134 return VC4_SCALING_TPZ; 135 else 136 return VC4_SCALING_NONE; 137 } 138 139 static bool plane_enabled(struct drm_plane_state *state) 140 { 141 return state->fb && state->crtc; 142 } 143 144 static struct drm_plane_state *vc4_plane_duplicate_state(struct drm_plane *plane) 145 { 146 struct vc4_plane_state *vc4_state; 147 148 if (WARN_ON(!plane->state)) 149 return NULL; 150 151 vc4_state = kmemdup(plane->state, sizeof(*vc4_state), GFP_KERNEL); 152 if (!vc4_state) 153 return NULL; 154 155 memset(&vc4_state->lbm, 0, sizeof(vc4_state->lbm)); 156 157 __drm_atomic_helper_plane_duplicate_state(plane, &vc4_state->base); 158 159 if (vc4_state->dlist) { 160 vc4_state->dlist = kmemdup(vc4_state->dlist, 161 vc4_state->dlist_count * 4, 162 GFP_KERNEL); 163 if (!vc4_state->dlist) { 164 kfree(vc4_state); 165 return NULL; 166 } 167 vc4_state->dlist_size = vc4_state->dlist_count; 168 } 169 170 return &vc4_state->base; 171 } 172 173 static void vc4_plane_destroy_state(struct drm_plane *plane, 174 struct drm_plane_state *state) 175 { 176 struct vc4_dev *vc4 = to_vc4_dev(plane->dev); 177 struct vc4_plane_state *vc4_state = to_vc4_plane_state(state); 178 179 if (vc4_state->lbm.allocated) { 180 unsigned long irqflags; 181 182 spin_lock_irqsave(&vc4->hvs->mm_lock, irqflags); 183 drm_mm_remove_node(&vc4_state->lbm); 184 spin_unlock_irqrestore(&vc4->hvs->mm_lock, irqflags); 185 } 186 187 kfree(vc4_state->dlist); 188 __drm_atomic_helper_plane_destroy_state(&vc4_state->base); 189 kfree(state); 190 } 191 192 /* Called during init to allocate the plane's atomic state. */ 193 static void vc4_plane_reset(struct drm_plane *plane) 194 { 195 struct vc4_plane_state *vc4_state; 196 197 WARN_ON(plane->state); 198 199 vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL); 200 if (!vc4_state) 201 return; 202 203 plane->state = &vc4_state->base; 204 plane->state->alpha = DRM_BLEND_ALPHA_OPAQUE; 205 vc4_state->base.plane = plane; 206 } 207 208 static void vc4_dlist_write(struct vc4_plane_state *vc4_state, u32 val) 209 { 210 if (vc4_state->dlist_count == vc4_state->dlist_size) { 211 u32 new_size = max(4u, vc4_state->dlist_count * 2); 212 u32 *new_dlist = kmalloc_array(new_size, 4, GFP_KERNEL); 213 214 if (!new_dlist) 215 return; 216 memcpy(new_dlist, vc4_state->dlist, vc4_state->dlist_count * 4); 217 218 kfree(vc4_state->dlist); 219 vc4_state->dlist = new_dlist; 220 vc4_state->dlist_size = new_size; 221 } 222 223 vc4_state->dlist[vc4_state->dlist_count++] = val; 224 } 225 226 /* Returns the scl0/scl1 field based on whether the dimensions need to 227 * be up/down/non-scaled. 228 * 229 * This is a replication of a table from the spec. 230 */ 231 static u32 vc4_get_scl_field(struct drm_plane_state *state, int plane) 232 { 233 struct vc4_plane_state *vc4_state = to_vc4_plane_state(state); 234 235 switch (vc4_state->x_scaling[plane] << 2 | vc4_state->y_scaling[plane]) { 236 case VC4_SCALING_PPF << 2 | VC4_SCALING_PPF: 237 return SCALER_CTL0_SCL_H_PPF_V_PPF; 238 case VC4_SCALING_TPZ << 2 | VC4_SCALING_PPF: 239 return SCALER_CTL0_SCL_H_TPZ_V_PPF; 240 case VC4_SCALING_PPF << 2 | VC4_SCALING_TPZ: 241 return SCALER_CTL0_SCL_H_PPF_V_TPZ; 242 case VC4_SCALING_TPZ << 2 | VC4_SCALING_TPZ: 243 return SCALER_CTL0_SCL_H_TPZ_V_TPZ; 244 case VC4_SCALING_PPF << 2 | VC4_SCALING_NONE: 245 return SCALER_CTL0_SCL_H_PPF_V_NONE; 246 case VC4_SCALING_NONE << 2 | VC4_SCALING_PPF: 247 return SCALER_CTL0_SCL_H_NONE_V_PPF; 248 case VC4_SCALING_NONE << 2 | VC4_SCALING_TPZ: 249 return SCALER_CTL0_SCL_H_NONE_V_TPZ; 250 case VC4_SCALING_TPZ << 2 | VC4_SCALING_NONE: 251 return SCALER_CTL0_SCL_H_TPZ_V_NONE; 252 default: 253 case VC4_SCALING_NONE << 2 | VC4_SCALING_NONE: 254 /* The unity case is independently handled by 255 * SCALER_CTL0_UNITY. 256 */ 257 return 0; 258 } 259 } 260 261 static int vc4_plane_setup_clipping_and_scaling(struct drm_plane_state *state) 262 { 263 struct drm_plane *plane = state->plane; 264 struct vc4_plane_state *vc4_state = to_vc4_plane_state(state); 265 struct drm_framebuffer *fb = state->fb; 266 struct drm_gem_cma_object *bo = drm_fb_cma_get_gem_obj(fb, 0); 267 u32 subpixel_src_mask = (1 << 16) - 1; 268 u32 format = fb->format->format; 269 int num_planes = fb->format->num_planes; 270 u32 h_subsample = 1; 271 u32 v_subsample = 1; 272 int i; 273 274 for (i = 0; i < num_planes; i++) 275 vc4_state->offsets[i] = bo->paddr + fb->offsets[i]; 276 277 /* We don't support subpixel source positioning for scaling. */ 278 if ((state->src_x & subpixel_src_mask) || 279 (state->src_y & subpixel_src_mask) || 280 (state->src_w & subpixel_src_mask) || 281 (state->src_h & subpixel_src_mask)) { 282 return -EINVAL; 283 } 284 285 vc4_state->src_x = state->src_x >> 16; 286 vc4_state->src_y = state->src_y >> 16; 287 vc4_state->src_w[0] = state->src_w >> 16; 288 vc4_state->src_h[0] = state->src_h >> 16; 289 290 vc4_state->crtc_x = state->crtc_x; 291 vc4_state->crtc_y = state->crtc_y; 292 vc4_state->crtc_w = state->crtc_w; 293 vc4_state->crtc_h = state->crtc_h; 294 295 vc4_state->x_scaling[0] = vc4_get_scaling_mode(vc4_state->src_w[0], 296 vc4_state->crtc_w); 297 vc4_state->y_scaling[0] = vc4_get_scaling_mode(vc4_state->src_h[0], 298 vc4_state->crtc_h); 299 300 if (num_planes > 1) { 301 vc4_state->is_yuv = true; 302 303 h_subsample = drm_format_horz_chroma_subsampling(format); 304 v_subsample = drm_format_vert_chroma_subsampling(format); 305 vc4_state->src_w[1] = vc4_state->src_w[0] / h_subsample; 306 vc4_state->src_h[1] = vc4_state->src_h[0] / v_subsample; 307 308 vc4_state->x_scaling[1] = 309 vc4_get_scaling_mode(vc4_state->src_w[1], 310 vc4_state->crtc_w); 311 vc4_state->y_scaling[1] = 312 vc4_get_scaling_mode(vc4_state->src_h[1], 313 vc4_state->crtc_h); 314 315 /* YUV conversion requires that scaling be enabled, 316 * even on a plane that's otherwise 1:1. Choose TPZ 317 * for simplicity. 318 */ 319 if (vc4_state->x_scaling[0] == VC4_SCALING_NONE) 320 vc4_state->x_scaling[0] = VC4_SCALING_TPZ; 321 if (vc4_state->y_scaling[0] == VC4_SCALING_NONE) 322 vc4_state->y_scaling[0] = VC4_SCALING_TPZ; 323 } 324 325 vc4_state->is_unity = (vc4_state->x_scaling[0] == VC4_SCALING_NONE && 326 vc4_state->y_scaling[0] == VC4_SCALING_NONE && 327 vc4_state->x_scaling[1] == VC4_SCALING_NONE && 328 vc4_state->y_scaling[1] == VC4_SCALING_NONE); 329 330 /* No configuring scaling on the cursor plane, since it gets 331 non-vblank-synced updates, and scaling requires requires 332 LBM changes which have to be vblank-synced. 333 */ 334 if (plane->type == DRM_PLANE_TYPE_CURSOR && !vc4_state->is_unity) 335 return -EINVAL; 336 337 /* Clamp the on-screen start x/y to 0. The hardware doesn't 338 * support negative y, and negative x wastes bandwidth. 339 */ 340 if (vc4_state->crtc_x < 0) { 341 for (i = 0; i < num_planes; i++) { 342 u32 cpp = fb->format->cpp[i]; 343 u32 subs = ((i == 0) ? 1 : h_subsample); 344 345 vc4_state->offsets[i] += (cpp * 346 (-vc4_state->crtc_x) / subs); 347 } 348 vc4_state->src_w[0] += vc4_state->crtc_x; 349 vc4_state->src_w[1] += vc4_state->crtc_x / h_subsample; 350 vc4_state->crtc_x = 0; 351 } 352 353 if (vc4_state->crtc_y < 0) { 354 for (i = 0; i < num_planes; i++) { 355 u32 subs = ((i == 0) ? 1 : v_subsample); 356 357 vc4_state->offsets[i] += (fb->pitches[i] * 358 (-vc4_state->crtc_y) / subs); 359 } 360 vc4_state->src_h[0] += vc4_state->crtc_y; 361 vc4_state->src_h[1] += vc4_state->crtc_y / v_subsample; 362 vc4_state->crtc_y = 0; 363 } 364 365 return 0; 366 } 367 368 static void vc4_write_tpz(struct vc4_plane_state *vc4_state, u32 src, u32 dst) 369 { 370 u32 scale, recip; 371 372 scale = (1 << 16) * src / dst; 373 374 /* The specs note that while the reciprocal would be defined 375 * as (1<<32)/scale, ~0 is close enough. 376 */ 377 recip = ~0 / scale; 378 379 vc4_dlist_write(vc4_state, 380 VC4_SET_FIELD(scale, SCALER_TPZ0_SCALE) | 381 VC4_SET_FIELD(0, SCALER_TPZ0_IPHASE)); 382 vc4_dlist_write(vc4_state, 383 VC4_SET_FIELD(recip, SCALER_TPZ1_RECIP)); 384 } 385 386 static void vc4_write_ppf(struct vc4_plane_state *vc4_state, u32 src, u32 dst) 387 { 388 u32 scale = (1 << 16) * src / dst; 389 390 vc4_dlist_write(vc4_state, 391 SCALER_PPF_AGC | 392 VC4_SET_FIELD(scale, SCALER_PPF_SCALE) | 393 VC4_SET_FIELD(0, SCALER_PPF_IPHASE)); 394 } 395 396 static u32 vc4_lbm_size(struct drm_plane_state *state) 397 { 398 struct vc4_plane_state *vc4_state = to_vc4_plane_state(state); 399 /* This is the worst case number. One of the two sizes will 400 * be used depending on the scaling configuration. 401 */ 402 u32 pix_per_line = max(vc4_state->src_w[0], (u32)vc4_state->crtc_w); 403 u32 lbm; 404 405 if (!vc4_state->is_yuv) { 406 if (vc4_state->is_unity) 407 return 0; 408 else if (vc4_state->y_scaling[0] == VC4_SCALING_TPZ) 409 lbm = pix_per_line * 8; 410 else { 411 /* In special cases, this multiplier might be 12. */ 412 lbm = pix_per_line * 16; 413 } 414 } else { 415 /* There are cases for this going down to a multiplier 416 * of 2, but according to the firmware source, the 417 * table in the docs is somewhat wrong. 418 */ 419 lbm = pix_per_line * 16; 420 } 421 422 lbm = roundup(lbm, 32); 423 424 return lbm; 425 } 426 427 static void vc4_write_scaling_parameters(struct drm_plane_state *state, 428 int channel) 429 { 430 struct vc4_plane_state *vc4_state = to_vc4_plane_state(state); 431 432 /* Ch0 H-PPF Word 0: Scaling Parameters */ 433 if (vc4_state->x_scaling[channel] == VC4_SCALING_PPF) { 434 vc4_write_ppf(vc4_state, 435 vc4_state->src_w[channel], vc4_state->crtc_w); 436 } 437 438 /* Ch0 V-PPF Words 0-1: Scaling Parameters, Context */ 439 if (vc4_state->y_scaling[channel] == VC4_SCALING_PPF) { 440 vc4_write_ppf(vc4_state, 441 vc4_state->src_h[channel], vc4_state->crtc_h); 442 vc4_dlist_write(vc4_state, 0xc0c0c0c0); 443 } 444 445 /* Ch0 H-TPZ Words 0-1: Scaling Parameters, Recip */ 446 if (vc4_state->x_scaling[channel] == VC4_SCALING_TPZ) { 447 vc4_write_tpz(vc4_state, 448 vc4_state->src_w[channel], vc4_state->crtc_w); 449 } 450 451 /* Ch0 V-TPZ Words 0-2: Scaling Parameters, Recip, Context */ 452 if (vc4_state->y_scaling[channel] == VC4_SCALING_TPZ) { 453 vc4_write_tpz(vc4_state, 454 vc4_state->src_h[channel], vc4_state->crtc_h); 455 vc4_dlist_write(vc4_state, 0xc0c0c0c0); 456 } 457 } 458 459 /* Writes out a full display list for an active plane to the plane's 460 * private dlist state. 461 */ 462 static int vc4_plane_mode_set(struct drm_plane *plane, 463 struct drm_plane_state *state) 464 { 465 struct vc4_dev *vc4 = to_vc4_dev(plane->dev); 466 struct vc4_plane_state *vc4_state = to_vc4_plane_state(state); 467 struct drm_framebuffer *fb = state->fb; 468 u32 ctl0_offset = vc4_state->dlist_count; 469 const struct hvs_format *format = vc4_get_hvs_format(fb->format->format); 470 u64 base_format_mod = fourcc_mod_broadcom_mod(fb->modifier); 471 int num_planes = drm_format_num_planes(format->drm); 472 bool mix_plane_alpha; 473 bool covers_screen; 474 u32 scl0, scl1, pitch0; 475 u32 lbm_size, tiling; 476 unsigned long irqflags; 477 u32 hvs_format = format->hvs; 478 int ret, i; 479 480 ret = vc4_plane_setup_clipping_and_scaling(state); 481 if (ret) 482 return ret; 483 484 /* Allocate the LBM memory that the HVS will use for temporary 485 * storage due to our scaling/format conversion. 486 */ 487 lbm_size = vc4_lbm_size(state); 488 if (lbm_size) { 489 if (!vc4_state->lbm.allocated) { 490 spin_lock_irqsave(&vc4->hvs->mm_lock, irqflags); 491 ret = drm_mm_insert_node_generic(&vc4->hvs->lbm_mm, 492 &vc4_state->lbm, 493 lbm_size, 32, 0, 0); 494 spin_unlock_irqrestore(&vc4->hvs->mm_lock, irqflags); 495 } else { 496 WARN_ON_ONCE(lbm_size != vc4_state->lbm.size); 497 } 498 } 499 500 if (ret) 501 return ret; 502 503 /* SCL1 is used for Cb/Cr scaling of planar formats. For RGB 504 * and 4:4:4, scl1 should be set to scl0 so both channels of 505 * the scaler do the same thing. For YUV, the Y plane needs 506 * to be put in channel 1 and Cb/Cr in channel 0, so we swap 507 * the scl fields here. 508 */ 509 if (num_planes == 1) { 510 scl0 = vc4_get_scl_field(state, 0); 511 scl1 = scl0; 512 } else { 513 scl0 = vc4_get_scl_field(state, 1); 514 scl1 = vc4_get_scl_field(state, 0); 515 } 516 517 switch (base_format_mod) { 518 case DRM_FORMAT_MOD_LINEAR: 519 tiling = SCALER_CTL0_TILING_LINEAR; 520 pitch0 = VC4_SET_FIELD(fb->pitches[0], SCALER_SRC_PITCH); 521 break; 522 523 case DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED: { 524 /* For T-tiled, the FB pitch is "how many bytes from 525 * one row to the next, such that pitch * tile_h == 526 * tile_size * tiles_per_row." 527 */ 528 u32 tile_size_shift = 12; /* T tiles are 4kb */ 529 u32 tile_h_shift = 5; /* 16 and 32bpp are 32 pixels high */ 530 u32 tiles_w = fb->pitches[0] >> (tile_size_shift - tile_h_shift); 531 532 tiling = SCALER_CTL0_TILING_256B_OR_T; 533 534 pitch0 = (VC4_SET_FIELD(0, SCALER_PITCH0_TILE_Y_OFFSET) | 535 VC4_SET_FIELD(0, SCALER_PITCH0_TILE_WIDTH_L) | 536 VC4_SET_FIELD(tiles_w, SCALER_PITCH0_TILE_WIDTH_R)); 537 break; 538 } 539 540 case DRM_FORMAT_MOD_BROADCOM_SAND64: 541 case DRM_FORMAT_MOD_BROADCOM_SAND128: 542 case DRM_FORMAT_MOD_BROADCOM_SAND256: { 543 uint32_t param = fourcc_mod_broadcom_param(fb->modifier); 544 545 /* Column-based NV12 or RGBA. 546 */ 547 if (fb->format->num_planes > 1) { 548 if (hvs_format != HVS_PIXEL_FORMAT_YCBCR_YUV420_2PLANE) { 549 DRM_DEBUG_KMS("SAND format only valid for NV12/21"); 550 return -EINVAL; 551 } 552 hvs_format = HVS_PIXEL_FORMAT_H264; 553 } else { 554 if (base_format_mod == DRM_FORMAT_MOD_BROADCOM_SAND256) { 555 DRM_DEBUG_KMS("SAND256 format only valid for H.264"); 556 return -EINVAL; 557 } 558 } 559 560 switch (base_format_mod) { 561 case DRM_FORMAT_MOD_BROADCOM_SAND64: 562 tiling = SCALER_CTL0_TILING_64B; 563 break; 564 case DRM_FORMAT_MOD_BROADCOM_SAND128: 565 tiling = SCALER_CTL0_TILING_128B; 566 break; 567 case DRM_FORMAT_MOD_BROADCOM_SAND256: 568 tiling = SCALER_CTL0_TILING_256B_OR_T; 569 break; 570 default: 571 break; 572 } 573 574 if (param > SCALER_TILE_HEIGHT_MASK) { 575 DRM_DEBUG_KMS("SAND height too large (%d)\n", param); 576 return -EINVAL; 577 } 578 579 pitch0 = VC4_SET_FIELD(param, SCALER_TILE_HEIGHT); 580 break; 581 } 582 583 default: 584 DRM_DEBUG_KMS("Unsupported FB tiling flag 0x%16llx", 585 (long long)fb->modifier); 586 return -EINVAL; 587 } 588 589 /* Control word */ 590 vc4_dlist_write(vc4_state, 591 SCALER_CTL0_VALID | 592 VC4_SET_FIELD(SCALER_CTL0_RGBA_EXPAND_ROUND, SCALER_CTL0_RGBA_EXPAND) | 593 (format->pixel_order << SCALER_CTL0_ORDER_SHIFT) | 594 (hvs_format << SCALER_CTL0_PIXEL_FORMAT_SHIFT) | 595 VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) | 596 (vc4_state->is_unity ? SCALER_CTL0_UNITY : 0) | 597 VC4_SET_FIELD(scl0, SCALER_CTL0_SCL0) | 598 VC4_SET_FIELD(scl1, SCALER_CTL0_SCL1)); 599 600 /* Position Word 0: Image Positions and Alpha Value */ 601 vc4_state->pos0_offset = vc4_state->dlist_count; 602 vc4_dlist_write(vc4_state, 603 VC4_SET_FIELD(state->alpha >> 8, SCALER_POS0_FIXED_ALPHA) | 604 VC4_SET_FIELD(vc4_state->crtc_x, SCALER_POS0_START_X) | 605 VC4_SET_FIELD(vc4_state->crtc_y, SCALER_POS0_START_Y)); 606 607 /* Position Word 1: Scaled Image Dimensions. */ 608 if (!vc4_state->is_unity) { 609 vc4_dlist_write(vc4_state, 610 VC4_SET_FIELD(vc4_state->crtc_w, 611 SCALER_POS1_SCL_WIDTH) | 612 VC4_SET_FIELD(vc4_state->crtc_h, 613 SCALER_POS1_SCL_HEIGHT)); 614 } 615 616 /* Don't waste cycles mixing with plane alpha if the set alpha 617 * is opaque or there is no per-pixel alpha information. 618 * In any case we use the alpha property value as the fixed alpha. 619 */ 620 mix_plane_alpha = state->alpha != DRM_BLEND_ALPHA_OPAQUE && 621 fb->format->has_alpha; 622 623 /* Position Word 2: Source Image Size, Alpha */ 624 vc4_state->pos2_offset = vc4_state->dlist_count; 625 vc4_dlist_write(vc4_state, 626 VC4_SET_FIELD(fb->format->has_alpha ? 627 SCALER_POS2_ALPHA_MODE_PIPELINE : 628 SCALER_POS2_ALPHA_MODE_FIXED, 629 SCALER_POS2_ALPHA_MODE) | 630 (mix_plane_alpha ? SCALER_POS2_ALPHA_MIX : 0) | 631 (fb->format->has_alpha ? SCALER_POS2_ALPHA_PREMULT : 0) | 632 VC4_SET_FIELD(vc4_state->src_w[0], SCALER_POS2_WIDTH) | 633 VC4_SET_FIELD(vc4_state->src_h[0], SCALER_POS2_HEIGHT)); 634 635 /* Position Word 3: Context. Written by the HVS. */ 636 vc4_dlist_write(vc4_state, 0xc0c0c0c0); 637 638 639 /* Pointer Word 0/1/2: RGB / Y / Cb / Cr Pointers 640 * 641 * The pointers may be any byte address. 642 */ 643 vc4_state->ptr0_offset = vc4_state->dlist_count; 644 for (i = 0; i < num_planes; i++) 645 vc4_dlist_write(vc4_state, vc4_state->offsets[i]); 646 647 /* Pointer Context Word 0/1/2: Written by the HVS */ 648 for (i = 0; i < num_planes; i++) 649 vc4_dlist_write(vc4_state, 0xc0c0c0c0); 650 651 /* Pitch word 0 */ 652 vc4_dlist_write(vc4_state, pitch0); 653 654 /* Pitch word 1/2 */ 655 for (i = 1; i < num_planes; i++) { 656 if (hvs_format != HVS_PIXEL_FORMAT_H264) { 657 vc4_dlist_write(vc4_state, 658 VC4_SET_FIELD(fb->pitches[i], 659 SCALER_SRC_PITCH)); 660 } else { 661 vc4_dlist_write(vc4_state, pitch0); 662 } 663 } 664 665 /* Colorspace conversion words */ 666 if (vc4_state->is_yuv) { 667 vc4_dlist_write(vc4_state, SCALER_CSC0_ITR_R_601_5); 668 vc4_dlist_write(vc4_state, SCALER_CSC1_ITR_R_601_5); 669 vc4_dlist_write(vc4_state, SCALER_CSC2_ITR_R_601_5); 670 } 671 672 if (!vc4_state->is_unity) { 673 /* LBM Base Address. */ 674 if (vc4_state->y_scaling[0] != VC4_SCALING_NONE || 675 vc4_state->y_scaling[1] != VC4_SCALING_NONE) { 676 vc4_dlist_write(vc4_state, vc4_state->lbm.start); 677 } 678 679 if (num_planes > 1) { 680 /* Emit Cb/Cr as channel 0 and Y as channel 681 * 1. This matches how we set up scl0/scl1 682 * above. 683 */ 684 vc4_write_scaling_parameters(state, 1); 685 } 686 vc4_write_scaling_parameters(state, 0); 687 688 /* If any PPF setup was done, then all the kernel 689 * pointers get uploaded. 690 */ 691 if (vc4_state->x_scaling[0] == VC4_SCALING_PPF || 692 vc4_state->y_scaling[0] == VC4_SCALING_PPF || 693 vc4_state->x_scaling[1] == VC4_SCALING_PPF || 694 vc4_state->y_scaling[1] == VC4_SCALING_PPF) { 695 u32 kernel = VC4_SET_FIELD(vc4->hvs->mitchell_netravali_filter.start, 696 SCALER_PPF_KERNEL_OFFSET); 697 698 /* HPPF plane 0 */ 699 vc4_dlist_write(vc4_state, kernel); 700 /* VPPF plane 0 */ 701 vc4_dlist_write(vc4_state, kernel); 702 /* HPPF plane 1 */ 703 vc4_dlist_write(vc4_state, kernel); 704 /* VPPF plane 1 */ 705 vc4_dlist_write(vc4_state, kernel); 706 } 707 } 708 709 vc4_state->dlist[ctl0_offset] |= 710 VC4_SET_FIELD(vc4_state->dlist_count, SCALER_CTL0_SIZE); 711 712 /* crtc_* are already clipped coordinates. */ 713 covers_screen = vc4_state->crtc_x == 0 && vc4_state->crtc_y == 0 && 714 vc4_state->crtc_w == state->crtc->mode.hdisplay && 715 vc4_state->crtc_h == state->crtc->mode.vdisplay; 716 /* Background fill might be necessary when the plane has per-pixel 717 * alpha content or a non-opaque plane alpha and could blend from the 718 * background or does not cover the entire screen. 719 */ 720 vc4_state->needs_bg_fill = fb->format->has_alpha || !covers_screen || 721 state->alpha != DRM_BLEND_ALPHA_OPAQUE; 722 723 return 0; 724 } 725 726 /* If a modeset involves changing the setup of a plane, the atomic 727 * infrastructure will call this to validate a proposed plane setup. 728 * However, if a plane isn't getting updated, this (and the 729 * corresponding vc4_plane_atomic_update) won't get called. Thus, we 730 * compute the dlist here and have all active plane dlists get updated 731 * in the CRTC's flush. 732 */ 733 static int vc4_plane_atomic_check(struct drm_plane *plane, 734 struct drm_plane_state *state) 735 { 736 struct vc4_plane_state *vc4_state = to_vc4_plane_state(state); 737 738 vc4_state->dlist_count = 0; 739 740 if (plane_enabled(state)) 741 return vc4_plane_mode_set(plane, state); 742 else 743 return 0; 744 } 745 746 static void vc4_plane_atomic_update(struct drm_plane *plane, 747 struct drm_plane_state *old_state) 748 { 749 /* No contents here. Since we don't know where in the CRTC's 750 * dlist we should be stored, our dlist is uploaded to the 751 * hardware with vc4_plane_write_dlist() at CRTC atomic_flush 752 * time. 753 */ 754 } 755 756 u32 vc4_plane_write_dlist(struct drm_plane *plane, u32 __iomem *dlist) 757 { 758 struct vc4_plane_state *vc4_state = to_vc4_plane_state(plane->state); 759 int i; 760 761 vc4_state->hw_dlist = dlist; 762 763 /* Can't memcpy_toio() because it needs to be 32-bit writes. */ 764 for (i = 0; i < vc4_state->dlist_count; i++) 765 writel(vc4_state->dlist[i], &dlist[i]); 766 767 return vc4_state->dlist_count; 768 } 769 770 u32 vc4_plane_dlist_size(const struct drm_plane_state *state) 771 { 772 const struct vc4_plane_state *vc4_state = 773 container_of(state, typeof(*vc4_state), base); 774 775 return vc4_state->dlist_count; 776 } 777 778 /* Updates the plane to immediately (well, once the FIFO needs 779 * refilling) scan out from at a new framebuffer. 780 */ 781 void vc4_plane_async_set_fb(struct drm_plane *plane, struct drm_framebuffer *fb) 782 { 783 struct vc4_plane_state *vc4_state = to_vc4_plane_state(plane->state); 784 struct drm_gem_cma_object *bo = drm_fb_cma_get_gem_obj(fb, 0); 785 uint32_t addr; 786 787 /* We're skipping the address adjustment for negative origin, 788 * because this is only called on the primary plane. 789 */ 790 WARN_ON_ONCE(plane->state->crtc_x < 0 || plane->state->crtc_y < 0); 791 addr = bo->paddr + fb->offsets[0]; 792 793 /* Write the new address into the hardware immediately. The 794 * scanout will start from this address as soon as the FIFO 795 * needs to refill with pixels. 796 */ 797 writel(addr, &vc4_state->hw_dlist[vc4_state->ptr0_offset]); 798 799 /* Also update the CPU-side dlist copy, so that any later 800 * atomic updates that don't do a new modeset on our plane 801 * also use our updated address. 802 */ 803 vc4_state->dlist[vc4_state->ptr0_offset] = addr; 804 } 805 806 static void vc4_plane_atomic_async_update(struct drm_plane *plane, 807 struct drm_plane_state *state) 808 { 809 struct vc4_plane_state *vc4_state = to_vc4_plane_state(plane->state); 810 811 if (plane->state->fb != state->fb) { 812 vc4_plane_async_set_fb(plane, state->fb); 813 drm_atomic_set_fb_for_plane(plane->state, state->fb); 814 } 815 816 /* Set the cursor's position on the screen. This is the 817 * expected change from the drm_mode_cursor_universal() 818 * helper. 819 */ 820 plane->state->crtc_x = state->crtc_x; 821 plane->state->crtc_y = state->crtc_y; 822 823 /* Allow changing the start position within the cursor BO, if 824 * that matters. 825 */ 826 plane->state->src_x = state->src_x; 827 plane->state->src_y = state->src_y; 828 829 /* Update the display list based on the new crtc_x/y. */ 830 vc4_plane_atomic_check(plane, plane->state); 831 832 /* Note that we can't just call vc4_plane_write_dlist() 833 * because that would smash the context data that the HVS is 834 * currently using. 835 */ 836 writel(vc4_state->dlist[vc4_state->pos0_offset], 837 &vc4_state->hw_dlist[vc4_state->pos0_offset]); 838 writel(vc4_state->dlist[vc4_state->pos2_offset], 839 &vc4_state->hw_dlist[vc4_state->pos2_offset]); 840 writel(vc4_state->dlist[vc4_state->ptr0_offset], 841 &vc4_state->hw_dlist[vc4_state->ptr0_offset]); 842 } 843 844 static int vc4_plane_atomic_async_check(struct drm_plane *plane, 845 struct drm_plane_state *state) 846 { 847 /* No configuring new scaling in the fast path. */ 848 if (plane->state->crtc_w != state->crtc_w || 849 plane->state->crtc_h != state->crtc_h || 850 plane->state->src_w != state->src_w || 851 plane->state->src_h != state->src_h) 852 return -EINVAL; 853 854 return 0; 855 } 856 857 static int vc4_prepare_fb(struct drm_plane *plane, 858 struct drm_plane_state *state) 859 { 860 struct vc4_bo *bo; 861 struct dma_fence *fence; 862 int ret; 863 864 if (!state->fb) 865 return 0; 866 867 bo = to_vc4_bo(&drm_fb_cma_get_gem_obj(state->fb, 0)->base); 868 869 fence = reservation_object_get_excl_rcu(bo->resv); 870 drm_atomic_set_fence_for_plane(state, fence); 871 872 if (plane->state->fb == state->fb) 873 return 0; 874 875 ret = vc4_bo_inc_usecnt(bo); 876 if (ret) 877 return ret; 878 879 return 0; 880 } 881 882 static void vc4_cleanup_fb(struct drm_plane *plane, 883 struct drm_plane_state *state) 884 { 885 struct vc4_bo *bo; 886 887 if (plane->state->fb == state->fb || !state->fb) 888 return; 889 890 bo = to_vc4_bo(&drm_fb_cma_get_gem_obj(state->fb, 0)->base); 891 vc4_bo_dec_usecnt(bo); 892 } 893 894 static const struct drm_plane_helper_funcs vc4_plane_helper_funcs = { 895 .atomic_check = vc4_plane_atomic_check, 896 .atomic_update = vc4_plane_atomic_update, 897 .prepare_fb = vc4_prepare_fb, 898 .cleanup_fb = vc4_cleanup_fb, 899 .atomic_async_check = vc4_plane_atomic_async_check, 900 .atomic_async_update = vc4_plane_atomic_async_update, 901 }; 902 903 static void vc4_plane_destroy(struct drm_plane *plane) 904 { 905 drm_plane_helper_disable(plane, NULL); 906 drm_plane_cleanup(plane); 907 } 908 909 static bool vc4_format_mod_supported(struct drm_plane *plane, 910 uint32_t format, 911 uint64_t modifier) 912 { 913 /* Support T_TILING for RGB formats only. */ 914 switch (format) { 915 case DRM_FORMAT_XRGB8888: 916 case DRM_FORMAT_ARGB8888: 917 case DRM_FORMAT_ABGR8888: 918 case DRM_FORMAT_XBGR8888: 919 case DRM_FORMAT_RGB565: 920 case DRM_FORMAT_BGR565: 921 case DRM_FORMAT_ARGB1555: 922 case DRM_FORMAT_XRGB1555: 923 switch (fourcc_mod_broadcom_mod(modifier)) { 924 case DRM_FORMAT_MOD_LINEAR: 925 case DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED: 926 case DRM_FORMAT_MOD_BROADCOM_SAND64: 927 case DRM_FORMAT_MOD_BROADCOM_SAND128: 928 return true; 929 default: 930 return false; 931 } 932 case DRM_FORMAT_NV12: 933 case DRM_FORMAT_NV21: 934 switch (fourcc_mod_broadcom_mod(modifier)) { 935 case DRM_FORMAT_MOD_LINEAR: 936 case DRM_FORMAT_MOD_BROADCOM_SAND64: 937 case DRM_FORMAT_MOD_BROADCOM_SAND128: 938 case DRM_FORMAT_MOD_BROADCOM_SAND256: 939 return true; 940 default: 941 return false; 942 } 943 case DRM_FORMAT_YUV422: 944 case DRM_FORMAT_YVU422: 945 case DRM_FORMAT_YUV420: 946 case DRM_FORMAT_YVU420: 947 case DRM_FORMAT_NV16: 948 case DRM_FORMAT_NV61: 949 default: 950 return (modifier == DRM_FORMAT_MOD_LINEAR); 951 } 952 } 953 954 static const struct drm_plane_funcs vc4_plane_funcs = { 955 .update_plane = drm_atomic_helper_update_plane, 956 .disable_plane = drm_atomic_helper_disable_plane, 957 .destroy = vc4_plane_destroy, 958 .set_property = NULL, 959 .reset = vc4_plane_reset, 960 .atomic_duplicate_state = vc4_plane_duplicate_state, 961 .atomic_destroy_state = vc4_plane_destroy_state, 962 .format_mod_supported = vc4_format_mod_supported, 963 }; 964 965 struct drm_plane *vc4_plane_init(struct drm_device *dev, 966 enum drm_plane_type type) 967 { 968 struct drm_plane *plane = NULL; 969 struct vc4_plane *vc4_plane; 970 u32 formats[ARRAY_SIZE(hvs_formats)]; 971 u32 num_formats = 0; 972 int ret = 0; 973 unsigned i; 974 static const uint64_t modifiers[] = { 975 DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED, 976 DRM_FORMAT_MOD_BROADCOM_SAND128, 977 DRM_FORMAT_MOD_BROADCOM_SAND64, 978 DRM_FORMAT_MOD_BROADCOM_SAND256, 979 DRM_FORMAT_MOD_LINEAR, 980 DRM_FORMAT_MOD_INVALID 981 }; 982 983 vc4_plane = devm_kzalloc(dev->dev, sizeof(*vc4_plane), 984 GFP_KERNEL); 985 if (!vc4_plane) 986 return ERR_PTR(-ENOMEM); 987 988 for (i = 0; i < ARRAY_SIZE(hvs_formats); i++) { 989 /* Don't allow YUV in cursor planes, since that means 990 * tuning on the scaler, which we don't allow for the 991 * cursor. 992 */ 993 if (type != DRM_PLANE_TYPE_CURSOR || 994 hvs_formats[i].hvs < HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE) { 995 formats[num_formats++] = hvs_formats[i].drm; 996 } 997 } 998 plane = &vc4_plane->base; 999 ret = drm_universal_plane_init(dev, plane, 0, 1000 &vc4_plane_funcs, 1001 formats, num_formats, 1002 modifiers, type, NULL); 1003 1004 drm_plane_helper_add(plane, &vc4_plane_helper_funcs); 1005 1006 drm_plane_create_alpha_property(plane); 1007 1008 return plane; 1009 } 1010