1d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2c8b75bcaSEric Anholt /* 3c8b75bcaSEric Anholt * Copyright (C) 2015 Broadcom 4c8b75bcaSEric Anholt */ 5c8b75bcaSEric Anholt 6c8b75bcaSEric Anholt /** 7c8b75bcaSEric Anholt * DOC: VC4 KMS 8c8b75bcaSEric Anholt * 9c8b75bcaSEric Anholt * This is the general code for implementing KMS mode setting that 10c8b75bcaSEric Anholt * doesn't clearly associate with any of the other objects (plane, 11c8b75bcaSEric Anholt * crtc, HDMI encoder). 12c8b75bcaSEric Anholt */ 13c8b75bcaSEric Anholt 14d7d96c00SMaxime Ripard #include <linux/clk.h> 15d7d96c00SMaxime Ripard 16b7e8e25bSMasahiro Yamada #include <drm/drm_atomic.h> 17b7e8e25bSMasahiro Yamada #include <drm/drm_atomic_helper.h> 18fd6d6d80SSam Ravnborg #include <drm/drm_crtc.h> 199762477cSNoralf Trønnes #include <drm/drm_gem_framebuffer_helper.h> 20fcd70cd3SDaniel Vetter #include <drm/drm_plane_helper.h> 21fcd70cd3SDaniel Vetter #include <drm/drm_probe_helper.h> 22fd6d6d80SSam Ravnborg #include <drm/drm_vblank.h> 23fd6d6d80SSam Ravnborg 24c8b75bcaSEric Anholt #include "vc4_drv.h" 25766cc6b1SStefan Schake #include "vc4_regs.h" 26766cc6b1SStefan Schake 27a9661f27SMaxime Ripard #define HVS_NUM_CHANNELS 3 28a9661f27SMaxime Ripard 29766cc6b1SStefan Schake struct vc4_ctm_state { 30766cc6b1SStefan Schake struct drm_private_state base; 31766cc6b1SStefan Schake struct drm_color_ctm *ctm; 32766cc6b1SStefan Schake int fifo; 33766cc6b1SStefan Schake }; 34766cc6b1SStefan Schake 35766cc6b1SStefan Schake static struct vc4_ctm_state *to_vc4_ctm_state(struct drm_private_state *priv) 36766cc6b1SStefan Schake { 37766cc6b1SStefan Schake return container_of(priv, struct vc4_ctm_state, base); 38766cc6b1SStefan Schake } 39766cc6b1SStefan Schake 40f2df84e0SMaxime Ripard struct vc4_hvs_state { 41f2df84e0SMaxime Ripard struct drm_private_state base; 4216e10105SMaxime Ripard unsigned long core_clock_rate; 439ec03d7fSMaxime Ripard 449ec03d7fSMaxime Ripard struct { 459ec03d7fSMaxime Ripard unsigned in_use: 1; 4616e10105SMaxime Ripard unsigned long fifo_load; 479ec03d7fSMaxime Ripard struct drm_crtc_commit *pending_commit; 489ec03d7fSMaxime Ripard } fifo_state[HVS_NUM_CHANNELS]; 49f2df84e0SMaxime Ripard }; 50f2df84e0SMaxime Ripard 51f2df84e0SMaxime Ripard static struct vc4_hvs_state * 52f2df84e0SMaxime Ripard to_vc4_hvs_state(struct drm_private_state *priv) 53f2df84e0SMaxime Ripard { 54f2df84e0SMaxime Ripard return container_of(priv, struct vc4_hvs_state, base); 55f2df84e0SMaxime Ripard } 56f2df84e0SMaxime Ripard 574686da83SBoris Brezillon struct vc4_load_tracker_state { 584686da83SBoris Brezillon struct drm_private_state base; 594686da83SBoris Brezillon u64 hvs_load; 604686da83SBoris Brezillon u64 membus_load; 614686da83SBoris Brezillon }; 624686da83SBoris Brezillon 634686da83SBoris Brezillon static struct vc4_load_tracker_state * 644686da83SBoris Brezillon to_vc4_load_tracker_state(struct drm_private_state *priv) 654686da83SBoris Brezillon { 664686da83SBoris Brezillon return container_of(priv, struct vc4_load_tracker_state, base); 674686da83SBoris Brezillon } 684686da83SBoris Brezillon 69766cc6b1SStefan Schake static struct vc4_ctm_state *vc4_get_ctm_state(struct drm_atomic_state *state, 70766cc6b1SStefan Schake struct drm_private_obj *manager) 71766cc6b1SStefan Schake { 72766cc6b1SStefan Schake struct drm_device *dev = state->dev; 7388e08589SMaxime Ripard struct vc4_dev *vc4 = to_vc4_dev(dev); 74766cc6b1SStefan Schake struct drm_private_state *priv_state; 75766cc6b1SStefan Schake int ret; 76766cc6b1SStefan Schake 77766cc6b1SStefan Schake ret = drm_modeset_lock(&vc4->ctm_state_lock, state->acquire_ctx); 78766cc6b1SStefan Schake if (ret) 79766cc6b1SStefan Schake return ERR_PTR(ret); 80766cc6b1SStefan Schake 81766cc6b1SStefan Schake priv_state = drm_atomic_get_private_obj_state(state, manager); 82766cc6b1SStefan Schake if (IS_ERR(priv_state)) 83766cc6b1SStefan Schake return ERR_CAST(priv_state); 84766cc6b1SStefan Schake 85766cc6b1SStefan Schake return to_vc4_ctm_state(priv_state); 86766cc6b1SStefan Schake } 87766cc6b1SStefan Schake 88766cc6b1SStefan Schake static struct drm_private_state * 89766cc6b1SStefan Schake vc4_ctm_duplicate_state(struct drm_private_obj *obj) 90766cc6b1SStefan Schake { 91766cc6b1SStefan Schake struct vc4_ctm_state *state; 92766cc6b1SStefan Schake 93766cc6b1SStefan Schake state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL); 94766cc6b1SStefan Schake if (!state) 95766cc6b1SStefan Schake return NULL; 96766cc6b1SStefan Schake 97766cc6b1SStefan Schake __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base); 98766cc6b1SStefan Schake 99766cc6b1SStefan Schake return &state->base; 100766cc6b1SStefan Schake } 101766cc6b1SStefan Schake 102766cc6b1SStefan Schake static void vc4_ctm_destroy_state(struct drm_private_obj *obj, 103766cc6b1SStefan Schake struct drm_private_state *state) 104766cc6b1SStefan Schake { 105766cc6b1SStefan Schake struct vc4_ctm_state *ctm_state = to_vc4_ctm_state(state); 106766cc6b1SStefan Schake 107766cc6b1SStefan Schake kfree(ctm_state); 108766cc6b1SStefan Schake } 109766cc6b1SStefan Schake 110766cc6b1SStefan Schake static const struct drm_private_state_funcs vc4_ctm_state_funcs = { 111766cc6b1SStefan Schake .atomic_duplicate_state = vc4_ctm_duplicate_state, 112766cc6b1SStefan Schake .atomic_destroy_state = vc4_ctm_destroy_state, 113766cc6b1SStefan Schake }; 114766cc6b1SStefan Schake 115dcda7c28SMaxime Ripard static void vc4_ctm_obj_fini(struct drm_device *dev, void *unused) 116dcda7c28SMaxime Ripard { 117dcda7c28SMaxime Ripard struct vc4_dev *vc4 = to_vc4_dev(dev); 118dcda7c28SMaxime Ripard 119dcda7c28SMaxime Ripard drm_atomic_private_obj_fini(&vc4->ctm_manager); 120dcda7c28SMaxime Ripard } 121dcda7c28SMaxime Ripard 122dcda7c28SMaxime Ripard static int vc4_ctm_obj_init(struct vc4_dev *vc4) 123dcda7c28SMaxime Ripard { 124dcda7c28SMaxime Ripard struct vc4_ctm_state *ctm_state; 125dcda7c28SMaxime Ripard 126dcda7c28SMaxime Ripard drm_modeset_lock_init(&vc4->ctm_state_lock); 127dcda7c28SMaxime Ripard 128dcda7c28SMaxime Ripard ctm_state = kzalloc(sizeof(*ctm_state), GFP_KERNEL); 129dcda7c28SMaxime Ripard if (!ctm_state) 130dcda7c28SMaxime Ripard return -ENOMEM; 131dcda7c28SMaxime Ripard 132dcda7c28SMaxime Ripard drm_atomic_private_obj_init(&vc4->base, &vc4->ctm_manager, &ctm_state->base, 133dcda7c28SMaxime Ripard &vc4_ctm_state_funcs); 134dcda7c28SMaxime Ripard 1353c354ed1SMaxime Ripard return drmm_add_action_or_reset(&vc4->base, vc4_ctm_obj_fini, NULL); 136dcda7c28SMaxime Ripard } 137dcda7c28SMaxime Ripard 138766cc6b1SStefan Schake /* Converts a DRM S31.32 value to the HW S0.9 format. */ 139766cc6b1SStefan Schake static u16 vc4_ctm_s31_32_to_s0_9(u64 in) 140766cc6b1SStefan Schake { 141766cc6b1SStefan Schake u16 r; 142766cc6b1SStefan Schake 143766cc6b1SStefan Schake /* Sign bit. */ 144766cc6b1SStefan Schake r = in & BIT_ULL(63) ? BIT(9) : 0; 145766cc6b1SStefan Schake 146766cc6b1SStefan Schake if ((in & GENMASK_ULL(62, 32)) > 0) { 147766cc6b1SStefan Schake /* We have zero integer bits so we can only saturate here. */ 148766cc6b1SStefan Schake r |= GENMASK(8, 0); 149766cc6b1SStefan Schake } else { 150766cc6b1SStefan Schake /* Otherwise take the 9 most important fractional bits. */ 151766cc6b1SStefan Schake r |= (in >> 23) & GENMASK(8, 0); 152766cc6b1SStefan Schake } 153766cc6b1SStefan Schake 154766cc6b1SStefan Schake return r; 155766cc6b1SStefan Schake } 156766cc6b1SStefan Schake 157766cc6b1SStefan Schake static void 158766cc6b1SStefan Schake vc4_ctm_commit(struct vc4_dev *vc4, struct drm_atomic_state *state) 159766cc6b1SStefan Schake { 160766cc6b1SStefan Schake struct vc4_ctm_state *ctm_state = to_vc4_ctm_state(vc4->ctm_manager.state); 161766cc6b1SStefan Schake struct drm_color_ctm *ctm = ctm_state->ctm; 162766cc6b1SStefan Schake 163766cc6b1SStefan Schake if (ctm_state->fifo) { 164766cc6b1SStefan Schake HVS_WRITE(SCALER_OLEDCOEF2, 165766cc6b1SStefan Schake VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[0]), 166766cc6b1SStefan Schake SCALER_OLEDCOEF2_R_TO_R) | 167766cc6b1SStefan Schake VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[3]), 168766cc6b1SStefan Schake SCALER_OLEDCOEF2_R_TO_G) | 169766cc6b1SStefan Schake VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[6]), 170766cc6b1SStefan Schake SCALER_OLEDCOEF2_R_TO_B)); 171766cc6b1SStefan Schake HVS_WRITE(SCALER_OLEDCOEF1, 172766cc6b1SStefan Schake VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[1]), 173766cc6b1SStefan Schake SCALER_OLEDCOEF1_G_TO_R) | 174766cc6b1SStefan Schake VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[4]), 175766cc6b1SStefan Schake SCALER_OLEDCOEF1_G_TO_G) | 176766cc6b1SStefan Schake VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[7]), 177766cc6b1SStefan Schake SCALER_OLEDCOEF1_G_TO_B)); 178766cc6b1SStefan Schake HVS_WRITE(SCALER_OLEDCOEF0, 179766cc6b1SStefan Schake VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[2]), 180766cc6b1SStefan Schake SCALER_OLEDCOEF0_B_TO_R) | 181766cc6b1SStefan Schake VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[5]), 182766cc6b1SStefan Schake SCALER_OLEDCOEF0_B_TO_G) | 183766cc6b1SStefan Schake VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[8]), 184766cc6b1SStefan Schake SCALER_OLEDCOEF0_B_TO_B)); 185766cc6b1SStefan Schake } 186766cc6b1SStefan Schake 187766cc6b1SStefan Schake HVS_WRITE(SCALER_OLEDOFFS, 188766cc6b1SStefan Schake VC4_SET_FIELD(ctm_state->fifo, SCALER_OLEDOFFS_DISPFIFO)); 189766cc6b1SStefan Schake } 190c8b75bcaSEric Anholt 191f2df84e0SMaxime Ripard static struct vc4_hvs_state * 1929ec03d7fSMaxime Ripard vc4_hvs_get_new_global_state(struct drm_atomic_state *state) 1939ec03d7fSMaxime Ripard { 1949ec03d7fSMaxime Ripard struct vc4_dev *vc4 = to_vc4_dev(state->dev); 1959ec03d7fSMaxime Ripard struct drm_private_state *priv_state; 1969ec03d7fSMaxime Ripard 1979ec03d7fSMaxime Ripard priv_state = drm_atomic_get_new_private_obj_state(state, &vc4->hvs_channels); 1989ec03d7fSMaxime Ripard if (IS_ERR(priv_state)) 1999ec03d7fSMaxime Ripard return ERR_CAST(priv_state); 2009ec03d7fSMaxime Ripard 2019ec03d7fSMaxime Ripard return to_vc4_hvs_state(priv_state); 2029ec03d7fSMaxime Ripard } 2039ec03d7fSMaxime Ripard 2049ec03d7fSMaxime Ripard static struct vc4_hvs_state * 2059ec03d7fSMaxime Ripard vc4_hvs_get_old_global_state(struct drm_atomic_state *state) 2069ec03d7fSMaxime Ripard { 2079ec03d7fSMaxime Ripard struct vc4_dev *vc4 = to_vc4_dev(state->dev); 2089ec03d7fSMaxime Ripard struct drm_private_state *priv_state; 2099ec03d7fSMaxime Ripard 2109ec03d7fSMaxime Ripard priv_state = drm_atomic_get_old_private_obj_state(state, &vc4->hvs_channels); 2119ec03d7fSMaxime Ripard if (IS_ERR(priv_state)) 2129ec03d7fSMaxime Ripard return ERR_CAST(priv_state); 2139ec03d7fSMaxime Ripard 2149ec03d7fSMaxime Ripard return to_vc4_hvs_state(priv_state); 2159ec03d7fSMaxime Ripard } 2169ec03d7fSMaxime Ripard 2179ec03d7fSMaxime Ripard static struct vc4_hvs_state * 218f2df84e0SMaxime Ripard vc4_hvs_get_global_state(struct drm_atomic_state *state) 219f2df84e0SMaxime Ripard { 220f2df84e0SMaxime Ripard struct vc4_dev *vc4 = to_vc4_dev(state->dev); 221f2df84e0SMaxime Ripard struct drm_private_state *priv_state; 222f2df84e0SMaxime Ripard 223f2df84e0SMaxime Ripard priv_state = drm_atomic_get_private_obj_state(state, &vc4->hvs_channels); 224f2df84e0SMaxime Ripard if (IS_ERR(priv_state)) 225f2df84e0SMaxime Ripard return ERR_CAST(priv_state); 226f2df84e0SMaxime Ripard 227f2df84e0SMaxime Ripard return to_vc4_hvs_state(priv_state); 228f2df84e0SMaxime Ripard } 229f2df84e0SMaxime Ripard 23087ebcd42SMaxime Ripard static void vc4_hvs_pv_muxing_commit(struct vc4_dev *vc4, 23187ebcd42SMaxime Ripard struct drm_atomic_state *state) 23287ebcd42SMaxime Ripard { 23387ebcd42SMaxime Ripard struct drm_crtc_state *crtc_state; 23487ebcd42SMaxime Ripard struct drm_crtc *crtc; 23587ebcd42SMaxime Ripard unsigned int i; 23687ebcd42SMaxime Ripard 23787ebcd42SMaxime Ripard for_each_new_crtc_in_state(state, crtc, crtc_state, i) { 238*a16c6640SMaxime Ripard struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 23987ebcd42SMaxime Ripard struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state); 24087ebcd42SMaxime Ripard u32 dispctrl; 24187ebcd42SMaxime Ripard u32 dsp3_mux; 24287ebcd42SMaxime Ripard 24387ebcd42SMaxime Ripard if (!crtc_state->active) 24487ebcd42SMaxime Ripard continue; 24587ebcd42SMaxime Ripard 24687ebcd42SMaxime Ripard if (vc4_state->assigned_channel != 2) 24787ebcd42SMaxime Ripard continue; 24887ebcd42SMaxime Ripard 24987ebcd42SMaxime Ripard /* 25087ebcd42SMaxime Ripard * SCALER_DISPCTRL_DSP3 = X, where X < 2 means 'connect DSP3 to 25187ebcd42SMaxime Ripard * FIFO X'. 25287ebcd42SMaxime Ripard * SCALER_DISPCTRL_DSP3 = 3 means 'disable DSP 3'. 25387ebcd42SMaxime Ripard * 25487ebcd42SMaxime Ripard * DSP3 is connected to FIFO2 unless the transposer is 25587ebcd42SMaxime Ripard * enabled. In this case, FIFO 2 is directly accessed by the 25687ebcd42SMaxime Ripard * TXP IP, and we need to disable the FIFO2 -> pixelvalve1 25787ebcd42SMaxime Ripard * route. 25887ebcd42SMaxime Ripard */ 259*a16c6640SMaxime Ripard if (vc4_crtc->feeds_txp) 26087ebcd42SMaxime Ripard dsp3_mux = VC4_SET_FIELD(3, SCALER_DISPCTRL_DSP3_MUX); 26187ebcd42SMaxime Ripard else 26287ebcd42SMaxime Ripard dsp3_mux = VC4_SET_FIELD(2, SCALER_DISPCTRL_DSP3_MUX); 26387ebcd42SMaxime Ripard 26487ebcd42SMaxime Ripard dispctrl = HVS_READ(SCALER_DISPCTRL) & 26587ebcd42SMaxime Ripard ~SCALER_DISPCTRL_DSP3_MUX_MASK; 26687ebcd42SMaxime Ripard HVS_WRITE(SCALER_DISPCTRL, dispctrl | dsp3_mux); 26787ebcd42SMaxime Ripard } 26887ebcd42SMaxime Ripard } 26987ebcd42SMaxime Ripard 27087ebcd42SMaxime Ripard static void vc5_hvs_pv_muxing_commit(struct vc4_dev *vc4, 27187ebcd42SMaxime Ripard struct drm_atomic_state *state) 27287ebcd42SMaxime Ripard { 27387ebcd42SMaxime Ripard struct drm_crtc_state *crtc_state; 27487ebcd42SMaxime Ripard struct drm_crtc *crtc; 2752820526dSMaxime Ripard unsigned char mux; 27687ebcd42SMaxime Ripard unsigned int i; 27787ebcd42SMaxime Ripard u32 reg; 27887ebcd42SMaxime Ripard 27987ebcd42SMaxime Ripard for_each_new_crtc_in_state(state, crtc, crtc_state, i) { 28087ebcd42SMaxime Ripard struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state); 28187ebcd42SMaxime Ripard struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 28287ebcd42SMaxime Ripard 2832820526dSMaxime Ripard if (!vc4_state->update_muxing) 28487ebcd42SMaxime Ripard continue; 28587ebcd42SMaxime Ripard 28687ebcd42SMaxime Ripard switch (vc4_crtc->data->hvs_output) { 28787ebcd42SMaxime Ripard case 2: 2882820526dSMaxime Ripard mux = (vc4_state->assigned_channel == 2) ? 0 : 1; 2892820526dSMaxime Ripard reg = HVS_READ(SCALER_DISPECTRL); 2902820526dSMaxime Ripard HVS_WRITE(SCALER_DISPECTRL, 2912820526dSMaxime Ripard (reg & ~SCALER_DISPECTRL_DSP2_MUX_MASK) | 2922820526dSMaxime Ripard VC4_SET_FIELD(mux, SCALER_DISPECTRL_DSP2_MUX)); 29387ebcd42SMaxime Ripard break; 29487ebcd42SMaxime Ripard 29587ebcd42SMaxime Ripard case 3: 2962820526dSMaxime Ripard if (vc4_state->assigned_channel == VC4_HVS_CHANNEL_DISABLED) 2972820526dSMaxime Ripard mux = 3; 2982820526dSMaxime Ripard else 2992820526dSMaxime Ripard mux = vc4_state->assigned_channel; 3002820526dSMaxime Ripard 3012820526dSMaxime Ripard reg = HVS_READ(SCALER_DISPCTRL); 3022820526dSMaxime Ripard HVS_WRITE(SCALER_DISPCTRL, 3032820526dSMaxime Ripard (reg & ~SCALER_DISPCTRL_DSP3_MUX_MASK) | 3042820526dSMaxime Ripard VC4_SET_FIELD(mux, SCALER_DISPCTRL_DSP3_MUX)); 30587ebcd42SMaxime Ripard break; 30687ebcd42SMaxime Ripard 30787ebcd42SMaxime Ripard case 4: 3082820526dSMaxime Ripard if (vc4_state->assigned_channel == VC4_HVS_CHANNEL_DISABLED) 3092820526dSMaxime Ripard mux = 3; 3102820526dSMaxime Ripard else 3112820526dSMaxime Ripard mux = vc4_state->assigned_channel; 3122820526dSMaxime Ripard 3132820526dSMaxime Ripard reg = HVS_READ(SCALER_DISPEOLN); 3142820526dSMaxime Ripard HVS_WRITE(SCALER_DISPEOLN, 3152820526dSMaxime Ripard (reg & ~SCALER_DISPEOLN_DSP4_MUX_MASK) | 3162820526dSMaxime Ripard VC4_SET_FIELD(mux, SCALER_DISPEOLN_DSP4_MUX)); 3172820526dSMaxime Ripard 31887ebcd42SMaxime Ripard break; 31987ebcd42SMaxime Ripard 32087ebcd42SMaxime Ripard case 5: 3212820526dSMaxime Ripard if (vc4_state->assigned_channel == VC4_HVS_CHANNEL_DISABLED) 3222820526dSMaxime Ripard mux = 3; 3232820526dSMaxime Ripard else 3242820526dSMaxime Ripard mux = vc4_state->assigned_channel; 3252820526dSMaxime Ripard 3262820526dSMaxime Ripard reg = HVS_READ(SCALER_DISPDITHER); 3272820526dSMaxime Ripard HVS_WRITE(SCALER_DISPDITHER, 3282820526dSMaxime Ripard (reg & ~SCALER_DISPDITHER_DSP5_MUX_MASK) | 3292820526dSMaxime Ripard VC4_SET_FIELD(mux, SCALER_DISPDITHER_DSP5_MUX)); 33087ebcd42SMaxime Ripard break; 33187ebcd42SMaxime Ripard 33287ebcd42SMaxime Ripard default: 33387ebcd42SMaxime Ripard break; 33487ebcd42SMaxime Ripard } 33587ebcd42SMaxime Ripard } 33687ebcd42SMaxime Ripard } 33787ebcd42SMaxime Ripard 338f3c420feSMaxime Ripard static void vc4_atomic_commit_tail(struct drm_atomic_state *state) 339b501baccSEric Anholt { 340b501baccSEric Anholt struct drm_device *dev = state->dev; 341b501baccSEric Anholt struct vc4_dev *vc4 = to_vc4_dev(dev); 342d7d96c00SMaxime Ripard struct vc4_hvs *hvs = vc4->hvs; 3439ec03d7fSMaxime Ripard struct drm_crtc_state *old_crtc_state; 34459635667SMaxime Ripard struct drm_crtc_state *new_crtc_state; 34516e10105SMaxime Ripard struct vc4_hvs_state *new_hvs_state; 34659635667SMaxime Ripard struct drm_crtc *crtc; 3479ec03d7fSMaxime Ripard struct vc4_hvs_state *old_hvs_state; 348531a1b62SBoris Brezillon int i; 349531a1b62SBoris Brezillon 35016e10105SMaxime Ripard old_hvs_state = vc4_hvs_get_old_global_state(state); 35116e10105SMaxime Ripard if (WARN_ON(!old_hvs_state)) 35216e10105SMaxime Ripard return; 35316e10105SMaxime Ripard 35416e10105SMaxime Ripard new_hvs_state = vc4_hvs_get_new_global_state(state); 35516e10105SMaxime Ripard if (WARN_ON(!new_hvs_state)) 35616e10105SMaxime Ripard return; 35716e10105SMaxime Ripard 35859635667SMaxime Ripard for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 35987ebcd42SMaxime Ripard struct vc4_crtc_state *vc4_crtc_state; 36059635667SMaxime Ripard 36159635667SMaxime Ripard if (!new_crtc_state->commit) 362531a1b62SBoris Brezillon continue; 363531a1b62SBoris Brezillon 36487ebcd42SMaxime Ripard vc4_crtc_state = to_vc4_crtc_state(new_crtc_state); 36587ebcd42SMaxime Ripard vc4_hvs_mask_underrun(dev, vc4_crtc_state->assigned_channel); 366531a1b62SBoris Brezillon } 367b501baccSEric Anholt 36816e10105SMaxime Ripard if (vc4->hvs->hvs5) { 36916e10105SMaxime Ripard unsigned long core_rate = max_t(unsigned long, 37016e10105SMaxime Ripard 500000000, 37116e10105SMaxime Ripard new_hvs_state->core_clock_rate); 372d7d96c00SMaxime Ripard 37316e10105SMaxime Ripard clk_set_min_rate(hvs->core_clk, core_rate); 37416e10105SMaxime Ripard } 3759ec03d7fSMaxime Ripard 3769ec03d7fSMaxime Ripard for_each_old_crtc_in_state(state, crtc, old_crtc_state, i) { 3779ec03d7fSMaxime Ripard struct vc4_crtc_state *vc4_crtc_state = 3789ec03d7fSMaxime Ripard to_vc4_crtc_state(old_crtc_state); 3799ec03d7fSMaxime Ripard unsigned int channel = vc4_crtc_state->assigned_channel; 380b99c2c95SMaxime Ripard int ret; 3819ec03d7fSMaxime Ripard 3829ec03d7fSMaxime Ripard if (channel == VC4_HVS_CHANNEL_DISABLED) 3839ec03d7fSMaxime Ripard continue; 3849ec03d7fSMaxime Ripard 3859ec03d7fSMaxime Ripard if (!old_hvs_state->fifo_state[channel].in_use) 3869ec03d7fSMaxime Ripard continue; 3879ec03d7fSMaxime Ripard 3888a11e84bSMark Rutland ret = drm_crtc_commit_wait(old_hvs_state->fifo_state[channel].pending_commit); 389b99c2c95SMaxime Ripard if (ret) 390b99c2c95SMaxime Ripard drm_err(dev, "Timed out waiting for commit\n"); 3919ec03d7fSMaxime Ripard } 3929ec03d7fSMaxime Ripard 393b501baccSEric Anholt drm_atomic_helper_commit_modeset_disables(dev, state); 394b501baccSEric Anholt 395766cc6b1SStefan Schake vc4_ctm_commit(vc4, state); 396766cc6b1SStefan Schake 39787ebcd42SMaxime Ripard if (vc4->hvs->hvs5) 39887ebcd42SMaxime Ripard vc5_hvs_pv_muxing_commit(vc4, state); 39987ebcd42SMaxime Ripard else 40087ebcd42SMaxime Ripard vc4_hvs_pv_muxing_commit(vc4, state); 40187ebcd42SMaxime Ripard 4022b58e98dSLiu Ying drm_atomic_helper_commit_planes(dev, state, 0); 403b501baccSEric Anholt 404b501baccSEric Anholt drm_atomic_helper_commit_modeset_enables(dev, state); 405b501baccSEric Anholt 4061ebe99a7SBoris Brezillon drm_atomic_helper_fake_vblank(state); 4071ebe99a7SBoris Brezillon 40834c8ea40SBoris Brezillon drm_atomic_helper_commit_hw_done(state); 40934c8ea40SBoris Brezillon 410184d3cf4SBoris Brezillon drm_atomic_helper_wait_for_flip_done(dev, state); 411b501baccSEric Anholt 412b501baccSEric Anholt drm_atomic_helper_cleanup_planes(dev, state); 413b501baccSEric Anholt 41416e10105SMaxime Ripard if (vc4->hvs->hvs5) { 41516e10105SMaxime Ripard drm_dbg(dev, "Running the core clock at %lu Hz\n", 41616e10105SMaxime Ripard new_hvs_state->core_clock_rate); 41716e10105SMaxime Ripard 41816e10105SMaxime Ripard clk_set_min_rate(hvs->core_clk, new_hvs_state->core_clock_rate); 41916e10105SMaxime Ripard } 420b501baccSEric Anholt } 421b501baccSEric Anholt 4229ec03d7fSMaxime Ripard static int vc4_atomic_commit_setup(struct drm_atomic_state *state) 4239ec03d7fSMaxime Ripard { 4249ec03d7fSMaxime Ripard struct drm_crtc_state *crtc_state; 4259ec03d7fSMaxime Ripard struct vc4_hvs_state *hvs_state; 4269ec03d7fSMaxime Ripard struct drm_crtc *crtc; 4279ec03d7fSMaxime Ripard unsigned int i; 4289ec03d7fSMaxime Ripard 4299ec03d7fSMaxime Ripard hvs_state = vc4_hvs_get_new_global_state(state); 4309ec03d7fSMaxime Ripard if (!hvs_state) 4319ec03d7fSMaxime Ripard return -EINVAL; 4329ec03d7fSMaxime Ripard 4339ec03d7fSMaxime Ripard for_each_new_crtc_in_state(state, crtc, crtc_state, i) { 4349ec03d7fSMaxime Ripard struct vc4_crtc_state *vc4_crtc_state = 4359ec03d7fSMaxime Ripard to_vc4_crtc_state(crtc_state); 4369ec03d7fSMaxime Ripard unsigned int channel = 4379ec03d7fSMaxime Ripard vc4_crtc_state->assigned_channel; 4389ec03d7fSMaxime Ripard 4399ec03d7fSMaxime Ripard if (channel == VC4_HVS_CHANNEL_DISABLED) 4409ec03d7fSMaxime Ripard continue; 4419ec03d7fSMaxime Ripard 4429ec03d7fSMaxime Ripard if (!hvs_state->fifo_state[channel].in_use) 4439ec03d7fSMaxime Ripard continue; 4449ec03d7fSMaxime Ripard 4459ec03d7fSMaxime Ripard hvs_state->fifo_state[channel].pending_commit = 4469ec03d7fSMaxime Ripard drm_crtc_commit_get(crtc_state->commit); 4479ec03d7fSMaxime Ripard } 4489ec03d7fSMaxime Ripard 4499ec03d7fSMaxime Ripard return 0; 4509ec03d7fSMaxime Ripard } 4519ec03d7fSMaxime Ripard 45283753117SEric Anholt static struct drm_framebuffer *vc4_fb_create(struct drm_device *dev, 45383753117SEric Anholt struct drm_file *file_priv, 45483753117SEric Anholt const struct drm_mode_fb_cmd2 *mode_cmd) 45583753117SEric Anholt { 45683753117SEric Anholt struct drm_mode_fb_cmd2 mode_cmd_local; 45783753117SEric Anholt 45883753117SEric Anholt /* If the user didn't specify a modifier, use the 45983753117SEric Anholt * vc4_set_tiling_ioctl() state for the BO. 46083753117SEric Anholt */ 46183753117SEric Anholt if (!(mode_cmd->flags & DRM_MODE_FB_MODIFIERS)) { 46283753117SEric Anholt struct drm_gem_object *gem_obj; 46383753117SEric Anholt struct vc4_bo *bo; 46483753117SEric Anholt 46583753117SEric Anholt gem_obj = drm_gem_object_lookup(file_priv, 46683753117SEric Anholt mode_cmd->handles[0]); 46783753117SEric Anholt if (!gem_obj) { 468fb95992aSEric Anholt DRM_DEBUG("Failed to look up GEM BO %d\n", 46983753117SEric Anholt mode_cmd->handles[0]); 47083753117SEric Anholt return ERR_PTR(-ENOENT); 47183753117SEric Anholt } 47283753117SEric Anholt bo = to_vc4_bo(gem_obj); 47383753117SEric Anholt 47483753117SEric Anholt mode_cmd_local = *mode_cmd; 47583753117SEric Anholt 47683753117SEric Anholt if (bo->t_format) { 47783753117SEric Anholt mode_cmd_local.modifier[0] = 47883753117SEric Anholt DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED; 47983753117SEric Anholt } else { 48083753117SEric Anholt mode_cmd_local.modifier[0] = DRM_FORMAT_MOD_NONE; 48183753117SEric Anholt } 48283753117SEric Anholt 483f7a8cd30SEmil Velikov drm_gem_object_put(gem_obj); 48483753117SEric Anholt 48583753117SEric Anholt mode_cmd = &mode_cmd_local; 48683753117SEric Anholt } 48783753117SEric Anholt 4889762477cSNoralf Trønnes return drm_gem_fb_create(dev, file_priv, mode_cmd); 48983753117SEric Anholt } 49083753117SEric Anholt 491766cc6b1SStefan Schake /* Our CTM has some peculiar limitations: we can only enable it for one CRTC 492766cc6b1SStefan Schake * at a time and the HW only supports S0.9 scalars. To account for the latter, 493766cc6b1SStefan Schake * we don't allow userland to set a CTM that we have no hope of approximating. 494766cc6b1SStefan Schake */ 495766cc6b1SStefan Schake static int 496766cc6b1SStefan Schake vc4_ctm_atomic_check(struct drm_device *dev, struct drm_atomic_state *state) 497766cc6b1SStefan Schake { 498766cc6b1SStefan Schake struct vc4_dev *vc4 = to_vc4_dev(dev); 499766cc6b1SStefan Schake struct vc4_ctm_state *ctm_state = NULL; 500766cc6b1SStefan Schake struct drm_crtc *crtc; 501766cc6b1SStefan Schake struct drm_crtc_state *old_crtc_state, *new_crtc_state; 502766cc6b1SStefan Schake struct drm_color_ctm *ctm; 503766cc6b1SStefan Schake int i; 504766cc6b1SStefan Schake 505766cc6b1SStefan Schake for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 506766cc6b1SStefan Schake /* CTM is being disabled. */ 507766cc6b1SStefan Schake if (!new_crtc_state->ctm && old_crtc_state->ctm) { 508766cc6b1SStefan Schake ctm_state = vc4_get_ctm_state(state, &vc4->ctm_manager); 509766cc6b1SStefan Schake if (IS_ERR(ctm_state)) 510766cc6b1SStefan Schake return PTR_ERR(ctm_state); 511766cc6b1SStefan Schake ctm_state->fifo = 0; 512766cc6b1SStefan Schake } 513766cc6b1SStefan Schake } 514766cc6b1SStefan Schake 515766cc6b1SStefan Schake for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 516766cc6b1SStefan Schake if (new_crtc_state->ctm == old_crtc_state->ctm) 517766cc6b1SStefan Schake continue; 518766cc6b1SStefan Schake 519766cc6b1SStefan Schake if (!ctm_state) { 520766cc6b1SStefan Schake ctm_state = vc4_get_ctm_state(state, &vc4->ctm_manager); 521766cc6b1SStefan Schake if (IS_ERR(ctm_state)) 522766cc6b1SStefan Schake return PTR_ERR(ctm_state); 523766cc6b1SStefan Schake } 524766cc6b1SStefan Schake 525766cc6b1SStefan Schake /* CTM is being enabled or the matrix changed. */ 526766cc6b1SStefan Schake if (new_crtc_state->ctm) { 52787ebcd42SMaxime Ripard struct vc4_crtc_state *vc4_crtc_state = 52887ebcd42SMaxime Ripard to_vc4_crtc_state(new_crtc_state); 52987ebcd42SMaxime Ripard 530766cc6b1SStefan Schake /* fifo is 1-based since 0 disables CTM. */ 53187ebcd42SMaxime Ripard int fifo = vc4_crtc_state->assigned_channel + 1; 532766cc6b1SStefan Schake 533766cc6b1SStefan Schake /* Check userland isn't trying to turn on CTM for more 534766cc6b1SStefan Schake * than one CRTC at a time. 535766cc6b1SStefan Schake */ 536766cc6b1SStefan Schake if (ctm_state->fifo && ctm_state->fifo != fifo) { 537766cc6b1SStefan Schake DRM_DEBUG_DRIVER("Too many CTM configured\n"); 538766cc6b1SStefan Schake return -EINVAL; 539766cc6b1SStefan Schake } 540766cc6b1SStefan Schake 541766cc6b1SStefan Schake /* Check we can approximate the specified CTM. 542766cc6b1SStefan Schake * We disallow scalars |c| > 1.0 since the HW has 543766cc6b1SStefan Schake * no integer bits. 544766cc6b1SStefan Schake */ 545766cc6b1SStefan Schake ctm = new_crtc_state->ctm->data; 546766cc6b1SStefan Schake for (i = 0; i < ARRAY_SIZE(ctm->matrix); i++) { 547766cc6b1SStefan Schake u64 val = ctm->matrix[i]; 548766cc6b1SStefan Schake 549766cc6b1SStefan Schake val &= ~BIT_ULL(63); 550766cc6b1SStefan Schake if (val > BIT_ULL(32)) 551766cc6b1SStefan Schake return -EINVAL; 552766cc6b1SStefan Schake } 553766cc6b1SStefan Schake 554766cc6b1SStefan Schake ctm_state->fifo = fifo; 555766cc6b1SStefan Schake ctm_state->ctm = ctm; 556766cc6b1SStefan Schake } 557766cc6b1SStefan Schake } 558766cc6b1SStefan Schake 559766cc6b1SStefan Schake return 0; 560766cc6b1SStefan Schake } 561766cc6b1SStefan Schake 5624686da83SBoris Brezillon static int vc4_load_tracker_atomic_check(struct drm_atomic_state *state) 5634686da83SBoris Brezillon { 5644686da83SBoris Brezillon struct drm_plane_state *old_plane_state, *new_plane_state; 5654686da83SBoris Brezillon struct vc4_dev *vc4 = to_vc4_dev(state->dev); 5664686da83SBoris Brezillon struct vc4_load_tracker_state *load_state; 5674686da83SBoris Brezillon struct drm_private_state *priv_state; 5684686da83SBoris Brezillon struct drm_plane *plane; 5694686da83SBoris Brezillon int i; 5704686da83SBoris Brezillon 5714686da83SBoris Brezillon priv_state = drm_atomic_get_private_obj_state(state, 5724686da83SBoris Brezillon &vc4->load_tracker); 5734686da83SBoris Brezillon if (IS_ERR(priv_state)) 5744686da83SBoris Brezillon return PTR_ERR(priv_state); 5754686da83SBoris Brezillon 5764686da83SBoris Brezillon load_state = to_vc4_load_tracker_state(priv_state); 5774686da83SBoris Brezillon for_each_oldnew_plane_in_state(state, plane, old_plane_state, 5784686da83SBoris Brezillon new_plane_state, i) { 5794686da83SBoris Brezillon struct vc4_plane_state *vc4_plane_state; 5804686da83SBoris Brezillon 5814686da83SBoris Brezillon if (old_plane_state->fb && old_plane_state->crtc) { 5824686da83SBoris Brezillon vc4_plane_state = to_vc4_plane_state(old_plane_state); 5834686da83SBoris Brezillon load_state->membus_load -= vc4_plane_state->membus_load; 5844686da83SBoris Brezillon load_state->hvs_load -= vc4_plane_state->hvs_load; 5854686da83SBoris Brezillon } 5864686da83SBoris Brezillon 5874686da83SBoris Brezillon if (new_plane_state->fb && new_plane_state->crtc) { 5884686da83SBoris Brezillon vc4_plane_state = to_vc4_plane_state(new_plane_state); 5894686da83SBoris Brezillon load_state->membus_load += vc4_plane_state->membus_load; 5904686da83SBoris Brezillon load_state->hvs_load += vc4_plane_state->hvs_load; 5914686da83SBoris Brezillon } 5924686da83SBoris Brezillon } 5934686da83SBoris Brezillon 5946b5c029dSPaul Kocialkowski /* Don't check the load when the tracker is disabled. */ 5956b5c029dSPaul Kocialkowski if (!vc4->load_tracker_enabled) 5966b5c029dSPaul Kocialkowski return 0; 5976b5c029dSPaul Kocialkowski 5984686da83SBoris Brezillon /* The absolute limit is 2Gbyte/sec, but let's take a margin to let 5994686da83SBoris Brezillon * the system work when other blocks are accessing the memory. 6004686da83SBoris Brezillon */ 6014686da83SBoris Brezillon if (load_state->membus_load > SZ_1G + SZ_512M) 6024686da83SBoris Brezillon return -ENOSPC; 6034686da83SBoris Brezillon 6044686da83SBoris Brezillon /* HVS clock is supposed to run @ 250Mhz, let's take a margin and 6054686da83SBoris Brezillon * consider the maximum number of cycles is 240M. 6064686da83SBoris Brezillon */ 6074686da83SBoris Brezillon if (load_state->hvs_load > 240000000ULL) 6084686da83SBoris Brezillon return -ENOSPC; 6094686da83SBoris Brezillon 6104686da83SBoris Brezillon return 0; 6114686da83SBoris Brezillon } 6124686da83SBoris Brezillon 6134686da83SBoris Brezillon static struct drm_private_state * 6144686da83SBoris Brezillon vc4_load_tracker_duplicate_state(struct drm_private_obj *obj) 6154686da83SBoris Brezillon { 6164686da83SBoris Brezillon struct vc4_load_tracker_state *state; 6174686da83SBoris Brezillon 6184686da83SBoris Brezillon state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL); 6194686da83SBoris Brezillon if (!state) 6204686da83SBoris Brezillon return NULL; 6214686da83SBoris Brezillon 6224686da83SBoris Brezillon __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base); 6234686da83SBoris Brezillon 6244686da83SBoris Brezillon return &state->base; 6254686da83SBoris Brezillon } 6264686da83SBoris Brezillon 6274686da83SBoris Brezillon static void vc4_load_tracker_destroy_state(struct drm_private_obj *obj, 6284686da83SBoris Brezillon struct drm_private_state *state) 6294686da83SBoris Brezillon { 6304686da83SBoris Brezillon struct vc4_load_tracker_state *load_state; 6314686da83SBoris Brezillon 6324686da83SBoris Brezillon load_state = to_vc4_load_tracker_state(state); 6334686da83SBoris Brezillon kfree(load_state); 6344686da83SBoris Brezillon } 6354686da83SBoris Brezillon 6364686da83SBoris Brezillon static const struct drm_private_state_funcs vc4_load_tracker_state_funcs = { 6374686da83SBoris Brezillon .atomic_duplicate_state = vc4_load_tracker_duplicate_state, 6384686da83SBoris Brezillon .atomic_destroy_state = vc4_load_tracker_destroy_state, 6394686da83SBoris Brezillon }; 6404686da83SBoris Brezillon 641dcda7c28SMaxime Ripard static void vc4_load_tracker_obj_fini(struct drm_device *dev, void *unused) 642dcda7c28SMaxime Ripard { 643dcda7c28SMaxime Ripard struct vc4_dev *vc4 = to_vc4_dev(dev); 644dcda7c28SMaxime Ripard 645dcda7c28SMaxime Ripard drm_atomic_private_obj_fini(&vc4->load_tracker); 646dcda7c28SMaxime Ripard } 647dcda7c28SMaxime Ripard 648dcda7c28SMaxime Ripard static int vc4_load_tracker_obj_init(struct vc4_dev *vc4) 649dcda7c28SMaxime Ripard { 650dcda7c28SMaxime Ripard struct vc4_load_tracker_state *load_state; 651dcda7c28SMaxime Ripard 652dcda7c28SMaxime Ripard load_state = kzalloc(sizeof(*load_state), GFP_KERNEL); 653dcda7c28SMaxime Ripard if (!load_state) 654dcda7c28SMaxime Ripard return -ENOMEM; 655dcda7c28SMaxime Ripard 656dcda7c28SMaxime Ripard drm_atomic_private_obj_init(&vc4->base, &vc4->load_tracker, 657dcda7c28SMaxime Ripard &load_state->base, 658dcda7c28SMaxime Ripard &vc4_load_tracker_state_funcs); 659dcda7c28SMaxime Ripard 6603c354ed1SMaxime Ripard return drmm_add_action_or_reset(&vc4->base, vc4_load_tracker_obj_fini, NULL); 661dcda7c28SMaxime Ripard } 662dcda7c28SMaxime Ripard 663f2df84e0SMaxime Ripard static struct drm_private_state * 664f2df84e0SMaxime Ripard vc4_hvs_channels_duplicate_state(struct drm_private_obj *obj) 665f2df84e0SMaxime Ripard { 666f2df84e0SMaxime Ripard struct vc4_hvs_state *old_state = to_vc4_hvs_state(obj->state); 667f2df84e0SMaxime Ripard struct vc4_hvs_state *state; 6689ec03d7fSMaxime Ripard unsigned int i; 669f2df84e0SMaxime Ripard 670f2df84e0SMaxime Ripard state = kzalloc(sizeof(*state), GFP_KERNEL); 671f2df84e0SMaxime Ripard if (!state) 672f2df84e0SMaxime Ripard return NULL; 673f2df84e0SMaxime Ripard 674f2df84e0SMaxime Ripard __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base); 675f2df84e0SMaxime Ripard 6769ec03d7fSMaxime Ripard for (i = 0; i < HVS_NUM_CHANNELS; i++) { 6779ec03d7fSMaxime Ripard state->fifo_state[i].in_use = old_state->fifo_state[i].in_use; 67816e10105SMaxime Ripard state->fifo_state[i].fifo_load = old_state->fifo_state[i].fifo_load; 6799ec03d7fSMaxime Ripard 6809ec03d7fSMaxime Ripard if (!old_state->fifo_state[i].pending_commit) 6819ec03d7fSMaxime Ripard continue; 6829ec03d7fSMaxime Ripard 6839ec03d7fSMaxime Ripard state->fifo_state[i].pending_commit = 6849ec03d7fSMaxime Ripard drm_crtc_commit_get(old_state->fifo_state[i].pending_commit); 6859ec03d7fSMaxime Ripard } 6869ec03d7fSMaxime Ripard 68716e10105SMaxime Ripard state->core_clock_rate = old_state->core_clock_rate; 68816e10105SMaxime Ripard 689f2df84e0SMaxime Ripard return &state->base; 690f2df84e0SMaxime Ripard } 691f2df84e0SMaxime Ripard 692f2df84e0SMaxime Ripard static void vc4_hvs_channels_destroy_state(struct drm_private_obj *obj, 693f2df84e0SMaxime Ripard struct drm_private_state *state) 694f2df84e0SMaxime Ripard { 695f2df84e0SMaxime Ripard struct vc4_hvs_state *hvs_state = to_vc4_hvs_state(state); 6969ec03d7fSMaxime Ripard unsigned int i; 6979ec03d7fSMaxime Ripard 6989ec03d7fSMaxime Ripard for (i = 0; i < HVS_NUM_CHANNELS; i++) { 6999ec03d7fSMaxime Ripard if (!hvs_state->fifo_state[i].pending_commit) 7009ec03d7fSMaxime Ripard continue; 7019ec03d7fSMaxime Ripard 7029ec03d7fSMaxime Ripard drm_crtc_commit_put(hvs_state->fifo_state[i].pending_commit); 7039ec03d7fSMaxime Ripard } 704f2df84e0SMaxime Ripard 705f2df84e0SMaxime Ripard kfree(hvs_state); 706f2df84e0SMaxime Ripard } 707f2df84e0SMaxime Ripard 708f2df84e0SMaxime Ripard static const struct drm_private_state_funcs vc4_hvs_state_funcs = { 709f2df84e0SMaxime Ripard .atomic_duplicate_state = vc4_hvs_channels_duplicate_state, 710f2df84e0SMaxime Ripard .atomic_destroy_state = vc4_hvs_channels_destroy_state, 711f2df84e0SMaxime Ripard }; 712f2df84e0SMaxime Ripard 713f2df84e0SMaxime Ripard static void vc4_hvs_channels_obj_fini(struct drm_device *dev, void *unused) 714f2df84e0SMaxime Ripard { 715f2df84e0SMaxime Ripard struct vc4_dev *vc4 = to_vc4_dev(dev); 716f2df84e0SMaxime Ripard 717f2df84e0SMaxime Ripard drm_atomic_private_obj_fini(&vc4->hvs_channels); 718f2df84e0SMaxime Ripard } 719f2df84e0SMaxime Ripard 720f2df84e0SMaxime Ripard static int vc4_hvs_channels_obj_init(struct vc4_dev *vc4) 721f2df84e0SMaxime Ripard { 722f2df84e0SMaxime Ripard struct vc4_hvs_state *state; 723f2df84e0SMaxime Ripard 724f2df84e0SMaxime Ripard state = kzalloc(sizeof(*state), GFP_KERNEL); 725f2df84e0SMaxime Ripard if (!state) 726f2df84e0SMaxime Ripard return -ENOMEM; 727f2df84e0SMaxime Ripard 728f2df84e0SMaxime Ripard drm_atomic_private_obj_init(&vc4->base, &vc4->hvs_channels, 729f2df84e0SMaxime Ripard &state->base, 730f2df84e0SMaxime Ripard &vc4_hvs_state_funcs); 731f2df84e0SMaxime Ripard 732f2df84e0SMaxime Ripard return drmm_add_action_or_reset(&vc4->base, vc4_hvs_channels_obj_fini, NULL); 733f2df84e0SMaxime Ripard } 734f2df84e0SMaxime Ripard 735b5dbc4d3SMaxime Ripard /* 736b5dbc4d3SMaxime Ripard * The BCM2711 HVS has up to 7 outputs connected to the pixelvalves and 737b5dbc4d3SMaxime Ripard * the TXP (and therefore all the CRTCs found on that platform). 738b5dbc4d3SMaxime Ripard * 739b5dbc4d3SMaxime Ripard * The naive (and our initial) implementation would just iterate over 740b5dbc4d3SMaxime Ripard * all the active CRTCs, try to find a suitable FIFO, and then remove it 741b5dbc4d3SMaxime Ripard * from the pool of available FIFOs. However, there are a few corner 742b5dbc4d3SMaxime Ripard * cases that need to be considered: 743b5dbc4d3SMaxime Ripard * 744b5dbc4d3SMaxime Ripard * - When running in a dual-display setup (so with two CRTCs involved), 745b5dbc4d3SMaxime Ripard * we can update the state of a single CRTC (for example by changing 746b5dbc4d3SMaxime Ripard * its mode using xrandr under X11) without affecting the other. In 747b5dbc4d3SMaxime Ripard * this case, the other CRTC wouldn't be in the state at all, so we 748b5dbc4d3SMaxime Ripard * need to consider all the running CRTCs in the DRM device to assign 749b5dbc4d3SMaxime Ripard * a FIFO, not just the one in the state. 750b5dbc4d3SMaxime Ripard * 751f2df84e0SMaxime Ripard * - To fix the above, we can't use drm_atomic_get_crtc_state on all 752f2df84e0SMaxime Ripard * enabled CRTCs to pull their CRTC state into the global state, since 753f2df84e0SMaxime Ripard * a page flip would start considering their vblank to complete. Since 754f2df84e0SMaxime Ripard * we don't have a guarantee that they are actually active, that 755f2df84e0SMaxime Ripard * vblank might never happen, and shouldn't even be considered if we 756f2df84e0SMaxime Ripard * want to do a page flip on a single CRTC. That can be tested by 757f2df84e0SMaxime Ripard * doing a modetest -v first on HDMI1 and then on HDMI0. 758f2df84e0SMaxime Ripard * 759b5dbc4d3SMaxime Ripard * - Since we need the pixelvalve to be disabled and enabled back when 760b5dbc4d3SMaxime Ripard * the FIFO is changed, we should keep the FIFO assigned for as long 761b5dbc4d3SMaxime Ripard * as the CRTC is enabled, only considering it free again once that 762b5dbc4d3SMaxime Ripard * CRTC has been disabled. This can be tested by booting X11 on a 763b5dbc4d3SMaxime Ripard * single display, and changing the resolution down and then back up. 764b5dbc4d3SMaxime Ripard */ 765a72b0458SMaxime Ripard static int vc4_pv_muxing_atomic_check(struct drm_device *dev, 766a72b0458SMaxime Ripard struct drm_atomic_state *state) 767766cc6b1SStefan Schake { 768f2df84e0SMaxime Ripard struct vc4_hvs_state *hvs_new_state; 7698ba0b6d1SMaxime Ripard struct drm_crtc_state *old_crtc_state, *new_crtc_state; 77087ebcd42SMaxime Ripard struct drm_crtc *crtc; 77103b03efeSMaxime Ripard unsigned int unassigned_channels = 0; 772a72b0458SMaxime Ripard unsigned int i; 77387ebcd42SMaxime Ripard 774f2df84e0SMaxime Ripard hvs_new_state = vc4_hvs_get_global_state(state); 775f2df84e0SMaxime Ripard if (!hvs_new_state) 776f2df84e0SMaxime Ripard return -EINVAL; 777089d8341SMaxime Ripard 77803b03efeSMaxime Ripard for (i = 0; i < ARRAY_SIZE(hvs_new_state->fifo_state); i++) 77903b03efeSMaxime Ripard if (!hvs_new_state->fifo_state[i].in_use) 78003b03efeSMaxime Ripard unassigned_channels |= BIT(i); 78103b03efeSMaxime Ripard 7828ba0b6d1SMaxime Ripard for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 783f2df84e0SMaxime Ripard struct vc4_crtc_state *old_vc4_crtc_state = 784f2df84e0SMaxime Ripard to_vc4_crtc_state(old_crtc_state); 7858ba0b6d1SMaxime Ripard struct vc4_crtc_state *new_vc4_crtc_state = 7868ba0b6d1SMaxime Ripard to_vc4_crtc_state(new_crtc_state); 78787ebcd42SMaxime Ripard struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 78887ebcd42SMaxime Ripard unsigned int matching_channels; 789d62a8ed7SMaxime Ripard unsigned int channel; 79087ebcd42SMaxime Ripard 7912820526dSMaxime Ripard /* Nothing to do here, let's skip it */ 7922820526dSMaxime Ripard if (old_crtc_state->enable == new_crtc_state->enable) 7932820526dSMaxime Ripard continue; 7942820526dSMaxime Ripard 7952820526dSMaxime Ripard /* Muxing will need to be modified, mark it as such */ 7962820526dSMaxime Ripard new_vc4_crtc_state->update_muxing = true; 7972820526dSMaxime Ripard 7982820526dSMaxime Ripard /* If we're disabling our CRTC, we put back our channel */ 7992820526dSMaxime Ripard if (!new_crtc_state->enable) { 8009ec03d7fSMaxime Ripard channel = old_vc4_crtc_state->assigned_channel; 8019ec03d7fSMaxime Ripard hvs_new_state->fifo_state[channel].in_use = false; 8028ba0b6d1SMaxime Ripard new_vc4_crtc_state->assigned_channel = VC4_HVS_CHANNEL_DISABLED; 8032820526dSMaxime Ripard continue; 804f2df84e0SMaxime Ripard } 8058ba0b6d1SMaxime Ripard 80687ebcd42SMaxime Ripard /* 80787ebcd42SMaxime Ripard * The problem we have to solve here is that we have 80887ebcd42SMaxime Ripard * up to 7 encoders, connected to up to 6 CRTCs. 80987ebcd42SMaxime Ripard * 81087ebcd42SMaxime Ripard * Those CRTCs, depending on the instance, can be 81187ebcd42SMaxime Ripard * routed to 1, 2 or 3 HVS FIFOs, and we need to set 81287ebcd42SMaxime Ripard * the change the muxing between FIFOs and outputs in 81387ebcd42SMaxime Ripard * the HVS accordingly. 81487ebcd42SMaxime Ripard * 81587ebcd42SMaxime Ripard * It would be pretty hard to come up with an 81687ebcd42SMaxime Ripard * algorithm that would generically solve 81787ebcd42SMaxime Ripard * this. However, the current routing trees we support 81887ebcd42SMaxime Ripard * allow us to simplify a bit the problem. 81987ebcd42SMaxime Ripard * 82087ebcd42SMaxime Ripard * Indeed, with the current supported layouts, if we 82187ebcd42SMaxime Ripard * try to assign in the ascending crtc index order the 82287ebcd42SMaxime Ripard * FIFOs, we can't fall into the situation where an 82387ebcd42SMaxime Ripard * earlier CRTC that had multiple routes is assigned 82487ebcd42SMaxime Ripard * one that was the only option for a later CRTC. 82587ebcd42SMaxime Ripard * 82687ebcd42SMaxime Ripard * If the layout changes and doesn't give us that in 82787ebcd42SMaxime Ripard * the future, we will need to have something smarter, 82887ebcd42SMaxime Ripard * but it works so far. 82987ebcd42SMaxime Ripard */ 83003b03efeSMaxime Ripard matching_channels = unassigned_channels & vc4_crtc->data->hvs_available_channels; 831d62a8ed7SMaxime Ripard if (!matching_channels) 832d62a8ed7SMaxime Ripard return -EINVAL; 83387ebcd42SMaxime Ripard 834d62a8ed7SMaxime Ripard channel = ffs(matching_channels) - 1; 8358ba0b6d1SMaxime Ripard new_vc4_crtc_state->assigned_channel = channel; 83603b03efeSMaxime Ripard unassigned_channels &= ~BIT(channel); 8379ec03d7fSMaxime Ripard hvs_new_state->fifo_state[channel].in_use = true; 83887ebcd42SMaxime Ripard } 839766cc6b1SStefan Schake 840a72b0458SMaxime Ripard return 0; 841a72b0458SMaxime Ripard } 842a72b0458SMaxime Ripard 843a72b0458SMaxime Ripard static int 84416e10105SMaxime Ripard vc4_core_clock_atomic_check(struct drm_atomic_state *state) 84516e10105SMaxime Ripard { 84616e10105SMaxime Ripard struct vc4_dev *vc4 = to_vc4_dev(state->dev); 84716e10105SMaxime Ripard struct drm_private_state *priv_state; 84816e10105SMaxime Ripard struct vc4_hvs_state *hvs_new_state; 84916e10105SMaxime Ripard struct vc4_load_tracker_state *load_state; 85016e10105SMaxime Ripard struct drm_crtc_state *old_crtc_state, *new_crtc_state; 85116e10105SMaxime Ripard struct drm_crtc *crtc; 85216e10105SMaxime Ripard unsigned int num_outputs; 85316e10105SMaxime Ripard unsigned long pixel_rate; 85416e10105SMaxime Ripard unsigned long cob_rate; 85516e10105SMaxime Ripard unsigned int i; 85616e10105SMaxime Ripard 85716e10105SMaxime Ripard priv_state = drm_atomic_get_private_obj_state(state, 85816e10105SMaxime Ripard &vc4->load_tracker); 85916e10105SMaxime Ripard if (IS_ERR(priv_state)) 86016e10105SMaxime Ripard return PTR_ERR(priv_state); 86116e10105SMaxime Ripard 86216e10105SMaxime Ripard load_state = to_vc4_load_tracker_state(priv_state); 86316e10105SMaxime Ripard 86416e10105SMaxime Ripard hvs_new_state = vc4_hvs_get_global_state(state); 86516e10105SMaxime Ripard if (!hvs_new_state) 86616e10105SMaxime Ripard return -EINVAL; 86716e10105SMaxime Ripard 86816e10105SMaxime Ripard for_each_oldnew_crtc_in_state(state, crtc, 86916e10105SMaxime Ripard old_crtc_state, 87016e10105SMaxime Ripard new_crtc_state, 87116e10105SMaxime Ripard i) { 87216e10105SMaxime Ripard if (old_crtc_state->active) { 87316e10105SMaxime Ripard struct vc4_crtc_state *old_vc4_state = 87416e10105SMaxime Ripard to_vc4_crtc_state(old_crtc_state); 87516e10105SMaxime Ripard unsigned int channel = old_vc4_state->assigned_channel; 87616e10105SMaxime Ripard 87716e10105SMaxime Ripard hvs_new_state->fifo_state[channel].fifo_load = 0; 87816e10105SMaxime Ripard } 87916e10105SMaxime Ripard 88016e10105SMaxime Ripard if (new_crtc_state->active) { 88116e10105SMaxime Ripard struct vc4_crtc_state *new_vc4_state = 88216e10105SMaxime Ripard to_vc4_crtc_state(new_crtc_state); 88316e10105SMaxime Ripard unsigned int channel = new_vc4_state->assigned_channel; 88416e10105SMaxime Ripard 88516e10105SMaxime Ripard hvs_new_state->fifo_state[channel].fifo_load = 88616e10105SMaxime Ripard new_vc4_state->hvs_load; 88716e10105SMaxime Ripard } 88816e10105SMaxime Ripard } 88916e10105SMaxime Ripard 89016e10105SMaxime Ripard cob_rate = 0; 89116e10105SMaxime Ripard num_outputs = 0; 89216e10105SMaxime Ripard for (i = 0; i < HVS_NUM_CHANNELS; i++) { 89316e10105SMaxime Ripard if (!hvs_new_state->fifo_state[i].in_use) 89416e10105SMaxime Ripard continue; 89516e10105SMaxime Ripard 89616e10105SMaxime Ripard num_outputs++; 89716e10105SMaxime Ripard cob_rate += hvs_new_state->fifo_state[i].fifo_load; 89816e10105SMaxime Ripard } 89916e10105SMaxime Ripard 90016e10105SMaxime Ripard pixel_rate = load_state->hvs_load; 90116e10105SMaxime Ripard if (num_outputs > 1) { 90216e10105SMaxime Ripard pixel_rate = (pixel_rate * 40) / 100; 90316e10105SMaxime Ripard } else { 90416e10105SMaxime Ripard pixel_rate = (pixel_rate * 60) / 100; 90516e10105SMaxime Ripard } 90616e10105SMaxime Ripard 90716e10105SMaxime Ripard hvs_new_state->core_clock_rate = max(cob_rate, pixel_rate); 90816e10105SMaxime Ripard 90916e10105SMaxime Ripard return 0; 91016e10105SMaxime Ripard } 91116e10105SMaxime Ripard 91216e10105SMaxime Ripard 91316e10105SMaxime Ripard static int 914a72b0458SMaxime Ripard vc4_atomic_check(struct drm_device *dev, struct drm_atomic_state *state) 915a72b0458SMaxime Ripard { 916a72b0458SMaxime Ripard int ret; 917a72b0458SMaxime Ripard 918a72b0458SMaxime Ripard ret = vc4_pv_muxing_atomic_check(dev, state); 919a72b0458SMaxime Ripard if (ret) 920a72b0458SMaxime Ripard return ret; 921a72b0458SMaxime Ripard 922766cc6b1SStefan Schake ret = vc4_ctm_atomic_check(dev, state); 923766cc6b1SStefan Schake if (ret < 0) 924766cc6b1SStefan Schake return ret; 925766cc6b1SStefan Schake 9264686da83SBoris Brezillon ret = drm_atomic_helper_check(dev, state); 9274686da83SBoris Brezillon if (ret) 9284686da83SBoris Brezillon return ret; 9294686da83SBoris Brezillon 93016e10105SMaxime Ripard ret = vc4_load_tracker_atomic_check(state); 93116e10105SMaxime Ripard if (ret) 93216e10105SMaxime Ripard return ret; 93316e10105SMaxime Ripard 93416e10105SMaxime Ripard return vc4_core_clock_atomic_check(state); 935766cc6b1SStefan Schake } 936766cc6b1SStefan Schake 9379ec03d7fSMaxime Ripard static struct drm_mode_config_helper_funcs vc4_mode_config_helpers = { 9389ec03d7fSMaxime Ripard .atomic_commit_setup = vc4_atomic_commit_setup, 939f3c420feSMaxime Ripard .atomic_commit_tail = vc4_atomic_commit_tail, 9409ec03d7fSMaxime Ripard }; 9419ec03d7fSMaxime Ripard 942c8b75bcaSEric Anholt static const struct drm_mode_config_funcs vc4_mode_funcs = { 943766cc6b1SStefan Schake .atomic_check = vc4_atomic_check, 944f3c420feSMaxime Ripard .atomic_commit = drm_atomic_helper_commit, 94583753117SEric Anholt .fb_create = vc4_fb_create, 946c8b75bcaSEric Anholt }; 947c8b75bcaSEric Anholt 948c8b75bcaSEric Anholt int vc4_kms_load(struct drm_device *dev) 949c8b75bcaSEric Anholt { 95048666d56SDerek Foreman struct vc4_dev *vc4 = to_vc4_dev(dev); 951f437bc1eSMaxime Ripard bool is_vc5 = of_device_is_compatible(dev->dev->of_node, 952f437bc1eSMaxime Ripard "brcm,bcm2711-vc5"); 953c8b75bcaSEric Anholt int ret; 954c8b75bcaSEric Anholt 9557f817159SMaxime Ripard /* 9567f817159SMaxime Ripard * The limits enforced by the load tracker aren't relevant for 9577f817159SMaxime Ripard * the BCM2711, but the load tracker computations are used for 9587f817159SMaxime Ripard * the core clock rate calculation. 9597f817159SMaxime Ripard */ 960f437bc1eSMaxime Ripard if (!is_vc5) { 961f437bc1eSMaxime Ripard /* Start with the load tracker enabled. Can be 962f437bc1eSMaxime Ripard * disabled through the debugfs load_tracker file. 9636b5c029dSPaul Kocialkowski */ 9646b5c029dSPaul Kocialkowski vc4->load_tracker_enabled = true; 965f437bc1eSMaxime Ripard } 9666b5c029dSPaul Kocialkowski 9677d2818f5SMario Kleiner /* Set support for vblank irq fast disable, before drm_vblank_init() */ 9687d2818f5SMario Kleiner dev->vblank_disable_immediate = true; 9697d2818f5SMario Kleiner 970c8b75bcaSEric Anholt ret = drm_vblank_init(dev, dev->mode_config.num_crtc); 971c8b75bcaSEric Anholt if (ret < 0) { 972c8b75bcaSEric Anholt dev_err(dev->dev, "failed to initialize vblank\n"); 973c8b75bcaSEric Anholt return ret; 974c8b75bcaSEric Anholt } 975c8b75bcaSEric Anholt 976f437bc1eSMaxime Ripard if (is_vc5) { 977f437bc1eSMaxime Ripard dev->mode_config.max_width = 7680; 978f437bc1eSMaxime Ripard dev->mode_config.max_height = 7680; 979f437bc1eSMaxime Ripard } else { 980c8b75bcaSEric Anholt dev->mode_config.max_width = 2048; 981c8b75bcaSEric Anholt dev->mode_config.max_height = 2048; 982f437bc1eSMaxime Ripard } 983f437bc1eSMaxime Ripard 984c8b75bcaSEric Anholt dev->mode_config.funcs = &vc4_mode_funcs; 9859ec03d7fSMaxime Ripard dev->mode_config.helper_private = &vc4_mode_config_helpers; 986c8b75bcaSEric Anholt dev->mode_config.preferred_depth = 24; 987b501baccSEric Anholt dev->mode_config.async_page_flip = true; 988b501baccSEric Anholt 989dcda7c28SMaxime Ripard ret = vc4_ctm_obj_init(vc4); 990dcda7c28SMaxime Ripard if (ret) 991dcda7c28SMaxime Ripard return ret; 992766cc6b1SStefan Schake 993dcda7c28SMaxime Ripard ret = vc4_load_tracker_obj_init(vc4); 994dcda7c28SMaxime Ripard if (ret) 995dcda7c28SMaxime Ripard return ret; 9964686da83SBoris Brezillon 997f2df84e0SMaxime Ripard ret = vc4_hvs_channels_obj_init(vc4); 998f2df84e0SMaxime Ripard if (ret) 999f2df84e0SMaxime Ripard return ret; 1000f2df84e0SMaxime Ripard 1001c8b75bcaSEric Anholt drm_mode_config_reset(dev); 1002c8b75bcaSEric Anholt 1003c8b75bcaSEric Anholt drm_kms_helper_poll_init(dev); 1004c8b75bcaSEric Anholt 1005c8b75bcaSEric Anholt return 0; 1006c8b75bcaSEric Anholt } 1007