1d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2c8b75bcaSEric Anholt /* 3c8b75bcaSEric Anholt * Copyright (C) 2015 Broadcom 4c8b75bcaSEric Anholt */ 5c8b75bcaSEric Anholt 6c8b75bcaSEric Anholt /** 7c8b75bcaSEric Anholt * DOC: VC4 KMS 8c8b75bcaSEric Anholt * 9c8b75bcaSEric Anholt * This is the general code for implementing KMS mode setting that 10c8b75bcaSEric Anholt * doesn't clearly associate with any of the other objects (plane, 11c8b75bcaSEric Anholt * crtc, HDMI encoder). 12c8b75bcaSEric Anholt */ 13c8b75bcaSEric Anholt 14d7d96c00SMaxime Ripard #include <linux/clk.h> 15d7d96c00SMaxime Ripard 16b7e8e25bSMasahiro Yamada #include <drm/drm_atomic.h> 17b7e8e25bSMasahiro Yamada #include <drm/drm_atomic_helper.h> 18fd6d6d80SSam Ravnborg #include <drm/drm_crtc.h> 199762477cSNoralf Trønnes #include <drm/drm_gem_framebuffer_helper.h> 20fcd70cd3SDaniel Vetter #include <drm/drm_plane_helper.h> 21fcd70cd3SDaniel Vetter #include <drm/drm_probe_helper.h> 22fd6d6d80SSam Ravnborg #include <drm/drm_vblank.h> 23fd6d6d80SSam Ravnborg 24c8b75bcaSEric Anholt #include "vc4_drv.h" 25766cc6b1SStefan Schake #include "vc4_regs.h" 26766cc6b1SStefan Schake 27766cc6b1SStefan Schake struct vc4_ctm_state { 28766cc6b1SStefan Schake struct drm_private_state base; 29766cc6b1SStefan Schake struct drm_color_ctm *ctm; 30766cc6b1SStefan Schake int fifo; 31766cc6b1SStefan Schake }; 32766cc6b1SStefan Schake 33766cc6b1SStefan Schake static struct vc4_ctm_state *to_vc4_ctm_state(struct drm_private_state *priv) 34766cc6b1SStefan Schake { 35766cc6b1SStefan Schake return container_of(priv, struct vc4_ctm_state, base); 36766cc6b1SStefan Schake } 37766cc6b1SStefan Schake 384686da83SBoris Brezillon struct vc4_load_tracker_state { 394686da83SBoris Brezillon struct drm_private_state base; 404686da83SBoris Brezillon u64 hvs_load; 414686da83SBoris Brezillon u64 membus_load; 424686da83SBoris Brezillon }; 434686da83SBoris Brezillon 444686da83SBoris Brezillon static struct vc4_load_tracker_state * 454686da83SBoris Brezillon to_vc4_load_tracker_state(struct drm_private_state *priv) 464686da83SBoris Brezillon { 474686da83SBoris Brezillon return container_of(priv, struct vc4_load_tracker_state, base); 484686da83SBoris Brezillon } 494686da83SBoris Brezillon 50766cc6b1SStefan Schake static struct vc4_ctm_state *vc4_get_ctm_state(struct drm_atomic_state *state, 51766cc6b1SStefan Schake struct drm_private_obj *manager) 52766cc6b1SStefan Schake { 53766cc6b1SStefan Schake struct drm_device *dev = state->dev; 54766cc6b1SStefan Schake struct vc4_dev *vc4 = dev->dev_private; 55766cc6b1SStefan Schake struct drm_private_state *priv_state; 56766cc6b1SStefan Schake int ret; 57766cc6b1SStefan Schake 58766cc6b1SStefan Schake ret = drm_modeset_lock(&vc4->ctm_state_lock, state->acquire_ctx); 59766cc6b1SStefan Schake if (ret) 60766cc6b1SStefan Schake return ERR_PTR(ret); 61766cc6b1SStefan Schake 62766cc6b1SStefan Schake priv_state = drm_atomic_get_private_obj_state(state, manager); 63766cc6b1SStefan Schake if (IS_ERR(priv_state)) 64766cc6b1SStefan Schake return ERR_CAST(priv_state); 65766cc6b1SStefan Schake 66766cc6b1SStefan Schake return to_vc4_ctm_state(priv_state); 67766cc6b1SStefan Schake } 68766cc6b1SStefan Schake 69766cc6b1SStefan Schake static struct drm_private_state * 70766cc6b1SStefan Schake vc4_ctm_duplicate_state(struct drm_private_obj *obj) 71766cc6b1SStefan Schake { 72766cc6b1SStefan Schake struct vc4_ctm_state *state; 73766cc6b1SStefan Schake 74766cc6b1SStefan Schake state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL); 75766cc6b1SStefan Schake if (!state) 76766cc6b1SStefan Schake return NULL; 77766cc6b1SStefan Schake 78766cc6b1SStefan Schake __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base); 79766cc6b1SStefan Schake 80766cc6b1SStefan Schake return &state->base; 81766cc6b1SStefan Schake } 82766cc6b1SStefan Schake 83766cc6b1SStefan Schake static void vc4_ctm_destroy_state(struct drm_private_obj *obj, 84766cc6b1SStefan Schake struct drm_private_state *state) 85766cc6b1SStefan Schake { 86766cc6b1SStefan Schake struct vc4_ctm_state *ctm_state = to_vc4_ctm_state(state); 87766cc6b1SStefan Schake 88766cc6b1SStefan Schake kfree(ctm_state); 89766cc6b1SStefan Schake } 90766cc6b1SStefan Schake 91766cc6b1SStefan Schake static const struct drm_private_state_funcs vc4_ctm_state_funcs = { 92766cc6b1SStefan Schake .atomic_duplicate_state = vc4_ctm_duplicate_state, 93766cc6b1SStefan Schake .atomic_destroy_state = vc4_ctm_destroy_state, 94766cc6b1SStefan Schake }; 95766cc6b1SStefan Schake 96766cc6b1SStefan Schake /* Converts a DRM S31.32 value to the HW S0.9 format. */ 97766cc6b1SStefan Schake static u16 vc4_ctm_s31_32_to_s0_9(u64 in) 98766cc6b1SStefan Schake { 99766cc6b1SStefan Schake u16 r; 100766cc6b1SStefan Schake 101766cc6b1SStefan Schake /* Sign bit. */ 102766cc6b1SStefan Schake r = in & BIT_ULL(63) ? BIT(9) : 0; 103766cc6b1SStefan Schake 104766cc6b1SStefan Schake if ((in & GENMASK_ULL(62, 32)) > 0) { 105766cc6b1SStefan Schake /* We have zero integer bits so we can only saturate here. */ 106766cc6b1SStefan Schake r |= GENMASK(8, 0); 107766cc6b1SStefan Schake } else { 108766cc6b1SStefan Schake /* Otherwise take the 9 most important fractional bits. */ 109766cc6b1SStefan Schake r |= (in >> 23) & GENMASK(8, 0); 110766cc6b1SStefan Schake } 111766cc6b1SStefan Schake 112766cc6b1SStefan Schake return r; 113766cc6b1SStefan Schake } 114766cc6b1SStefan Schake 115766cc6b1SStefan Schake static void 116766cc6b1SStefan Schake vc4_ctm_commit(struct vc4_dev *vc4, struct drm_atomic_state *state) 117766cc6b1SStefan Schake { 118766cc6b1SStefan Schake struct vc4_ctm_state *ctm_state = to_vc4_ctm_state(vc4->ctm_manager.state); 119766cc6b1SStefan Schake struct drm_color_ctm *ctm = ctm_state->ctm; 120766cc6b1SStefan Schake 121766cc6b1SStefan Schake if (ctm_state->fifo) { 122766cc6b1SStefan Schake HVS_WRITE(SCALER_OLEDCOEF2, 123766cc6b1SStefan Schake VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[0]), 124766cc6b1SStefan Schake SCALER_OLEDCOEF2_R_TO_R) | 125766cc6b1SStefan Schake VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[3]), 126766cc6b1SStefan Schake SCALER_OLEDCOEF2_R_TO_G) | 127766cc6b1SStefan Schake VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[6]), 128766cc6b1SStefan Schake SCALER_OLEDCOEF2_R_TO_B)); 129766cc6b1SStefan Schake HVS_WRITE(SCALER_OLEDCOEF1, 130766cc6b1SStefan Schake VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[1]), 131766cc6b1SStefan Schake SCALER_OLEDCOEF1_G_TO_R) | 132766cc6b1SStefan Schake VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[4]), 133766cc6b1SStefan Schake SCALER_OLEDCOEF1_G_TO_G) | 134766cc6b1SStefan Schake VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[7]), 135766cc6b1SStefan Schake SCALER_OLEDCOEF1_G_TO_B)); 136766cc6b1SStefan Schake HVS_WRITE(SCALER_OLEDCOEF0, 137766cc6b1SStefan Schake VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[2]), 138766cc6b1SStefan Schake SCALER_OLEDCOEF0_B_TO_R) | 139766cc6b1SStefan Schake VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[5]), 140766cc6b1SStefan Schake SCALER_OLEDCOEF0_B_TO_G) | 141766cc6b1SStefan Schake VC4_SET_FIELD(vc4_ctm_s31_32_to_s0_9(ctm->matrix[8]), 142766cc6b1SStefan Schake SCALER_OLEDCOEF0_B_TO_B)); 143766cc6b1SStefan Schake } 144766cc6b1SStefan Schake 145766cc6b1SStefan Schake HVS_WRITE(SCALER_OLEDOFFS, 146766cc6b1SStefan Schake VC4_SET_FIELD(ctm_state->fifo, SCALER_OLEDOFFS_DISPFIFO)); 147766cc6b1SStefan Schake } 148c8b75bcaSEric Anholt 14987ebcd42SMaxime Ripard static void vc4_hvs_pv_muxing_commit(struct vc4_dev *vc4, 15087ebcd42SMaxime Ripard struct drm_atomic_state *state) 15187ebcd42SMaxime Ripard { 15287ebcd42SMaxime Ripard struct drm_crtc_state *crtc_state; 15387ebcd42SMaxime Ripard struct drm_crtc *crtc; 15487ebcd42SMaxime Ripard unsigned int i; 15587ebcd42SMaxime Ripard 15687ebcd42SMaxime Ripard for_each_new_crtc_in_state(state, crtc, crtc_state, i) { 15787ebcd42SMaxime Ripard struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state); 15887ebcd42SMaxime Ripard u32 dispctrl; 15987ebcd42SMaxime Ripard u32 dsp3_mux; 16087ebcd42SMaxime Ripard 16187ebcd42SMaxime Ripard if (!crtc_state->active) 16287ebcd42SMaxime Ripard continue; 16387ebcd42SMaxime Ripard 16487ebcd42SMaxime Ripard if (vc4_state->assigned_channel != 2) 16587ebcd42SMaxime Ripard continue; 16687ebcd42SMaxime Ripard 16787ebcd42SMaxime Ripard /* 16887ebcd42SMaxime Ripard * SCALER_DISPCTRL_DSP3 = X, where X < 2 means 'connect DSP3 to 16987ebcd42SMaxime Ripard * FIFO X'. 17087ebcd42SMaxime Ripard * SCALER_DISPCTRL_DSP3 = 3 means 'disable DSP 3'. 17187ebcd42SMaxime Ripard * 17287ebcd42SMaxime Ripard * DSP3 is connected to FIFO2 unless the transposer is 17387ebcd42SMaxime Ripard * enabled. In this case, FIFO 2 is directly accessed by the 17487ebcd42SMaxime Ripard * TXP IP, and we need to disable the FIFO2 -> pixelvalve1 17587ebcd42SMaxime Ripard * route. 17687ebcd42SMaxime Ripard */ 17787ebcd42SMaxime Ripard if (vc4_state->feed_txp) 17887ebcd42SMaxime Ripard dsp3_mux = VC4_SET_FIELD(3, SCALER_DISPCTRL_DSP3_MUX); 17987ebcd42SMaxime Ripard else 18087ebcd42SMaxime Ripard dsp3_mux = VC4_SET_FIELD(2, SCALER_DISPCTRL_DSP3_MUX); 18187ebcd42SMaxime Ripard 18287ebcd42SMaxime Ripard dispctrl = HVS_READ(SCALER_DISPCTRL) & 18387ebcd42SMaxime Ripard ~SCALER_DISPCTRL_DSP3_MUX_MASK; 18487ebcd42SMaxime Ripard HVS_WRITE(SCALER_DISPCTRL, dispctrl | dsp3_mux); 18587ebcd42SMaxime Ripard } 18687ebcd42SMaxime Ripard } 18787ebcd42SMaxime Ripard 18887ebcd42SMaxime Ripard static void vc5_hvs_pv_muxing_commit(struct vc4_dev *vc4, 18987ebcd42SMaxime Ripard struct drm_atomic_state *state) 19087ebcd42SMaxime Ripard { 19187ebcd42SMaxime Ripard struct drm_crtc_state *crtc_state; 19287ebcd42SMaxime Ripard struct drm_crtc *crtc; 19387ebcd42SMaxime Ripard unsigned char dsp2_mux = 0; 19487ebcd42SMaxime Ripard unsigned char dsp3_mux = 3; 19587ebcd42SMaxime Ripard unsigned char dsp4_mux = 3; 19687ebcd42SMaxime Ripard unsigned char dsp5_mux = 3; 19787ebcd42SMaxime Ripard unsigned int i; 19887ebcd42SMaxime Ripard u32 reg; 19987ebcd42SMaxime Ripard 20087ebcd42SMaxime Ripard for_each_new_crtc_in_state(state, crtc, crtc_state, i) { 20187ebcd42SMaxime Ripard struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state); 20287ebcd42SMaxime Ripard struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 20387ebcd42SMaxime Ripard 20487ebcd42SMaxime Ripard if (!crtc_state->active) 20587ebcd42SMaxime Ripard continue; 20687ebcd42SMaxime Ripard 20787ebcd42SMaxime Ripard switch (vc4_crtc->data->hvs_output) { 20887ebcd42SMaxime Ripard case 2: 20987ebcd42SMaxime Ripard dsp2_mux = (vc4_state->assigned_channel == 2) ? 0 : 1; 21087ebcd42SMaxime Ripard break; 21187ebcd42SMaxime Ripard 21287ebcd42SMaxime Ripard case 3: 21387ebcd42SMaxime Ripard dsp3_mux = vc4_state->assigned_channel; 21487ebcd42SMaxime Ripard break; 21587ebcd42SMaxime Ripard 21687ebcd42SMaxime Ripard case 4: 21787ebcd42SMaxime Ripard dsp4_mux = vc4_state->assigned_channel; 21887ebcd42SMaxime Ripard break; 21987ebcd42SMaxime Ripard 22087ebcd42SMaxime Ripard case 5: 22187ebcd42SMaxime Ripard dsp5_mux = vc4_state->assigned_channel; 22287ebcd42SMaxime Ripard break; 22387ebcd42SMaxime Ripard 22487ebcd42SMaxime Ripard default: 22587ebcd42SMaxime Ripard break; 22687ebcd42SMaxime Ripard } 22787ebcd42SMaxime Ripard } 22887ebcd42SMaxime Ripard 22987ebcd42SMaxime Ripard reg = HVS_READ(SCALER_DISPECTRL); 23087ebcd42SMaxime Ripard HVS_WRITE(SCALER_DISPECTRL, 23187ebcd42SMaxime Ripard (reg & ~SCALER_DISPECTRL_DSP2_MUX_MASK) | 23287ebcd42SMaxime Ripard VC4_SET_FIELD(dsp2_mux, SCALER_DISPECTRL_DSP2_MUX)); 23387ebcd42SMaxime Ripard 23487ebcd42SMaxime Ripard reg = HVS_READ(SCALER_DISPCTRL); 23587ebcd42SMaxime Ripard HVS_WRITE(SCALER_DISPCTRL, 23687ebcd42SMaxime Ripard (reg & ~SCALER_DISPCTRL_DSP3_MUX_MASK) | 23787ebcd42SMaxime Ripard VC4_SET_FIELD(dsp3_mux, SCALER_DISPCTRL_DSP3_MUX)); 23887ebcd42SMaxime Ripard 23987ebcd42SMaxime Ripard reg = HVS_READ(SCALER_DISPEOLN); 24087ebcd42SMaxime Ripard HVS_WRITE(SCALER_DISPEOLN, 24187ebcd42SMaxime Ripard (reg & ~SCALER_DISPEOLN_DSP4_MUX_MASK) | 24287ebcd42SMaxime Ripard VC4_SET_FIELD(dsp4_mux, SCALER_DISPEOLN_DSP4_MUX)); 24387ebcd42SMaxime Ripard 24487ebcd42SMaxime Ripard reg = HVS_READ(SCALER_DISPDITHER); 24587ebcd42SMaxime Ripard HVS_WRITE(SCALER_DISPDITHER, 24687ebcd42SMaxime Ripard (reg & ~SCALER_DISPDITHER_DSP5_MUX_MASK) | 24787ebcd42SMaxime Ripard VC4_SET_FIELD(dsp5_mux, SCALER_DISPDITHER_DSP5_MUX)); 24887ebcd42SMaxime Ripard } 24987ebcd42SMaxime Ripard 250b501baccSEric Anholt static void 251cf1b372eSEric Anholt vc4_atomic_complete_commit(struct drm_atomic_state *state) 252b501baccSEric Anholt { 253b501baccSEric Anholt struct drm_device *dev = state->dev; 254b501baccSEric Anholt struct vc4_dev *vc4 = to_vc4_dev(dev); 255d7d96c00SMaxime Ripard struct vc4_hvs *hvs = vc4->hvs; 25659635667SMaxime Ripard struct drm_crtc_state *new_crtc_state; 25759635667SMaxime Ripard struct drm_crtc *crtc; 258531a1b62SBoris Brezillon int i; 259531a1b62SBoris Brezillon 26059635667SMaxime Ripard for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { 26187ebcd42SMaxime Ripard struct vc4_crtc_state *vc4_crtc_state; 26259635667SMaxime Ripard 26359635667SMaxime Ripard if (!new_crtc_state->commit) 264531a1b62SBoris Brezillon continue; 265531a1b62SBoris Brezillon 26687ebcd42SMaxime Ripard vc4_crtc_state = to_vc4_crtc_state(new_crtc_state); 26787ebcd42SMaxime Ripard vc4_hvs_mask_underrun(dev, vc4_crtc_state->assigned_channel); 268531a1b62SBoris Brezillon } 269b501baccSEric Anholt 270d7d96c00SMaxime Ripard if (vc4->hvs->hvs5) 271d7d96c00SMaxime Ripard clk_set_min_rate(hvs->core_clk, 500000000); 272d7d96c00SMaxime Ripard 27334c8ea40SBoris Brezillon drm_atomic_helper_wait_for_fences(dev, state, false); 27434c8ea40SBoris Brezillon 27534c8ea40SBoris Brezillon drm_atomic_helper_wait_for_dependencies(state); 27634c8ea40SBoris Brezillon 277b501baccSEric Anholt drm_atomic_helper_commit_modeset_disables(dev, state); 278b501baccSEric Anholt 279766cc6b1SStefan Schake vc4_ctm_commit(vc4, state); 280766cc6b1SStefan Schake 28187ebcd42SMaxime Ripard if (vc4->hvs->hvs5) 28287ebcd42SMaxime Ripard vc5_hvs_pv_muxing_commit(vc4, state); 28387ebcd42SMaxime Ripard else 28487ebcd42SMaxime Ripard vc4_hvs_pv_muxing_commit(vc4, state); 28587ebcd42SMaxime Ripard 2862b58e98dSLiu Ying drm_atomic_helper_commit_planes(dev, state, 0); 287b501baccSEric Anholt 288b501baccSEric Anholt drm_atomic_helper_commit_modeset_enables(dev, state); 289b501baccSEric Anholt 2901ebe99a7SBoris Brezillon drm_atomic_helper_fake_vblank(state); 2911ebe99a7SBoris Brezillon 29234c8ea40SBoris Brezillon drm_atomic_helper_commit_hw_done(state); 29334c8ea40SBoris Brezillon 294184d3cf4SBoris Brezillon drm_atomic_helper_wait_for_flip_done(dev, state); 295b501baccSEric Anholt 296b501baccSEric Anholt drm_atomic_helper_cleanup_planes(dev, state); 297b501baccSEric Anholt 29834c8ea40SBoris Brezillon drm_atomic_helper_commit_cleanup_done(state); 29934c8ea40SBoris Brezillon 300d7d96c00SMaxime Ripard if (vc4->hvs->hvs5) 301d7d96c00SMaxime Ripard clk_set_min_rate(hvs->core_clk, 0); 302d7d96c00SMaxime Ripard 3030853695cSChris Wilson drm_atomic_state_put(state); 304b501baccSEric Anholt 305b501baccSEric Anholt up(&vc4->async_modeset); 306b501baccSEric Anholt } 307b501baccSEric Anholt 308cf1b372eSEric Anholt static void commit_work(struct work_struct *work) 309b501baccSEric Anholt { 310cf1b372eSEric Anholt struct drm_atomic_state *state = container_of(work, 311cf1b372eSEric Anholt struct drm_atomic_state, 312cf1b372eSEric Anholt commit_work); 313cf1b372eSEric Anholt vc4_atomic_complete_commit(state); 314b501baccSEric Anholt } 315b501baccSEric Anholt 316b501baccSEric Anholt /** 317b501baccSEric Anholt * vc4_atomic_commit - commit validated state object 318b501baccSEric Anholt * @dev: DRM device 319b501baccSEric Anholt * @state: the driver state object 320eb63961bSMaarten Lankhorst * @nonblock: nonblocking commit 321b501baccSEric Anholt * 322b501baccSEric Anholt * This function commits a with drm_atomic_helper_check() pre-validated state 323b501baccSEric Anholt * object. This can still fail when e.g. the framebuffer reservation fails. For 324b501baccSEric Anholt * now this doesn't implement asynchronous commits. 325b501baccSEric Anholt * 326b501baccSEric Anholt * RETURNS 327b501baccSEric Anholt * Zero for success or -errno. 328b501baccSEric Anholt */ 329b501baccSEric Anholt static int vc4_atomic_commit(struct drm_device *dev, 330b501baccSEric Anholt struct drm_atomic_state *state, 331eb63961bSMaarten Lankhorst bool nonblock) 332b501baccSEric Anholt { 333b501baccSEric Anholt struct vc4_dev *vc4 = to_vc4_dev(dev); 334b501baccSEric Anholt int ret; 335b501baccSEric Anholt 336539c320bSGustavo Padovan if (state->async_update) { 337539c320bSGustavo Padovan ret = down_interruptible(&vc4->async_modeset); 338539c320bSGustavo Padovan if (ret) 339539c320bSGustavo Padovan return ret; 340539c320bSGustavo Padovan 341539c320bSGustavo Padovan ret = drm_atomic_helper_prepare_planes(dev, state); 342539c320bSGustavo Padovan if (ret) { 343539c320bSGustavo Padovan up(&vc4->async_modeset); 344539c320bSGustavo Padovan return ret; 345539c320bSGustavo Padovan } 346539c320bSGustavo Padovan 347539c320bSGustavo Padovan drm_atomic_helper_async_commit(dev, state); 348539c320bSGustavo Padovan 349539c320bSGustavo Padovan drm_atomic_helper_cleanup_planes(dev, state); 350539c320bSGustavo Padovan 351539c320bSGustavo Padovan up(&vc4->async_modeset); 352539c320bSGustavo Padovan 353539c320bSGustavo Padovan return 0; 354539c320bSGustavo Padovan } 355539c320bSGustavo Padovan 356fcc86cb4SBoris Brezillon /* We know for sure we don't want an async update here. Set 357fcc86cb4SBoris Brezillon * state->legacy_cursor_update to false to prevent 358fcc86cb4SBoris Brezillon * drm_atomic_helper_setup_commit() from auto-completing 359fcc86cb4SBoris Brezillon * commit->flip_done. 360fcc86cb4SBoris Brezillon */ 361fcc86cb4SBoris Brezillon state->legacy_cursor_update = false; 36234c8ea40SBoris Brezillon ret = drm_atomic_helper_setup_commit(state, nonblock); 36334c8ea40SBoris Brezillon if (ret) 36434c8ea40SBoris Brezillon return ret; 36526fc78f6SDerek Foreman 366cf1b372eSEric Anholt INIT_WORK(&state->commit_work, commit_work); 367cf1b372eSEric Anholt 368b501baccSEric Anholt ret = down_interruptible(&vc4->async_modeset); 369cf1b372eSEric Anholt if (ret) 370b501baccSEric Anholt return ret; 371b501baccSEric Anholt 372b501baccSEric Anholt ret = drm_atomic_helper_prepare_planes(dev, state); 373b501baccSEric Anholt if (ret) { 374b501baccSEric Anholt up(&vc4->async_modeset); 375b501baccSEric Anholt return ret; 376b501baccSEric Anholt } 377b501baccSEric Anholt 37853ad0694SEric Anholt if (!nonblock) { 37953ad0694SEric Anholt ret = drm_atomic_helper_wait_for_fences(dev, state, true); 38053ad0694SEric Anholt if (ret) { 38153ad0694SEric Anholt drm_atomic_helper_cleanup_planes(dev, state); 38253ad0694SEric Anholt up(&vc4->async_modeset); 38353ad0694SEric Anholt return ret; 38453ad0694SEric Anholt } 38553ad0694SEric Anholt } 38653ad0694SEric Anholt 387b501baccSEric Anholt /* 388b501baccSEric Anholt * This is the point of no return - everything below never fails except 389b501baccSEric Anholt * when the hw goes bonghits. Which means we can commit the new state on 390b501baccSEric Anholt * the software side now. 391b501baccSEric Anholt */ 392b501baccSEric Anholt 393d68bc0e7SMaarten Lankhorst BUG_ON(drm_atomic_helper_swap_state(state, false) < 0); 394b501baccSEric Anholt 395b501baccSEric Anholt /* 396b501baccSEric Anholt * Everything below can be run asynchronously without the need to grab 397b501baccSEric Anholt * any modeset locks at all under one condition: It must be guaranteed 398b501baccSEric Anholt * that the asynchronous work has either been cancelled (if the driver 399b501baccSEric Anholt * supports it, which at least requires that the framebuffers get 400b501baccSEric Anholt * cleaned up with drm_atomic_helper_cleanup_planes()) or completed 401b501baccSEric Anholt * before the new state gets committed on the software side with 402b501baccSEric Anholt * drm_atomic_helper_swap_state(). 403b501baccSEric Anholt * 404b501baccSEric Anholt * This scheme allows new atomic state updates to be prepared and 405b501baccSEric Anholt * checked in parallel to the asynchronous completion of the previous 406b501baccSEric Anholt * update. Which is important since compositors need to figure out the 407b501baccSEric Anholt * composition of the next frame right after having submitted the 408b501baccSEric Anholt * current layout. 409b501baccSEric Anholt */ 410b501baccSEric Anholt 4110853695cSChris Wilson drm_atomic_state_get(state); 412cf1b372eSEric Anholt if (nonblock) 413cf1b372eSEric Anholt queue_work(system_unbound_wq, &state->commit_work); 414cf1b372eSEric Anholt else 415cf1b372eSEric Anholt vc4_atomic_complete_commit(state); 416b501baccSEric Anholt 417b501baccSEric Anholt return 0; 418b501baccSEric Anholt } 419b501baccSEric Anholt 42083753117SEric Anholt static struct drm_framebuffer *vc4_fb_create(struct drm_device *dev, 42183753117SEric Anholt struct drm_file *file_priv, 42283753117SEric Anholt const struct drm_mode_fb_cmd2 *mode_cmd) 42383753117SEric Anholt { 42483753117SEric Anholt struct drm_mode_fb_cmd2 mode_cmd_local; 42583753117SEric Anholt 42683753117SEric Anholt /* If the user didn't specify a modifier, use the 42783753117SEric Anholt * vc4_set_tiling_ioctl() state for the BO. 42883753117SEric Anholt */ 42983753117SEric Anholt if (!(mode_cmd->flags & DRM_MODE_FB_MODIFIERS)) { 43083753117SEric Anholt struct drm_gem_object *gem_obj; 43183753117SEric Anholt struct vc4_bo *bo; 43283753117SEric Anholt 43383753117SEric Anholt gem_obj = drm_gem_object_lookup(file_priv, 43483753117SEric Anholt mode_cmd->handles[0]); 43583753117SEric Anholt if (!gem_obj) { 436fb95992aSEric Anholt DRM_DEBUG("Failed to look up GEM BO %d\n", 43783753117SEric Anholt mode_cmd->handles[0]); 43883753117SEric Anholt return ERR_PTR(-ENOENT); 43983753117SEric Anholt } 44083753117SEric Anholt bo = to_vc4_bo(gem_obj); 44183753117SEric Anholt 44283753117SEric Anholt mode_cmd_local = *mode_cmd; 44383753117SEric Anholt 44483753117SEric Anholt if (bo->t_format) { 44583753117SEric Anholt mode_cmd_local.modifier[0] = 44683753117SEric Anholt DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED; 44783753117SEric Anholt } else { 44883753117SEric Anholt mode_cmd_local.modifier[0] = DRM_FORMAT_MOD_NONE; 44983753117SEric Anholt } 45083753117SEric Anholt 451f7a8cd30SEmil Velikov drm_gem_object_put(gem_obj); 45283753117SEric Anholt 45383753117SEric Anholt mode_cmd = &mode_cmd_local; 45483753117SEric Anholt } 45583753117SEric Anholt 4569762477cSNoralf Trønnes return drm_gem_fb_create(dev, file_priv, mode_cmd); 45783753117SEric Anholt } 45883753117SEric Anholt 459766cc6b1SStefan Schake /* Our CTM has some peculiar limitations: we can only enable it for one CRTC 460766cc6b1SStefan Schake * at a time and the HW only supports S0.9 scalars. To account for the latter, 461766cc6b1SStefan Schake * we don't allow userland to set a CTM that we have no hope of approximating. 462766cc6b1SStefan Schake */ 463766cc6b1SStefan Schake static int 464766cc6b1SStefan Schake vc4_ctm_atomic_check(struct drm_device *dev, struct drm_atomic_state *state) 465766cc6b1SStefan Schake { 466766cc6b1SStefan Schake struct vc4_dev *vc4 = to_vc4_dev(dev); 467766cc6b1SStefan Schake struct vc4_ctm_state *ctm_state = NULL; 468766cc6b1SStefan Schake struct drm_crtc *crtc; 469766cc6b1SStefan Schake struct drm_crtc_state *old_crtc_state, *new_crtc_state; 470766cc6b1SStefan Schake struct drm_color_ctm *ctm; 471766cc6b1SStefan Schake int i; 472766cc6b1SStefan Schake 473766cc6b1SStefan Schake for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 474766cc6b1SStefan Schake /* CTM is being disabled. */ 475766cc6b1SStefan Schake if (!new_crtc_state->ctm && old_crtc_state->ctm) { 476766cc6b1SStefan Schake ctm_state = vc4_get_ctm_state(state, &vc4->ctm_manager); 477766cc6b1SStefan Schake if (IS_ERR(ctm_state)) 478766cc6b1SStefan Schake return PTR_ERR(ctm_state); 479766cc6b1SStefan Schake ctm_state->fifo = 0; 480766cc6b1SStefan Schake } 481766cc6b1SStefan Schake } 482766cc6b1SStefan Schake 483766cc6b1SStefan Schake for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { 484766cc6b1SStefan Schake if (new_crtc_state->ctm == old_crtc_state->ctm) 485766cc6b1SStefan Schake continue; 486766cc6b1SStefan Schake 487766cc6b1SStefan Schake if (!ctm_state) { 488766cc6b1SStefan Schake ctm_state = vc4_get_ctm_state(state, &vc4->ctm_manager); 489766cc6b1SStefan Schake if (IS_ERR(ctm_state)) 490766cc6b1SStefan Schake return PTR_ERR(ctm_state); 491766cc6b1SStefan Schake } 492766cc6b1SStefan Schake 493766cc6b1SStefan Schake /* CTM is being enabled or the matrix changed. */ 494766cc6b1SStefan Schake if (new_crtc_state->ctm) { 49587ebcd42SMaxime Ripard struct vc4_crtc_state *vc4_crtc_state = 49687ebcd42SMaxime Ripard to_vc4_crtc_state(new_crtc_state); 49787ebcd42SMaxime Ripard 498766cc6b1SStefan Schake /* fifo is 1-based since 0 disables CTM. */ 49987ebcd42SMaxime Ripard int fifo = vc4_crtc_state->assigned_channel + 1; 500766cc6b1SStefan Schake 501766cc6b1SStefan Schake /* Check userland isn't trying to turn on CTM for more 502766cc6b1SStefan Schake * than one CRTC at a time. 503766cc6b1SStefan Schake */ 504766cc6b1SStefan Schake if (ctm_state->fifo && ctm_state->fifo != fifo) { 505766cc6b1SStefan Schake DRM_DEBUG_DRIVER("Too many CTM configured\n"); 506766cc6b1SStefan Schake return -EINVAL; 507766cc6b1SStefan Schake } 508766cc6b1SStefan Schake 509766cc6b1SStefan Schake /* Check we can approximate the specified CTM. 510766cc6b1SStefan Schake * We disallow scalars |c| > 1.0 since the HW has 511766cc6b1SStefan Schake * no integer bits. 512766cc6b1SStefan Schake */ 513766cc6b1SStefan Schake ctm = new_crtc_state->ctm->data; 514766cc6b1SStefan Schake for (i = 0; i < ARRAY_SIZE(ctm->matrix); i++) { 515766cc6b1SStefan Schake u64 val = ctm->matrix[i]; 516766cc6b1SStefan Schake 517766cc6b1SStefan Schake val &= ~BIT_ULL(63); 518766cc6b1SStefan Schake if (val > BIT_ULL(32)) 519766cc6b1SStefan Schake return -EINVAL; 520766cc6b1SStefan Schake } 521766cc6b1SStefan Schake 522766cc6b1SStefan Schake ctm_state->fifo = fifo; 523766cc6b1SStefan Schake ctm_state->ctm = ctm; 524766cc6b1SStefan Schake } 525766cc6b1SStefan Schake } 526766cc6b1SStefan Schake 527766cc6b1SStefan Schake return 0; 528766cc6b1SStefan Schake } 529766cc6b1SStefan Schake 5304686da83SBoris Brezillon static int vc4_load_tracker_atomic_check(struct drm_atomic_state *state) 5314686da83SBoris Brezillon { 5324686da83SBoris Brezillon struct drm_plane_state *old_plane_state, *new_plane_state; 5334686da83SBoris Brezillon struct vc4_dev *vc4 = to_vc4_dev(state->dev); 5344686da83SBoris Brezillon struct vc4_load_tracker_state *load_state; 5354686da83SBoris Brezillon struct drm_private_state *priv_state; 5364686da83SBoris Brezillon struct drm_plane *plane; 5374686da83SBoris Brezillon int i; 5384686da83SBoris Brezillon 539f437bc1eSMaxime Ripard if (!vc4->load_tracker_available) 540f437bc1eSMaxime Ripard return 0; 541f437bc1eSMaxime Ripard 5424686da83SBoris Brezillon priv_state = drm_atomic_get_private_obj_state(state, 5434686da83SBoris Brezillon &vc4->load_tracker); 5444686da83SBoris Brezillon if (IS_ERR(priv_state)) 5454686da83SBoris Brezillon return PTR_ERR(priv_state); 5464686da83SBoris Brezillon 5474686da83SBoris Brezillon load_state = to_vc4_load_tracker_state(priv_state); 5484686da83SBoris Brezillon for_each_oldnew_plane_in_state(state, plane, old_plane_state, 5494686da83SBoris Brezillon new_plane_state, i) { 5504686da83SBoris Brezillon struct vc4_plane_state *vc4_plane_state; 5514686da83SBoris Brezillon 5524686da83SBoris Brezillon if (old_plane_state->fb && old_plane_state->crtc) { 5534686da83SBoris Brezillon vc4_plane_state = to_vc4_plane_state(old_plane_state); 5544686da83SBoris Brezillon load_state->membus_load -= vc4_plane_state->membus_load; 5554686da83SBoris Brezillon load_state->hvs_load -= vc4_plane_state->hvs_load; 5564686da83SBoris Brezillon } 5574686da83SBoris Brezillon 5584686da83SBoris Brezillon if (new_plane_state->fb && new_plane_state->crtc) { 5594686da83SBoris Brezillon vc4_plane_state = to_vc4_plane_state(new_plane_state); 5604686da83SBoris Brezillon load_state->membus_load += vc4_plane_state->membus_load; 5614686da83SBoris Brezillon load_state->hvs_load += vc4_plane_state->hvs_load; 5624686da83SBoris Brezillon } 5634686da83SBoris Brezillon } 5644686da83SBoris Brezillon 5656b5c029dSPaul Kocialkowski /* Don't check the load when the tracker is disabled. */ 5666b5c029dSPaul Kocialkowski if (!vc4->load_tracker_enabled) 5676b5c029dSPaul Kocialkowski return 0; 5686b5c029dSPaul Kocialkowski 5694686da83SBoris Brezillon /* The absolute limit is 2Gbyte/sec, but let's take a margin to let 5704686da83SBoris Brezillon * the system work when other blocks are accessing the memory. 5714686da83SBoris Brezillon */ 5724686da83SBoris Brezillon if (load_state->membus_load > SZ_1G + SZ_512M) 5734686da83SBoris Brezillon return -ENOSPC; 5744686da83SBoris Brezillon 5754686da83SBoris Brezillon /* HVS clock is supposed to run @ 250Mhz, let's take a margin and 5764686da83SBoris Brezillon * consider the maximum number of cycles is 240M. 5774686da83SBoris Brezillon */ 5784686da83SBoris Brezillon if (load_state->hvs_load > 240000000ULL) 5794686da83SBoris Brezillon return -ENOSPC; 5804686da83SBoris Brezillon 5814686da83SBoris Brezillon return 0; 5824686da83SBoris Brezillon } 5834686da83SBoris Brezillon 5844686da83SBoris Brezillon static struct drm_private_state * 5854686da83SBoris Brezillon vc4_load_tracker_duplicate_state(struct drm_private_obj *obj) 5864686da83SBoris Brezillon { 5874686da83SBoris Brezillon struct vc4_load_tracker_state *state; 5884686da83SBoris Brezillon 5894686da83SBoris Brezillon state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL); 5904686da83SBoris Brezillon if (!state) 5914686da83SBoris Brezillon return NULL; 5924686da83SBoris Brezillon 5934686da83SBoris Brezillon __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base); 5944686da83SBoris Brezillon 5954686da83SBoris Brezillon return &state->base; 5964686da83SBoris Brezillon } 5974686da83SBoris Brezillon 5984686da83SBoris Brezillon static void vc4_load_tracker_destroy_state(struct drm_private_obj *obj, 5994686da83SBoris Brezillon struct drm_private_state *state) 6004686da83SBoris Brezillon { 6014686da83SBoris Brezillon struct vc4_load_tracker_state *load_state; 6024686da83SBoris Brezillon 6034686da83SBoris Brezillon load_state = to_vc4_load_tracker_state(state); 6044686da83SBoris Brezillon kfree(load_state); 6054686da83SBoris Brezillon } 6064686da83SBoris Brezillon 6074686da83SBoris Brezillon static const struct drm_private_state_funcs vc4_load_tracker_state_funcs = { 6084686da83SBoris Brezillon .atomic_duplicate_state = vc4_load_tracker_duplicate_state, 6094686da83SBoris Brezillon .atomic_destroy_state = vc4_load_tracker_destroy_state, 6104686da83SBoris Brezillon }; 6114686da83SBoris Brezillon 61287ebcd42SMaxime Ripard #define NUM_OUTPUTS 6 61387ebcd42SMaxime Ripard #define NUM_CHANNELS 3 61487ebcd42SMaxime Ripard 615766cc6b1SStefan Schake static int 616766cc6b1SStefan Schake vc4_atomic_check(struct drm_device *dev, struct drm_atomic_state *state) 617766cc6b1SStefan Schake { 61887ebcd42SMaxime Ripard unsigned long unassigned_channels = GENMASK(NUM_CHANNELS - 1, 0); 61987ebcd42SMaxime Ripard struct drm_crtc_state *crtc_state; 62087ebcd42SMaxime Ripard struct drm_crtc *crtc; 62187ebcd42SMaxime Ripard int i, ret; 62287ebcd42SMaxime Ripard 623089d8341SMaxime Ripard /* 624089d8341SMaxime Ripard * Since the HVS FIFOs are shared across all the pixelvalves and 625089d8341SMaxime Ripard * the TXP (and thus all the CRTCs), we need to pull the current 626089d8341SMaxime Ripard * state of all the enabled CRTCs so that an update to a single 627089d8341SMaxime Ripard * CRTC still keeps the previous FIFOs enabled and assigned to 628089d8341SMaxime Ripard * the same CRTCs, instead of evaluating only the CRTC being 629089d8341SMaxime Ripard * modified. 630089d8341SMaxime Ripard */ 631089d8341SMaxime Ripard list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 632089d8341SMaxime Ripard if (!crtc->state->enable) 633089d8341SMaxime Ripard continue; 634089d8341SMaxime Ripard 635089d8341SMaxime Ripard crtc_state = drm_atomic_get_crtc_state(state, crtc); 636089d8341SMaxime Ripard if (IS_ERR(crtc_state)) 637089d8341SMaxime Ripard return PTR_ERR(crtc_state); 638089d8341SMaxime Ripard } 639089d8341SMaxime Ripard 64087ebcd42SMaxime Ripard for_each_new_crtc_in_state(state, crtc, crtc_state, i) { 64187ebcd42SMaxime Ripard struct vc4_crtc_state *vc4_crtc_state = 64287ebcd42SMaxime Ripard to_vc4_crtc_state(crtc_state); 64387ebcd42SMaxime Ripard struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 64487ebcd42SMaxime Ripard unsigned int matching_channels; 64587ebcd42SMaxime Ripard 64687ebcd42SMaxime Ripard if (!crtc_state->active) 64787ebcd42SMaxime Ripard continue; 64887ebcd42SMaxime Ripard 64987ebcd42SMaxime Ripard /* 65087ebcd42SMaxime Ripard * The problem we have to solve here is that we have 65187ebcd42SMaxime Ripard * up to 7 encoders, connected to up to 6 CRTCs. 65287ebcd42SMaxime Ripard * 65387ebcd42SMaxime Ripard * Those CRTCs, depending on the instance, can be 65487ebcd42SMaxime Ripard * routed to 1, 2 or 3 HVS FIFOs, and we need to set 65587ebcd42SMaxime Ripard * the change the muxing between FIFOs and outputs in 65687ebcd42SMaxime Ripard * the HVS accordingly. 65787ebcd42SMaxime Ripard * 65887ebcd42SMaxime Ripard * It would be pretty hard to come up with an 65987ebcd42SMaxime Ripard * algorithm that would generically solve 66087ebcd42SMaxime Ripard * this. However, the current routing trees we support 66187ebcd42SMaxime Ripard * allow us to simplify a bit the problem. 66287ebcd42SMaxime Ripard * 66387ebcd42SMaxime Ripard * Indeed, with the current supported layouts, if we 66487ebcd42SMaxime Ripard * try to assign in the ascending crtc index order the 66587ebcd42SMaxime Ripard * FIFOs, we can't fall into the situation where an 66687ebcd42SMaxime Ripard * earlier CRTC that had multiple routes is assigned 66787ebcd42SMaxime Ripard * one that was the only option for a later CRTC. 66887ebcd42SMaxime Ripard * 66987ebcd42SMaxime Ripard * If the layout changes and doesn't give us that in 67087ebcd42SMaxime Ripard * the future, we will need to have something smarter, 67187ebcd42SMaxime Ripard * but it works so far. 67287ebcd42SMaxime Ripard */ 67387ebcd42SMaxime Ripard matching_channels = unassigned_channels & vc4_crtc->data->hvs_available_channels; 67487ebcd42SMaxime Ripard if (matching_channels) { 67587ebcd42SMaxime Ripard unsigned int channel = ffs(matching_channels) - 1; 67687ebcd42SMaxime Ripard 67787ebcd42SMaxime Ripard vc4_crtc_state->assigned_channel = channel; 67887ebcd42SMaxime Ripard unassigned_channels &= ~BIT(channel); 67987ebcd42SMaxime Ripard } else { 68087ebcd42SMaxime Ripard return -EINVAL; 68187ebcd42SMaxime Ripard } 68287ebcd42SMaxime Ripard } 683766cc6b1SStefan Schake 684766cc6b1SStefan Schake ret = vc4_ctm_atomic_check(dev, state); 685766cc6b1SStefan Schake if (ret < 0) 686766cc6b1SStefan Schake return ret; 687766cc6b1SStefan Schake 6884686da83SBoris Brezillon ret = drm_atomic_helper_check(dev, state); 6894686da83SBoris Brezillon if (ret) 6904686da83SBoris Brezillon return ret; 6914686da83SBoris Brezillon 6924686da83SBoris Brezillon return vc4_load_tracker_atomic_check(state); 693766cc6b1SStefan Schake } 694766cc6b1SStefan Schake 695c8b75bcaSEric Anholt static const struct drm_mode_config_funcs vc4_mode_funcs = { 696766cc6b1SStefan Schake .atomic_check = vc4_atomic_check, 697b501baccSEric Anholt .atomic_commit = vc4_atomic_commit, 69883753117SEric Anholt .fb_create = vc4_fb_create, 699c8b75bcaSEric Anholt }; 700c8b75bcaSEric Anholt 701c8b75bcaSEric Anholt int vc4_kms_load(struct drm_device *dev) 702c8b75bcaSEric Anholt { 70348666d56SDerek Foreman struct vc4_dev *vc4 = to_vc4_dev(dev); 704766cc6b1SStefan Schake struct vc4_ctm_state *ctm_state; 7054686da83SBoris Brezillon struct vc4_load_tracker_state *load_state; 706f437bc1eSMaxime Ripard bool is_vc5 = of_device_is_compatible(dev->dev->of_node, 707f437bc1eSMaxime Ripard "brcm,bcm2711-vc5"); 708c8b75bcaSEric Anholt int ret; 709c8b75bcaSEric Anholt 710f437bc1eSMaxime Ripard if (!is_vc5) { 711f437bc1eSMaxime Ripard vc4->load_tracker_available = true; 712f437bc1eSMaxime Ripard 713f437bc1eSMaxime Ripard /* Start with the load tracker enabled. Can be 714f437bc1eSMaxime Ripard * disabled through the debugfs load_tracker file. 7156b5c029dSPaul Kocialkowski */ 7166b5c029dSPaul Kocialkowski vc4->load_tracker_enabled = true; 717f437bc1eSMaxime Ripard } 7186b5c029dSPaul Kocialkowski 719b501baccSEric Anholt sema_init(&vc4->async_modeset, 1); 720b501baccSEric Anholt 7217d2818f5SMario Kleiner /* Set support for vblank irq fast disable, before drm_vblank_init() */ 7227d2818f5SMario Kleiner dev->vblank_disable_immediate = true; 7237d2818f5SMario Kleiner 724ffc26740SEric Anholt dev->irq_enabled = true; 725c8b75bcaSEric Anholt ret = drm_vblank_init(dev, dev->mode_config.num_crtc); 726c8b75bcaSEric Anholt if (ret < 0) { 727c8b75bcaSEric Anholt dev_err(dev->dev, "failed to initialize vblank\n"); 728c8b75bcaSEric Anholt return ret; 729c8b75bcaSEric Anholt } 730c8b75bcaSEric Anholt 731f437bc1eSMaxime Ripard if (is_vc5) { 732f437bc1eSMaxime Ripard dev->mode_config.max_width = 7680; 733f437bc1eSMaxime Ripard dev->mode_config.max_height = 7680; 734f437bc1eSMaxime Ripard } else { 735c8b75bcaSEric Anholt dev->mode_config.max_width = 2048; 736c8b75bcaSEric Anholt dev->mode_config.max_height = 2048; 737f437bc1eSMaxime Ripard } 738f437bc1eSMaxime Ripard 739c8b75bcaSEric Anholt dev->mode_config.funcs = &vc4_mode_funcs; 740c8b75bcaSEric Anholt dev->mode_config.preferred_depth = 24; 741b501baccSEric Anholt dev->mode_config.async_page_flip = true; 742423ad7b3SDaniel Stone dev->mode_config.allow_fb_modifiers = true; 743b501baccSEric Anholt 744766cc6b1SStefan Schake drm_modeset_lock_init(&vc4->ctm_state_lock); 745766cc6b1SStefan Schake 746766cc6b1SStefan Schake ctm_state = kzalloc(sizeof(*ctm_state), GFP_KERNEL); 747766cc6b1SStefan Schake if (!ctm_state) 748766cc6b1SStefan Schake return -ENOMEM; 749b962a120SRob Clark 750b962a120SRob Clark drm_atomic_private_obj_init(dev, &vc4->ctm_manager, &ctm_state->base, 751766cc6b1SStefan Schake &vc4_ctm_state_funcs); 752766cc6b1SStefan Schake 753f437bc1eSMaxime Ripard if (vc4->load_tracker_available) { 7544686da83SBoris Brezillon load_state = kzalloc(sizeof(*load_state), GFP_KERNEL); 7554686da83SBoris Brezillon if (!load_state) { 7564686da83SBoris Brezillon drm_atomic_private_obj_fini(&vc4->ctm_manager); 7574686da83SBoris Brezillon return -ENOMEM; 7584686da83SBoris Brezillon } 7594686da83SBoris Brezillon 760f437bc1eSMaxime Ripard drm_atomic_private_obj_init(dev, &vc4->load_tracker, 761f437bc1eSMaxime Ripard &load_state->base, 7624686da83SBoris Brezillon &vc4_load_tracker_state_funcs); 763f437bc1eSMaxime Ripard } 7644686da83SBoris Brezillon 765c8b75bcaSEric Anholt drm_mode_config_reset(dev); 766c8b75bcaSEric Anholt 767c8b75bcaSEric Anholt drm_kms_helper_poll_init(dev); 768c8b75bcaSEric Anholt 769c8b75bcaSEric Anholt return 0; 770c8b75bcaSEric Anholt } 771