1 /* 2 * Copyright © 2014 Broadcom 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24 /** 25 * DOC: Interrupt management for the V3D engine 26 * 27 * We have an interrupt status register (V3D_INTCTL) which reports 28 * interrupts, and where writing 1 bits clears those interrupts. 29 * There are also a pair of interrupt registers 30 * (V3D_INTENA/V3D_INTDIS) where writing a 1 to their bits enables or 31 * disables that specific interrupt, and 0s written are ignored 32 * (reading either one returns the set of enabled interrupts). 33 * 34 * When we take a binning flush done interrupt, we need to submit the 35 * next frame for binning and move the finished frame to the render 36 * thread. 37 * 38 * When we take a render frame interrupt, we need to wake the 39 * processes waiting for some frame to be done, and get the next frame 40 * submitted ASAP (so the hardware doesn't sit idle when there's work 41 * to do). 42 * 43 * When we take the binner out of memory interrupt, we need to 44 * allocate some new memory and pass it to the binner so that the 45 * current job can make progress. 46 */ 47 48 #include "vc4_drv.h" 49 #include "vc4_regs.h" 50 51 #define V3D_DRIVER_IRQS (V3D_INT_OUTOMEM | \ 52 V3D_INT_FLDONE | \ 53 V3D_INT_FRDONE) 54 55 DECLARE_WAIT_QUEUE_HEAD(render_wait); 56 57 static void 58 vc4_overflow_mem_work(struct work_struct *work) 59 { 60 struct vc4_dev *vc4 = 61 container_of(work, struct vc4_dev, overflow_mem_work); 62 struct vc4_bo *bo = vc4->bin_bo; 63 int bin_bo_slot; 64 struct vc4_exec_info *exec; 65 unsigned long irqflags; 66 67 bin_bo_slot = vc4_v3d_get_bin_slot(vc4); 68 if (bin_bo_slot < 0) { 69 DRM_ERROR("Couldn't allocate binner overflow mem\n"); 70 return; 71 } 72 73 spin_lock_irqsave(&vc4->job_lock, irqflags); 74 75 if (vc4->bin_alloc_overflow) { 76 /* If we had overflow memory allocated previously, 77 * then that chunk will free when the current bin job 78 * is done. If we don't have a bin job running, then 79 * the chunk will be done whenever the list of render 80 * jobs has drained. 81 */ 82 exec = vc4_first_bin_job(vc4); 83 if (!exec) 84 exec = vc4_last_render_job(vc4); 85 if (exec) { 86 exec->bin_slots |= vc4->bin_alloc_overflow; 87 } else { 88 /* There's nothing queued in the hardware, so 89 * the old slot is free immediately. 90 */ 91 vc4->bin_alloc_used &= ~vc4->bin_alloc_overflow; 92 } 93 } 94 vc4->bin_alloc_overflow = BIT(bin_bo_slot); 95 96 V3D_WRITE(V3D_BPOA, bo->base.paddr + bin_bo_slot * vc4->bin_alloc_size); 97 V3D_WRITE(V3D_BPOS, bo->base.base.size); 98 V3D_WRITE(V3D_INTCTL, V3D_INT_OUTOMEM); 99 V3D_WRITE(V3D_INTENA, V3D_INT_OUTOMEM); 100 spin_unlock_irqrestore(&vc4->job_lock, irqflags); 101 } 102 103 static void 104 vc4_irq_finish_bin_job(struct drm_device *dev) 105 { 106 struct vc4_dev *vc4 = to_vc4_dev(dev); 107 struct vc4_exec_info *exec = vc4_first_bin_job(vc4); 108 109 if (!exec) 110 return; 111 112 vc4_move_job_to_render(dev, exec); 113 vc4_submit_next_bin_job(dev); 114 } 115 116 static void 117 vc4_cancel_bin_job(struct drm_device *dev) 118 { 119 struct vc4_dev *vc4 = to_vc4_dev(dev); 120 struct vc4_exec_info *exec = vc4_first_bin_job(vc4); 121 122 if (!exec) 123 return; 124 125 list_move_tail(&exec->head, &vc4->bin_job_list); 126 vc4_submit_next_bin_job(dev); 127 } 128 129 static void 130 vc4_irq_finish_render_job(struct drm_device *dev) 131 { 132 struct vc4_dev *vc4 = to_vc4_dev(dev); 133 struct vc4_exec_info *exec = vc4_first_render_job(vc4); 134 135 if (!exec) 136 return; 137 138 vc4->finished_seqno++; 139 list_move_tail(&exec->head, &vc4->job_done_list); 140 if (exec->fence) { 141 dma_fence_signal_locked(exec->fence); 142 exec->fence = NULL; 143 } 144 vc4_submit_next_render_job(dev); 145 146 wake_up_all(&vc4->job_wait_queue); 147 schedule_work(&vc4->job_done_work); 148 } 149 150 irqreturn_t 151 vc4_irq(int irq, void *arg) 152 { 153 struct drm_device *dev = arg; 154 struct vc4_dev *vc4 = to_vc4_dev(dev); 155 uint32_t intctl; 156 irqreturn_t status = IRQ_NONE; 157 158 barrier(); 159 intctl = V3D_READ(V3D_INTCTL); 160 161 /* Acknowledge the interrupts we're handling here. The binner 162 * last flush / render frame done interrupt will be cleared, 163 * while OUTOMEM will stay high until the underlying cause is 164 * cleared. 165 */ 166 V3D_WRITE(V3D_INTCTL, intctl); 167 168 if (intctl & V3D_INT_OUTOMEM) { 169 /* Disable OUTOMEM until the work is done. */ 170 V3D_WRITE(V3D_INTDIS, V3D_INT_OUTOMEM); 171 schedule_work(&vc4->overflow_mem_work); 172 status = IRQ_HANDLED; 173 } 174 175 if (intctl & V3D_INT_FLDONE) { 176 spin_lock(&vc4->job_lock); 177 vc4_irq_finish_bin_job(dev); 178 spin_unlock(&vc4->job_lock); 179 status = IRQ_HANDLED; 180 } 181 182 if (intctl & V3D_INT_FRDONE) { 183 spin_lock(&vc4->job_lock); 184 vc4_irq_finish_render_job(dev); 185 spin_unlock(&vc4->job_lock); 186 status = IRQ_HANDLED; 187 } 188 189 return status; 190 } 191 192 void 193 vc4_irq_preinstall(struct drm_device *dev) 194 { 195 struct vc4_dev *vc4 = to_vc4_dev(dev); 196 197 init_waitqueue_head(&vc4->job_wait_queue); 198 INIT_WORK(&vc4->overflow_mem_work, vc4_overflow_mem_work); 199 200 /* Clear any pending interrupts someone might have left around 201 * for us. 202 */ 203 V3D_WRITE(V3D_INTCTL, V3D_DRIVER_IRQS); 204 } 205 206 int 207 vc4_irq_postinstall(struct drm_device *dev) 208 { 209 struct vc4_dev *vc4 = to_vc4_dev(dev); 210 211 /* Enable both the render done and out of memory interrupts. */ 212 V3D_WRITE(V3D_INTENA, V3D_DRIVER_IRQS); 213 214 return 0; 215 } 216 217 void 218 vc4_irq_uninstall(struct drm_device *dev) 219 { 220 struct vc4_dev *vc4 = to_vc4_dev(dev); 221 222 /* Disable sending interrupts for our driver's IRQs. */ 223 V3D_WRITE(V3D_INTDIS, V3D_DRIVER_IRQS); 224 225 /* Clear any pending interrupts we might have left. */ 226 V3D_WRITE(V3D_INTCTL, V3D_DRIVER_IRQS); 227 228 cancel_work_sync(&vc4->overflow_mem_work); 229 } 230 231 /** Reinitializes interrupt registers when a GPU reset is performed. */ 232 void vc4_irq_reset(struct drm_device *dev) 233 { 234 struct vc4_dev *vc4 = to_vc4_dev(dev); 235 unsigned long irqflags; 236 237 /* Acknowledge any stale IRQs. */ 238 V3D_WRITE(V3D_INTCTL, V3D_DRIVER_IRQS); 239 240 /* 241 * Turn all our interrupts on. Binner out of memory is the 242 * only one we expect to trigger at this point, since we've 243 * just come from poweron and haven't supplied any overflow 244 * memory yet. 245 */ 246 V3D_WRITE(V3D_INTENA, V3D_DRIVER_IRQS); 247 248 spin_lock_irqsave(&vc4->job_lock, irqflags); 249 vc4_cancel_bin_job(dev); 250 vc4_irq_finish_render_job(dev); 251 spin_unlock_irqrestore(&vc4->job_lock, irqflags); 252 } 253