1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 Broadcom 4 */ 5 6 /** 7 * DOC: VC4 HVS module. 8 * 9 * The Hardware Video Scaler (HVS) is the piece of hardware that does 10 * translation, scaling, colorspace conversion, and compositing of 11 * pixels stored in framebuffers into a FIFO of pixels going out to 12 * the Pixel Valve (CRTC). It operates at the system clock rate (the 13 * system audio clock gate, specifically), which is much higher than 14 * the pixel clock rate. 15 * 16 * There is a single global HVS, with multiple output FIFOs that can 17 * be consumed by the PVs. This file just manages the resources for 18 * the HVS, while the vc4_crtc.c code actually drives HVS setup for 19 * each CRTC. 20 */ 21 22 #include <linux/bitfield.h> 23 #include <linux/clk.h> 24 #include <linux/component.h> 25 #include <linux/platform_device.h> 26 27 #include <drm/drm_atomic_helper.h> 28 #include <drm/drm_drv.h> 29 #include <drm/drm_vblank.h> 30 31 #include "vc4_drv.h" 32 #include "vc4_regs.h" 33 34 static const struct debugfs_reg32 hvs_regs[] = { 35 VC4_REG32(SCALER_DISPCTRL), 36 VC4_REG32(SCALER_DISPSTAT), 37 VC4_REG32(SCALER_DISPID), 38 VC4_REG32(SCALER_DISPECTRL), 39 VC4_REG32(SCALER_DISPPROF), 40 VC4_REG32(SCALER_DISPDITHER), 41 VC4_REG32(SCALER_DISPEOLN), 42 VC4_REG32(SCALER_DISPLIST0), 43 VC4_REG32(SCALER_DISPLIST1), 44 VC4_REG32(SCALER_DISPLIST2), 45 VC4_REG32(SCALER_DISPLSTAT), 46 VC4_REG32(SCALER_DISPLACT0), 47 VC4_REG32(SCALER_DISPLACT1), 48 VC4_REG32(SCALER_DISPLACT2), 49 VC4_REG32(SCALER_DISPCTRL0), 50 VC4_REG32(SCALER_DISPBKGND0), 51 VC4_REG32(SCALER_DISPSTAT0), 52 VC4_REG32(SCALER_DISPBASE0), 53 VC4_REG32(SCALER_DISPCTRL1), 54 VC4_REG32(SCALER_DISPBKGND1), 55 VC4_REG32(SCALER_DISPSTAT1), 56 VC4_REG32(SCALER_DISPBASE1), 57 VC4_REG32(SCALER_DISPCTRL2), 58 VC4_REG32(SCALER_DISPBKGND2), 59 VC4_REG32(SCALER_DISPSTAT2), 60 VC4_REG32(SCALER_DISPBASE2), 61 VC4_REG32(SCALER_DISPALPHA2), 62 VC4_REG32(SCALER_OLEDOFFS), 63 VC4_REG32(SCALER_OLEDCOEF0), 64 VC4_REG32(SCALER_OLEDCOEF1), 65 VC4_REG32(SCALER_OLEDCOEF2), 66 }; 67 68 void vc4_hvs_dump_state(struct vc4_hvs *hvs) 69 { 70 struct drm_device *drm = &hvs->vc4->base; 71 struct drm_printer p = drm_info_printer(&hvs->pdev->dev); 72 int idx, i; 73 74 if (!drm_dev_enter(drm, &idx)) 75 return; 76 77 drm_print_regset32(&p, &hvs->regset); 78 79 DRM_INFO("HVS ctx:\n"); 80 for (i = 0; i < 64; i += 4) { 81 DRM_INFO("0x%08x (%s): 0x%08x 0x%08x 0x%08x 0x%08x\n", 82 i * 4, i < HVS_BOOTLOADER_DLIST_END ? "B" : "D", 83 readl((u32 __iomem *)hvs->dlist + i + 0), 84 readl((u32 __iomem *)hvs->dlist + i + 1), 85 readl((u32 __iomem *)hvs->dlist + i + 2), 86 readl((u32 __iomem *)hvs->dlist + i + 3)); 87 } 88 89 drm_dev_exit(idx); 90 } 91 92 static int vc4_hvs_debugfs_underrun(struct seq_file *m, void *data) 93 { 94 struct drm_info_node *node = m->private; 95 struct drm_device *dev = node->minor->dev; 96 struct vc4_dev *vc4 = to_vc4_dev(dev); 97 struct drm_printer p = drm_seq_file_printer(m); 98 99 drm_printf(&p, "%d\n", atomic_read(&vc4->underrun)); 100 101 return 0; 102 } 103 104 static int vc4_hvs_debugfs_dlist(struct seq_file *m, void *data) 105 { 106 struct drm_info_node *node = m->private; 107 struct drm_device *dev = node->minor->dev; 108 struct vc4_dev *vc4 = to_vc4_dev(dev); 109 struct vc4_hvs *hvs = vc4->hvs; 110 struct drm_printer p = drm_seq_file_printer(m); 111 unsigned int next_entry_start = 0; 112 unsigned int i, j; 113 u32 dlist_word, dispstat; 114 115 for (i = 0; i < SCALER_CHANNELS_COUNT; i++) { 116 dispstat = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(i)), 117 SCALER_DISPSTATX_MODE); 118 if (dispstat == SCALER_DISPSTATX_MODE_DISABLED || 119 dispstat == SCALER_DISPSTATX_MODE_EOF) { 120 drm_printf(&p, "HVS chan %u disabled\n", i); 121 continue; 122 } 123 124 drm_printf(&p, "HVS chan %u:\n", i); 125 126 for (j = HVS_READ(SCALER_DISPLISTX(i)); j < 256; j++) { 127 dlist_word = readl((u32 __iomem *)vc4->hvs->dlist + j); 128 drm_printf(&p, "dlist: %02d: 0x%08x\n", j, 129 dlist_word); 130 if (!next_entry_start || 131 next_entry_start == j) { 132 if (dlist_word & SCALER_CTL0_END) 133 break; 134 next_entry_start = j + 135 VC4_GET_FIELD(dlist_word, 136 SCALER_CTL0_SIZE); 137 } 138 } 139 } 140 141 return 0; 142 } 143 144 /* The filter kernel is composed of dwords each containing 3 9-bit 145 * signed integers packed next to each other. 146 */ 147 #define VC4_INT_TO_COEFF(coeff) (coeff & 0x1ff) 148 #define VC4_PPF_FILTER_WORD(c0, c1, c2) \ 149 ((((c0) & 0x1ff) << 0) | \ 150 (((c1) & 0x1ff) << 9) | \ 151 (((c2) & 0x1ff) << 18)) 152 153 /* The whole filter kernel is arranged as the coefficients 0-16 going 154 * up, then a pad, then 17-31 going down and reversed within the 155 * dwords. This means that a linear phase kernel (where it's 156 * symmetrical at the boundary between 15 and 16) has the last 5 157 * dwords matching the first 5, but reversed. 158 */ 159 #define VC4_LINEAR_PHASE_KERNEL(c0, c1, c2, c3, c4, c5, c6, c7, c8, \ 160 c9, c10, c11, c12, c13, c14, c15) \ 161 {VC4_PPF_FILTER_WORD(c0, c1, c2), \ 162 VC4_PPF_FILTER_WORD(c3, c4, c5), \ 163 VC4_PPF_FILTER_WORD(c6, c7, c8), \ 164 VC4_PPF_FILTER_WORD(c9, c10, c11), \ 165 VC4_PPF_FILTER_WORD(c12, c13, c14), \ 166 VC4_PPF_FILTER_WORD(c15, c15, 0)} 167 168 #define VC4_LINEAR_PHASE_KERNEL_DWORDS 6 169 #define VC4_KERNEL_DWORDS (VC4_LINEAR_PHASE_KERNEL_DWORDS * 2 - 1) 170 171 /* Recommended B=1/3, C=1/3 filter choice from Mitchell/Netravali. 172 * http://www.cs.utexas.edu/~fussell/courses/cs384g/lectures/mitchell/Mitchell.pdf 173 */ 174 static const u32 mitchell_netravali_1_3_1_3_kernel[] = 175 VC4_LINEAR_PHASE_KERNEL(0, -2, -6, -8, -10, -8, -3, 2, 18, 176 50, 82, 119, 155, 187, 213, 227); 177 178 static int vc4_hvs_upload_linear_kernel(struct vc4_hvs *hvs, 179 struct drm_mm_node *space, 180 const u32 *kernel) 181 { 182 int ret, i; 183 u32 __iomem *dst_kernel; 184 185 /* 186 * NOTE: We don't need a call to drm_dev_enter()/drm_dev_exit() 187 * here since that function is only called from vc4_hvs_bind(). 188 */ 189 190 ret = drm_mm_insert_node(&hvs->dlist_mm, space, VC4_KERNEL_DWORDS); 191 if (ret) { 192 DRM_ERROR("Failed to allocate space for filter kernel: %d\n", 193 ret); 194 return ret; 195 } 196 197 dst_kernel = hvs->dlist + space->start; 198 199 for (i = 0; i < VC4_KERNEL_DWORDS; i++) { 200 if (i < VC4_LINEAR_PHASE_KERNEL_DWORDS) 201 writel(kernel[i], &dst_kernel[i]); 202 else { 203 writel(kernel[VC4_KERNEL_DWORDS - i - 1], 204 &dst_kernel[i]); 205 } 206 } 207 208 return 0; 209 } 210 211 static void vc4_hvs_lut_load(struct vc4_hvs *hvs, 212 struct vc4_crtc *vc4_crtc) 213 { 214 struct drm_device *drm = &hvs->vc4->base; 215 struct drm_crtc *crtc = &vc4_crtc->base; 216 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state); 217 int idx; 218 u32 i; 219 220 if (!drm_dev_enter(drm, &idx)) 221 return; 222 223 /* The LUT memory is laid out with each HVS channel in order, 224 * each of which takes 256 writes for R, 256 for G, then 256 225 * for B. 226 */ 227 HVS_WRITE(SCALER_GAMADDR, 228 SCALER_GAMADDR_AUTOINC | 229 (vc4_state->assigned_channel * 3 * crtc->gamma_size)); 230 231 for (i = 0; i < crtc->gamma_size; i++) 232 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_r[i]); 233 for (i = 0; i < crtc->gamma_size; i++) 234 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_g[i]); 235 for (i = 0; i < crtc->gamma_size; i++) 236 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_b[i]); 237 238 drm_dev_exit(idx); 239 } 240 241 static void vc4_hvs_update_gamma_lut(struct vc4_hvs *hvs, 242 struct vc4_crtc *vc4_crtc) 243 { 244 struct drm_crtc_state *crtc_state = vc4_crtc->base.state; 245 struct drm_color_lut *lut = crtc_state->gamma_lut->data; 246 u32 length = drm_color_lut_size(crtc_state->gamma_lut); 247 u32 i; 248 249 for (i = 0; i < length; i++) { 250 vc4_crtc->lut_r[i] = drm_color_lut_extract(lut[i].red, 8); 251 vc4_crtc->lut_g[i] = drm_color_lut_extract(lut[i].green, 8); 252 vc4_crtc->lut_b[i] = drm_color_lut_extract(lut[i].blue, 8); 253 } 254 255 vc4_hvs_lut_load(hvs, vc4_crtc); 256 } 257 258 u8 vc4_hvs_get_fifo_frame_count(struct vc4_hvs *hvs, unsigned int fifo) 259 { 260 struct drm_device *drm = &hvs->vc4->base; 261 u8 field = 0; 262 int idx; 263 264 if (!drm_dev_enter(drm, &idx)) 265 return 0; 266 267 switch (fifo) { 268 case 0: 269 field = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTAT1), 270 SCALER_DISPSTAT1_FRCNT0); 271 break; 272 case 1: 273 field = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTAT1), 274 SCALER_DISPSTAT1_FRCNT1); 275 break; 276 case 2: 277 field = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTAT2), 278 SCALER_DISPSTAT2_FRCNT2); 279 break; 280 } 281 282 drm_dev_exit(idx); 283 return field; 284 } 285 286 int vc4_hvs_get_fifo_from_output(struct vc4_hvs *hvs, unsigned int output) 287 { 288 struct vc4_dev *vc4 = hvs->vc4; 289 u32 reg; 290 int ret; 291 292 if (!vc4->is_vc5) 293 return output; 294 295 /* 296 * NOTE: We should probably use drm_dev_enter()/drm_dev_exit() 297 * here, but this function is only used during the DRM device 298 * initialization, so we should be fine. 299 */ 300 301 switch (output) { 302 case 0: 303 return 0; 304 305 case 1: 306 return 1; 307 308 case 2: 309 reg = HVS_READ(SCALER_DISPECTRL); 310 ret = FIELD_GET(SCALER_DISPECTRL_DSP2_MUX_MASK, reg); 311 if (ret == 0) 312 return 2; 313 314 return 0; 315 316 case 3: 317 reg = HVS_READ(SCALER_DISPCTRL); 318 ret = FIELD_GET(SCALER_DISPCTRL_DSP3_MUX_MASK, reg); 319 if (ret == 3) 320 return -EPIPE; 321 322 return ret; 323 324 case 4: 325 reg = HVS_READ(SCALER_DISPEOLN); 326 ret = FIELD_GET(SCALER_DISPEOLN_DSP4_MUX_MASK, reg); 327 if (ret == 3) 328 return -EPIPE; 329 330 return ret; 331 332 case 5: 333 reg = HVS_READ(SCALER_DISPDITHER); 334 ret = FIELD_GET(SCALER_DISPDITHER_DSP5_MUX_MASK, reg); 335 if (ret == 3) 336 return -EPIPE; 337 338 return ret; 339 340 default: 341 return -EPIPE; 342 } 343 } 344 345 static int vc4_hvs_init_channel(struct vc4_hvs *hvs, struct drm_crtc *crtc, 346 struct drm_display_mode *mode, bool oneshot) 347 { 348 struct vc4_dev *vc4 = hvs->vc4; 349 struct drm_device *drm = &vc4->base; 350 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 351 struct vc4_crtc_state *vc4_crtc_state = to_vc4_crtc_state(crtc->state); 352 unsigned int chan = vc4_crtc_state->assigned_channel; 353 bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE; 354 u32 dispbkgndx; 355 u32 dispctrl; 356 int idx; 357 358 if (!drm_dev_enter(drm, &idx)) 359 return -ENODEV; 360 361 HVS_WRITE(SCALER_DISPCTRLX(chan), 0); 362 HVS_WRITE(SCALER_DISPCTRLX(chan), SCALER_DISPCTRLX_RESET); 363 HVS_WRITE(SCALER_DISPCTRLX(chan), 0); 364 365 /* Turn on the scaler, which will wait for vstart to start 366 * compositing. 367 * When feeding the transposer, we should operate in oneshot 368 * mode. 369 */ 370 dispctrl = SCALER_DISPCTRLX_ENABLE; 371 372 if (!vc4->is_vc5) 373 dispctrl |= VC4_SET_FIELD(mode->hdisplay, 374 SCALER_DISPCTRLX_WIDTH) | 375 VC4_SET_FIELD(mode->vdisplay, 376 SCALER_DISPCTRLX_HEIGHT) | 377 (oneshot ? SCALER_DISPCTRLX_ONESHOT : 0); 378 else 379 dispctrl |= VC4_SET_FIELD(mode->hdisplay, 380 SCALER5_DISPCTRLX_WIDTH) | 381 VC4_SET_FIELD(mode->vdisplay, 382 SCALER5_DISPCTRLX_HEIGHT) | 383 (oneshot ? SCALER5_DISPCTRLX_ONESHOT : 0); 384 385 HVS_WRITE(SCALER_DISPCTRLX(chan), dispctrl); 386 387 dispbkgndx = HVS_READ(SCALER_DISPBKGNDX(chan)); 388 dispbkgndx &= ~SCALER_DISPBKGND_GAMMA; 389 dispbkgndx &= ~SCALER_DISPBKGND_INTERLACE; 390 391 HVS_WRITE(SCALER_DISPBKGNDX(chan), dispbkgndx | 392 SCALER_DISPBKGND_AUTOHS | 393 ((!vc4->is_vc5) ? SCALER_DISPBKGND_GAMMA : 0) | 394 (interlace ? SCALER_DISPBKGND_INTERLACE : 0)); 395 396 /* Reload the LUT, since the SRAMs would have been disabled if 397 * all CRTCs had SCALER_DISPBKGND_GAMMA unset at once. 398 */ 399 vc4_hvs_lut_load(hvs, vc4_crtc); 400 401 drm_dev_exit(idx); 402 403 return 0; 404 } 405 406 void vc4_hvs_stop_channel(struct vc4_hvs *hvs, unsigned int chan) 407 { 408 struct drm_device *drm = &hvs->vc4->base; 409 int idx; 410 411 if (!drm_dev_enter(drm, &idx)) 412 return; 413 414 if (HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_ENABLE) 415 goto out; 416 417 HVS_WRITE(SCALER_DISPCTRLX(chan), 418 HVS_READ(SCALER_DISPCTRLX(chan)) | SCALER_DISPCTRLX_RESET); 419 HVS_WRITE(SCALER_DISPCTRLX(chan), 420 HVS_READ(SCALER_DISPCTRLX(chan)) & ~SCALER_DISPCTRLX_ENABLE); 421 422 /* Once we leave, the scaler should be disabled and its fifo empty. */ 423 WARN_ON_ONCE(HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_RESET); 424 425 WARN_ON_ONCE(VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(chan)), 426 SCALER_DISPSTATX_MODE) != 427 SCALER_DISPSTATX_MODE_DISABLED); 428 429 WARN_ON_ONCE((HVS_READ(SCALER_DISPSTATX(chan)) & 430 (SCALER_DISPSTATX_FULL | SCALER_DISPSTATX_EMPTY)) != 431 SCALER_DISPSTATX_EMPTY); 432 433 out: 434 drm_dev_exit(idx); 435 } 436 437 int vc4_hvs_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *state) 438 { 439 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 440 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state); 441 struct drm_device *dev = crtc->dev; 442 struct vc4_dev *vc4 = to_vc4_dev(dev); 443 struct drm_plane *plane; 444 unsigned long flags; 445 const struct drm_plane_state *plane_state; 446 u32 dlist_count = 0; 447 int ret; 448 449 /* The pixelvalve can only feed one encoder (and encoders are 450 * 1:1 with connectors.) 451 */ 452 if (hweight32(crtc_state->connector_mask) > 1) 453 return -EINVAL; 454 455 drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) 456 dlist_count += vc4_plane_dlist_size(plane_state); 457 458 dlist_count++; /* Account for SCALER_CTL0_END. */ 459 460 spin_lock_irqsave(&vc4->hvs->mm_lock, flags); 461 ret = drm_mm_insert_node(&vc4->hvs->dlist_mm, &vc4_state->mm, 462 dlist_count); 463 spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags); 464 if (ret) 465 return ret; 466 467 return 0; 468 } 469 470 static void vc4_hvs_install_dlist(struct drm_crtc *crtc) 471 { 472 struct drm_device *dev = crtc->dev; 473 struct vc4_dev *vc4 = to_vc4_dev(dev); 474 struct vc4_hvs *hvs = vc4->hvs; 475 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state); 476 int idx; 477 478 if (!drm_dev_enter(dev, &idx)) 479 return; 480 481 HVS_WRITE(SCALER_DISPLISTX(vc4_state->assigned_channel), 482 vc4_state->mm.start); 483 484 drm_dev_exit(idx); 485 } 486 487 static void vc4_hvs_update_dlist(struct drm_crtc *crtc) 488 { 489 struct drm_device *dev = crtc->dev; 490 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 491 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state); 492 unsigned long flags; 493 494 if (crtc->state->event) { 495 crtc->state->event->pipe = drm_crtc_index(crtc); 496 497 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 498 499 spin_lock_irqsave(&dev->event_lock, flags); 500 501 if (!vc4_crtc->feeds_txp || vc4_state->txp_armed) { 502 vc4_crtc->event = crtc->state->event; 503 crtc->state->event = NULL; 504 } 505 506 spin_unlock_irqrestore(&dev->event_lock, flags); 507 } 508 509 spin_lock_irqsave(&vc4_crtc->irq_lock, flags); 510 vc4_crtc->current_dlist = vc4_state->mm.start; 511 spin_unlock_irqrestore(&vc4_crtc->irq_lock, flags); 512 } 513 514 void vc4_hvs_atomic_begin(struct drm_crtc *crtc, 515 struct drm_atomic_state *state) 516 { 517 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 518 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state); 519 unsigned long flags; 520 521 spin_lock_irqsave(&vc4_crtc->irq_lock, flags); 522 vc4_crtc->current_hvs_channel = vc4_state->assigned_channel; 523 spin_unlock_irqrestore(&vc4_crtc->irq_lock, flags); 524 } 525 526 void vc4_hvs_atomic_enable(struct drm_crtc *crtc, 527 struct drm_atomic_state *state) 528 { 529 struct drm_device *dev = crtc->dev; 530 struct vc4_dev *vc4 = to_vc4_dev(dev); 531 struct drm_display_mode *mode = &crtc->state->adjusted_mode; 532 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 533 bool oneshot = vc4_crtc->feeds_txp; 534 535 vc4_hvs_install_dlist(crtc); 536 vc4_hvs_update_dlist(crtc); 537 vc4_hvs_init_channel(vc4->hvs, crtc, mode, oneshot); 538 } 539 540 void vc4_hvs_atomic_disable(struct drm_crtc *crtc, 541 struct drm_atomic_state *state) 542 { 543 struct drm_device *dev = crtc->dev; 544 struct vc4_dev *vc4 = to_vc4_dev(dev); 545 struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state, crtc); 546 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(old_state); 547 unsigned int chan = vc4_state->assigned_channel; 548 549 vc4_hvs_stop_channel(vc4->hvs, chan); 550 } 551 552 void vc4_hvs_atomic_flush(struct drm_crtc *crtc, 553 struct drm_atomic_state *state) 554 { 555 struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state, 556 crtc); 557 struct drm_device *dev = crtc->dev; 558 struct vc4_dev *vc4 = to_vc4_dev(dev); 559 struct vc4_hvs *hvs = vc4->hvs; 560 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 561 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state); 562 unsigned int channel = vc4_state->assigned_channel; 563 struct drm_plane *plane; 564 struct vc4_plane_state *vc4_plane_state; 565 bool debug_dump_regs = false; 566 bool enable_bg_fill = false; 567 u32 __iomem *dlist_start = vc4->hvs->dlist + vc4_state->mm.start; 568 u32 __iomem *dlist_next = dlist_start; 569 int idx; 570 571 if (!drm_dev_enter(dev, &idx)) { 572 vc4_crtc_send_vblank(crtc); 573 return; 574 } 575 576 if (debug_dump_regs) { 577 DRM_INFO("CRTC %d HVS before:\n", drm_crtc_index(crtc)); 578 vc4_hvs_dump_state(hvs); 579 } 580 581 /* Copy all the active planes' dlist contents to the hardware dlist. */ 582 drm_atomic_crtc_for_each_plane(plane, crtc) { 583 /* Is this the first active plane? */ 584 if (dlist_next == dlist_start) { 585 /* We need to enable background fill when a plane 586 * could be alpha blending from the background, i.e. 587 * where no other plane is underneath. It suffices to 588 * consider the first active plane here since we set 589 * needs_bg_fill such that either the first plane 590 * already needs it or all planes on top blend from 591 * the first or a lower plane. 592 */ 593 vc4_plane_state = to_vc4_plane_state(plane->state); 594 enable_bg_fill = vc4_plane_state->needs_bg_fill; 595 } 596 597 dlist_next += vc4_plane_write_dlist(plane, dlist_next); 598 } 599 600 writel(SCALER_CTL0_END, dlist_next); 601 dlist_next++; 602 603 WARN_ON_ONCE(dlist_next - dlist_start != vc4_state->mm.size); 604 605 if (enable_bg_fill) 606 /* This sets a black background color fill, as is the case 607 * with other DRM drivers. 608 */ 609 HVS_WRITE(SCALER_DISPBKGNDX(channel), 610 HVS_READ(SCALER_DISPBKGNDX(channel)) | 611 SCALER_DISPBKGND_FILL); 612 613 /* Only update DISPLIST if the CRTC was already running and is not 614 * being disabled. 615 * vc4_crtc_enable() takes care of updating the dlist just after 616 * re-enabling VBLANK interrupts and before enabling the engine. 617 * If the CRTC is being disabled, there's no point in updating this 618 * information. 619 */ 620 if (crtc->state->active && old_state->active) { 621 vc4_hvs_install_dlist(crtc); 622 vc4_hvs_update_dlist(crtc); 623 } 624 625 if (crtc->state->color_mgmt_changed) { 626 u32 dispbkgndx = HVS_READ(SCALER_DISPBKGNDX(channel)); 627 628 if (crtc->state->gamma_lut) { 629 vc4_hvs_update_gamma_lut(hvs, vc4_crtc); 630 dispbkgndx |= SCALER_DISPBKGND_GAMMA; 631 } else { 632 /* Unsetting DISPBKGND_GAMMA skips the gamma lut step 633 * in hardware, which is the same as a linear lut that 634 * DRM expects us to use in absence of a user lut. 635 */ 636 dispbkgndx &= ~SCALER_DISPBKGND_GAMMA; 637 } 638 HVS_WRITE(SCALER_DISPBKGNDX(channel), dispbkgndx); 639 } 640 641 if (debug_dump_regs) { 642 DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc)); 643 vc4_hvs_dump_state(hvs); 644 } 645 646 drm_dev_exit(idx); 647 } 648 649 void vc4_hvs_mask_underrun(struct vc4_hvs *hvs, int channel) 650 { 651 struct drm_device *drm = &hvs->vc4->base; 652 u32 dispctrl; 653 int idx; 654 655 if (!drm_dev_enter(drm, &idx)) 656 return; 657 658 dispctrl = HVS_READ(SCALER_DISPCTRL); 659 dispctrl &= ~SCALER_DISPCTRL_DSPEISLUR(channel); 660 661 HVS_WRITE(SCALER_DISPCTRL, dispctrl); 662 663 drm_dev_exit(idx); 664 } 665 666 void vc4_hvs_unmask_underrun(struct vc4_hvs *hvs, int channel) 667 { 668 struct drm_device *drm = &hvs->vc4->base; 669 u32 dispctrl; 670 int idx; 671 672 if (!drm_dev_enter(drm, &idx)) 673 return; 674 675 dispctrl = HVS_READ(SCALER_DISPCTRL); 676 dispctrl |= SCALER_DISPCTRL_DSPEISLUR(channel); 677 678 HVS_WRITE(SCALER_DISPSTAT, 679 SCALER_DISPSTAT_EUFLOW(channel)); 680 HVS_WRITE(SCALER_DISPCTRL, dispctrl); 681 682 drm_dev_exit(idx); 683 } 684 685 static void vc4_hvs_report_underrun(struct drm_device *dev) 686 { 687 struct vc4_dev *vc4 = to_vc4_dev(dev); 688 689 atomic_inc(&vc4->underrun); 690 DRM_DEV_ERROR(dev->dev, "HVS underrun\n"); 691 } 692 693 static irqreturn_t vc4_hvs_irq_handler(int irq, void *data) 694 { 695 struct drm_device *dev = data; 696 struct vc4_dev *vc4 = to_vc4_dev(dev); 697 struct vc4_hvs *hvs = vc4->hvs; 698 irqreturn_t irqret = IRQ_NONE; 699 int channel; 700 u32 control; 701 u32 status; 702 703 /* 704 * NOTE: We don't need to protect the register access using 705 * drm_dev_enter() there because the interrupt handler lifetime 706 * is tied to the device itself, and not to the DRM device. 707 * 708 * So when the device will be gone, one of the first thing we 709 * will be doing will be to unregister the interrupt handler, 710 * and then unregister the DRM device. drm_dev_enter() would 711 * thus always succeed if we are here. 712 */ 713 714 status = HVS_READ(SCALER_DISPSTAT); 715 control = HVS_READ(SCALER_DISPCTRL); 716 717 for (channel = 0; channel < SCALER_CHANNELS_COUNT; channel++) { 718 /* Interrupt masking is not always honored, so check it here. */ 719 if (status & SCALER_DISPSTAT_EUFLOW(channel) && 720 control & SCALER_DISPCTRL_DSPEISLUR(channel)) { 721 vc4_hvs_mask_underrun(hvs, channel); 722 vc4_hvs_report_underrun(dev); 723 724 irqret = IRQ_HANDLED; 725 } 726 } 727 728 /* Clear every per-channel interrupt flag. */ 729 HVS_WRITE(SCALER_DISPSTAT, SCALER_DISPSTAT_IRQMASK(0) | 730 SCALER_DISPSTAT_IRQMASK(1) | 731 SCALER_DISPSTAT_IRQMASK(2)); 732 733 return irqret; 734 } 735 736 int vc4_hvs_debugfs_init(struct drm_minor *minor) 737 { 738 struct drm_device *drm = minor->dev; 739 struct vc4_dev *vc4 = to_vc4_dev(drm); 740 struct vc4_hvs *hvs = vc4->hvs; 741 int ret; 742 743 if (!vc4->hvs) 744 return -ENODEV; 745 746 if (!vc4->is_vc5) 747 debugfs_create_bool("hvs_load_tracker", S_IRUGO | S_IWUSR, 748 minor->debugfs_root, 749 &vc4->load_tracker_enabled); 750 751 ret = vc4_debugfs_add_file(minor, "hvs_dlists", 752 vc4_hvs_debugfs_dlist, NULL); 753 if (ret) 754 return ret; 755 756 ret = vc4_debugfs_add_file(minor, "hvs_underrun", 757 vc4_hvs_debugfs_underrun, NULL); 758 if (ret) 759 return ret; 760 761 ret = vc4_debugfs_add_regset32(minor, "hvs_regs", 762 &hvs->regset); 763 if (ret) 764 return ret; 765 766 return 0; 767 } 768 769 static int vc4_hvs_bind(struct device *dev, struct device *master, void *data) 770 { 771 struct platform_device *pdev = to_platform_device(dev); 772 struct drm_device *drm = dev_get_drvdata(master); 773 struct vc4_dev *vc4 = to_vc4_dev(drm); 774 struct vc4_hvs *hvs = NULL; 775 int ret; 776 u32 dispctrl; 777 u32 reg; 778 779 hvs = drmm_kzalloc(drm, sizeof(*hvs), GFP_KERNEL); 780 if (!hvs) 781 return -ENOMEM; 782 hvs->vc4 = vc4; 783 hvs->pdev = pdev; 784 785 hvs->regs = vc4_ioremap_regs(pdev, 0); 786 if (IS_ERR(hvs->regs)) 787 return PTR_ERR(hvs->regs); 788 789 hvs->regset.base = hvs->regs; 790 hvs->regset.regs = hvs_regs; 791 hvs->regset.nregs = ARRAY_SIZE(hvs_regs); 792 793 if (vc4->is_vc5) { 794 hvs->core_clk = devm_clk_get(&pdev->dev, NULL); 795 if (IS_ERR(hvs->core_clk)) { 796 dev_err(&pdev->dev, "Couldn't get core clock\n"); 797 return PTR_ERR(hvs->core_clk); 798 } 799 800 ret = clk_prepare_enable(hvs->core_clk); 801 if (ret) { 802 dev_err(&pdev->dev, "Couldn't enable the core clock\n"); 803 return ret; 804 } 805 } 806 807 if (!vc4->is_vc5) 808 hvs->dlist = hvs->regs + SCALER_DLIST_START; 809 else 810 hvs->dlist = hvs->regs + SCALER5_DLIST_START; 811 812 spin_lock_init(&hvs->mm_lock); 813 814 /* Set up the HVS display list memory manager. We never 815 * overwrite the setup from the bootloader (just 128b out of 816 * our 16K), since we don't want to scramble the screen when 817 * transitioning from the firmware's boot setup to runtime. 818 */ 819 drm_mm_init(&hvs->dlist_mm, 820 HVS_BOOTLOADER_DLIST_END, 821 (SCALER_DLIST_SIZE >> 2) - HVS_BOOTLOADER_DLIST_END); 822 823 /* Set up the HVS LBM memory manager. We could have some more 824 * complicated data structure that allowed reuse of LBM areas 825 * between planes when they don't overlap on the screen, but 826 * for now we just allocate globally. 827 */ 828 if (!vc4->is_vc5) 829 /* 48k words of 2x12-bit pixels */ 830 drm_mm_init(&hvs->lbm_mm, 0, 48 * 1024); 831 else 832 /* 60k words of 4x12-bit pixels */ 833 drm_mm_init(&hvs->lbm_mm, 0, 60 * 1024); 834 835 /* Upload filter kernels. We only have the one for now, so we 836 * keep it around for the lifetime of the driver. 837 */ 838 ret = vc4_hvs_upload_linear_kernel(hvs, 839 &hvs->mitchell_netravali_filter, 840 mitchell_netravali_1_3_1_3_kernel); 841 if (ret) 842 return ret; 843 844 vc4->hvs = hvs; 845 846 reg = HVS_READ(SCALER_DISPECTRL); 847 reg &= ~SCALER_DISPECTRL_DSP2_MUX_MASK; 848 HVS_WRITE(SCALER_DISPECTRL, 849 reg | VC4_SET_FIELD(0, SCALER_DISPECTRL_DSP2_MUX)); 850 851 reg = HVS_READ(SCALER_DISPCTRL); 852 reg &= ~SCALER_DISPCTRL_DSP3_MUX_MASK; 853 HVS_WRITE(SCALER_DISPCTRL, 854 reg | VC4_SET_FIELD(3, SCALER_DISPCTRL_DSP3_MUX)); 855 856 reg = HVS_READ(SCALER_DISPEOLN); 857 reg &= ~SCALER_DISPEOLN_DSP4_MUX_MASK; 858 HVS_WRITE(SCALER_DISPEOLN, 859 reg | VC4_SET_FIELD(3, SCALER_DISPEOLN_DSP4_MUX)); 860 861 reg = HVS_READ(SCALER_DISPDITHER); 862 reg &= ~SCALER_DISPDITHER_DSP5_MUX_MASK; 863 HVS_WRITE(SCALER_DISPDITHER, 864 reg | VC4_SET_FIELD(3, SCALER_DISPDITHER_DSP5_MUX)); 865 866 dispctrl = HVS_READ(SCALER_DISPCTRL); 867 868 dispctrl |= SCALER_DISPCTRL_ENABLE; 869 dispctrl |= SCALER_DISPCTRL_DISPEIRQ(0) | 870 SCALER_DISPCTRL_DISPEIRQ(1) | 871 SCALER_DISPCTRL_DISPEIRQ(2); 872 873 dispctrl &= ~(SCALER_DISPCTRL_DMAEIRQ | 874 SCALER_DISPCTRL_SLVWREIRQ | 875 SCALER_DISPCTRL_SLVRDEIRQ | 876 SCALER_DISPCTRL_DSPEIEOF(0) | 877 SCALER_DISPCTRL_DSPEIEOF(1) | 878 SCALER_DISPCTRL_DSPEIEOF(2) | 879 SCALER_DISPCTRL_DSPEIEOLN(0) | 880 SCALER_DISPCTRL_DSPEIEOLN(1) | 881 SCALER_DISPCTRL_DSPEIEOLN(2) | 882 SCALER_DISPCTRL_DSPEISLUR(0) | 883 SCALER_DISPCTRL_DSPEISLUR(1) | 884 SCALER_DISPCTRL_DSPEISLUR(2) | 885 SCALER_DISPCTRL_SCLEIRQ); 886 887 HVS_WRITE(SCALER_DISPCTRL, dispctrl); 888 889 ret = devm_request_irq(dev, platform_get_irq(pdev, 0), 890 vc4_hvs_irq_handler, 0, "vc4 hvs", drm); 891 if (ret) 892 return ret; 893 894 return 0; 895 } 896 897 static void vc4_hvs_unbind(struct device *dev, struct device *master, 898 void *data) 899 { 900 struct drm_device *drm = dev_get_drvdata(master); 901 struct vc4_dev *vc4 = to_vc4_dev(drm); 902 struct vc4_hvs *hvs = vc4->hvs; 903 struct drm_mm_node *node, *next; 904 905 if (drm_mm_node_allocated(&vc4->hvs->mitchell_netravali_filter)) 906 drm_mm_remove_node(&vc4->hvs->mitchell_netravali_filter); 907 908 drm_mm_for_each_node_safe(node, next, &vc4->hvs->dlist_mm) 909 drm_mm_remove_node(node); 910 911 drm_mm_takedown(&vc4->hvs->dlist_mm); 912 913 drm_mm_for_each_node_safe(node, next, &vc4->hvs->lbm_mm) 914 drm_mm_remove_node(node); 915 drm_mm_takedown(&vc4->hvs->lbm_mm); 916 917 clk_disable_unprepare(hvs->core_clk); 918 919 vc4->hvs = NULL; 920 } 921 922 static const struct component_ops vc4_hvs_ops = { 923 .bind = vc4_hvs_bind, 924 .unbind = vc4_hvs_unbind, 925 }; 926 927 static int vc4_hvs_dev_probe(struct platform_device *pdev) 928 { 929 return component_add(&pdev->dev, &vc4_hvs_ops); 930 } 931 932 static int vc4_hvs_dev_remove(struct platform_device *pdev) 933 { 934 component_del(&pdev->dev, &vc4_hvs_ops); 935 return 0; 936 } 937 938 static const struct of_device_id vc4_hvs_dt_match[] = { 939 { .compatible = "brcm,bcm2711-hvs" }, 940 { .compatible = "brcm,bcm2835-hvs" }, 941 {} 942 }; 943 944 struct platform_driver vc4_hvs_driver = { 945 .probe = vc4_hvs_dev_probe, 946 .remove = vc4_hvs_dev_remove, 947 .driver = { 948 .name = "vc4_hvs", 949 .of_match_table = vc4_hvs_dt_match, 950 }, 951 }; 952