1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 Broadcom 4 */ 5 6 /** 7 * DOC: VC4 HVS module. 8 * 9 * The Hardware Video Scaler (HVS) is the piece of hardware that does 10 * translation, scaling, colorspace conversion, and compositing of 11 * pixels stored in framebuffers into a FIFO of pixels going out to 12 * the Pixel Valve (CRTC). It operates at the system clock rate (the 13 * system audio clock gate, specifically), which is much higher than 14 * the pixel clock rate. 15 * 16 * There is a single global HVS, with multiple output FIFOs that can 17 * be consumed by the PVs. This file just manages the resources for 18 * the HVS, while the vc4_crtc.c code actually drives HVS setup for 19 * each CRTC. 20 */ 21 22 #include <linux/bitfield.h> 23 #include <linux/clk.h> 24 #include <linux/component.h> 25 #include <linux/platform_device.h> 26 27 #include <drm/drm_atomic_helper.h> 28 #include <drm/drm_vblank.h> 29 30 #include "vc4_drv.h" 31 #include "vc4_regs.h" 32 33 static const struct debugfs_reg32 hvs_regs[] = { 34 VC4_REG32(SCALER_DISPCTRL), 35 VC4_REG32(SCALER_DISPSTAT), 36 VC4_REG32(SCALER_DISPID), 37 VC4_REG32(SCALER_DISPECTRL), 38 VC4_REG32(SCALER_DISPPROF), 39 VC4_REG32(SCALER_DISPDITHER), 40 VC4_REG32(SCALER_DISPEOLN), 41 VC4_REG32(SCALER_DISPLIST0), 42 VC4_REG32(SCALER_DISPLIST1), 43 VC4_REG32(SCALER_DISPLIST2), 44 VC4_REG32(SCALER_DISPLSTAT), 45 VC4_REG32(SCALER_DISPLACT0), 46 VC4_REG32(SCALER_DISPLACT1), 47 VC4_REG32(SCALER_DISPLACT2), 48 VC4_REG32(SCALER_DISPCTRL0), 49 VC4_REG32(SCALER_DISPBKGND0), 50 VC4_REG32(SCALER_DISPSTAT0), 51 VC4_REG32(SCALER_DISPBASE0), 52 VC4_REG32(SCALER_DISPCTRL1), 53 VC4_REG32(SCALER_DISPBKGND1), 54 VC4_REG32(SCALER_DISPSTAT1), 55 VC4_REG32(SCALER_DISPBASE1), 56 VC4_REG32(SCALER_DISPCTRL2), 57 VC4_REG32(SCALER_DISPBKGND2), 58 VC4_REG32(SCALER_DISPSTAT2), 59 VC4_REG32(SCALER_DISPBASE2), 60 VC4_REG32(SCALER_DISPALPHA2), 61 VC4_REG32(SCALER_OLEDOFFS), 62 VC4_REG32(SCALER_OLEDCOEF0), 63 VC4_REG32(SCALER_OLEDCOEF1), 64 VC4_REG32(SCALER_OLEDCOEF2), 65 }; 66 67 void vc4_hvs_dump_state(struct vc4_hvs *hvs) 68 { 69 struct drm_printer p = drm_info_printer(&hvs->pdev->dev); 70 int i; 71 72 drm_print_regset32(&p, &hvs->regset); 73 74 DRM_INFO("HVS ctx:\n"); 75 for (i = 0; i < 64; i += 4) { 76 DRM_INFO("0x%08x (%s): 0x%08x 0x%08x 0x%08x 0x%08x\n", 77 i * 4, i < HVS_BOOTLOADER_DLIST_END ? "B" : "D", 78 readl((u32 __iomem *)hvs->dlist + i + 0), 79 readl((u32 __iomem *)hvs->dlist + i + 1), 80 readl((u32 __iomem *)hvs->dlist + i + 2), 81 readl((u32 __iomem *)hvs->dlist + i + 3)); 82 } 83 } 84 85 static int vc4_hvs_debugfs_underrun(struct seq_file *m, void *data) 86 { 87 struct drm_info_node *node = m->private; 88 struct drm_device *dev = node->minor->dev; 89 struct vc4_dev *vc4 = to_vc4_dev(dev); 90 struct drm_printer p = drm_seq_file_printer(m); 91 92 drm_printf(&p, "%d\n", atomic_read(&vc4->underrun)); 93 94 return 0; 95 } 96 97 /* The filter kernel is composed of dwords each containing 3 9-bit 98 * signed integers packed next to each other. 99 */ 100 #define VC4_INT_TO_COEFF(coeff) (coeff & 0x1ff) 101 #define VC4_PPF_FILTER_WORD(c0, c1, c2) \ 102 ((((c0) & 0x1ff) << 0) | \ 103 (((c1) & 0x1ff) << 9) | \ 104 (((c2) & 0x1ff) << 18)) 105 106 /* The whole filter kernel is arranged as the coefficients 0-16 going 107 * up, then a pad, then 17-31 going down and reversed within the 108 * dwords. This means that a linear phase kernel (where it's 109 * symmetrical at the boundary between 15 and 16) has the last 5 110 * dwords matching the first 5, but reversed. 111 */ 112 #define VC4_LINEAR_PHASE_KERNEL(c0, c1, c2, c3, c4, c5, c6, c7, c8, \ 113 c9, c10, c11, c12, c13, c14, c15) \ 114 {VC4_PPF_FILTER_WORD(c0, c1, c2), \ 115 VC4_PPF_FILTER_WORD(c3, c4, c5), \ 116 VC4_PPF_FILTER_WORD(c6, c7, c8), \ 117 VC4_PPF_FILTER_WORD(c9, c10, c11), \ 118 VC4_PPF_FILTER_WORD(c12, c13, c14), \ 119 VC4_PPF_FILTER_WORD(c15, c15, 0)} 120 121 #define VC4_LINEAR_PHASE_KERNEL_DWORDS 6 122 #define VC4_KERNEL_DWORDS (VC4_LINEAR_PHASE_KERNEL_DWORDS * 2 - 1) 123 124 /* Recommended B=1/3, C=1/3 filter choice from Mitchell/Netravali. 125 * http://www.cs.utexas.edu/~fussell/courses/cs384g/lectures/mitchell/Mitchell.pdf 126 */ 127 static const u32 mitchell_netravali_1_3_1_3_kernel[] = 128 VC4_LINEAR_PHASE_KERNEL(0, -2, -6, -8, -10, -8, -3, 2, 18, 129 50, 82, 119, 155, 187, 213, 227); 130 131 static int vc4_hvs_upload_linear_kernel(struct vc4_hvs *hvs, 132 struct drm_mm_node *space, 133 const u32 *kernel) 134 { 135 int ret, i; 136 u32 __iomem *dst_kernel; 137 138 ret = drm_mm_insert_node(&hvs->dlist_mm, space, VC4_KERNEL_DWORDS); 139 if (ret) { 140 DRM_ERROR("Failed to allocate space for filter kernel: %d\n", 141 ret); 142 return ret; 143 } 144 145 dst_kernel = hvs->dlist + space->start; 146 147 for (i = 0; i < VC4_KERNEL_DWORDS; i++) { 148 if (i < VC4_LINEAR_PHASE_KERNEL_DWORDS) 149 writel(kernel[i], &dst_kernel[i]); 150 else { 151 writel(kernel[VC4_KERNEL_DWORDS - i - 1], 152 &dst_kernel[i]); 153 } 154 } 155 156 return 0; 157 } 158 159 static void vc4_hvs_lut_load(struct vc4_hvs *hvs, 160 struct vc4_crtc *vc4_crtc) 161 { 162 struct drm_crtc *crtc = &vc4_crtc->base; 163 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state); 164 u32 i; 165 166 /* The LUT memory is laid out with each HVS channel in order, 167 * each of which takes 256 writes for R, 256 for G, then 256 168 * for B. 169 */ 170 HVS_WRITE(SCALER_GAMADDR, 171 SCALER_GAMADDR_AUTOINC | 172 (vc4_state->assigned_channel * 3 * crtc->gamma_size)); 173 174 for (i = 0; i < crtc->gamma_size; i++) 175 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_r[i]); 176 for (i = 0; i < crtc->gamma_size; i++) 177 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_g[i]); 178 for (i = 0; i < crtc->gamma_size; i++) 179 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_b[i]); 180 } 181 182 static void vc4_hvs_update_gamma_lut(struct vc4_hvs *hvs, 183 struct vc4_crtc *vc4_crtc) 184 { 185 struct drm_crtc_state *crtc_state = vc4_crtc->base.state; 186 struct drm_color_lut *lut = crtc_state->gamma_lut->data; 187 u32 length = drm_color_lut_size(crtc_state->gamma_lut); 188 u32 i; 189 190 for (i = 0; i < length; i++) { 191 vc4_crtc->lut_r[i] = drm_color_lut_extract(lut[i].red, 8); 192 vc4_crtc->lut_g[i] = drm_color_lut_extract(lut[i].green, 8); 193 vc4_crtc->lut_b[i] = drm_color_lut_extract(lut[i].blue, 8); 194 } 195 196 vc4_hvs_lut_load(hvs, vc4_crtc); 197 } 198 199 u8 vc4_hvs_get_fifo_frame_count(struct vc4_hvs *hvs, unsigned int fifo) 200 { 201 u8 field = 0; 202 203 switch (fifo) { 204 case 0: 205 field = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTAT1), 206 SCALER_DISPSTAT1_FRCNT0); 207 break; 208 case 1: 209 field = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTAT1), 210 SCALER_DISPSTAT1_FRCNT1); 211 break; 212 case 2: 213 field = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTAT2), 214 SCALER_DISPSTAT2_FRCNT2); 215 break; 216 } 217 218 return field; 219 } 220 221 int vc4_hvs_get_fifo_from_output(struct vc4_hvs *hvs, unsigned int output) 222 { 223 u32 reg; 224 int ret; 225 226 if (!hvs->hvs5) 227 return output; 228 229 switch (output) { 230 case 0: 231 return 0; 232 233 case 1: 234 return 1; 235 236 case 2: 237 reg = HVS_READ(SCALER_DISPECTRL); 238 ret = FIELD_GET(SCALER_DISPECTRL_DSP2_MUX_MASK, reg); 239 if (ret == 0) 240 return 2; 241 242 return 0; 243 244 case 3: 245 reg = HVS_READ(SCALER_DISPCTRL); 246 ret = FIELD_GET(SCALER_DISPCTRL_DSP3_MUX_MASK, reg); 247 if (ret == 3) 248 return -EPIPE; 249 250 return ret; 251 252 case 4: 253 reg = HVS_READ(SCALER_DISPEOLN); 254 ret = FIELD_GET(SCALER_DISPEOLN_DSP4_MUX_MASK, reg); 255 if (ret == 3) 256 return -EPIPE; 257 258 return ret; 259 260 case 5: 261 reg = HVS_READ(SCALER_DISPDITHER); 262 ret = FIELD_GET(SCALER_DISPDITHER_DSP5_MUX_MASK, reg); 263 if (ret == 3) 264 return -EPIPE; 265 266 return ret; 267 268 default: 269 return -EPIPE; 270 } 271 } 272 273 static int vc4_hvs_init_channel(struct vc4_hvs *hvs, struct drm_crtc *crtc, 274 struct drm_display_mode *mode, bool oneshot) 275 { 276 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 277 struct vc4_crtc_state *vc4_crtc_state = to_vc4_crtc_state(crtc->state); 278 unsigned int chan = vc4_crtc_state->assigned_channel; 279 bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE; 280 u32 dispbkgndx; 281 u32 dispctrl; 282 283 HVS_WRITE(SCALER_DISPCTRLX(chan), 0); 284 HVS_WRITE(SCALER_DISPCTRLX(chan), SCALER_DISPCTRLX_RESET); 285 HVS_WRITE(SCALER_DISPCTRLX(chan), 0); 286 287 /* Turn on the scaler, which will wait for vstart to start 288 * compositing. 289 * When feeding the transposer, we should operate in oneshot 290 * mode. 291 */ 292 dispctrl = SCALER_DISPCTRLX_ENABLE; 293 294 if (!hvs->hvs5) 295 dispctrl |= VC4_SET_FIELD(mode->hdisplay, 296 SCALER_DISPCTRLX_WIDTH) | 297 VC4_SET_FIELD(mode->vdisplay, 298 SCALER_DISPCTRLX_HEIGHT) | 299 (oneshot ? SCALER_DISPCTRLX_ONESHOT : 0); 300 else 301 dispctrl |= VC4_SET_FIELD(mode->hdisplay, 302 SCALER5_DISPCTRLX_WIDTH) | 303 VC4_SET_FIELD(mode->vdisplay, 304 SCALER5_DISPCTRLX_HEIGHT) | 305 (oneshot ? SCALER5_DISPCTRLX_ONESHOT : 0); 306 307 HVS_WRITE(SCALER_DISPCTRLX(chan), dispctrl); 308 309 dispbkgndx = HVS_READ(SCALER_DISPBKGNDX(chan)); 310 dispbkgndx &= ~SCALER_DISPBKGND_GAMMA; 311 dispbkgndx &= ~SCALER_DISPBKGND_INTERLACE; 312 313 HVS_WRITE(SCALER_DISPBKGNDX(chan), dispbkgndx | 314 SCALER_DISPBKGND_AUTOHS | 315 ((!hvs->hvs5) ? SCALER_DISPBKGND_GAMMA : 0) | 316 (interlace ? SCALER_DISPBKGND_INTERLACE : 0)); 317 318 /* Reload the LUT, since the SRAMs would have been disabled if 319 * all CRTCs had SCALER_DISPBKGND_GAMMA unset at once. 320 */ 321 vc4_hvs_lut_load(hvs, vc4_crtc); 322 323 return 0; 324 } 325 326 void vc4_hvs_stop_channel(struct vc4_hvs *hvs, unsigned int chan) 327 { 328 if (HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_ENABLE) 329 return; 330 331 HVS_WRITE(SCALER_DISPCTRLX(chan), 332 HVS_READ(SCALER_DISPCTRLX(chan)) | SCALER_DISPCTRLX_RESET); 333 HVS_WRITE(SCALER_DISPCTRLX(chan), 334 HVS_READ(SCALER_DISPCTRLX(chan)) & ~SCALER_DISPCTRLX_ENABLE); 335 336 /* Once we leave, the scaler should be disabled and its fifo empty. */ 337 WARN_ON_ONCE(HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_RESET); 338 339 WARN_ON_ONCE(VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(chan)), 340 SCALER_DISPSTATX_MODE) != 341 SCALER_DISPSTATX_MODE_DISABLED); 342 343 WARN_ON_ONCE((HVS_READ(SCALER_DISPSTATX(chan)) & 344 (SCALER_DISPSTATX_FULL | SCALER_DISPSTATX_EMPTY)) != 345 SCALER_DISPSTATX_EMPTY); 346 } 347 348 int vc4_hvs_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *state) 349 { 350 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 351 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state); 352 struct drm_device *dev = crtc->dev; 353 struct vc4_dev *vc4 = to_vc4_dev(dev); 354 struct drm_plane *plane; 355 unsigned long flags; 356 const struct drm_plane_state *plane_state; 357 u32 dlist_count = 0; 358 int ret; 359 360 /* The pixelvalve can only feed one encoder (and encoders are 361 * 1:1 with connectors.) 362 */ 363 if (hweight32(crtc_state->connector_mask) > 1) 364 return -EINVAL; 365 366 drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) 367 dlist_count += vc4_plane_dlist_size(plane_state); 368 369 dlist_count++; /* Account for SCALER_CTL0_END. */ 370 371 spin_lock_irqsave(&vc4->hvs->mm_lock, flags); 372 ret = drm_mm_insert_node(&vc4->hvs->dlist_mm, &vc4_state->mm, 373 dlist_count); 374 spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags); 375 if (ret) 376 return ret; 377 378 return 0; 379 } 380 381 static void vc4_hvs_install_dlist(struct drm_crtc *crtc) 382 { 383 struct drm_device *dev = crtc->dev; 384 struct vc4_dev *vc4 = to_vc4_dev(dev); 385 struct vc4_hvs *hvs = vc4->hvs; 386 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state); 387 388 HVS_WRITE(SCALER_DISPLISTX(vc4_state->assigned_channel), 389 vc4_state->mm.start); 390 } 391 392 static void vc4_hvs_update_dlist(struct drm_crtc *crtc) 393 { 394 struct drm_device *dev = crtc->dev; 395 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 396 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state); 397 unsigned long flags; 398 399 if (crtc->state->event) { 400 crtc->state->event->pipe = drm_crtc_index(crtc); 401 402 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 403 404 spin_lock_irqsave(&dev->event_lock, flags); 405 406 if (!vc4_crtc->feeds_txp || vc4_state->txp_armed) { 407 vc4_crtc->event = crtc->state->event; 408 crtc->state->event = NULL; 409 } 410 411 spin_unlock_irqrestore(&dev->event_lock, flags); 412 } 413 414 spin_lock_irqsave(&vc4_crtc->irq_lock, flags); 415 vc4_crtc->current_dlist = vc4_state->mm.start; 416 spin_unlock_irqrestore(&vc4_crtc->irq_lock, flags); 417 } 418 419 void vc4_hvs_atomic_begin(struct drm_crtc *crtc, 420 struct drm_atomic_state *state) 421 { 422 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 423 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state); 424 unsigned long flags; 425 426 spin_lock_irqsave(&vc4_crtc->irq_lock, flags); 427 vc4_crtc->current_hvs_channel = vc4_state->assigned_channel; 428 spin_unlock_irqrestore(&vc4_crtc->irq_lock, flags); 429 } 430 431 void vc4_hvs_atomic_enable(struct drm_crtc *crtc, 432 struct drm_atomic_state *state) 433 { 434 struct drm_device *dev = crtc->dev; 435 struct vc4_dev *vc4 = to_vc4_dev(dev); 436 struct drm_display_mode *mode = &crtc->state->adjusted_mode; 437 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 438 bool oneshot = vc4_crtc->feeds_txp; 439 440 vc4_hvs_install_dlist(crtc); 441 vc4_hvs_update_dlist(crtc); 442 vc4_hvs_init_channel(vc4->hvs, crtc, mode, oneshot); 443 } 444 445 void vc4_hvs_atomic_disable(struct drm_crtc *crtc, 446 struct drm_atomic_state *state) 447 { 448 struct drm_device *dev = crtc->dev; 449 struct vc4_dev *vc4 = to_vc4_dev(dev); 450 struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state, crtc); 451 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(old_state); 452 unsigned int chan = vc4_state->assigned_channel; 453 454 vc4_hvs_stop_channel(vc4->hvs, chan); 455 } 456 457 void vc4_hvs_atomic_flush(struct drm_crtc *crtc, 458 struct drm_atomic_state *state) 459 { 460 struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state, 461 crtc); 462 struct drm_device *dev = crtc->dev; 463 struct vc4_dev *vc4 = to_vc4_dev(dev); 464 struct vc4_hvs *hvs = vc4->hvs; 465 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 466 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state); 467 unsigned int channel = vc4_state->assigned_channel; 468 struct drm_plane *plane; 469 struct vc4_plane_state *vc4_plane_state; 470 bool debug_dump_regs = false; 471 bool enable_bg_fill = false; 472 u32 __iomem *dlist_start = vc4->hvs->dlist + vc4_state->mm.start; 473 u32 __iomem *dlist_next = dlist_start; 474 475 if (debug_dump_regs) { 476 DRM_INFO("CRTC %d HVS before:\n", drm_crtc_index(crtc)); 477 vc4_hvs_dump_state(hvs); 478 } 479 480 /* Copy all the active planes' dlist contents to the hardware dlist. */ 481 drm_atomic_crtc_for_each_plane(plane, crtc) { 482 /* Is this the first active plane? */ 483 if (dlist_next == dlist_start) { 484 /* We need to enable background fill when a plane 485 * could be alpha blending from the background, i.e. 486 * where no other plane is underneath. It suffices to 487 * consider the first active plane here since we set 488 * needs_bg_fill such that either the first plane 489 * already needs it or all planes on top blend from 490 * the first or a lower plane. 491 */ 492 vc4_plane_state = to_vc4_plane_state(plane->state); 493 enable_bg_fill = vc4_plane_state->needs_bg_fill; 494 } 495 496 dlist_next += vc4_plane_write_dlist(plane, dlist_next); 497 } 498 499 writel(SCALER_CTL0_END, dlist_next); 500 dlist_next++; 501 502 WARN_ON_ONCE(dlist_next - dlist_start != vc4_state->mm.size); 503 504 if (enable_bg_fill) 505 /* This sets a black background color fill, as is the case 506 * with other DRM drivers. 507 */ 508 HVS_WRITE(SCALER_DISPBKGNDX(channel), 509 HVS_READ(SCALER_DISPBKGNDX(channel)) | 510 SCALER_DISPBKGND_FILL); 511 512 /* Only update DISPLIST if the CRTC was already running and is not 513 * being disabled. 514 * vc4_crtc_enable() takes care of updating the dlist just after 515 * re-enabling VBLANK interrupts and before enabling the engine. 516 * If the CRTC is being disabled, there's no point in updating this 517 * information. 518 */ 519 if (crtc->state->active && old_state->active) { 520 vc4_hvs_install_dlist(crtc); 521 vc4_hvs_update_dlist(crtc); 522 } 523 524 if (crtc->state->color_mgmt_changed) { 525 u32 dispbkgndx = HVS_READ(SCALER_DISPBKGNDX(channel)); 526 527 if (crtc->state->gamma_lut) { 528 vc4_hvs_update_gamma_lut(hvs, vc4_crtc); 529 dispbkgndx |= SCALER_DISPBKGND_GAMMA; 530 } else { 531 /* Unsetting DISPBKGND_GAMMA skips the gamma lut step 532 * in hardware, which is the same as a linear lut that 533 * DRM expects us to use in absence of a user lut. 534 */ 535 dispbkgndx &= ~SCALER_DISPBKGND_GAMMA; 536 } 537 HVS_WRITE(SCALER_DISPBKGNDX(channel), dispbkgndx); 538 } 539 540 if (debug_dump_regs) { 541 DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc)); 542 vc4_hvs_dump_state(hvs); 543 } 544 } 545 546 void vc4_hvs_mask_underrun(struct vc4_hvs *hvs, int channel) 547 { 548 u32 dispctrl = HVS_READ(SCALER_DISPCTRL); 549 550 dispctrl &= ~SCALER_DISPCTRL_DSPEISLUR(channel); 551 552 HVS_WRITE(SCALER_DISPCTRL, dispctrl); 553 } 554 555 void vc4_hvs_unmask_underrun(struct vc4_hvs *hvs, int channel) 556 { 557 u32 dispctrl = HVS_READ(SCALER_DISPCTRL); 558 559 dispctrl |= SCALER_DISPCTRL_DSPEISLUR(channel); 560 561 HVS_WRITE(SCALER_DISPSTAT, 562 SCALER_DISPSTAT_EUFLOW(channel)); 563 HVS_WRITE(SCALER_DISPCTRL, dispctrl); 564 } 565 566 static void vc4_hvs_report_underrun(struct drm_device *dev) 567 { 568 struct vc4_dev *vc4 = to_vc4_dev(dev); 569 570 atomic_inc(&vc4->underrun); 571 DRM_DEV_ERROR(dev->dev, "HVS underrun\n"); 572 } 573 574 static irqreturn_t vc4_hvs_irq_handler(int irq, void *data) 575 { 576 struct drm_device *dev = data; 577 struct vc4_dev *vc4 = to_vc4_dev(dev); 578 struct vc4_hvs *hvs = vc4->hvs; 579 irqreturn_t irqret = IRQ_NONE; 580 int channel; 581 u32 control; 582 u32 status; 583 584 status = HVS_READ(SCALER_DISPSTAT); 585 control = HVS_READ(SCALER_DISPCTRL); 586 587 for (channel = 0; channel < SCALER_CHANNELS_COUNT; channel++) { 588 /* Interrupt masking is not always honored, so check it here. */ 589 if (status & SCALER_DISPSTAT_EUFLOW(channel) && 590 control & SCALER_DISPCTRL_DSPEISLUR(channel)) { 591 vc4_hvs_mask_underrun(hvs, channel); 592 vc4_hvs_report_underrun(dev); 593 594 irqret = IRQ_HANDLED; 595 } 596 } 597 598 /* Clear every per-channel interrupt flag. */ 599 HVS_WRITE(SCALER_DISPSTAT, SCALER_DISPSTAT_IRQMASK(0) | 600 SCALER_DISPSTAT_IRQMASK(1) | 601 SCALER_DISPSTAT_IRQMASK(2)); 602 603 return irqret; 604 } 605 606 static int vc4_hvs_bind(struct device *dev, struct device *master, void *data) 607 { 608 struct platform_device *pdev = to_platform_device(dev); 609 struct drm_device *drm = dev_get_drvdata(master); 610 struct vc4_dev *vc4 = to_vc4_dev(drm); 611 struct vc4_hvs *hvs = NULL; 612 int ret; 613 u32 dispctrl; 614 u32 reg; 615 616 hvs = devm_kzalloc(&pdev->dev, sizeof(*hvs), GFP_KERNEL); 617 if (!hvs) 618 return -ENOMEM; 619 620 hvs->pdev = pdev; 621 622 if (of_device_is_compatible(pdev->dev.of_node, "brcm,bcm2711-hvs")) 623 hvs->hvs5 = true; 624 625 hvs->regs = vc4_ioremap_regs(pdev, 0); 626 if (IS_ERR(hvs->regs)) 627 return PTR_ERR(hvs->regs); 628 629 hvs->regset.base = hvs->regs; 630 hvs->regset.regs = hvs_regs; 631 hvs->regset.nregs = ARRAY_SIZE(hvs_regs); 632 633 if (hvs->hvs5) { 634 hvs->core_clk = devm_clk_get(&pdev->dev, NULL); 635 if (IS_ERR(hvs->core_clk)) { 636 dev_err(&pdev->dev, "Couldn't get core clock\n"); 637 return PTR_ERR(hvs->core_clk); 638 } 639 640 ret = clk_prepare_enable(hvs->core_clk); 641 if (ret) { 642 dev_err(&pdev->dev, "Couldn't enable the core clock\n"); 643 return ret; 644 } 645 } 646 647 if (!hvs->hvs5) 648 hvs->dlist = hvs->regs + SCALER_DLIST_START; 649 else 650 hvs->dlist = hvs->regs + SCALER5_DLIST_START; 651 652 spin_lock_init(&hvs->mm_lock); 653 654 /* Set up the HVS display list memory manager. We never 655 * overwrite the setup from the bootloader (just 128b out of 656 * our 16K), since we don't want to scramble the screen when 657 * transitioning from the firmware's boot setup to runtime. 658 */ 659 drm_mm_init(&hvs->dlist_mm, 660 HVS_BOOTLOADER_DLIST_END, 661 (SCALER_DLIST_SIZE >> 2) - HVS_BOOTLOADER_DLIST_END); 662 663 /* Set up the HVS LBM memory manager. We could have some more 664 * complicated data structure that allowed reuse of LBM areas 665 * between planes when they don't overlap on the screen, but 666 * for now we just allocate globally. 667 */ 668 if (!hvs->hvs5) 669 /* 48k words of 2x12-bit pixels */ 670 drm_mm_init(&hvs->lbm_mm, 0, 48 * 1024); 671 else 672 /* 60k words of 4x12-bit pixels */ 673 drm_mm_init(&hvs->lbm_mm, 0, 60 * 1024); 674 675 /* Upload filter kernels. We only have the one for now, so we 676 * keep it around for the lifetime of the driver. 677 */ 678 ret = vc4_hvs_upload_linear_kernel(hvs, 679 &hvs->mitchell_netravali_filter, 680 mitchell_netravali_1_3_1_3_kernel); 681 if (ret) 682 return ret; 683 684 vc4->hvs = hvs; 685 686 reg = HVS_READ(SCALER_DISPECTRL); 687 reg &= ~SCALER_DISPECTRL_DSP2_MUX_MASK; 688 HVS_WRITE(SCALER_DISPECTRL, 689 reg | VC4_SET_FIELD(0, SCALER_DISPECTRL_DSP2_MUX)); 690 691 reg = HVS_READ(SCALER_DISPCTRL); 692 reg &= ~SCALER_DISPCTRL_DSP3_MUX_MASK; 693 HVS_WRITE(SCALER_DISPCTRL, 694 reg | VC4_SET_FIELD(3, SCALER_DISPCTRL_DSP3_MUX)); 695 696 reg = HVS_READ(SCALER_DISPEOLN); 697 reg &= ~SCALER_DISPEOLN_DSP4_MUX_MASK; 698 HVS_WRITE(SCALER_DISPEOLN, 699 reg | VC4_SET_FIELD(3, SCALER_DISPEOLN_DSP4_MUX)); 700 701 reg = HVS_READ(SCALER_DISPDITHER); 702 reg &= ~SCALER_DISPDITHER_DSP5_MUX_MASK; 703 HVS_WRITE(SCALER_DISPDITHER, 704 reg | VC4_SET_FIELD(3, SCALER_DISPDITHER_DSP5_MUX)); 705 706 dispctrl = HVS_READ(SCALER_DISPCTRL); 707 708 dispctrl |= SCALER_DISPCTRL_ENABLE; 709 dispctrl |= SCALER_DISPCTRL_DISPEIRQ(0) | 710 SCALER_DISPCTRL_DISPEIRQ(1) | 711 SCALER_DISPCTRL_DISPEIRQ(2); 712 713 dispctrl &= ~(SCALER_DISPCTRL_DMAEIRQ | 714 SCALER_DISPCTRL_SLVWREIRQ | 715 SCALER_DISPCTRL_SLVRDEIRQ | 716 SCALER_DISPCTRL_DSPEIEOF(0) | 717 SCALER_DISPCTRL_DSPEIEOF(1) | 718 SCALER_DISPCTRL_DSPEIEOF(2) | 719 SCALER_DISPCTRL_DSPEIEOLN(0) | 720 SCALER_DISPCTRL_DSPEIEOLN(1) | 721 SCALER_DISPCTRL_DSPEIEOLN(2) | 722 SCALER_DISPCTRL_DSPEISLUR(0) | 723 SCALER_DISPCTRL_DSPEISLUR(1) | 724 SCALER_DISPCTRL_DSPEISLUR(2) | 725 SCALER_DISPCTRL_SCLEIRQ); 726 727 HVS_WRITE(SCALER_DISPCTRL, dispctrl); 728 729 ret = devm_request_irq(dev, platform_get_irq(pdev, 0), 730 vc4_hvs_irq_handler, 0, "vc4 hvs", drm); 731 if (ret) 732 return ret; 733 734 vc4_debugfs_add_regset32(drm, "hvs_regs", &hvs->regset); 735 vc4_debugfs_add_file(drm, "hvs_underrun", vc4_hvs_debugfs_underrun, 736 NULL); 737 738 return 0; 739 } 740 741 static void vc4_hvs_unbind(struct device *dev, struct device *master, 742 void *data) 743 { 744 struct drm_device *drm = dev_get_drvdata(master); 745 struct vc4_dev *vc4 = to_vc4_dev(drm); 746 struct vc4_hvs *hvs = vc4->hvs; 747 748 if (drm_mm_node_allocated(&vc4->hvs->mitchell_netravali_filter)) 749 drm_mm_remove_node(&vc4->hvs->mitchell_netravali_filter); 750 751 drm_mm_takedown(&vc4->hvs->dlist_mm); 752 drm_mm_takedown(&vc4->hvs->lbm_mm); 753 754 clk_disable_unprepare(hvs->core_clk); 755 756 vc4->hvs = NULL; 757 } 758 759 static const struct component_ops vc4_hvs_ops = { 760 .bind = vc4_hvs_bind, 761 .unbind = vc4_hvs_unbind, 762 }; 763 764 static int vc4_hvs_dev_probe(struct platform_device *pdev) 765 { 766 return component_add(&pdev->dev, &vc4_hvs_ops); 767 } 768 769 static int vc4_hvs_dev_remove(struct platform_device *pdev) 770 { 771 component_del(&pdev->dev, &vc4_hvs_ops); 772 return 0; 773 } 774 775 static const struct of_device_id vc4_hvs_dt_match[] = { 776 { .compatible = "brcm,bcm2711-hvs" }, 777 { .compatible = "brcm,bcm2835-hvs" }, 778 {} 779 }; 780 781 struct platform_driver vc4_hvs_driver = { 782 .probe = vc4_hvs_dev_probe, 783 .remove = vc4_hvs_dev_remove, 784 .driver = { 785 .name = "vc4_hvs", 786 .of_match_table = vc4_hvs_dt_match, 787 }, 788 }; 789