1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 Broadcom 4 */ 5 6 /** 7 * DOC: VC4 HVS module. 8 * 9 * The Hardware Video Scaler (HVS) is the piece of hardware that does 10 * translation, scaling, colorspace conversion, and compositing of 11 * pixels stored in framebuffers into a FIFO of pixels going out to 12 * the Pixel Valve (CRTC). It operates at the system clock rate (the 13 * system audio clock gate, specifically), which is much higher than 14 * the pixel clock rate. 15 * 16 * There is a single global HVS, with multiple output FIFOs that can 17 * be consumed by the PVs. This file just manages the resources for 18 * the HVS, while the vc4_crtc.c code actually drives HVS setup for 19 * each CRTC. 20 */ 21 22 #include <linux/bitfield.h> 23 #include <linux/clk.h> 24 #include <linux/component.h> 25 #include <linux/platform_device.h> 26 27 #include <drm/drm_atomic_helper.h> 28 #include <drm/drm_drv.h> 29 #include <drm/drm_vblank.h> 30 31 #include <soc/bcm2835/raspberrypi-firmware.h> 32 33 #include "vc4_drv.h" 34 #include "vc4_regs.h" 35 36 static const struct debugfs_reg32 hvs_regs[] = { 37 VC4_REG32(SCALER_DISPCTRL), 38 VC4_REG32(SCALER_DISPSTAT), 39 VC4_REG32(SCALER_DISPID), 40 VC4_REG32(SCALER_DISPECTRL), 41 VC4_REG32(SCALER_DISPPROF), 42 VC4_REG32(SCALER_DISPDITHER), 43 VC4_REG32(SCALER_DISPEOLN), 44 VC4_REG32(SCALER_DISPLIST0), 45 VC4_REG32(SCALER_DISPLIST1), 46 VC4_REG32(SCALER_DISPLIST2), 47 VC4_REG32(SCALER_DISPLSTAT), 48 VC4_REG32(SCALER_DISPLACT0), 49 VC4_REG32(SCALER_DISPLACT1), 50 VC4_REG32(SCALER_DISPLACT2), 51 VC4_REG32(SCALER_DISPCTRL0), 52 VC4_REG32(SCALER_DISPBKGND0), 53 VC4_REG32(SCALER_DISPSTAT0), 54 VC4_REG32(SCALER_DISPBASE0), 55 VC4_REG32(SCALER_DISPCTRL1), 56 VC4_REG32(SCALER_DISPBKGND1), 57 VC4_REG32(SCALER_DISPSTAT1), 58 VC4_REG32(SCALER_DISPBASE1), 59 VC4_REG32(SCALER_DISPCTRL2), 60 VC4_REG32(SCALER_DISPBKGND2), 61 VC4_REG32(SCALER_DISPSTAT2), 62 VC4_REG32(SCALER_DISPBASE2), 63 VC4_REG32(SCALER_DISPALPHA2), 64 VC4_REG32(SCALER_OLEDOFFS), 65 VC4_REG32(SCALER_OLEDCOEF0), 66 VC4_REG32(SCALER_OLEDCOEF1), 67 VC4_REG32(SCALER_OLEDCOEF2), 68 }; 69 70 void vc4_hvs_dump_state(struct vc4_hvs *hvs) 71 { 72 struct drm_device *drm = &hvs->vc4->base; 73 struct drm_printer p = drm_info_printer(&hvs->pdev->dev); 74 int idx, i; 75 76 if (!drm_dev_enter(drm, &idx)) 77 return; 78 79 drm_print_regset32(&p, &hvs->regset); 80 81 DRM_INFO("HVS ctx:\n"); 82 for (i = 0; i < 64; i += 4) { 83 DRM_INFO("0x%08x (%s): 0x%08x 0x%08x 0x%08x 0x%08x\n", 84 i * 4, i < HVS_BOOTLOADER_DLIST_END ? "B" : "D", 85 readl((u32 __iomem *)hvs->dlist + i + 0), 86 readl((u32 __iomem *)hvs->dlist + i + 1), 87 readl((u32 __iomem *)hvs->dlist + i + 2), 88 readl((u32 __iomem *)hvs->dlist + i + 3)); 89 } 90 91 drm_dev_exit(idx); 92 } 93 94 static int vc4_hvs_debugfs_underrun(struct seq_file *m, void *data) 95 { 96 struct drm_info_node *node = m->private; 97 struct drm_device *dev = node->minor->dev; 98 struct vc4_dev *vc4 = to_vc4_dev(dev); 99 struct drm_printer p = drm_seq_file_printer(m); 100 101 drm_printf(&p, "%d\n", atomic_read(&vc4->underrun)); 102 103 return 0; 104 } 105 106 static int vc4_hvs_debugfs_dlist(struct seq_file *m, void *data) 107 { 108 struct drm_info_node *node = m->private; 109 struct drm_device *dev = node->minor->dev; 110 struct vc4_dev *vc4 = to_vc4_dev(dev); 111 struct vc4_hvs *hvs = vc4->hvs; 112 struct drm_printer p = drm_seq_file_printer(m); 113 unsigned int next_entry_start = 0; 114 unsigned int i, j; 115 u32 dlist_word, dispstat; 116 117 for (i = 0; i < SCALER_CHANNELS_COUNT; i++) { 118 dispstat = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(i)), 119 SCALER_DISPSTATX_MODE); 120 if (dispstat == SCALER_DISPSTATX_MODE_DISABLED || 121 dispstat == SCALER_DISPSTATX_MODE_EOF) { 122 drm_printf(&p, "HVS chan %u disabled\n", i); 123 continue; 124 } 125 126 drm_printf(&p, "HVS chan %u:\n", i); 127 128 for (j = HVS_READ(SCALER_DISPLISTX(i)); j < 256; j++) { 129 dlist_word = readl((u32 __iomem *)vc4->hvs->dlist + j); 130 drm_printf(&p, "dlist: %02d: 0x%08x\n", j, 131 dlist_word); 132 if (!next_entry_start || 133 next_entry_start == j) { 134 if (dlist_word & SCALER_CTL0_END) 135 break; 136 next_entry_start = j + 137 VC4_GET_FIELD(dlist_word, 138 SCALER_CTL0_SIZE); 139 } 140 } 141 } 142 143 return 0; 144 } 145 146 /* The filter kernel is composed of dwords each containing 3 9-bit 147 * signed integers packed next to each other. 148 */ 149 #define VC4_INT_TO_COEFF(coeff) (coeff & 0x1ff) 150 #define VC4_PPF_FILTER_WORD(c0, c1, c2) \ 151 ((((c0) & 0x1ff) << 0) | \ 152 (((c1) & 0x1ff) << 9) | \ 153 (((c2) & 0x1ff) << 18)) 154 155 /* The whole filter kernel is arranged as the coefficients 0-16 going 156 * up, then a pad, then 17-31 going down and reversed within the 157 * dwords. This means that a linear phase kernel (where it's 158 * symmetrical at the boundary between 15 and 16) has the last 5 159 * dwords matching the first 5, but reversed. 160 */ 161 #define VC4_LINEAR_PHASE_KERNEL(c0, c1, c2, c3, c4, c5, c6, c7, c8, \ 162 c9, c10, c11, c12, c13, c14, c15) \ 163 {VC4_PPF_FILTER_WORD(c0, c1, c2), \ 164 VC4_PPF_FILTER_WORD(c3, c4, c5), \ 165 VC4_PPF_FILTER_WORD(c6, c7, c8), \ 166 VC4_PPF_FILTER_WORD(c9, c10, c11), \ 167 VC4_PPF_FILTER_WORD(c12, c13, c14), \ 168 VC4_PPF_FILTER_WORD(c15, c15, 0)} 169 170 #define VC4_LINEAR_PHASE_KERNEL_DWORDS 6 171 #define VC4_KERNEL_DWORDS (VC4_LINEAR_PHASE_KERNEL_DWORDS * 2 - 1) 172 173 /* Recommended B=1/3, C=1/3 filter choice from Mitchell/Netravali. 174 * http://www.cs.utexas.edu/~fussell/courses/cs384g/lectures/mitchell/Mitchell.pdf 175 */ 176 static const u32 mitchell_netravali_1_3_1_3_kernel[] = 177 VC4_LINEAR_PHASE_KERNEL(0, -2, -6, -8, -10, -8, -3, 2, 18, 178 50, 82, 119, 155, 187, 213, 227); 179 180 static int vc4_hvs_upload_linear_kernel(struct vc4_hvs *hvs, 181 struct drm_mm_node *space, 182 const u32 *kernel) 183 { 184 int ret, i; 185 u32 __iomem *dst_kernel; 186 187 /* 188 * NOTE: We don't need a call to drm_dev_enter()/drm_dev_exit() 189 * here since that function is only called from vc4_hvs_bind(). 190 */ 191 192 ret = drm_mm_insert_node(&hvs->dlist_mm, space, VC4_KERNEL_DWORDS); 193 if (ret) { 194 DRM_ERROR("Failed to allocate space for filter kernel: %d\n", 195 ret); 196 return ret; 197 } 198 199 dst_kernel = hvs->dlist + space->start; 200 201 for (i = 0; i < VC4_KERNEL_DWORDS; i++) { 202 if (i < VC4_LINEAR_PHASE_KERNEL_DWORDS) 203 writel(kernel[i], &dst_kernel[i]); 204 else { 205 writel(kernel[VC4_KERNEL_DWORDS - i - 1], 206 &dst_kernel[i]); 207 } 208 } 209 210 return 0; 211 } 212 213 static void vc4_hvs_lut_load(struct vc4_hvs *hvs, 214 struct vc4_crtc *vc4_crtc) 215 { 216 struct drm_device *drm = &hvs->vc4->base; 217 struct drm_crtc *crtc = &vc4_crtc->base; 218 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state); 219 int idx; 220 u32 i; 221 222 if (!drm_dev_enter(drm, &idx)) 223 return; 224 225 /* The LUT memory is laid out with each HVS channel in order, 226 * each of which takes 256 writes for R, 256 for G, then 256 227 * for B. 228 */ 229 HVS_WRITE(SCALER_GAMADDR, 230 SCALER_GAMADDR_AUTOINC | 231 (vc4_state->assigned_channel * 3 * crtc->gamma_size)); 232 233 for (i = 0; i < crtc->gamma_size; i++) 234 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_r[i]); 235 for (i = 0; i < crtc->gamma_size; i++) 236 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_g[i]); 237 for (i = 0; i < crtc->gamma_size; i++) 238 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_b[i]); 239 240 drm_dev_exit(idx); 241 } 242 243 static void vc4_hvs_update_gamma_lut(struct vc4_hvs *hvs, 244 struct vc4_crtc *vc4_crtc) 245 { 246 struct drm_crtc_state *crtc_state = vc4_crtc->base.state; 247 struct drm_color_lut *lut = crtc_state->gamma_lut->data; 248 u32 length = drm_color_lut_size(crtc_state->gamma_lut); 249 u32 i; 250 251 for (i = 0; i < length; i++) { 252 vc4_crtc->lut_r[i] = drm_color_lut_extract(lut[i].red, 8); 253 vc4_crtc->lut_g[i] = drm_color_lut_extract(lut[i].green, 8); 254 vc4_crtc->lut_b[i] = drm_color_lut_extract(lut[i].blue, 8); 255 } 256 257 vc4_hvs_lut_load(hvs, vc4_crtc); 258 } 259 260 u8 vc4_hvs_get_fifo_frame_count(struct vc4_hvs *hvs, unsigned int fifo) 261 { 262 struct drm_device *drm = &hvs->vc4->base; 263 u8 field = 0; 264 int idx; 265 266 if (!drm_dev_enter(drm, &idx)) 267 return 0; 268 269 switch (fifo) { 270 case 0: 271 field = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTAT1), 272 SCALER_DISPSTAT1_FRCNT0); 273 break; 274 case 1: 275 field = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTAT1), 276 SCALER_DISPSTAT1_FRCNT1); 277 break; 278 case 2: 279 field = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTAT2), 280 SCALER_DISPSTAT2_FRCNT2); 281 break; 282 } 283 284 drm_dev_exit(idx); 285 return field; 286 } 287 288 int vc4_hvs_get_fifo_from_output(struct vc4_hvs *hvs, unsigned int output) 289 { 290 struct vc4_dev *vc4 = hvs->vc4; 291 u32 reg; 292 int ret; 293 294 if (!vc4->is_vc5) 295 return output; 296 297 /* 298 * NOTE: We should probably use drm_dev_enter()/drm_dev_exit() 299 * here, but this function is only used during the DRM device 300 * initialization, so we should be fine. 301 */ 302 303 switch (output) { 304 case 0: 305 return 0; 306 307 case 1: 308 return 1; 309 310 case 2: 311 reg = HVS_READ(SCALER_DISPECTRL); 312 ret = FIELD_GET(SCALER_DISPECTRL_DSP2_MUX_MASK, reg); 313 if (ret == 0) 314 return 2; 315 316 return 0; 317 318 case 3: 319 reg = HVS_READ(SCALER_DISPCTRL); 320 ret = FIELD_GET(SCALER_DISPCTRL_DSP3_MUX_MASK, reg); 321 if (ret == 3) 322 return -EPIPE; 323 324 return ret; 325 326 case 4: 327 reg = HVS_READ(SCALER_DISPEOLN); 328 ret = FIELD_GET(SCALER_DISPEOLN_DSP4_MUX_MASK, reg); 329 if (ret == 3) 330 return -EPIPE; 331 332 return ret; 333 334 case 5: 335 reg = HVS_READ(SCALER_DISPDITHER); 336 ret = FIELD_GET(SCALER_DISPDITHER_DSP5_MUX_MASK, reg); 337 if (ret == 3) 338 return -EPIPE; 339 340 return ret; 341 342 default: 343 return -EPIPE; 344 } 345 } 346 347 static int vc4_hvs_init_channel(struct vc4_hvs *hvs, struct drm_crtc *crtc, 348 struct drm_display_mode *mode, bool oneshot) 349 { 350 struct vc4_dev *vc4 = hvs->vc4; 351 struct drm_device *drm = &vc4->base; 352 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 353 struct vc4_crtc_state *vc4_crtc_state = to_vc4_crtc_state(crtc->state); 354 unsigned int chan = vc4_crtc_state->assigned_channel; 355 bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE; 356 u32 dispbkgndx; 357 u32 dispctrl; 358 int idx; 359 360 if (!drm_dev_enter(drm, &idx)) 361 return -ENODEV; 362 363 HVS_WRITE(SCALER_DISPCTRLX(chan), 0); 364 HVS_WRITE(SCALER_DISPCTRLX(chan), SCALER_DISPCTRLX_RESET); 365 HVS_WRITE(SCALER_DISPCTRLX(chan), 0); 366 367 /* Turn on the scaler, which will wait for vstart to start 368 * compositing. 369 * When feeding the transposer, we should operate in oneshot 370 * mode. 371 */ 372 dispctrl = SCALER_DISPCTRLX_ENABLE; 373 374 if (!vc4->is_vc5) 375 dispctrl |= VC4_SET_FIELD(mode->hdisplay, 376 SCALER_DISPCTRLX_WIDTH) | 377 VC4_SET_FIELD(mode->vdisplay, 378 SCALER_DISPCTRLX_HEIGHT) | 379 (oneshot ? SCALER_DISPCTRLX_ONESHOT : 0); 380 else 381 dispctrl |= VC4_SET_FIELD(mode->hdisplay, 382 SCALER5_DISPCTRLX_WIDTH) | 383 VC4_SET_FIELD(mode->vdisplay, 384 SCALER5_DISPCTRLX_HEIGHT) | 385 (oneshot ? SCALER5_DISPCTRLX_ONESHOT : 0); 386 387 HVS_WRITE(SCALER_DISPCTRLX(chan), dispctrl); 388 389 dispbkgndx = HVS_READ(SCALER_DISPBKGNDX(chan)); 390 dispbkgndx &= ~SCALER_DISPBKGND_GAMMA; 391 dispbkgndx &= ~SCALER_DISPBKGND_INTERLACE; 392 393 HVS_WRITE(SCALER_DISPBKGNDX(chan), dispbkgndx | 394 SCALER_DISPBKGND_AUTOHS | 395 ((!vc4->is_vc5) ? SCALER_DISPBKGND_GAMMA : 0) | 396 (interlace ? SCALER_DISPBKGND_INTERLACE : 0)); 397 398 /* Reload the LUT, since the SRAMs would have been disabled if 399 * all CRTCs had SCALER_DISPBKGND_GAMMA unset at once. 400 */ 401 vc4_hvs_lut_load(hvs, vc4_crtc); 402 403 drm_dev_exit(idx); 404 405 return 0; 406 } 407 408 void vc4_hvs_stop_channel(struct vc4_hvs *hvs, unsigned int chan) 409 { 410 struct drm_device *drm = &hvs->vc4->base; 411 int idx; 412 413 if (!drm_dev_enter(drm, &idx)) 414 return; 415 416 if (HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_ENABLE) 417 goto out; 418 419 HVS_WRITE(SCALER_DISPCTRLX(chan), 420 HVS_READ(SCALER_DISPCTRLX(chan)) | SCALER_DISPCTRLX_RESET); 421 HVS_WRITE(SCALER_DISPCTRLX(chan), 422 HVS_READ(SCALER_DISPCTRLX(chan)) & ~SCALER_DISPCTRLX_ENABLE); 423 424 /* Once we leave, the scaler should be disabled and its fifo empty. */ 425 WARN_ON_ONCE(HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_RESET); 426 427 WARN_ON_ONCE(VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(chan)), 428 SCALER_DISPSTATX_MODE) != 429 SCALER_DISPSTATX_MODE_DISABLED); 430 431 WARN_ON_ONCE((HVS_READ(SCALER_DISPSTATX(chan)) & 432 (SCALER_DISPSTATX_FULL | SCALER_DISPSTATX_EMPTY)) != 433 SCALER_DISPSTATX_EMPTY); 434 435 out: 436 drm_dev_exit(idx); 437 } 438 439 int vc4_hvs_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *state) 440 { 441 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 442 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state); 443 struct drm_device *dev = crtc->dev; 444 struct vc4_dev *vc4 = to_vc4_dev(dev); 445 struct drm_plane *plane; 446 unsigned long flags; 447 const struct drm_plane_state *plane_state; 448 u32 dlist_count = 0; 449 int ret; 450 451 /* The pixelvalve can only feed one encoder (and encoders are 452 * 1:1 with connectors.) 453 */ 454 if (hweight32(crtc_state->connector_mask) > 1) 455 return -EINVAL; 456 457 drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) 458 dlist_count += vc4_plane_dlist_size(plane_state); 459 460 dlist_count++; /* Account for SCALER_CTL0_END. */ 461 462 spin_lock_irqsave(&vc4->hvs->mm_lock, flags); 463 ret = drm_mm_insert_node(&vc4->hvs->dlist_mm, &vc4_state->mm, 464 dlist_count); 465 spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags); 466 if (ret) 467 return ret; 468 469 return 0; 470 } 471 472 static void vc4_hvs_install_dlist(struct drm_crtc *crtc) 473 { 474 struct drm_device *dev = crtc->dev; 475 struct vc4_dev *vc4 = to_vc4_dev(dev); 476 struct vc4_hvs *hvs = vc4->hvs; 477 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state); 478 int idx; 479 480 if (!drm_dev_enter(dev, &idx)) 481 return; 482 483 HVS_WRITE(SCALER_DISPLISTX(vc4_state->assigned_channel), 484 vc4_state->mm.start); 485 486 drm_dev_exit(idx); 487 } 488 489 static void vc4_hvs_update_dlist(struct drm_crtc *crtc) 490 { 491 struct drm_device *dev = crtc->dev; 492 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 493 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state); 494 unsigned long flags; 495 496 if (crtc->state->event) { 497 crtc->state->event->pipe = drm_crtc_index(crtc); 498 499 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 500 501 spin_lock_irqsave(&dev->event_lock, flags); 502 503 if (!vc4_crtc->feeds_txp || vc4_state->txp_armed) { 504 vc4_crtc->event = crtc->state->event; 505 crtc->state->event = NULL; 506 } 507 508 spin_unlock_irqrestore(&dev->event_lock, flags); 509 } 510 511 spin_lock_irqsave(&vc4_crtc->irq_lock, flags); 512 vc4_crtc->current_dlist = vc4_state->mm.start; 513 spin_unlock_irqrestore(&vc4_crtc->irq_lock, flags); 514 } 515 516 void vc4_hvs_atomic_begin(struct drm_crtc *crtc, 517 struct drm_atomic_state *state) 518 { 519 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 520 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state); 521 unsigned long flags; 522 523 spin_lock_irqsave(&vc4_crtc->irq_lock, flags); 524 vc4_crtc->current_hvs_channel = vc4_state->assigned_channel; 525 spin_unlock_irqrestore(&vc4_crtc->irq_lock, flags); 526 } 527 528 void vc4_hvs_atomic_enable(struct drm_crtc *crtc, 529 struct drm_atomic_state *state) 530 { 531 struct drm_device *dev = crtc->dev; 532 struct vc4_dev *vc4 = to_vc4_dev(dev); 533 struct drm_display_mode *mode = &crtc->state->adjusted_mode; 534 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 535 bool oneshot = vc4_crtc->feeds_txp; 536 537 vc4_hvs_install_dlist(crtc); 538 vc4_hvs_update_dlist(crtc); 539 vc4_hvs_init_channel(vc4->hvs, crtc, mode, oneshot); 540 } 541 542 void vc4_hvs_atomic_disable(struct drm_crtc *crtc, 543 struct drm_atomic_state *state) 544 { 545 struct drm_device *dev = crtc->dev; 546 struct vc4_dev *vc4 = to_vc4_dev(dev); 547 struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state, crtc); 548 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(old_state); 549 unsigned int chan = vc4_state->assigned_channel; 550 551 vc4_hvs_stop_channel(vc4->hvs, chan); 552 } 553 554 void vc4_hvs_atomic_flush(struct drm_crtc *crtc, 555 struct drm_atomic_state *state) 556 { 557 struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state, 558 crtc); 559 struct drm_device *dev = crtc->dev; 560 struct vc4_dev *vc4 = to_vc4_dev(dev); 561 struct vc4_hvs *hvs = vc4->hvs; 562 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 563 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state); 564 unsigned int channel = vc4_state->assigned_channel; 565 struct drm_plane *plane; 566 struct vc4_plane_state *vc4_plane_state; 567 bool debug_dump_regs = false; 568 bool enable_bg_fill = false; 569 u32 __iomem *dlist_start = vc4->hvs->dlist + vc4_state->mm.start; 570 u32 __iomem *dlist_next = dlist_start; 571 int idx; 572 573 if (!drm_dev_enter(dev, &idx)) { 574 vc4_crtc_send_vblank(crtc); 575 return; 576 } 577 578 if (debug_dump_regs) { 579 DRM_INFO("CRTC %d HVS before:\n", drm_crtc_index(crtc)); 580 vc4_hvs_dump_state(hvs); 581 } 582 583 /* Copy all the active planes' dlist contents to the hardware dlist. */ 584 drm_atomic_crtc_for_each_plane(plane, crtc) { 585 /* Is this the first active plane? */ 586 if (dlist_next == dlist_start) { 587 /* We need to enable background fill when a plane 588 * could be alpha blending from the background, i.e. 589 * where no other plane is underneath. It suffices to 590 * consider the first active plane here since we set 591 * needs_bg_fill such that either the first plane 592 * already needs it or all planes on top blend from 593 * the first or a lower plane. 594 */ 595 vc4_plane_state = to_vc4_plane_state(plane->state); 596 enable_bg_fill = vc4_plane_state->needs_bg_fill; 597 } 598 599 dlist_next += vc4_plane_write_dlist(plane, dlist_next); 600 } 601 602 writel(SCALER_CTL0_END, dlist_next); 603 dlist_next++; 604 605 WARN_ON_ONCE(dlist_next - dlist_start != vc4_state->mm.size); 606 607 if (enable_bg_fill) 608 /* This sets a black background color fill, as is the case 609 * with other DRM drivers. 610 */ 611 HVS_WRITE(SCALER_DISPBKGNDX(channel), 612 HVS_READ(SCALER_DISPBKGNDX(channel)) | 613 SCALER_DISPBKGND_FILL); 614 615 /* Only update DISPLIST if the CRTC was already running and is not 616 * being disabled. 617 * vc4_crtc_enable() takes care of updating the dlist just after 618 * re-enabling VBLANK interrupts and before enabling the engine. 619 * If the CRTC is being disabled, there's no point in updating this 620 * information. 621 */ 622 if (crtc->state->active && old_state->active) { 623 vc4_hvs_install_dlist(crtc); 624 vc4_hvs_update_dlist(crtc); 625 } 626 627 if (crtc->state->color_mgmt_changed) { 628 u32 dispbkgndx = HVS_READ(SCALER_DISPBKGNDX(channel)); 629 630 if (crtc->state->gamma_lut) { 631 vc4_hvs_update_gamma_lut(hvs, vc4_crtc); 632 dispbkgndx |= SCALER_DISPBKGND_GAMMA; 633 } else { 634 /* Unsetting DISPBKGND_GAMMA skips the gamma lut step 635 * in hardware, which is the same as a linear lut that 636 * DRM expects us to use in absence of a user lut. 637 */ 638 dispbkgndx &= ~SCALER_DISPBKGND_GAMMA; 639 } 640 HVS_WRITE(SCALER_DISPBKGNDX(channel), dispbkgndx); 641 } 642 643 if (debug_dump_regs) { 644 DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc)); 645 vc4_hvs_dump_state(hvs); 646 } 647 648 drm_dev_exit(idx); 649 } 650 651 void vc4_hvs_mask_underrun(struct vc4_hvs *hvs, int channel) 652 { 653 struct drm_device *drm = &hvs->vc4->base; 654 u32 dispctrl; 655 int idx; 656 657 if (!drm_dev_enter(drm, &idx)) 658 return; 659 660 dispctrl = HVS_READ(SCALER_DISPCTRL); 661 dispctrl &= ~SCALER_DISPCTRL_DSPEISLUR(channel); 662 663 HVS_WRITE(SCALER_DISPCTRL, dispctrl); 664 665 drm_dev_exit(idx); 666 } 667 668 void vc4_hvs_unmask_underrun(struct vc4_hvs *hvs, int channel) 669 { 670 struct drm_device *drm = &hvs->vc4->base; 671 u32 dispctrl; 672 int idx; 673 674 if (!drm_dev_enter(drm, &idx)) 675 return; 676 677 dispctrl = HVS_READ(SCALER_DISPCTRL); 678 dispctrl |= SCALER_DISPCTRL_DSPEISLUR(channel); 679 680 HVS_WRITE(SCALER_DISPSTAT, 681 SCALER_DISPSTAT_EUFLOW(channel)); 682 HVS_WRITE(SCALER_DISPCTRL, dispctrl); 683 684 drm_dev_exit(idx); 685 } 686 687 static void vc4_hvs_report_underrun(struct drm_device *dev) 688 { 689 struct vc4_dev *vc4 = to_vc4_dev(dev); 690 691 atomic_inc(&vc4->underrun); 692 DRM_DEV_ERROR(dev->dev, "HVS underrun\n"); 693 } 694 695 static irqreturn_t vc4_hvs_irq_handler(int irq, void *data) 696 { 697 struct drm_device *dev = data; 698 struct vc4_dev *vc4 = to_vc4_dev(dev); 699 struct vc4_hvs *hvs = vc4->hvs; 700 irqreturn_t irqret = IRQ_NONE; 701 int channel; 702 u32 control; 703 u32 status; 704 705 /* 706 * NOTE: We don't need to protect the register access using 707 * drm_dev_enter() there because the interrupt handler lifetime 708 * is tied to the device itself, and not to the DRM device. 709 * 710 * So when the device will be gone, one of the first thing we 711 * will be doing will be to unregister the interrupt handler, 712 * and then unregister the DRM device. drm_dev_enter() would 713 * thus always succeed if we are here. 714 */ 715 716 status = HVS_READ(SCALER_DISPSTAT); 717 control = HVS_READ(SCALER_DISPCTRL); 718 719 for (channel = 0; channel < SCALER_CHANNELS_COUNT; channel++) { 720 /* Interrupt masking is not always honored, so check it here. */ 721 if (status & SCALER_DISPSTAT_EUFLOW(channel) && 722 control & SCALER_DISPCTRL_DSPEISLUR(channel)) { 723 vc4_hvs_mask_underrun(hvs, channel); 724 vc4_hvs_report_underrun(dev); 725 726 irqret = IRQ_HANDLED; 727 } 728 } 729 730 /* Clear every per-channel interrupt flag. */ 731 HVS_WRITE(SCALER_DISPSTAT, SCALER_DISPSTAT_IRQMASK(0) | 732 SCALER_DISPSTAT_IRQMASK(1) | 733 SCALER_DISPSTAT_IRQMASK(2)); 734 735 return irqret; 736 } 737 738 int vc4_hvs_debugfs_init(struct drm_minor *minor) 739 { 740 struct drm_device *drm = minor->dev; 741 struct vc4_dev *vc4 = to_vc4_dev(drm); 742 struct vc4_hvs *hvs = vc4->hvs; 743 int ret; 744 745 if (!vc4->hvs) 746 return -ENODEV; 747 748 if (!vc4->is_vc5) 749 debugfs_create_bool("hvs_load_tracker", S_IRUGO | S_IWUSR, 750 minor->debugfs_root, 751 &vc4->load_tracker_enabled); 752 753 ret = vc4_debugfs_add_file(minor, "hvs_dlists", 754 vc4_hvs_debugfs_dlist, NULL); 755 if (ret) 756 return ret; 757 758 ret = vc4_debugfs_add_file(minor, "hvs_underrun", 759 vc4_hvs_debugfs_underrun, NULL); 760 if (ret) 761 return ret; 762 763 ret = vc4_debugfs_add_regset32(minor, "hvs_regs", 764 &hvs->regset); 765 if (ret) 766 return ret; 767 768 return 0; 769 } 770 771 static int vc4_hvs_bind(struct device *dev, struct device *master, void *data) 772 { 773 struct platform_device *pdev = to_platform_device(dev); 774 struct drm_device *drm = dev_get_drvdata(master); 775 struct vc4_dev *vc4 = to_vc4_dev(drm); 776 struct vc4_hvs *hvs = NULL; 777 int ret; 778 u32 dispctrl; 779 u32 reg; 780 781 hvs = drmm_kzalloc(drm, sizeof(*hvs), GFP_KERNEL); 782 if (!hvs) 783 return -ENOMEM; 784 hvs->vc4 = vc4; 785 hvs->pdev = pdev; 786 787 hvs->regs = vc4_ioremap_regs(pdev, 0); 788 if (IS_ERR(hvs->regs)) 789 return PTR_ERR(hvs->regs); 790 791 hvs->regset.base = hvs->regs; 792 hvs->regset.regs = hvs_regs; 793 hvs->regset.nregs = ARRAY_SIZE(hvs_regs); 794 795 if (vc4->is_vc5) { 796 struct rpi_firmware *firmware; 797 struct device_node *node; 798 unsigned int max_rate; 799 800 node = rpi_firmware_find_node(); 801 if (!node) 802 return -EINVAL; 803 804 firmware = rpi_firmware_get(node); 805 of_node_put(node); 806 if (!firmware) 807 return -EPROBE_DEFER; 808 809 hvs->core_clk = devm_clk_get(&pdev->dev, NULL); 810 if (IS_ERR(hvs->core_clk)) { 811 dev_err(&pdev->dev, "Couldn't get core clock\n"); 812 return PTR_ERR(hvs->core_clk); 813 } 814 815 max_rate = rpi_firmware_clk_get_max_rate(firmware, 816 RPI_FIRMWARE_CORE_CLK_ID); 817 rpi_firmware_put(firmware); 818 if (max_rate >= 550000000) 819 hvs->vc5_hdmi_enable_hdmi_20 = true; 820 821 if (max_rate >= 600000000) 822 hvs->vc5_hdmi_enable_4096by2160 = true; 823 824 hvs->max_core_rate = max_rate; 825 826 ret = clk_prepare_enable(hvs->core_clk); 827 if (ret) { 828 dev_err(&pdev->dev, "Couldn't enable the core clock\n"); 829 return ret; 830 } 831 } 832 833 if (!vc4->is_vc5) 834 hvs->dlist = hvs->regs + SCALER_DLIST_START; 835 else 836 hvs->dlist = hvs->regs + SCALER5_DLIST_START; 837 838 spin_lock_init(&hvs->mm_lock); 839 840 /* Set up the HVS display list memory manager. We never 841 * overwrite the setup from the bootloader (just 128b out of 842 * our 16K), since we don't want to scramble the screen when 843 * transitioning from the firmware's boot setup to runtime. 844 */ 845 drm_mm_init(&hvs->dlist_mm, 846 HVS_BOOTLOADER_DLIST_END, 847 (SCALER_DLIST_SIZE >> 2) - HVS_BOOTLOADER_DLIST_END); 848 849 /* Set up the HVS LBM memory manager. We could have some more 850 * complicated data structure that allowed reuse of LBM areas 851 * between planes when they don't overlap on the screen, but 852 * for now we just allocate globally. 853 */ 854 if (!vc4->is_vc5) 855 /* 48k words of 2x12-bit pixels */ 856 drm_mm_init(&hvs->lbm_mm, 0, 48 * 1024); 857 else 858 /* 60k words of 4x12-bit pixels */ 859 drm_mm_init(&hvs->lbm_mm, 0, 60 * 1024); 860 861 /* Upload filter kernels. We only have the one for now, so we 862 * keep it around for the lifetime of the driver. 863 */ 864 ret = vc4_hvs_upload_linear_kernel(hvs, 865 &hvs->mitchell_netravali_filter, 866 mitchell_netravali_1_3_1_3_kernel); 867 if (ret) 868 return ret; 869 870 vc4->hvs = hvs; 871 872 reg = HVS_READ(SCALER_DISPECTRL); 873 reg &= ~SCALER_DISPECTRL_DSP2_MUX_MASK; 874 HVS_WRITE(SCALER_DISPECTRL, 875 reg | VC4_SET_FIELD(0, SCALER_DISPECTRL_DSP2_MUX)); 876 877 reg = HVS_READ(SCALER_DISPCTRL); 878 reg &= ~SCALER_DISPCTRL_DSP3_MUX_MASK; 879 HVS_WRITE(SCALER_DISPCTRL, 880 reg | VC4_SET_FIELD(3, SCALER_DISPCTRL_DSP3_MUX)); 881 882 reg = HVS_READ(SCALER_DISPEOLN); 883 reg &= ~SCALER_DISPEOLN_DSP4_MUX_MASK; 884 HVS_WRITE(SCALER_DISPEOLN, 885 reg | VC4_SET_FIELD(3, SCALER_DISPEOLN_DSP4_MUX)); 886 887 reg = HVS_READ(SCALER_DISPDITHER); 888 reg &= ~SCALER_DISPDITHER_DSP5_MUX_MASK; 889 HVS_WRITE(SCALER_DISPDITHER, 890 reg | VC4_SET_FIELD(3, SCALER_DISPDITHER_DSP5_MUX)); 891 892 dispctrl = HVS_READ(SCALER_DISPCTRL); 893 894 dispctrl |= SCALER_DISPCTRL_ENABLE; 895 dispctrl |= SCALER_DISPCTRL_DISPEIRQ(0) | 896 SCALER_DISPCTRL_DISPEIRQ(1) | 897 SCALER_DISPCTRL_DISPEIRQ(2); 898 899 dispctrl &= ~(SCALER_DISPCTRL_DMAEIRQ | 900 SCALER_DISPCTRL_SLVWREIRQ | 901 SCALER_DISPCTRL_SLVRDEIRQ | 902 SCALER_DISPCTRL_DSPEIEOF(0) | 903 SCALER_DISPCTRL_DSPEIEOF(1) | 904 SCALER_DISPCTRL_DSPEIEOF(2) | 905 SCALER_DISPCTRL_DSPEIEOLN(0) | 906 SCALER_DISPCTRL_DSPEIEOLN(1) | 907 SCALER_DISPCTRL_DSPEIEOLN(2) | 908 SCALER_DISPCTRL_DSPEISLUR(0) | 909 SCALER_DISPCTRL_DSPEISLUR(1) | 910 SCALER_DISPCTRL_DSPEISLUR(2) | 911 SCALER_DISPCTRL_SCLEIRQ); 912 913 HVS_WRITE(SCALER_DISPCTRL, dispctrl); 914 915 ret = devm_request_irq(dev, platform_get_irq(pdev, 0), 916 vc4_hvs_irq_handler, 0, "vc4 hvs", drm); 917 if (ret) 918 return ret; 919 920 return 0; 921 } 922 923 static void vc4_hvs_unbind(struct device *dev, struct device *master, 924 void *data) 925 { 926 struct drm_device *drm = dev_get_drvdata(master); 927 struct vc4_dev *vc4 = to_vc4_dev(drm); 928 struct vc4_hvs *hvs = vc4->hvs; 929 struct drm_mm_node *node, *next; 930 931 if (drm_mm_node_allocated(&vc4->hvs->mitchell_netravali_filter)) 932 drm_mm_remove_node(&vc4->hvs->mitchell_netravali_filter); 933 934 drm_mm_for_each_node_safe(node, next, &vc4->hvs->dlist_mm) 935 drm_mm_remove_node(node); 936 937 drm_mm_takedown(&vc4->hvs->dlist_mm); 938 939 drm_mm_for_each_node_safe(node, next, &vc4->hvs->lbm_mm) 940 drm_mm_remove_node(node); 941 drm_mm_takedown(&vc4->hvs->lbm_mm); 942 943 clk_disable_unprepare(hvs->core_clk); 944 945 vc4->hvs = NULL; 946 } 947 948 static const struct component_ops vc4_hvs_ops = { 949 .bind = vc4_hvs_bind, 950 .unbind = vc4_hvs_unbind, 951 }; 952 953 static int vc4_hvs_dev_probe(struct platform_device *pdev) 954 { 955 return component_add(&pdev->dev, &vc4_hvs_ops); 956 } 957 958 static int vc4_hvs_dev_remove(struct platform_device *pdev) 959 { 960 component_del(&pdev->dev, &vc4_hvs_ops); 961 return 0; 962 } 963 964 static const struct of_device_id vc4_hvs_dt_match[] = { 965 { .compatible = "brcm,bcm2711-hvs" }, 966 { .compatible = "brcm,bcm2835-hvs" }, 967 {} 968 }; 969 970 struct platform_driver vc4_hvs_driver = { 971 .probe = vc4_hvs_dev_probe, 972 .remove = vc4_hvs_dev_remove, 973 .driver = { 974 .name = "vc4_hvs", 975 .of_match_table = vc4_hvs_dt_match, 976 }, 977 }; 978