1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 Broadcom 4 */ 5 6 /** 7 * DOC: VC4 HVS module. 8 * 9 * The Hardware Video Scaler (HVS) is the piece of hardware that does 10 * translation, scaling, colorspace conversion, and compositing of 11 * pixels stored in framebuffers into a FIFO of pixels going out to 12 * the Pixel Valve (CRTC). It operates at the system clock rate (the 13 * system audio clock gate, specifically), which is much higher than 14 * the pixel clock rate. 15 * 16 * There is a single global HVS, with multiple output FIFOs that can 17 * be consumed by the PVs. This file just manages the resources for 18 * the HVS, while the vc4_crtc.c code actually drives HVS setup for 19 * each CRTC. 20 */ 21 22 #include <linux/bitfield.h> 23 #include <linux/clk.h> 24 #include <linux/component.h> 25 #include <linux/platform_device.h> 26 27 #include <drm/drm_atomic_helper.h> 28 #include <drm/drm_vblank.h> 29 30 #include "vc4_drv.h" 31 #include "vc4_regs.h" 32 33 static const struct debugfs_reg32 hvs_regs[] = { 34 VC4_REG32(SCALER_DISPCTRL), 35 VC4_REG32(SCALER_DISPSTAT), 36 VC4_REG32(SCALER_DISPID), 37 VC4_REG32(SCALER_DISPECTRL), 38 VC4_REG32(SCALER_DISPPROF), 39 VC4_REG32(SCALER_DISPDITHER), 40 VC4_REG32(SCALER_DISPEOLN), 41 VC4_REG32(SCALER_DISPLIST0), 42 VC4_REG32(SCALER_DISPLIST1), 43 VC4_REG32(SCALER_DISPLIST2), 44 VC4_REG32(SCALER_DISPLSTAT), 45 VC4_REG32(SCALER_DISPLACT0), 46 VC4_REG32(SCALER_DISPLACT1), 47 VC4_REG32(SCALER_DISPLACT2), 48 VC4_REG32(SCALER_DISPCTRL0), 49 VC4_REG32(SCALER_DISPBKGND0), 50 VC4_REG32(SCALER_DISPSTAT0), 51 VC4_REG32(SCALER_DISPBASE0), 52 VC4_REG32(SCALER_DISPCTRL1), 53 VC4_REG32(SCALER_DISPBKGND1), 54 VC4_REG32(SCALER_DISPSTAT1), 55 VC4_REG32(SCALER_DISPBASE1), 56 VC4_REG32(SCALER_DISPCTRL2), 57 VC4_REG32(SCALER_DISPBKGND2), 58 VC4_REG32(SCALER_DISPSTAT2), 59 VC4_REG32(SCALER_DISPBASE2), 60 VC4_REG32(SCALER_DISPALPHA2), 61 VC4_REG32(SCALER_OLEDOFFS), 62 VC4_REG32(SCALER_OLEDCOEF0), 63 VC4_REG32(SCALER_OLEDCOEF1), 64 VC4_REG32(SCALER_OLEDCOEF2), 65 }; 66 67 void vc4_hvs_dump_state(struct vc4_hvs *hvs) 68 { 69 struct drm_printer p = drm_info_printer(&hvs->pdev->dev); 70 int i; 71 72 drm_print_regset32(&p, &hvs->regset); 73 74 DRM_INFO("HVS ctx:\n"); 75 for (i = 0; i < 64; i += 4) { 76 DRM_INFO("0x%08x (%s): 0x%08x 0x%08x 0x%08x 0x%08x\n", 77 i * 4, i < HVS_BOOTLOADER_DLIST_END ? "B" : "D", 78 readl((u32 __iomem *)hvs->dlist + i + 0), 79 readl((u32 __iomem *)hvs->dlist + i + 1), 80 readl((u32 __iomem *)hvs->dlist + i + 2), 81 readl((u32 __iomem *)hvs->dlist + i + 3)); 82 } 83 } 84 85 static int vc4_hvs_debugfs_underrun(struct seq_file *m, void *data) 86 { 87 struct drm_info_node *node = m->private; 88 struct drm_device *dev = node->minor->dev; 89 struct vc4_dev *vc4 = to_vc4_dev(dev); 90 struct drm_printer p = drm_seq_file_printer(m); 91 92 drm_printf(&p, "%d\n", atomic_read(&vc4->underrun)); 93 94 return 0; 95 } 96 97 static int vc4_hvs_debugfs_dlist(struct seq_file *m, void *data) 98 { 99 struct drm_info_node *node = m->private; 100 struct drm_device *dev = node->minor->dev; 101 struct vc4_dev *vc4 = to_vc4_dev(dev); 102 struct vc4_hvs *hvs = vc4->hvs; 103 struct drm_printer p = drm_seq_file_printer(m); 104 unsigned int next_entry_start = 0; 105 unsigned int i, j; 106 u32 dlist_word, dispstat; 107 108 for (i = 0; i < SCALER_CHANNELS_COUNT; i++) { 109 dispstat = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(i)), 110 SCALER_DISPSTATX_MODE); 111 if (dispstat == SCALER_DISPSTATX_MODE_DISABLED || 112 dispstat == SCALER_DISPSTATX_MODE_EOF) { 113 drm_printf(&p, "HVS chan %u disabled\n", i); 114 continue; 115 } 116 117 drm_printf(&p, "HVS chan %u:\n", i); 118 119 for (j = HVS_READ(SCALER_DISPLISTX(i)); j < 256; j++) { 120 dlist_word = readl((u32 __iomem *)vc4->hvs->dlist + j); 121 drm_printf(&p, "dlist: %02d: 0x%08x\n", j, 122 dlist_word); 123 if (!next_entry_start || 124 next_entry_start == j) { 125 if (dlist_word & SCALER_CTL0_END) 126 break; 127 next_entry_start = j + 128 VC4_GET_FIELD(dlist_word, 129 SCALER_CTL0_SIZE); 130 } 131 } 132 } 133 134 return 0; 135 } 136 137 /* The filter kernel is composed of dwords each containing 3 9-bit 138 * signed integers packed next to each other. 139 */ 140 #define VC4_INT_TO_COEFF(coeff) (coeff & 0x1ff) 141 #define VC4_PPF_FILTER_WORD(c0, c1, c2) \ 142 ((((c0) & 0x1ff) << 0) | \ 143 (((c1) & 0x1ff) << 9) | \ 144 (((c2) & 0x1ff) << 18)) 145 146 /* The whole filter kernel is arranged as the coefficients 0-16 going 147 * up, then a pad, then 17-31 going down and reversed within the 148 * dwords. This means that a linear phase kernel (where it's 149 * symmetrical at the boundary between 15 and 16) has the last 5 150 * dwords matching the first 5, but reversed. 151 */ 152 #define VC4_LINEAR_PHASE_KERNEL(c0, c1, c2, c3, c4, c5, c6, c7, c8, \ 153 c9, c10, c11, c12, c13, c14, c15) \ 154 {VC4_PPF_FILTER_WORD(c0, c1, c2), \ 155 VC4_PPF_FILTER_WORD(c3, c4, c5), \ 156 VC4_PPF_FILTER_WORD(c6, c7, c8), \ 157 VC4_PPF_FILTER_WORD(c9, c10, c11), \ 158 VC4_PPF_FILTER_WORD(c12, c13, c14), \ 159 VC4_PPF_FILTER_WORD(c15, c15, 0)} 160 161 #define VC4_LINEAR_PHASE_KERNEL_DWORDS 6 162 #define VC4_KERNEL_DWORDS (VC4_LINEAR_PHASE_KERNEL_DWORDS * 2 - 1) 163 164 /* Recommended B=1/3, C=1/3 filter choice from Mitchell/Netravali. 165 * http://www.cs.utexas.edu/~fussell/courses/cs384g/lectures/mitchell/Mitchell.pdf 166 */ 167 static const u32 mitchell_netravali_1_3_1_3_kernel[] = 168 VC4_LINEAR_PHASE_KERNEL(0, -2, -6, -8, -10, -8, -3, 2, 18, 169 50, 82, 119, 155, 187, 213, 227); 170 171 static int vc4_hvs_upload_linear_kernel(struct vc4_hvs *hvs, 172 struct drm_mm_node *space, 173 const u32 *kernel) 174 { 175 int ret, i; 176 u32 __iomem *dst_kernel; 177 178 ret = drm_mm_insert_node(&hvs->dlist_mm, space, VC4_KERNEL_DWORDS); 179 if (ret) { 180 DRM_ERROR("Failed to allocate space for filter kernel: %d\n", 181 ret); 182 return ret; 183 } 184 185 dst_kernel = hvs->dlist + space->start; 186 187 for (i = 0; i < VC4_KERNEL_DWORDS; i++) { 188 if (i < VC4_LINEAR_PHASE_KERNEL_DWORDS) 189 writel(kernel[i], &dst_kernel[i]); 190 else { 191 writel(kernel[VC4_KERNEL_DWORDS - i - 1], 192 &dst_kernel[i]); 193 } 194 } 195 196 return 0; 197 } 198 199 static void vc4_hvs_lut_load(struct vc4_hvs *hvs, 200 struct vc4_crtc *vc4_crtc) 201 { 202 struct drm_crtc *crtc = &vc4_crtc->base; 203 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state); 204 u32 i; 205 206 /* The LUT memory is laid out with each HVS channel in order, 207 * each of which takes 256 writes for R, 256 for G, then 256 208 * for B. 209 */ 210 HVS_WRITE(SCALER_GAMADDR, 211 SCALER_GAMADDR_AUTOINC | 212 (vc4_state->assigned_channel * 3 * crtc->gamma_size)); 213 214 for (i = 0; i < crtc->gamma_size; i++) 215 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_r[i]); 216 for (i = 0; i < crtc->gamma_size; i++) 217 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_g[i]); 218 for (i = 0; i < crtc->gamma_size; i++) 219 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_b[i]); 220 } 221 222 static void vc4_hvs_update_gamma_lut(struct vc4_hvs *hvs, 223 struct vc4_crtc *vc4_crtc) 224 { 225 struct drm_crtc_state *crtc_state = vc4_crtc->base.state; 226 struct drm_color_lut *lut = crtc_state->gamma_lut->data; 227 u32 length = drm_color_lut_size(crtc_state->gamma_lut); 228 u32 i; 229 230 for (i = 0; i < length; i++) { 231 vc4_crtc->lut_r[i] = drm_color_lut_extract(lut[i].red, 8); 232 vc4_crtc->lut_g[i] = drm_color_lut_extract(lut[i].green, 8); 233 vc4_crtc->lut_b[i] = drm_color_lut_extract(lut[i].blue, 8); 234 } 235 236 vc4_hvs_lut_load(hvs, vc4_crtc); 237 } 238 239 u8 vc4_hvs_get_fifo_frame_count(struct vc4_hvs *hvs, unsigned int fifo) 240 { 241 u8 field = 0; 242 243 switch (fifo) { 244 case 0: 245 field = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTAT1), 246 SCALER_DISPSTAT1_FRCNT0); 247 break; 248 case 1: 249 field = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTAT1), 250 SCALER_DISPSTAT1_FRCNT1); 251 break; 252 case 2: 253 field = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTAT2), 254 SCALER_DISPSTAT2_FRCNT2); 255 break; 256 } 257 258 return field; 259 } 260 261 int vc4_hvs_get_fifo_from_output(struct vc4_hvs *hvs, unsigned int output) 262 { 263 struct vc4_dev *vc4 = hvs->vc4; 264 u32 reg; 265 int ret; 266 267 if (!vc4->is_vc5) 268 return output; 269 270 switch (output) { 271 case 0: 272 return 0; 273 274 case 1: 275 return 1; 276 277 case 2: 278 reg = HVS_READ(SCALER_DISPECTRL); 279 ret = FIELD_GET(SCALER_DISPECTRL_DSP2_MUX_MASK, reg); 280 if (ret == 0) 281 return 2; 282 283 return 0; 284 285 case 3: 286 reg = HVS_READ(SCALER_DISPCTRL); 287 ret = FIELD_GET(SCALER_DISPCTRL_DSP3_MUX_MASK, reg); 288 if (ret == 3) 289 return -EPIPE; 290 291 return ret; 292 293 case 4: 294 reg = HVS_READ(SCALER_DISPEOLN); 295 ret = FIELD_GET(SCALER_DISPEOLN_DSP4_MUX_MASK, reg); 296 if (ret == 3) 297 return -EPIPE; 298 299 return ret; 300 301 case 5: 302 reg = HVS_READ(SCALER_DISPDITHER); 303 ret = FIELD_GET(SCALER_DISPDITHER_DSP5_MUX_MASK, reg); 304 if (ret == 3) 305 return -EPIPE; 306 307 return ret; 308 309 default: 310 return -EPIPE; 311 } 312 } 313 314 static int vc4_hvs_init_channel(struct vc4_hvs *hvs, struct drm_crtc *crtc, 315 struct drm_display_mode *mode, bool oneshot) 316 { 317 struct vc4_dev *vc4 = hvs->vc4; 318 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 319 struct vc4_crtc_state *vc4_crtc_state = to_vc4_crtc_state(crtc->state); 320 unsigned int chan = vc4_crtc_state->assigned_channel; 321 bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE; 322 u32 dispbkgndx; 323 u32 dispctrl; 324 325 HVS_WRITE(SCALER_DISPCTRLX(chan), 0); 326 HVS_WRITE(SCALER_DISPCTRLX(chan), SCALER_DISPCTRLX_RESET); 327 HVS_WRITE(SCALER_DISPCTRLX(chan), 0); 328 329 /* Turn on the scaler, which will wait for vstart to start 330 * compositing. 331 * When feeding the transposer, we should operate in oneshot 332 * mode. 333 */ 334 dispctrl = SCALER_DISPCTRLX_ENABLE; 335 336 if (!vc4->is_vc5) 337 dispctrl |= VC4_SET_FIELD(mode->hdisplay, 338 SCALER_DISPCTRLX_WIDTH) | 339 VC4_SET_FIELD(mode->vdisplay, 340 SCALER_DISPCTRLX_HEIGHT) | 341 (oneshot ? SCALER_DISPCTRLX_ONESHOT : 0); 342 else 343 dispctrl |= VC4_SET_FIELD(mode->hdisplay, 344 SCALER5_DISPCTRLX_WIDTH) | 345 VC4_SET_FIELD(mode->vdisplay, 346 SCALER5_DISPCTRLX_HEIGHT) | 347 (oneshot ? SCALER5_DISPCTRLX_ONESHOT : 0); 348 349 HVS_WRITE(SCALER_DISPCTRLX(chan), dispctrl); 350 351 dispbkgndx = HVS_READ(SCALER_DISPBKGNDX(chan)); 352 dispbkgndx &= ~SCALER_DISPBKGND_GAMMA; 353 dispbkgndx &= ~SCALER_DISPBKGND_INTERLACE; 354 355 HVS_WRITE(SCALER_DISPBKGNDX(chan), dispbkgndx | 356 SCALER_DISPBKGND_AUTOHS | 357 ((!vc4->is_vc5) ? SCALER_DISPBKGND_GAMMA : 0) | 358 (interlace ? SCALER_DISPBKGND_INTERLACE : 0)); 359 360 /* Reload the LUT, since the SRAMs would have been disabled if 361 * all CRTCs had SCALER_DISPBKGND_GAMMA unset at once. 362 */ 363 vc4_hvs_lut_load(hvs, vc4_crtc); 364 365 return 0; 366 } 367 368 void vc4_hvs_stop_channel(struct vc4_hvs *hvs, unsigned int chan) 369 { 370 if (HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_ENABLE) 371 return; 372 373 HVS_WRITE(SCALER_DISPCTRLX(chan), 374 HVS_READ(SCALER_DISPCTRLX(chan)) | SCALER_DISPCTRLX_RESET); 375 HVS_WRITE(SCALER_DISPCTRLX(chan), 376 HVS_READ(SCALER_DISPCTRLX(chan)) & ~SCALER_DISPCTRLX_ENABLE); 377 378 /* Once we leave, the scaler should be disabled and its fifo empty. */ 379 WARN_ON_ONCE(HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_RESET); 380 381 WARN_ON_ONCE(VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(chan)), 382 SCALER_DISPSTATX_MODE) != 383 SCALER_DISPSTATX_MODE_DISABLED); 384 385 WARN_ON_ONCE((HVS_READ(SCALER_DISPSTATX(chan)) & 386 (SCALER_DISPSTATX_FULL | SCALER_DISPSTATX_EMPTY)) != 387 SCALER_DISPSTATX_EMPTY); 388 } 389 390 int vc4_hvs_atomic_check(struct drm_crtc *crtc, struct drm_atomic_state *state) 391 { 392 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 393 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc_state); 394 struct drm_device *dev = crtc->dev; 395 struct vc4_dev *vc4 = to_vc4_dev(dev); 396 struct drm_plane *plane; 397 unsigned long flags; 398 const struct drm_plane_state *plane_state; 399 u32 dlist_count = 0; 400 int ret; 401 402 /* The pixelvalve can only feed one encoder (and encoders are 403 * 1:1 with connectors.) 404 */ 405 if (hweight32(crtc_state->connector_mask) > 1) 406 return -EINVAL; 407 408 drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) 409 dlist_count += vc4_plane_dlist_size(plane_state); 410 411 dlist_count++; /* Account for SCALER_CTL0_END. */ 412 413 spin_lock_irqsave(&vc4->hvs->mm_lock, flags); 414 ret = drm_mm_insert_node(&vc4->hvs->dlist_mm, &vc4_state->mm, 415 dlist_count); 416 spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags); 417 if (ret) 418 return ret; 419 420 return 0; 421 } 422 423 static void vc4_hvs_install_dlist(struct drm_crtc *crtc) 424 { 425 struct drm_device *dev = crtc->dev; 426 struct vc4_dev *vc4 = to_vc4_dev(dev); 427 struct vc4_hvs *hvs = vc4->hvs; 428 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state); 429 430 HVS_WRITE(SCALER_DISPLISTX(vc4_state->assigned_channel), 431 vc4_state->mm.start); 432 } 433 434 static void vc4_hvs_update_dlist(struct drm_crtc *crtc) 435 { 436 struct drm_device *dev = crtc->dev; 437 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 438 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state); 439 unsigned long flags; 440 441 if (crtc->state->event) { 442 crtc->state->event->pipe = drm_crtc_index(crtc); 443 444 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 445 446 spin_lock_irqsave(&dev->event_lock, flags); 447 448 if (!vc4_crtc->feeds_txp || vc4_state->txp_armed) { 449 vc4_crtc->event = crtc->state->event; 450 crtc->state->event = NULL; 451 } 452 453 spin_unlock_irqrestore(&dev->event_lock, flags); 454 } 455 456 spin_lock_irqsave(&vc4_crtc->irq_lock, flags); 457 vc4_crtc->current_dlist = vc4_state->mm.start; 458 spin_unlock_irqrestore(&vc4_crtc->irq_lock, flags); 459 } 460 461 void vc4_hvs_atomic_begin(struct drm_crtc *crtc, 462 struct drm_atomic_state *state) 463 { 464 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 465 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state); 466 unsigned long flags; 467 468 spin_lock_irqsave(&vc4_crtc->irq_lock, flags); 469 vc4_crtc->current_hvs_channel = vc4_state->assigned_channel; 470 spin_unlock_irqrestore(&vc4_crtc->irq_lock, flags); 471 } 472 473 void vc4_hvs_atomic_enable(struct drm_crtc *crtc, 474 struct drm_atomic_state *state) 475 { 476 struct drm_device *dev = crtc->dev; 477 struct vc4_dev *vc4 = to_vc4_dev(dev); 478 struct drm_display_mode *mode = &crtc->state->adjusted_mode; 479 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 480 bool oneshot = vc4_crtc->feeds_txp; 481 482 vc4_hvs_install_dlist(crtc); 483 vc4_hvs_update_dlist(crtc); 484 vc4_hvs_init_channel(vc4->hvs, crtc, mode, oneshot); 485 } 486 487 void vc4_hvs_atomic_disable(struct drm_crtc *crtc, 488 struct drm_atomic_state *state) 489 { 490 struct drm_device *dev = crtc->dev; 491 struct vc4_dev *vc4 = to_vc4_dev(dev); 492 struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state, crtc); 493 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(old_state); 494 unsigned int chan = vc4_state->assigned_channel; 495 496 vc4_hvs_stop_channel(vc4->hvs, chan); 497 } 498 499 void vc4_hvs_atomic_flush(struct drm_crtc *crtc, 500 struct drm_atomic_state *state) 501 { 502 struct drm_crtc_state *old_state = drm_atomic_get_old_crtc_state(state, 503 crtc); 504 struct drm_device *dev = crtc->dev; 505 struct vc4_dev *vc4 = to_vc4_dev(dev); 506 struct vc4_hvs *hvs = vc4->hvs; 507 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 508 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state); 509 unsigned int channel = vc4_state->assigned_channel; 510 struct drm_plane *plane; 511 struct vc4_plane_state *vc4_plane_state; 512 bool debug_dump_regs = false; 513 bool enable_bg_fill = false; 514 u32 __iomem *dlist_start = vc4->hvs->dlist + vc4_state->mm.start; 515 u32 __iomem *dlist_next = dlist_start; 516 517 if (debug_dump_regs) { 518 DRM_INFO("CRTC %d HVS before:\n", drm_crtc_index(crtc)); 519 vc4_hvs_dump_state(hvs); 520 } 521 522 /* Copy all the active planes' dlist contents to the hardware dlist. */ 523 drm_atomic_crtc_for_each_plane(plane, crtc) { 524 /* Is this the first active plane? */ 525 if (dlist_next == dlist_start) { 526 /* We need to enable background fill when a plane 527 * could be alpha blending from the background, i.e. 528 * where no other plane is underneath. It suffices to 529 * consider the first active plane here since we set 530 * needs_bg_fill such that either the first plane 531 * already needs it or all planes on top blend from 532 * the first or a lower plane. 533 */ 534 vc4_plane_state = to_vc4_plane_state(plane->state); 535 enable_bg_fill = vc4_plane_state->needs_bg_fill; 536 } 537 538 dlist_next += vc4_plane_write_dlist(plane, dlist_next); 539 } 540 541 writel(SCALER_CTL0_END, dlist_next); 542 dlist_next++; 543 544 WARN_ON_ONCE(dlist_next - dlist_start != vc4_state->mm.size); 545 546 if (enable_bg_fill) 547 /* This sets a black background color fill, as is the case 548 * with other DRM drivers. 549 */ 550 HVS_WRITE(SCALER_DISPBKGNDX(channel), 551 HVS_READ(SCALER_DISPBKGNDX(channel)) | 552 SCALER_DISPBKGND_FILL); 553 554 /* Only update DISPLIST if the CRTC was already running and is not 555 * being disabled. 556 * vc4_crtc_enable() takes care of updating the dlist just after 557 * re-enabling VBLANK interrupts and before enabling the engine. 558 * If the CRTC is being disabled, there's no point in updating this 559 * information. 560 */ 561 if (crtc->state->active && old_state->active) { 562 vc4_hvs_install_dlist(crtc); 563 vc4_hvs_update_dlist(crtc); 564 } 565 566 if (crtc->state->color_mgmt_changed) { 567 u32 dispbkgndx = HVS_READ(SCALER_DISPBKGNDX(channel)); 568 569 if (crtc->state->gamma_lut) { 570 vc4_hvs_update_gamma_lut(hvs, vc4_crtc); 571 dispbkgndx |= SCALER_DISPBKGND_GAMMA; 572 } else { 573 /* Unsetting DISPBKGND_GAMMA skips the gamma lut step 574 * in hardware, which is the same as a linear lut that 575 * DRM expects us to use in absence of a user lut. 576 */ 577 dispbkgndx &= ~SCALER_DISPBKGND_GAMMA; 578 } 579 HVS_WRITE(SCALER_DISPBKGNDX(channel), dispbkgndx); 580 } 581 582 if (debug_dump_regs) { 583 DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc)); 584 vc4_hvs_dump_state(hvs); 585 } 586 } 587 588 void vc4_hvs_mask_underrun(struct vc4_hvs *hvs, int channel) 589 { 590 u32 dispctrl = HVS_READ(SCALER_DISPCTRL); 591 592 dispctrl &= ~SCALER_DISPCTRL_DSPEISLUR(channel); 593 594 HVS_WRITE(SCALER_DISPCTRL, dispctrl); 595 } 596 597 void vc4_hvs_unmask_underrun(struct vc4_hvs *hvs, int channel) 598 { 599 u32 dispctrl = HVS_READ(SCALER_DISPCTRL); 600 601 dispctrl |= SCALER_DISPCTRL_DSPEISLUR(channel); 602 603 HVS_WRITE(SCALER_DISPSTAT, 604 SCALER_DISPSTAT_EUFLOW(channel)); 605 HVS_WRITE(SCALER_DISPCTRL, dispctrl); 606 } 607 608 static void vc4_hvs_report_underrun(struct drm_device *dev) 609 { 610 struct vc4_dev *vc4 = to_vc4_dev(dev); 611 612 atomic_inc(&vc4->underrun); 613 DRM_DEV_ERROR(dev->dev, "HVS underrun\n"); 614 } 615 616 static irqreturn_t vc4_hvs_irq_handler(int irq, void *data) 617 { 618 struct drm_device *dev = data; 619 struct vc4_dev *vc4 = to_vc4_dev(dev); 620 struct vc4_hvs *hvs = vc4->hvs; 621 irqreturn_t irqret = IRQ_NONE; 622 int channel; 623 u32 control; 624 u32 status; 625 626 status = HVS_READ(SCALER_DISPSTAT); 627 control = HVS_READ(SCALER_DISPCTRL); 628 629 for (channel = 0; channel < SCALER_CHANNELS_COUNT; channel++) { 630 /* Interrupt masking is not always honored, so check it here. */ 631 if (status & SCALER_DISPSTAT_EUFLOW(channel) && 632 control & SCALER_DISPCTRL_DSPEISLUR(channel)) { 633 vc4_hvs_mask_underrun(hvs, channel); 634 vc4_hvs_report_underrun(dev); 635 636 irqret = IRQ_HANDLED; 637 } 638 } 639 640 /* Clear every per-channel interrupt flag. */ 641 HVS_WRITE(SCALER_DISPSTAT, SCALER_DISPSTAT_IRQMASK(0) | 642 SCALER_DISPSTAT_IRQMASK(1) | 643 SCALER_DISPSTAT_IRQMASK(2)); 644 645 return irqret; 646 } 647 648 static int vc4_hvs_bind(struct device *dev, struct device *master, void *data) 649 { 650 struct platform_device *pdev = to_platform_device(dev); 651 struct drm_device *drm = dev_get_drvdata(master); 652 struct vc4_dev *vc4 = to_vc4_dev(drm); 653 struct vc4_hvs *hvs = NULL; 654 int ret; 655 u32 dispctrl; 656 u32 reg; 657 658 hvs = devm_kzalloc(&pdev->dev, sizeof(*hvs), GFP_KERNEL); 659 if (!hvs) 660 return -ENOMEM; 661 662 hvs->vc4 = vc4; 663 hvs->pdev = pdev; 664 665 hvs->regs = vc4_ioremap_regs(pdev, 0); 666 if (IS_ERR(hvs->regs)) 667 return PTR_ERR(hvs->regs); 668 669 hvs->regset.base = hvs->regs; 670 hvs->regset.regs = hvs_regs; 671 hvs->regset.nregs = ARRAY_SIZE(hvs_regs); 672 673 if (vc4->is_vc5) { 674 hvs->core_clk = devm_clk_get(&pdev->dev, NULL); 675 if (IS_ERR(hvs->core_clk)) { 676 dev_err(&pdev->dev, "Couldn't get core clock\n"); 677 return PTR_ERR(hvs->core_clk); 678 } 679 680 ret = clk_prepare_enable(hvs->core_clk); 681 if (ret) { 682 dev_err(&pdev->dev, "Couldn't enable the core clock\n"); 683 return ret; 684 } 685 } 686 687 if (!vc4->is_vc5) 688 hvs->dlist = hvs->regs + SCALER_DLIST_START; 689 else 690 hvs->dlist = hvs->regs + SCALER5_DLIST_START; 691 692 spin_lock_init(&hvs->mm_lock); 693 694 /* Set up the HVS display list memory manager. We never 695 * overwrite the setup from the bootloader (just 128b out of 696 * our 16K), since we don't want to scramble the screen when 697 * transitioning from the firmware's boot setup to runtime. 698 */ 699 drm_mm_init(&hvs->dlist_mm, 700 HVS_BOOTLOADER_DLIST_END, 701 (SCALER_DLIST_SIZE >> 2) - HVS_BOOTLOADER_DLIST_END); 702 703 /* Set up the HVS LBM memory manager. We could have some more 704 * complicated data structure that allowed reuse of LBM areas 705 * between planes when they don't overlap on the screen, but 706 * for now we just allocate globally. 707 */ 708 if (!vc4->is_vc5) 709 /* 48k words of 2x12-bit pixels */ 710 drm_mm_init(&hvs->lbm_mm, 0, 48 * 1024); 711 else 712 /* 60k words of 4x12-bit pixels */ 713 drm_mm_init(&hvs->lbm_mm, 0, 60 * 1024); 714 715 /* Upload filter kernels. We only have the one for now, so we 716 * keep it around for the lifetime of the driver. 717 */ 718 ret = vc4_hvs_upload_linear_kernel(hvs, 719 &hvs->mitchell_netravali_filter, 720 mitchell_netravali_1_3_1_3_kernel); 721 if (ret) 722 return ret; 723 724 vc4->hvs = hvs; 725 726 reg = HVS_READ(SCALER_DISPECTRL); 727 reg &= ~SCALER_DISPECTRL_DSP2_MUX_MASK; 728 HVS_WRITE(SCALER_DISPECTRL, 729 reg | VC4_SET_FIELD(0, SCALER_DISPECTRL_DSP2_MUX)); 730 731 reg = HVS_READ(SCALER_DISPCTRL); 732 reg &= ~SCALER_DISPCTRL_DSP3_MUX_MASK; 733 HVS_WRITE(SCALER_DISPCTRL, 734 reg | VC4_SET_FIELD(3, SCALER_DISPCTRL_DSP3_MUX)); 735 736 reg = HVS_READ(SCALER_DISPEOLN); 737 reg &= ~SCALER_DISPEOLN_DSP4_MUX_MASK; 738 HVS_WRITE(SCALER_DISPEOLN, 739 reg | VC4_SET_FIELD(3, SCALER_DISPEOLN_DSP4_MUX)); 740 741 reg = HVS_READ(SCALER_DISPDITHER); 742 reg &= ~SCALER_DISPDITHER_DSP5_MUX_MASK; 743 HVS_WRITE(SCALER_DISPDITHER, 744 reg | VC4_SET_FIELD(3, SCALER_DISPDITHER_DSP5_MUX)); 745 746 dispctrl = HVS_READ(SCALER_DISPCTRL); 747 748 dispctrl |= SCALER_DISPCTRL_ENABLE; 749 dispctrl |= SCALER_DISPCTRL_DISPEIRQ(0) | 750 SCALER_DISPCTRL_DISPEIRQ(1) | 751 SCALER_DISPCTRL_DISPEIRQ(2); 752 753 dispctrl &= ~(SCALER_DISPCTRL_DMAEIRQ | 754 SCALER_DISPCTRL_SLVWREIRQ | 755 SCALER_DISPCTRL_SLVRDEIRQ | 756 SCALER_DISPCTRL_DSPEIEOF(0) | 757 SCALER_DISPCTRL_DSPEIEOF(1) | 758 SCALER_DISPCTRL_DSPEIEOF(2) | 759 SCALER_DISPCTRL_DSPEIEOLN(0) | 760 SCALER_DISPCTRL_DSPEIEOLN(1) | 761 SCALER_DISPCTRL_DSPEIEOLN(2) | 762 SCALER_DISPCTRL_DSPEISLUR(0) | 763 SCALER_DISPCTRL_DSPEISLUR(1) | 764 SCALER_DISPCTRL_DSPEISLUR(2) | 765 SCALER_DISPCTRL_SCLEIRQ); 766 767 HVS_WRITE(SCALER_DISPCTRL, dispctrl); 768 769 ret = devm_request_irq(dev, platform_get_irq(pdev, 0), 770 vc4_hvs_irq_handler, 0, "vc4 hvs", drm); 771 if (ret) 772 return ret; 773 774 vc4_debugfs_add_regset32(drm, "hvs_regs", &hvs->regset); 775 vc4_debugfs_add_file(drm, "hvs_underrun", vc4_hvs_debugfs_underrun, 776 NULL); 777 vc4_debugfs_add_file(drm, "hvs_dlists", vc4_hvs_debugfs_dlist, 778 NULL); 779 780 return 0; 781 } 782 783 static void vc4_hvs_unbind(struct device *dev, struct device *master, 784 void *data) 785 { 786 struct drm_device *drm = dev_get_drvdata(master); 787 struct vc4_dev *vc4 = to_vc4_dev(drm); 788 struct vc4_hvs *hvs = vc4->hvs; 789 790 if (drm_mm_node_allocated(&vc4->hvs->mitchell_netravali_filter)) 791 drm_mm_remove_node(&vc4->hvs->mitchell_netravali_filter); 792 793 drm_mm_takedown(&vc4->hvs->dlist_mm); 794 drm_mm_takedown(&vc4->hvs->lbm_mm); 795 796 clk_disable_unprepare(hvs->core_clk); 797 798 vc4->hvs = NULL; 799 } 800 801 static const struct component_ops vc4_hvs_ops = { 802 .bind = vc4_hvs_bind, 803 .unbind = vc4_hvs_unbind, 804 }; 805 806 static int vc4_hvs_dev_probe(struct platform_device *pdev) 807 { 808 return component_add(&pdev->dev, &vc4_hvs_ops); 809 } 810 811 static int vc4_hvs_dev_remove(struct platform_device *pdev) 812 { 813 component_del(&pdev->dev, &vc4_hvs_ops); 814 return 0; 815 } 816 817 static const struct of_device_id vc4_hvs_dt_match[] = { 818 { .compatible = "brcm,bcm2711-hvs" }, 819 { .compatible = "brcm,bcm2835-hvs" }, 820 {} 821 }; 822 823 struct platform_driver vc4_hvs_driver = { 824 .probe = vc4_hvs_dev_probe, 825 .remove = vc4_hvs_dev_remove, 826 .driver = { 827 .name = "vc4_hvs", 828 .of_match_table = vc4_hvs_dt_match, 829 }, 830 }; 831