1 #ifndef _VC4_HDMI_REGS_H_ 2 #define _VC4_HDMI_REGS_H_ 3 4 #include "vc4_hdmi.h" 5 6 #define VC4_HDMI_PACKET_STRIDE 0x24 7 8 enum vc4_hdmi_regs { 9 VC4_INVALID = 0, 10 VC4_HDMI, 11 VC4_HD, 12 VC5_CEC, 13 VC5_CSC, 14 VC5_DVP, 15 VC5_PHY, 16 VC5_RAM, 17 VC5_RM, 18 }; 19 20 enum vc4_hdmi_field { 21 HDMI_AUDIO_PACKET_CONFIG, 22 HDMI_CEC_CNTRL_1, 23 HDMI_CEC_CNTRL_2, 24 HDMI_CEC_CNTRL_3, 25 HDMI_CEC_CNTRL_4, 26 HDMI_CEC_CNTRL_5, 27 HDMI_CEC_CPU_CLEAR, 28 HDMI_CEC_CPU_MASK_CLEAR, 29 HDMI_CEC_CPU_MASK_SET, 30 HDMI_CEC_CPU_MASK_STATUS, 31 HDMI_CEC_CPU_STATUS, 32 33 /* 34 * Transmit data, first byte is low byte of the 32-bit reg. 35 * MSB of each byte transmitted first. 36 */ 37 HDMI_CEC_RX_DATA_1, 38 HDMI_CEC_RX_DATA_2, 39 HDMI_CEC_RX_DATA_3, 40 HDMI_CEC_RX_DATA_4, 41 HDMI_CEC_TX_DATA_1, 42 HDMI_CEC_TX_DATA_2, 43 HDMI_CEC_TX_DATA_3, 44 HDMI_CEC_TX_DATA_4, 45 HDMI_CLOCK_STOP, 46 HDMI_CORE_REV, 47 HDMI_CRP_CFG, 48 HDMI_CSC_12_11, 49 HDMI_CSC_14_13, 50 HDMI_CSC_22_21, 51 HDMI_CSC_24_23, 52 HDMI_CSC_32_31, 53 HDMI_CSC_34_33, 54 HDMI_CSC_CTL, 55 56 /* 57 * 20-bit fields containing CTS values to be transmitted if 58 * !EXTERNAL_CTS_EN 59 */ 60 HDMI_CTS_0, 61 HDMI_CTS_1, 62 HDMI_DEEP_COLOR_CONFIG_1, 63 HDMI_DVP_CTL, 64 HDMI_FIFO_CTL, 65 HDMI_FRAME_COUNT, 66 HDMI_GCP_CONFIG, 67 HDMI_GCP_WORD_1, 68 HDMI_HORZA, 69 HDMI_HORZB, 70 HDMI_HOTPLUG, 71 HDMI_HOTPLUG_INT, 72 73 /* 74 * 3 bits per field, where each field maps from that 75 * corresponding MAI bus channel to the given HDMI channel. 76 */ 77 HDMI_MAI_CHANNEL_MAP, 78 HDMI_MAI_CONFIG, 79 HDMI_MAI_CTL, 80 81 /* 82 * Register for DMAing in audio data to be transported over 83 * the MAI bus to the Falcon core. 84 */ 85 HDMI_MAI_DATA, 86 87 /* Format header to be placed on the MAI data. Unused. */ 88 HDMI_MAI_FMT, 89 90 /* Last received format word on the MAI bus. */ 91 HDMI_MAI_FORMAT, 92 HDMI_MAI_SMP, 93 HDMI_MAI_THR, 94 HDMI_M_CTL, 95 HDMI_RAM_PACKET_CONFIG, 96 HDMI_RAM_PACKET_START, 97 HDMI_RAM_PACKET_STATUS, 98 HDMI_RM_CONTROL, 99 HDMI_RM_FORMAT, 100 HDMI_RM_OFFSET, 101 HDMI_SCHEDULER_CONTROL, 102 HDMI_SW_RESET_CONTROL, 103 HDMI_TX_PHY_CHANNEL_SWAP, 104 HDMI_TX_PHY_CLK_DIV, 105 HDMI_TX_PHY_CTL_0, 106 HDMI_TX_PHY_CTL_1, 107 HDMI_TX_PHY_CTL_2, 108 HDMI_TX_PHY_CTL_3, 109 HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1, 110 HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2, 111 HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4, 112 HDMI_TX_PHY_PLL_CFG, 113 HDMI_TX_PHY_PLL_CTL_0, 114 HDMI_TX_PHY_PLL_CTL_1, 115 HDMI_TX_PHY_POWERDOWN_CTL, 116 HDMI_TX_PHY_RESET_CTL, 117 HDMI_TX_PHY_TMDS_CLK_WORD_SEL, 118 HDMI_VEC_INTERFACE_XBAR, 119 HDMI_VERTA0, 120 HDMI_VERTA1, 121 HDMI_VERTB0, 122 HDMI_VERTB1, 123 HDMI_VID_CTL, 124 }; 125 126 struct vc4_hdmi_register { 127 char *name; 128 enum vc4_hdmi_regs reg; 129 unsigned int offset; 130 }; 131 132 #define _VC4_REG(_base, _reg, _offset) \ 133 [_reg] = { \ 134 .name = #_reg, \ 135 .reg = _base, \ 136 .offset = _offset, \ 137 } 138 139 #define VC4_HD_REG(reg, offset) _VC4_REG(VC4_HD, reg, offset) 140 #define VC4_HDMI_REG(reg, offset) _VC4_REG(VC4_HDMI, reg, offset) 141 #define VC5_CEC_REG(reg, offset) _VC4_REG(VC5_CEC, reg, offset) 142 #define VC5_CSC_REG(reg, offset) _VC4_REG(VC5_CSC, reg, offset) 143 #define VC5_DVP_REG(reg, offset) _VC4_REG(VC5_DVP, reg, offset) 144 #define VC5_PHY_REG(reg, offset) _VC4_REG(VC5_PHY, reg, offset) 145 #define VC5_RAM_REG(reg, offset) _VC4_REG(VC5_RAM, reg, offset) 146 #define VC5_RM_REG(reg, offset) _VC4_REG(VC5_RM, reg, offset) 147 148 static const struct vc4_hdmi_register __maybe_unused vc4_hdmi_fields[] = { 149 VC4_HD_REG(HDMI_M_CTL, 0x000c), 150 VC4_HD_REG(HDMI_MAI_CTL, 0x0014), 151 VC4_HD_REG(HDMI_MAI_THR, 0x0018), 152 VC4_HD_REG(HDMI_MAI_FMT, 0x001c), 153 VC4_HD_REG(HDMI_MAI_DATA, 0x0020), 154 VC4_HD_REG(HDMI_MAI_SMP, 0x002c), 155 VC4_HD_REG(HDMI_VID_CTL, 0x0038), 156 VC4_HD_REG(HDMI_CSC_CTL, 0x0040), 157 VC4_HD_REG(HDMI_CSC_12_11, 0x0044), 158 VC4_HD_REG(HDMI_CSC_14_13, 0x0048), 159 VC4_HD_REG(HDMI_CSC_22_21, 0x004c), 160 VC4_HD_REG(HDMI_CSC_24_23, 0x0050), 161 VC4_HD_REG(HDMI_CSC_32_31, 0x0054), 162 VC4_HD_REG(HDMI_CSC_34_33, 0x0058), 163 VC4_HD_REG(HDMI_FRAME_COUNT, 0x0068), 164 165 VC4_HDMI_REG(HDMI_CORE_REV, 0x0000), 166 VC4_HDMI_REG(HDMI_SW_RESET_CONTROL, 0x0004), 167 VC4_HDMI_REG(HDMI_HOTPLUG_INT, 0x0008), 168 VC4_HDMI_REG(HDMI_HOTPLUG, 0x000c), 169 VC4_HDMI_REG(HDMI_FIFO_CTL, 0x005c), 170 VC4_HDMI_REG(HDMI_MAI_CHANNEL_MAP, 0x0090), 171 VC4_HDMI_REG(HDMI_MAI_CONFIG, 0x0094), 172 VC4_HDMI_REG(HDMI_MAI_FORMAT, 0x0098), 173 VC4_HDMI_REG(HDMI_AUDIO_PACKET_CONFIG, 0x009c), 174 VC4_HDMI_REG(HDMI_RAM_PACKET_CONFIG, 0x00a0), 175 VC4_HDMI_REG(HDMI_RAM_PACKET_STATUS, 0x00a4), 176 VC4_HDMI_REG(HDMI_CRP_CFG, 0x00a8), 177 VC4_HDMI_REG(HDMI_CTS_0, 0x00ac), 178 VC4_HDMI_REG(HDMI_CTS_1, 0x00b0), 179 VC4_HDMI_REG(HDMI_SCHEDULER_CONTROL, 0x00c0), 180 VC4_HDMI_REG(HDMI_HORZA, 0x00c4), 181 VC4_HDMI_REG(HDMI_HORZB, 0x00c8), 182 VC4_HDMI_REG(HDMI_VERTA0, 0x00cc), 183 VC4_HDMI_REG(HDMI_VERTB0, 0x00d0), 184 VC4_HDMI_REG(HDMI_VERTA1, 0x00d4), 185 VC4_HDMI_REG(HDMI_VERTB1, 0x00d8), 186 VC4_HDMI_REG(HDMI_CEC_CNTRL_1, 0x00e8), 187 VC4_HDMI_REG(HDMI_CEC_CNTRL_2, 0x00ec), 188 VC4_HDMI_REG(HDMI_CEC_CNTRL_3, 0x00f0), 189 VC4_HDMI_REG(HDMI_CEC_CNTRL_4, 0x00f4), 190 VC4_HDMI_REG(HDMI_CEC_CNTRL_5, 0x00f8), 191 VC4_HDMI_REG(HDMI_CEC_TX_DATA_1, 0x00fc), 192 VC4_HDMI_REG(HDMI_CEC_TX_DATA_2, 0x0100), 193 VC4_HDMI_REG(HDMI_CEC_TX_DATA_3, 0x0104), 194 VC4_HDMI_REG(HDMI_CEC_TX_DATA_4, 0x0108), 195 VC4_HDMI_REG(HDMI_CEC_RX_DATA_1, 0x010c), 196 VC4_HDMI_REG(HDMI_CEC_RX_DATA_2, 0x0110), 197 VC4_HDMI_REG(HDMI_CEC_RX_DATA_3, 0x0114), 198 VC4_HDMI_REG(HDMI_CEC_RX_DATA_4, 0x0118), 199 VC4_HDMI_REG(HDMI_TX_PHY_RESET_CTL, 0x02c0), 200 VC4_HDMI_REG(HDMI_TX_PHY_CTL_0, 0x02c4), 201 VC4_HDMI_REG(HDMI_CEC_CPU_STATUS, 0x0340), 202 VC4_HDMI_REG(HDMI_CEC_CPU_CLEAR, 0x0348), 203 VC4_HDMI_REG(HDMI_CEC_CPU_MASK_STATUS, 0x034c), 204 VC4_HDMI_REG(HDMI_CEC_CPU_MASK_SET, 0x034c), 205 VC4_HDMI_REG(HDMI_CEC_CPU_MASK_CLEAR, 0x0354), 206 VC4_HDMI_REG(HDMI_RAM_PACKET_START, 0x0400), 207 }; 208 209 static const struct vc4_hdmi_register __maybe_unused vc5_hdmi_hdmi0_fields[] = { 210 VC4_HD_REG(HDMI_DVP_CTL, 0x0000), 211 VC4_HD_REG(HDMI_MAI_CTL, 0x0010), 212 VC4_HD_REG(HDMI_MAI_THR, 0x0014), 213 VC4_HD_REG(HDMI_MAI_FMT, 0x0018), 214 VC4_HD_REG(HDMI_MAI_DATA, 0x001c), 215 VC4_HD_REG(HDMI_MAI_SMP, 0x0020), 216 VC4_HD_REG(HDMI_VID_CTL, 0x0044), 217 VC4_HD_REG(HDMI_FRAME_COUNT, 0x0060), 218 219 VC4_HDMI_REG(HDMI_FIFO_CTL, 0x074), 220 VC4_HDMI_REG(HDMI_AUDIO_PACKET_CONFIG, 0x0b8), 221 VC4_HDMI_REG(HDMI_RAM_PACKET_CONFIG, 0x0bc), 222 VC4_HDMI_REG(HDMI_RAM_PACKET_STATUS, 0x0c4), 223 VC4_HDMI_REG(HDMI_CRP_CFG, 0x0c8), 224 VC4_HDMI_REG(HDMI_CTS_0, 0x0cc), 225 VC4_HDMI_REG(HDMI_CTS_1, 0x0d0), 226 VC4_HDMI_REG(HDMI_SCHEDULER_CONTROL, 0x0e0), 227 VC4_HDMI_REG(HDMI_HORZA, 0x0e4), 228 VC4_HDMI_REG(HDMI_HORZB, 0x0e8), 229 VC4_HDMI_REG(HDMI_VERTA0, 0x0ec), 230 VC4_HDMI_REG(HDMI_VERTB0, 0x0f0), 231 VC4_HDMI_REG(HDMI_VERTA1, 0x0f4), 232 VC4_HDMI_REG(HDMI_VERTB1, 0x0f8), 233 VC4_HDMI_REG(HDMI_MAI_CHANNEL_MAP, 0x09c), 234 VC4_HDMI_REG(HDMI_MAI_CONFIG, 0x0a0), 235 VC4_HDMI_REG(HDMI_DEEP_COLOR_CONFIG_1, 0x170), 236 VC4_HDMI_REG(HDMI_GCP_CONFIG, 0x178), 237 VC4_HDMI_REG(HDMI_GCP_WORD_1, 0x17c), 238 VC4_HDMI_REG(HDMI_HOTPLUG, 0x1a8), 239 240 VC5_DVP_REG(HDMI_CLOCK_STOP, 0x0bc), 241 VC5_DVP_REG(HDMI_VEC_INTERFACE_XBAR, 0x0f0), 242 243 VC5_PHY_REG(HDMI_TX_PHY_RESET_CTL, 0x000), 244 VC5_PHY_REG(HDMI_TX_PHY_POWERDOWN_CTL, 0x004), 245 VC5_PHY_REG(HDMI_TX_PHY_CTL_0, 0x008), 246 VC5_PHY_REG(HDMI_TX_PHY_CTL_1, 0x00c), 247 VC5_PHY_REG(HDMI_TX_PHY_CTL_2, 0x010), 248 VC5_PHY_REG(HDMI_TX_PHY_CTL_3, 0x014), 249 VC5_PHY_REG(HDMI_TX_PHY_PLL_CTL_0, 0x01c), 250 VC5_PHY_REG(HDMI_TX_PHY_PLL_CTL_1, 0x020), 251 VC5_PHY_REG(HDMI_TX_PHY_CLK_DIV, 0x028), 252 VC5_PHY_REG(HDMI_TX_PHY_PLL_CFG, 0x034), 253 VC5_PHY_REG(HDMI_TX_PHY_TMDS_CLK_WORD_SEL, 0x044), 254 VC5_PHY_REG(HDMI_TX_PHY_CHANNEL_SWAP, 0x04c), 255 VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1, 0x050), 256 VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2, 0x054), 257 VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4, 0x05c), 258 259 VC5_RM_REG(HDMI_RM_CONTROL, 0x000), 260 VC5_RM_REG(HDMI_RM_OFFSET, 0x018), 261 VC5_RM_REG(HDMI_RM_FORMAT, 0x01c), 262 263 VC5_RAM_REG(HDMI_RAM_PACKET_START, 0x000), 264 265 VC5_CEC_REG(HDMI_CEC_CNTRL_1, 0x010), 266 VC5_CEC_REG(HDMI_CEC_CNTRL_2, 0x014), 267 VC5_CEC_REG(HDMI_CEC_CNTRL_3, 0x018), 268 VC5_CEC_REG(HDMI_CEC_CNTRL_4, 0x01c), 269 VC5_CEC_REG(HDMI_CEC_CNTRL_5, 0x020), 270 VC5_CEC_REG(HDMI_CEC_TX_DATA_1, 0x028), 271 VC5_CEC_REG(HDMI_CEC_TX_DATA_2, 0x02c), 272 VC5_CEC_REG(HDMI_CEC_TX_DATA_3, 0x030), 273 VC5_CEC_REG(HDMI_CEC_TX_DATA_4, 0x034), 274 VC5_CEC_REG(HDMI_CEC_RX_DATA_1, 0x038), 275 VC5_CEC_REG(HDMI_CEC_RX_DATA_2, 0x03c), 276 VC5_CEC_REG(HDMI_CEC_RX_DATA_3, 0x040), 277 VC5_CEC_REG(HDMI_CEC_RX_DATA_4, 0x044), 278 279 VC5_CSC_REG(HDMI_CSC_CTL, 0x000), 280 VC5_CSC_REG(HDMI_CSC_12_11, 0x004), 281 VC5_CSC_REG(HDMI_CSC_14_13, 0x008), 282 VC5_CSC_REG(HDMI_CSC_22_21, 0x00c), 283 VC5_CSC_REG(HDMI_CSC_24_23, 0x010), 284 VC5_CSC_REG(HDMI_CSC_32_31, 0x014), 285 VC5_CSC_REG(HDMI_CSC_34_33, 0x018), 286 }; 287 288 static const struct vc4_hdmi_register __maybe_unused vc5_hdmi_hdmi1_fields[] = { 289 VC4_HD_REG(HDMI_DVP_CTL, 0x0000), 290 VC4_HD_REG(HDMI_MAI_CTL, 0x0030), 291 VC4_HD_REG(HDMI_MAI_THR, 0x0034), 292 VC4_HD_REG(HDMI_MAI_FMT, 0x0038), 293 VC4_HD_REG(HDMI_MAI_DATA, 0x003c), 294 VC4_HD_REG(HDMI_MAI_SMP, 0x0040), 295 VC4_HD_REG(HDMI_VID_CTL, 0x0048), 296 VC4_HD_REG(HDMI_FRAME_COUNT, 0x0064), 297 298 VC4_HDMI_REG(HDMI_FIFO_CTL, 0x074), 299 VC4_HDMI_REG(HDMI_AUDIO_PACKET_CONFIG, 0x0b8), 300 VC4_HDMI_REG(HDMI_RAM_PACKET_CONFIG, 0x0bc), 301 VC4_HDMI_REG(HDMI_RAM_PACKET_STATUS, 0x0c4), 302 VC4_HDMI_REG(HDMI_CRP_CFG, 0x0c8), 303 VC4_HDMI_REG(HDMI_CTS_0, 0x0cc), 304 VC4_HDMI_REG(HDMI_CTS_1, 0x0d0), 305 VC4_HDMI_REG(HDMI_SCHEDULER_CONTROL, 0x0e0), 306 VC4_HDMI_REG(HDMI_HORZA, 0x0e4), 307 VC4_HDMI_REG(HDMI_HORZB, 0x0e8), 308 VC4_HDMI_REG(HDMI_VERTA0, 0x0ec), 309 VC4_HDMI_REG(HDMI_VERTB0, 0x0f0), 310 VC4_HDMI_REG(HDMI_VERTA1, 0x0f4), 311 VC4_HDMI_REG(HDMI_VERTB1, 0x0f8), 312 VC4_HDMI_REG(HDMI_MAI_CHANNEL_MAP, 0x09c), 313 VC4_HDMI_REG(HDMI_MAI_CONFIG, 0x0a0), 314 VC4_HDMI_REG(HDMI_DEEP_COLOR_CONFIG_1, 0x170), 315 VC4_HDMI_REG(HDMI_GCP_CONFIG, 0x178), 316 VC4_HDMI_REG(HDMI_GCP_WORD_1, 0x17c), 317 VC4_HDMI_REG(HDMI_HOTPLUG, 0x1a8), 318 319 VC5_DVP_REG(HDMI_CLOCK_STOP, 0x0bc), 320 VC5_DVP_REG(HDMI_VEC_INTERFACE_XBAR, 0x0f0), 321 322 VC5_PHY_REG(HDMI_TX_PHY_RESET_CTL, 0x000), 323 VC5_PHY_REG(HDMI_TX_PHY_POWERDOWN_CTL, 0x004), 324 VC5_PHY_REG(HDMI_TX_PHY_CTL_0, 0x008), 325 VC5_PHY_REG(HDMI_TX_PHY_CTL_1, 0x00c), 326 VC5_PHY_REG(HDMI_TX_PHY_CTL_2, 0x010), 327 VC5_PHY_REG(HDMI_TX_PHY_CTL_3, 0x014), 328 VC5_PHY_REG(HDMI_TX_PHY_PLL_CTL_0, 0x01c), 329 VC5_PHY_REG(HDMI_TX_PHY_PLL_CTL_1, 0x020), 330 VC5_PHY_REG(HDMI_TX_PHY_CLK_DIV, 0x028), 331 VC5_PHY_REG(HDMI_TX_PHY_PLL_CFG, 0x034), 332 VC5_PHY_REG(HDMI_TX_PHY_CHANNEL_SWAP, 0x04c), 333 VC5_PHY_REG(HDMI_TX_PHY_TMDS_CLK_WORD_SEL, 0x044), 334 VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1, 0x050), 335 VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2, 0x054), 336 VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4, 0x05c), 337 338 VC5_RM_REG(HDMI_RM_CONTROL, 0x000), 339 VC5_RM_REG(HDMI_RM_OFFSET, 0x018), 340 VC5_RM_REG(HDMI_RM_FORMAT, 0x01c), 341 342 VC5_RAM_REG(HDMI_RAM_PACKET_START, 0x000), 343 344 VC5_CEC_REG(HDMI_CEC_CNTRL_1, 0x010), 345 VC5_CEC_REG(HDMI_CEC_CNTRL_2, 0x014), 346 VC5_CEC_REG(HDMI_CEC_CNTRL_3, 0x018), 347 VC5_CEC_REG(HDMI_CEC_CNTRL_4, 0x01c), 348 VC5_CEC_REG(HDMI_CEC_CNTRL_5, 0x020), 349 VC5_CEC_REG(HDMI_CEC_TX_DATA_1, 0x028), 350 VC5_CEC_REG(HDMI_CEC_TX_DATA_2, 0x02c), 351 VC5_CEC_REG(HDMI_CEC_TX_DATA_3, 0x030), 352 VC5_CEC_REG(HDMI_CEC_TX_DATA_4, 0x034), 353 VC5_CEC_REG(HDMI_CEC_RX_DATA_1, 0x038), 354 VC5_CEC_REG(HDMI_CEC_RX_DATA_2, 0x03c), 355 VC5_CEC_REG(HDMI_CEC_RX_DATA_3, 0x040), 356 VC5_CEC_REG(HDMI_CEC_RX_DATA_4, 0x044), 357 358 VC5_CSC_REG(HDMI_CSC_CTL, 0x000), 359 VC5_CSC_REG(HDMI_CSC_12_11, 0x004), 360 VC5_CSC_REG(HDMI_CSC_14_13, 0x008), 361 VC5_CSC_REG(HDMI_CSC_22_21, 0x00c), 362 VC5_CSC_REG(HDMI_CSC_24_23, 0x010), 363 VC5_CSC_REG(HDMI_CSC_32_31, 0x014), 364 VC5_CSC_REG(HDMI_CSC_34_33, 0x018), 365 }; 366 367 static inline 368 void __iomem *__vc4_hdmi_get_field_base(struct vc4_hdmi *hdmi, 369 enum vc4_hdmi_regs reg) 370 { 371 switch (reg) { 372 case VC4_HD: 373 return hdmi->hd_regs; 374 375 case VC4_HDMI: 376 return hdmi->hdmicore_regs; 377 378 case VC5_CSC: 379 return hdmi->csc_regs; 380 381 case VC5_CEC: 382 return hdmi->cec_regs; 383 384 case VC5_DVP: 385 return hdmi->dvp_regs; 386 387 case VC5_PHY: 388 return hdmi->phy_regs; 389 390 case VC5_RAM: 391 return hdmi->ram_regs; 392 393 case VC5_RM: 394 return hdmi->rm_regs; 395 396 default: 397 return NULL; 398 } 399 400 return NULL; 401 } 402 403 static inline u32 vc4_hdmi_read(struct vc4_hdmi *hdmi, 404 enum vc4_hdmi_field reg) 405 { 406 const struct vc4_hdmi_register *field; 407 const struct vc4_hdmi_variant *variant = hdmi->variant; 408 void __iomem *base; 409 410 if (reg >= variant->num_registers) { 411 dev_warn(&hdmi->pdev->dev, 412 "Invalid register ID %u\n", reg); 413 return 0; 414 } 415 416 field = &variant->registers[reg]; 417 base = __vc4_hdmi_get_field_base(hdmi, field->reg); 418 if (!base) { 419 dev_warn(&hdmi->pdev->dev, 420 "Unknown register ID %u\n", reg); 421 return 0; 422 } 423 424 return readl(base + field->offset); 425 } 426 #define HDMI_READ(reg) vc4_hdmi_read(vc4_hdmi, reg) 427 428 static inline void vc4_hdmi_write(struct vc4_hdmi *hdmi, 429 enum vc4_hdmi_field reg, 430 u32 value) 431 { 432 const struct vc4_hdmi_register *field; 433 const struct vc4_hdmi_variant *variant = hdmi->variant; 434 void __iomem *base; 435 436 if (reg >= variant->num_registers) { 437 dev_warn(&hdmi->pdev->dev, 438 "Invalid register ID %u\n", reg); 439 return; 440 } 441 442 field = &variant->registers[reg]; 443 base = __vc4_hdmi_get_field_base(hdmi, field->reg); 444 if (!base) 445 return; 446 447 writel(value, base + field->offset); 448 } 449 #define HDMI_WRITE(reg, val) vc4_hdmi_write(vc4_hdmi, reg, val) 450 451 #endif /* _VC4_HDMI_REGS_H_ */ 452