1 #ifndef _VC4_HDMI_REGS_H_ 2 #define _VC4_HDMI_REGS_H_ 3 4 #include "vc4_hdmi.h" 5 6 #define VC4_HDMI_PACKET_STRIDE 0x24 7 8 enum vc4_hdmi_regs { 9 VC4_INVALID = 0, 10 VC4_HDMI, 11 VC4_HD, 12 VC5_CEC, 13 VC5_CSC, 14 VC5_DVP, 15 VC5_PHY, 16 VC5_RAM, 17 VC5_RM, 18 }; 19 20 enum vc4_hdmi_field { 21 HDMI_AUDIO_PACKET_CONFIG, 22 HDMI_CEC_CNTRL_1, 23 HDMI_CEC_CNTRL_2, 24 HDMI_CEC_CNTRL_3, 25 HDMI_CEC_CNTRL_4, 26 HDMI_CEC_CNTRL_5, 27 HDMI_CEC_CPU_CLEAR, 28 HDMI_CEC_CPU_MASK_CLEAR, 29 HDMI_CEC_CPU_MASK_SET, 30 HDMI_CEC_CPU_MASK_STATUS, 31 HDMI_CEC_CPU_STATUS, 32 33 /* 34 * Transmit data, first byte is low byte of the 32-bit reg. 35 * MSB of each byte transmitted first. 36 */ 37 HDMI_CEC_RX_DATA_1, 38 HDMI_CEC_RX_DATA_2, 39 HDMI_CEC_RX_DATA_3, 40 HDMI_CEC_RX_DATA_4, 41 HDMI_CEC_TX_DATA_1, 42 HDMI_CEC_TX_DATA_2, 43 HDMI_CEC_TX_DATA_3, 44 HDMI_CEC_TX_DATA_4, 45 HDMI_CLOCK_STOP, 46 HDMI_CORE_REV, 47 HDMI_CRP_CFG, 48 HDMI_CSC_12_11, 49 HDMI_CSC_14_13, 50 HDMI_CSC_22_21, 51 HDMI_CSC_24_23, 52 HDMI_CSC_32_31, 53 HDMI_CSC_34_33, 54 HDMI_CSC_CTL, 55 56 /* 57 * 20-bit fields containing CTS values to be transmitted if 58 * !EXTERNAL_CTS_EN 59 */ 60 HDMI_CTS_0, 61 HDMI_CTS_1, 62 HDMI_DVP_CTL, 63 HDMI_FIFO_CTL, 64 HDMI_FRAME_COUNT, 65 HDMI_HORZA, 66 HDMI_HORZB, 67 HDMI_HOTPLUG, 68 HDMI_HOTPLUG_INT, 69 70 /* 71 * 3 bits per field, where each field maps from that 72 * corresponding MAI bus channel to the given HDMI channel. 73 */ 74 HDMI_MAI_CHANNEL_MAP, 75 HDMI_MAI_CONFIG, 76 HDMI_MAI_CTL, 77 78 /* 79 * Register for DMAing in audio data to be transported over 80 * the MAI bus to the Falcon core. 81 */ 82 HDMI_MAI_DATA, 83 84 /* Format header to be placed on the MAI data. Unused. */ 85 HDMI_MAI_FMT, 86 87 /* Last received format word on the MAI bus. */ 88 HDMI_MAI_FORMAT, 89 HDMI_MAI_SMP, 90 HDMI_MAI_THR, 91 HDMI_M_CTL, 92 HDMI_RAM_PACKET_CONFIG, 93 HDMI_RAM_PACKET_START, 94 HDMI_RAM_PACKET_STATUS, 95 HDMI_RM_CONTROL, 96 HDMI_RM_FORMAT, 97 HDMI_RM_OFFSET, 98 HDMI_SCHEDULER_CONTROL, 99 HDMI_SW_RESET_CONTROL, 100 HDMI_TX_PHY_CHANNEL_SWAP, 101 HDMI_TX_PHY_CLK_DIV, 102 HDMI_TX_PHY_CTL_0, 103 HDMI_TX_PHY_CTL_1, 104 HDMI_TX_PHY_CTL_2, 105 HDMI_TX_PHY_CTL_3, 106 HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1, 107 HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2, 108 HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4, 109 HDMI_TX_PHY_PLL_CFG, 110 HDMI_TX_PHY_PLL_CTL_0, 111 HDMI_TX_PHY_PLL_CTL_1, 112 HDMI_TX_PHY_POWERDOWN_CTL, 113 HDMI_TX_PHY_RESET_CTL, 114 HDMI_TX_PHY_TMDS_CLK_WORD_SEL, 115 HDMI_VEC_INTERFACE_XBAR, 116 HDMI_VERTA0, 117 HDMI_VERTA1, 118 HDMI_VERTB0, 119 HDMI_VERTB1, 120 HDMI_VID_CTL, 121 }; 122 123 struct vc4_hdmi_register { 124 char *name; 125 enum vc4_hdmi_regs reg; 126 unsigned int offset; 127 }; 128 129 #define _VC4_REG(_base, _reg, _offset) \ 130 [_reg] = { \ 131 .name = #_reg, \ 132 .reg = _base, \ 133 .offset = _offset, \ 134 } 135 136 #define VC4_HD_REG(reg, offset) _VC4_REG(VC4_HD, reg, offset) 137 #define VC4_HDMI_REG(reg, offset) _VC4_REG(VC4_HDMI, reg, offset) 138 #define VC5_CEC_REG(reg, offset) _VC4_REG(VC5_CEC, reg, offset) 139 #define VC5_CSC_REG(reg, offset) _VC4_REG(VC5_CSC, reg, offset) 140 #define VC5_DVP_REG(reg, offset) _VC4_REG(VC5_DVP, reg, offset) 141 #define VC5_PHY_REG(reg, offset) _VC4_REG(VC5_PHY, reg, offset) 142 #define VC5_RAM_REG(reg, offset) _VC4_REG(VC5_RAM, reg, offset) 143 #define VC5_RM_REG(reg, offset) _VC4_REG(VC5_RM, reg, offset) 144 145 static const struct vc4_hdmi_register vc4_hdmi_fields[] = { 146 VC4_HD_REG(HDMI_M_CTL, 0x000c), 147 VC4_HD_REG(HDMI_MAI_CTL, 0x0014), 148 VC4_HD_REG(HDMI_MAI_THR, 0x0018), 149 VC4_HD_REG(HDMI_MAI_FMT, 0x001c), 150 VC4_HD_REG(HDMI_MAI_DATA, 0x0020), 151 VC4_HD_REG(HDMI_MAI_SMP, 0x002c), 152 VC4_HD_REG(HDMI_VID_CTL, 0x0038), 153 VC4_HD_REG(HDMI_CSC_CTL, 0x0040), 154 VC4_HD_REG(HDMI_CSC_12_11, 0x0044), 155 VC4_HD_REG(HDMI_CSC_14_13, 0x0048), 156 VC4_HD_REG(HDMI_CSC_22_21, 0x004c), 157 VC4_HD_REG(HDMI_CSC_24_23, 0x0050), 158 VC4_HD_REG(HDMI_CSC_32_31, 0x0054), 159 VC4_HD_REG(HDMI_CSC_34_33, 0x0058), 160 VC4_HD_REG(HDMI_FRAME_COUNT, 0x0068), 161 162 VC4_HDMI_REG(HDMI_CORE_REV, 0x0000), 163 VC4_HDMI_REG(HDMI_SW_RESET_CONTROL, 0x0004), 164 VC4_HDMI_REG(HDMI_HOTPLUG_INT, 0x0008), 165 VC4_HDMI_REG(HDMI_HOTPLUG, 0x000c), 166 VC4_HDMI_REG(HDMI_FIFO_CTL, 0x005c), 167 VC4_HDMI_REG(HDMI_MAI_CHANNEL_MAP, 0x0090), 168 VC4_HDMI_REG(HDMI_MAI_CONFIG, 0x0094), 169 VC4_HDMI_REG(HDMI_MAI_FORMAT, 0x0098), 170 VC4_HDMI_REG(HDMI_AUDIO_PACKET_CONFIG, 0x009c), 171 VC4_HDMI_REG(HDMI_RAM_PACKET_CONFIG, 0x00a0), 172 VC4_HDMI_REG(HDMI_RAM_PACKET_STATUS, 0x00a4), 173 VC4_HDMI_REG(HDMI_CRP_CFG, 0x00a8), 174 VC4_HDMI_REG(HDMI_CTS_0, 0x00ac), 175 VC4_HDMI_REG(HDMI_CTS_1, 0x00b0), 176 VC4_HDMI_REG(HDMI_SCHEDULER_CONTROL, 0x00c0), 177 VC4_HDMI_REG(HDMI_HORZA, 0x00c4), 178 VC4_HDMI_REG(HDMI_HORZB, 0x00c8), 179 VC4_HDMI_REG(HDMI_VERTA0, 0x00cc), 180 VC4_HDMI_REG(HDMI_VERTB0, 0x00d0), 181 VC4_HDMI_REG(HDMI_VERTA1, 0x00d4), 182 VC4_HDMI_REG(HDMI_VERTB1, 0x00d8), 183 VC4_HDMI_REG(HDMI_CEC_CNTRL_1, 0x00e8), 184 VC4_HDMI_REG(HDMI_CEC_CNTRL_2, 0x00ec), 185 VC4_HDMI_REG(HDMI_CEC_CNTRL_3, 0x00f0), 186 VC4_HDMI_REG(HDMI_CEC_CNTRL_4, 0x00f4), 187 VC4_HDMI_REG(HDMI_CEC_CNTRL_5, 0x00f8), 188 VC4_HDMI_REG(HDMI_CEC_TX_DATA_1, 0x00fc), 189 VC4_HDMI_REG(HDMI_CEC_TX_DATA_2, 0x0100), 190 VC4_HDMI_REG(HDMI_CEC_TX_DATA_3, 0x0104), 191 VC4_HDMI_REG(HDMI_CEC_TX_DATA_4, 0x0108), 192 VC4_HDMI_REG(HDMI_CEC_RX_DATA_1, 0x010c), 193 VC4_HDMI_REG(HDMI_CEC_RX_DATA_2, 0x0110), 194 VC4_HDMI_REG(HDMI_CEC_RX_DATA_3, 0x0114), 195 VC4_HDMI_REG(HDMI_CEC_RX_DATA_4, 0x0118), 196 VC4_HDMI_REG(HDMI_TX_PHY_RESET_CTL, 0x02c0), 197 VC4_HDMI_REG(HDMI_TX_PHY_CTL_0, 0x02c4), 198 VC4_HDMI_REG(HDMI_CEC_CPU_STATUS, 0x0340), 199 VC4_HDMI_REG(HDMI_CEC_CPU_CLEAR, 0x0348), 200 VC4_HDMI_REG(HDMI_CEC_CPU_MASK_STATUS, 0x034c), 201 VC4_HDMI_REG(HDMI_CEC_CPU_MASK_SET, 0x034c), 202 VC4_HDMI_REG(HDMI_CEC_CPU_MASK_CLEAR, 0x0354), 203 VC4_HDMI_REG(HDMI_RAM_PACKET_START, 0x0400), 204 }; 205 206 static const struct vc4_hdmi_register vc5_hdmi_hdmi0_fields[] = { 207 VC4_HD_REG(HDMI_DVP_CTL, 0x0000), 208 VC4_HD_REG(HDMI_MAI_CTL, 0x0010), 209 VC4_HD_REG(HDMI_MAI_THR, 0x0014), 210 VC4_HD_REG(HDMI_MAI_FMT, 0x0018), 211 VC4_HD_REG(HDMI_MAI_DATA, 0x001c), 212 VC4_HD_REG(HDMI_MAI_SMP, 0x0020), 213 VC4_HD_REG(HDMI_VID_CTL, 0x0044), 214 VC4_HD_REG(HDMI_FRAME_COUNT, 0x0060), 215 216 VC4_HDMI_REG(HDMI_FIFO_CTL, 0x074), 217 VC4_HDMI_REG(HDMI_AUDIO_PACKET_CONFIG, 0x0b8), 218 VC4_HDMI_REG(HDMI_RAM_PACKET_CONFIG, 0x0bc), 219 VC4_HDMI_REG(HDMI_RAM_PACKET_STATUS, 0x0c4), 220 VC4_HDMI_REG(HDMI_CRP_CFG, 0x0c8), 221 VC4_HDMI_REG(HDMI_CTS_0, 0x0cc), 222 VC4_HDMI_REG(HDMI_CTS_1, 0x0d0), 223 VC4_HDMI_REG(HDMI_SCHEDULER_CONTROL, 0x0e0), 224 VC4_HDMI_REG(HDMI_HORZA, 0x0e4), 225 VC4_HDMI_REG(HDMI_HORZB, 0x0e8), 226 VC4_HDMI_REG(HDMI_VERTA0, 0x0ec), 227 VC4_HDMI_REG(HDMI_VERTB0, 0x0f0), 228 VC4_HDMI_REG(HDMI_VERTA1, 0x0f4), 229 VC4_HDMI_REG(HDMI_VERTB1, 0x0f8), 230 VC4_HDMI_REG(HDMI_MAI_CHANNEL_MAP, 0x09c), 231 VC4_HDMI_REG(HDMI_MAI_CONFIG, 0x0a0), 232 VC4_HDMI_REG(HDMI_HOTPLUG, 0x1a8), 233 234 VC5_DVP_REG(HDMI_CLOCK_STOP, 0x0bc), 235 VC5_DVP_REG(HDMI_VEC_INTERFACE_XBAR, 0x0f0), 236 237 VC5_PHY_REG(HDMI_TX_PHY_RESET_CTL, 0x000), 238 VC5_PHY_REG(HDMI_TX_PHY_POWERDOWN_CTL, 0x004), 239 VC5_PHY_REG(HDMI_TX_PHY_CTL_0, 0x008), 240 VC5_PHY_REG(HDMI_TX_PHY_CTL_1, 0x00c), 241 VC5_PHY_REG(HDMI_TX_PHY_CTL_2, 0x010), 242 VC5_PHY_REG(HDMI_TX_PHY_CTL_3, 0x014), 243 VC5_PHY_REG(HDMI_TX_PHY_PLL_CTL_0, 0x01c), 244 VC5_PHY_REG(HDMI_TX_PHY_PLL_CTL_1, 0x020), 245 VC5_PHY_REG(HDMI_TX_PHY_CLK_DIV, 0x028), 246 VC5_PHY_REG(HDMI_TX_PHY_PLL_CFG, 0x034), 247 VC5_PHY_REG(HDMI_TX_PHY_TMDS_CLK_WORD_SEL, 0x044), 248 VC5_PHY_REG(HDMI_TX_PHY_CHANNEL_SWAP, 0x04c), 249 VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1, 0x050), 250 VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2, 0x054), 251 VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4, 0x05c), 252 253 VC5_RM_REG(HDMI_RM_CONTROL, 0x000), 254 VC5_RM_REG(HDMI_RM_OFFSET, 0x018), 255 VC5_RM_REG(HDMI_RM_FORMAT, 0x01c), 256 257 VC5_RAM_REG(HDMI_RAM_PACKET_START, 0x000), 258 259 VC5_CEC_REG(HDMI_CEC_CNTRL_1, 0x010), 260 VC5_CEC_REG(HDMI_CEC_CNTRL_2, 0x014), 261 VC5_CEC_REG(HDMI_CEC_CNTRL_3, 0x018), 262 VC5_CEC_REG(HDMI_CEC_CNTRL_4, 0x01c), 263 VC5_CEC_REG(HDMI_CEC_CNTRL_5, 0x020), 264 VC5_CEC_REG(HDMI_CEC_TX_DATA_1, 0x028), 265 VC5_CEC_REG(HDMI_CEC_TX_DATA_2, 0x02c), 266 VC5_CEC_REG(HDMI_CEC_TX_DATA_3, 0x030), 267 VC5_CEC_REG(HDMI_CEC_TX_DATA_4, 0x034), 268 VC5_CEC_REG(HDMI_CEC_RX_DATA_1, 0x038), 269 VC5_CEC_REG(HDMI_CEC_RX_DATA_2, 0x03c), 270 VC5_CEC_REG(HDMI_CEC_RX_DATA_3, 0x040), 271 VC5_CEC_REG(HDMI_CEC_RX_DATA_4, 0x044), 272 273 VC5_CSC_REG(HDMI_CSC_CTL, 0x000), 274 VC5_CSC_REG(HDMI_CSC_12_11, 0x004), 275 VC5_CSC_REG(HDMI_CSC_14_13, 0x008), 276 VC5_CSC_REG(HDMI_CSC_22_21, 0x00c), 277 VC5_CSC_REG(HDMI_CSC_24_23, 0x010), 278 VC5_CSC_REG(HDMI_CSC_32_31, 0x014), 279 VC5_CSC_REG(HDMI_CSC_34_33, 0x018), 280 }; 281 282 static const struct vc4_hdmi_register vc5_hdmi_hdmi1_fields[] = { 283 VC4_HD_REG(HDMI_DVP_CTL, 0x0000), 284 VC4_HD_REG(HDMI_MAI_CTL, 0x0030), 285 VC4_HD_REG(HDMI_MAI_THR, 0x0034), 286 VC4_HD_REG(HDMI_MAI_FMT, 0x0038), 287 VC4_HD_REG(HDMI_MAI_DATA, 0x003c), 288 VC4_HD_REG(HDMI_MAI_SMP, 0x0040), 289 VC4_HD_REG(HDMI_VID_CTL, 0x0048), 290 VC4_HD_REG(HDMI_FRAME_COUNT, 0x0064), 291 292 VC4_HDMI_REG(HDMI_FIFO_CTL, 0x074), 293 VC4_HDMI_REG(HDMI_AUDIO_PACKET_CONFIG, 0x0b8), 294 VC4_HDMI_REG(HDMI_RAM_PACKET_CONFIG, 0x0bc), 295 VC4_HDMI_REG(HDMI_RAM_PACKET_STATUS, 0x0c4), 296 VC4_HDMI_REG(HDMI_CRP_CFG, 0x0c8), 297 VC4_HDMI_REG(HDMI_CTS_0, 0x0cc), 298 VC4_HDMI_REG(HDMI_CTS_1, 0x0d0), 299 VC4_HDMI_REG(HDMI_SCHEDULER_CONTROL, 0x0e0), 300 VC4_HDMI_REG(HDMI_HORZA, 0x0e4), 301 VC4_HDMI_REG(HDMI_HORZB, 0x0e8), 302 VC4_HDMI_REG(HDMI_VERTA0, 0x0ec), 303 VC4_HDMI_REG(HDMI_VERTB0, 0x0f0), 304 VC4_HDMI_REG(HDMI_VERTA1, 0x0f4), 305 VC4_HDMI_REG(HDMI_VERTB1, 0x0f8), 306 VC4_HDMI_REG(HDMI_MAI_CHANNEL_MAP, 0x09c), 307 VC4_HDMI_REG(HDMI_MAI_CONFIG, 0x0a0), 308 VC4_HDMI_REG(HDMI_HOTPLUG, 0x1a8), 309 310 VC5_DVP_REG(HDMI_CLOCK_STOP, 0x0bc), 311 VC5_DVP_REG(HDMI_VEC_INTERFACE_XBAR, 0x0f0), 312 313 VC5_PHY_REG(HDMI_TX_PHY_RESET_CTL, 0x000), 314 VC5_PHY_REG(HDMI_TX_PHY_POWERDOWN_CTL, 0x004), 315 VC5_PHY_REG(HDMI_TX_PHY_CTL_0, 0x008), 316 VC5_PHY_REG(HDMI_TX_PHY_CTL_1, 0x00c), 317 VC5_PHY_REG(HDMI_TX_PHY_CTL_2, 0x010), 318 VC5_PHY_REG(HDMI_TX_PHY_CTL_3, 0x014), 319 VC5_PHY_REG(HDMI_TX_PHY_PLL_CTL_0, 0x01c), 320 VC5_PHY_REG(HDMI_TX_PHY_PLL_CTL_1, 0x020), 321 VC5_PHY_REG(HDMI_TX_PHY_CLK_DIV, 0x028), 322 VC5_PHY_REG(HDMI_TX_PHY_PLL_CFG, 0x034), 323 VC5_PHY_REG(HDMI_TX_PHY_CHANNEL_SWAP, 0x04c), 324 VC5_PHY_REG(HDMI_TX_PHY_TMDS_CLK_WORD_SEL, 0x044), 325 VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1, 0x050), 326 VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2, 0x054), 327 VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4, 0x05c), 328 329 VC5_RM_REG(HDMI_RM_CONTROL, 0x000), 330 VC5_RM_REG(HDMI_RM_OFFSET, 0x018), 331 VC5_RM_REG(HDMI_RM_FORMAT, 0x01c), 332 333 VC5_RAM_REG(HDMI_RAM_PACKET_START, 0x000), 334 335 VC5_CEC_REG(HDMI_CEC_CNTRL_1, 0x010), 336 VC5_CEC_REG(HDMI_CEC_CNTRL_2, 0x014), 337 VC5_CEC_REG(HDMI_CEC_CNTRL_3, 0x018), 338 VC5_CEC_REG(HDMI_CEC_CNTRL_4, 0x01c), 339 VC5_CEC_REG(HDMI_CEC_CNTRL_5, 0x020), 340 VC5_CEC_REG(HDMI_CEC_TX_DATA_1, 0x028), 341 VC5_CEC_REG(HDMI_CEC_TX_DATA_2, 0x02c), 342 VC5_CEC_REG(HDMI_CEC_TX_DATA_3, 0x030), 343 VC5_CEC_REG(HDMI_CEC_TX_DATA_4, 0x034), 344 VC5_CEC_REG(HDMI_CEC_RX_DATA_1, 0x038), 345 VC5_CEC_REG(HDMI_CEC_RX_DATA_2, 0x03c), 346 VC5_CEC_REG(HDMI_CEC_RX_DATA_3, 0x040), 347 VC5_CEC_REG(HDMI_CEC_RX_DATA_4, 0x044), 348 349 VC5_CSC_REG(HDMI_CSC_CTL, 0x000), 350 VC5_CSC_REG(HDMI_CSC_12_11, 0x004), 351 VC5_CSC_REG(HDMI_CSC_14_13, 0x008), 352 VC5_CSC_REG(HDMI_CSC_22_21, 0x00c), 353 VC5_CSC_REG(HDMI_CSC_24_23, 0x010), 354 VC5_CSC_REG(HDMI_CSC_32_31, 0x014), 355 VC5_CSC_REG(HDMI_CSC_34_33, 0x018), 356 }; 357 358 static inline 359 void __iomem *__vc4_hdmi_get_field_base(struct vc4_hdmi *hdmi, 360 enum vc4_hdmi_regs reg) 361 { 362 switch (reg) { 363 case VC4_HD: 364 return hdmi->hd_regs; 365 366 case VC4_HDMI: 367 return hdmi->hdmicore_regs; 368 369 case VC5_CSC: 370 return hdmi->csc_regs; 371 372 case VC5_CEC: 373 return hdmi->cec_regs; 374 375 case VC5_DVP: 376 return hdmi->dvp_regs; 377 378 case VC5_PHY: 379 return hdmi->phy_regs; 380 381 case VC5_RAM: 382 return hdmi->ram_regs; 383 384 case VC5_RM: 385 return hdmi->rm_regs; 386 387 default: 388 return NULL; 389 } 390 391 return NULL; 392 } 393 394 static inline u32 vc4_hdmi_read(struct vc4_hdmi *hdmi, 395 enum vc4_hdmi_field reg) 396 { 397 const struct vc4_hdmi_register *field; 398 const struct vc4_hdmi_variant *variant = hdmi->variant; 399 void __iomem *base; 400 401 if (reg >= variant->num_registers) { 402 dev_warn(&hdmi->pdev->dev, 403 "Invalid register ID %u\n", reg); 404 return 0; 405 } 406 407 field = &variant->registers[reg]; 408 base = __vc4_hdmi_get_field_base(hdmi, field->reg); 409 if (!base) { 410 dev_warn(&hdmi->pdev->dev, 411 "Unknown register ID %u\n", reg); 412 return 0; 413 } 414 415 return readl(base + field->offset); 416 } 417 #define HDMI_READ(reg) vc4_hdmi_read(vc4_hdmi, reg) 418 419 static inline void vc4_hdmi_write(struct vc4_hdmi *hdmi, 420 enum vc4_hdmi_field reg, 421 u32 value) 422 { 423 const struct vc4_hdmi_register *field; 424 const struct vc4_hdmi_variant *variant = hdmi->variant; 425 void __iomem *base; 426 427 if (reg >= variant->num_registers) { 428 dev_warn(&hdmi->pdev->dev, 429 "Invalid register ID %u\n", reg); 430 return; 431 } 432 433 field = &variant->registers[reg]; 434 base = __vc4_hdmi_get_field_base(hdmi, field->reg); 435 if (!base) 436 return; 437 438 writel(value, base + field->offset); 439 } 440 #define HDMI_WRITE(reg, val) vc4_hdmi_write(vc4_hdmi, reg, val) 441 442 #endif /* _VC4_HDMI_REGS_H_ */ 443