1 #ifndef _VC4_HDMI_REGS_H_ 2 #define _VC4_HDMI_REGS_H_ 3 4 #include <linux/pm_runtime.h> 5 6 #include "vc4_hdmi.h" 7 8 #define VC4_HDMI_PACKET_STRIDE 0x24 9 10 enum vc4_hdmi_regs { 11 VC4_INVALID = 0, 12 VC4_HDMI, 13 VC4_HD, 14 VC5_CEC, 15 VC5_CSC, 16 VC5_DVP, 17 VC5_PHY, 18 VC5_RAM, 19 VC5_RM, 20 }; 21 22 enum vc4_hdmi_field { 23 HDMI_AUDIO_PACKET_CONFIG, 24 HDMI_CEC_CNTRL_1, 25 HDMI_CEC_CNTRL_2, 26 HDMI_CEC_CNTRL_3, 27 HDMI_CEC_CNTRL_4, 28 HDMI_CEC_CNTRL_5, 29 HDMI_CEC_CPU_CLEAR, 30 HDMI_CEC_CPU_MASK_CLEAR, 31 HDMI_CEC_CPU_MASK_SET, 32 HDMI_CEC_CPU_MASK_STATUS, 33 HDMI_CEC_CPU_STATUS, 34 HDMI_CEC_CPU_SET, 35 36 /* 37 * Transmit data, first byte is low byte of the 32-bit reg. 38 * MSB of each byte transmitted first. 39 */ 40 HDMI_CEC_RX_DATA_1, 41 HDMI_CEC_RX_DATA_2, 42 HDMI_CEC_RX_DATA_3, 43 HDMI_CEC_RX_DATA_4, 44 HDMI_CEC_TX_DATA_1, 45 HDMI_CEC_TX_DATA_2, 46 HDMI_CEC_TX_DATA_3, 47 HDMI_CEC_TX_DATA_4, 48 HDMI_CLOCK_STOP, 49 HDMI_CORE_REV, 50 HDMI_CRP_CFG, 51 HDMI_CSC_12_11, 52 HDMI_CSC_14_13, 53 HDMI_CSC_22_21, 54 HDMI_CSC_24_23, 55 HDMI_CSC_32_31, 56 HDMI_CSC_34_33, 57 HDMI_CSC_CTL, 58 59 /* 60 * 20-bit fields containing CTS values to be transmitted if 61 * !EXTERNAL_CTS_EN 62 */ 63 HDMI_CTS_0, 64 HDMI_CTS_1, 65 HDMI_DEEP_COLOR_CONFIG_1, 66 HDMI_DVP_CTL, 67 HDMI_FIFO_CTL, 68 HDMI_FRAME_COUNT, 69 HDMI_GCP_CONFIG, 70 HDMI_GCP_WORD_1, 71 HDMI_HORZA, 72 HDMI_HORZB, 73 HDMI_HOTPLUG, 74 HDMI_HOTPLUG_INT, 75 76 /* 77 * 3 bits per field, where each field maps from that 78 * corresponding MAI bus channel to the given HDMI channel. 79 */ 80 HDMI_MAI_CHANNEL_MAP, 81 HDMI_MAI_CONFIG, 82 HDMI_MAI_CTL, 83 84 /* 85 * Register for DMAing in audio data to be transported over 86 * the MAI bus to the Falcon core. 87 */ 88 HDMI_MAI_DATA, 89 90 /* Format header to be placed on the MAI data. Unused. */ 91 HDMI_MAI_FMT, 92 93 /* Last received format word on the MAI bus. */ 94 HDMI_MAI_FORMAT, 95 HDMI_MAI_SMP, 96 HDMI_MAI_THR, 97 HDMI_M_CTL, 98 HDMI_RAM_PACKET_CONFIG, 99 HDMI_RAM_PACKET_START, 100 HDMI_RAM_PACKET_STATUS, 101 HDMI_RM_CONTROL, 102 HDMI_RM_FORMAT, 103 HDMI_RM_OFFSET, 104 HDMI_SCHEDULER_CONTROL, 105 HDMI_SCRAMBLER_CTL, 106 HDMI_SW_RESET_CONTROL, 107 HDMI_TX_PHY_CHANNEL_SWAP, 108 HDMI_TX_PHY_CLK_DIV, 109 HDMI_TX_PHY_CTL_0, 110 HDMI_TX_PHY_CTL_1, 111 HDMI_TX_PHY_CTL_2, 112 HDMI_TX_PHY_CTL_3, 113 HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1, 114 HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2, 115 HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4, 116 HDMI_TX_PHY_PLL_CFG, 117 HDMI_TX_PHY_PLL_CTL_0, 118 HDMI_TX_PHY_PLL_CTL_1, 119 HDMI_TX_PHY_POWERDOWN_CTL, 120 HDMI_TX_PHY_RESET_CTL, 121 HDMI_TX_PHY_TMDS_CLK_WORD_SEL, 122 HDMI_VEC_INTERFACE_XBAR, 123 HDMI_VERTA0, 124 HDMI_VERTA1, 125 HDMI_VERTB0, 126 HDMI_VERTB1, 127 HDMI_VID_CTL, 128 }; 129 130 struct vc4_hdmi_register { 131 char *name; 132 enum vc4_hdmi_regs reg; 133 unsigned int offset; 134 }; 135 136 #define _VC4_REG(_base, _reg, _offset) \ 137 [_reg] = { \ 138 .name = #_reg, \ 139 .reg = _base, \ 140 .offset = _offset, \ 141 } 142 143 #define VC4_HD_REG(reg, offset) _VC4_REG(VC4_HD, reg, offset) 144 #define VC4_HDMI_REG(reg, offset) _VC4_REG(VC4_HDMI, reg, offset) 145 #define VC5_CEC_REG(reg, offset) _VC4_REG(VC5_CEC, reg, offset) 146 #define VC5_CSC_REG(reg, offset) _VC4_REG(VC5_CSC, reg, offset) 147 #define VC5_DVP_REG(reg, offset) _VC4_REG(VC5_DVP, reg, offset) 148 #define VC5_PHY_REG(reg, offset) _VC4_REG(VC5_PHY, reg, offset) 149 #define VC5_RAM_REG(reg, offset) _VC4_REG(VC5_RAM, reg, offset) 150 #define VC5_RM_REG(reg, offset) _VC4_REG(VC5_RM, reg, offset) 151 152 static const struct vc4_hdmi_register __maybe_unused vc4_hdmi_fields[] = { 153 VC4_HD_REG(HDMI_M_CTL, 0x000c), 154 VC4_HD_REG(HDMI_MAI_CTL, 0x0014), 155 VC4_HD_REG(HDMI_MAI_THR, 0x0018), 156 VC4_HD_REG(HDMI_MAI_FMT, 0x001c), 157 VC4_HD_REG(HDMI_MAI_DATA, 0x0020), 158 VC4_HD_REG(HDMI_MAI_SMP, 0x002c), 159 VC4_HD_REG(HDMI_VID_CTL, 0x0038), 160 VC4_HD_REG(HDMI_CSC_CTL, 0x0040), 161 VC4_HD_REG(HDMI_CSC_12_11, 0x0044), 162 VC4_HD_REG(HDMI_CSC_14_13, 0x0048), 163 VC4_HD_REG(HDMI_CSC_22_21, 0x004c), 164 VC4_HD_REG(HDMI_CSC_24_23, 0x0050), 165 VC4_HD_REG(HDMI_CSC_32_31, 0x0054), 166 VC4_HD_REG(HDMI_CSC_34_33, 0x0058), 167 VC4_HD_REG(HDMI_FRAME_COUNT, 0x0068), 168 169 VC4_HDMI_REG(HDMI_CORE_REV, 0x0000), 170 VC4_HDMI_REG(HDMI_SW_RESET_CONTROL, 0x0004), 171 VC4_HDMI_REG(HDMI_HOTPLUG_INT, 0x0008), 172 VC4_HDMI_REG(HDMI_HOTPLUG, 0x000c), 173 VC4_HDMI_REG(HDMI_FIFO_CTL, 0x005c), 174 VC4_HDMI_REG(HDMI_MAI_CHANNEL_MAP, 0x0090), 175 VC4_HDMI_REG(HDMI_MAI_CONFIG, 0x0094), 176 VC4_HDMI_REG(HDMI_MAI_FORMAT, 0x0098), 177 VC4_HDMI_REG(HDMI_AUDIO_PACKET_CONFIG, 0x009c), 178 VC4_HDMI_REG(HDMI_RAM_PACKET_CONFIG, 0x00a0), 179 VC4_HDMI_REG(HDMI_RAM_PACKET_STATUS, 0x00a4), 180 VC4_HDMI_REG(HDMI_CRP_CFG, 0x00a8), 181 VC4_HDMI_REG(HDMI_CTS_0, 0x00ac), 182 VC4_HDMI_REG(HDMI_CTS_1, 0x00b0), 183 VC4_HDMI_REG(HDMI_SCHEDULER_CONTROL, 0x00c0), 184 VC4_HDMI_REG(HDMI_HORZA, 0x00c4), 185 VC4_HDMI_REG(HDMI_HORZB, 0x00c8), 186 VC4_HDMI_REG(HDMI_VERTA0, 0x00cc), 187 VC4_HDMI_REG(HDMI_VERTB0, 0x00d0), 188 VC4_HDMI_REG(HDMI_VERTA1, 0x00d4), 189 VC4_HDMI_REG(HDMI_VERTB1, 0x00d8), 190 VC4_HDMI_REG(HDMI_CEC_CNTRL_1, 0x00e8), 191 VC4_HDMI_REG(HDMI_CEC_CNTRL_2, 0x00ec), 192 VC4_HDMI_REG(HDMI_CEC_CNTRL_3, 0x00f0), 193 VC4_HDMI_REG(HDMI_CEC_CNTRL_4, 0x00f4), 194 VC4_HDMI_REG(HDMI_CEC_CNTRL_5, 0x00f8), 195 VC4_HDMI_REG(HDMI_CEC_TX_DATA_1, 0x00fc), 196 VC4_HDMI_REG(HDMI_CEC_TX_DATA_2, 0x0100), 197 VC4_HDMI_REG(HDMI_CEC_TX_DATA_3, 0x0104), 198 VC4_HDMI_REG(HDMI_CEC_TX_DATA_4, 0x0108), 199 VC4_HDMI_REG(HDMI_CEC_RX_DATA_1, 0x010c), 200 VC4_HDMI_REG(HDMI_CEC_RX_DATA_2, 0x0110), 201 VC4_HDMI_REG(HDMI_CEC_RX_DATA_3, 0x0114), 202 VC4_HDMI_REG(HDMI_CEC_RX_DATA_4, 0x0118), 203 VC4_HDMI_REG(HDMI_TX_PHY_RESET_CTL, 0x02c0), 204 VC4_HDMI_REG(HDMI_TX_PHY_CTL_0, 0x02c4), 205 VC4_HDMI_REG(HDMI_CEC_CPU_STATUS, 0x0340), 206 VC4_HDMI_REG(HDMI_CEC_CPU_SET, 0x0344), 207 VC4_HDMI_REG(HDMI_CEC_CPU_CLEAR, 0x0348), 208 VC4_HDMI_REG(HDMI_CEC_CPU_MASK_STATUS, 0x034c), 209 VC4_HDMI_REG(HDMI_CEC_CPU_MASK_SET, 0x0350), 210 VC4_HDMI_REG(HDMI_CEC_CPU_MASK_CLEAR, 0x0354), 211 VC4_HDMI_REG(HDMI_RAM_PACKET_START, 0x0400), 212 }; 213 214 static const struct vc4_hdmi_register __maybe_unused vc5_hdmi_hdmi0_fields[] = { 215 VC4_HD_REG(HDMI_DVP_CTL, 0x0000), 216 VC4_HD_REG(HDMI_MAI_CTL, 0x0010), 217 VC4_HD_REG(HDMI_MAI_THR, 0x0014), 218 VC4_HD_REG(HDMI_MAI_FMT, 0x0018), 219 VC4_HD_REG(HDMI_MAI_DATA, 0x001c), 220 VC4_HD_REG(HDMI_MAI_SMP, 0x0020), 221 VC4_HD_REG(HDMI_VID_CTL, 0x0044), 222 VC4_HD_REG(HDMI_FRAME_COUNT, 0x0060), 223 224 VC4_HDMI_REG(HDMI_FIFO_CTL, 0x074), 225 VC4_HDMI_REG(HDMI_AUDIO_PACKET_CONFIG, 0x0b8), 226 VC4_HDMI_REG(HDMI_RAM_PACKET_CONFIG, 0x0bc), 227 VC4_HDMI_REG(HDMI_RAM_PACKET_STATUS, 0x0c4), 228 VC4_HDMI_REG(HDMI_CRP_CFG, 0x0c8), 229 VC4_HDMI_REG(HDMI_CTS_0, 0x0cc), 230 VC4_HDMI_REG(HDMI_CTS_1, 0x0d0), 231 VC4_HDMI_REG(HDMI_SCHEDULER_CONTROL, 0x0e0), 232 VC4_HDMI_REG(HDMI_HORZA, 0x0e4), 233 VC4_HDMI_REG(HDMI_HORZB, 0x0e8), 234 VC4_HDMI_REG(HDMI_VERTA0, 0x0ec), 235 VC4_HDMI_REG(HDMI_VERTB0, 0x0f0), 236 VC4_HDMI_REG(HDMI_VERTA1, 0x0f4), 237 VC4_HDMI_REG(HDMI_VERTB1, 0x0f8), 238 VC4_HDMI_REG(HDMI_MAI_CHANNEL_MAP, 0x09c), 239 VC4_HDMI_REG(HDMI_MAI_CONFIG, 0x0a0), 240 VC4_HDMI_REG(HDMI_DEEP_COLOR_CONFIG_1, 0x170), 241 VC4_HDMI_REG(HDMI_GCP_CONFIG, 0x178), 242 VC4_HDMI_REG(HDMI_GCP_WORD_1, 0x17c), 243 VC4_HDMI_REG(HDMI_HOTPLUG, 0x1a8), 244 VC4_HDMI_REG(HDMI_SCRAMBLER_CTL, 0x1c4), 245 246 VC5_DVP_REG(HDMI_CLOCK_STOP, 0x0bc), 247 VC5_DVP_REG(HDMI_VEC_INTERFACE_XBAR, 0x0f0), 248 249 VC5_PHY_REG(HDMI_TX_PHY_RESET_CTL, 0x000), 250 VC5_PHY_REG(HDMI_TX_PHY_POWERDOWN_CTL, 0x004), 251 VC5_PHY_REG(HDMI_TX_PHY_CTL_0, 0x008), 252 VC5_PHY_REG(HDMI_TX_PHY_CTL_1, 0x00c), 253 VC5_PHY_REG(HDMI_TX_PHY_CTL_2, 0x010), 254 VC5_PHY_REG(HDMI_TX_PHY_CTL_3, 0x014), 255 VC5_PHY_REG(HDMI_TX_PHY_PLL_CTL_0, 0x01c), 256 VC5_PHY_REG(HDMI_TX_PHY_PLL_CTL_1, 0x020), 257 VC5_PHY_REG(HDMI_TX_PHY_CLK_DIV, 0x028), 258 VC5_PHY_REG(HDMI_TX_PHY_PLL_CFG, 0x034), 259 VC5_PHY_REG(HDMI_TX_PHY_TMDS_CLK_WORD_SEL, 0x044), 260 VC5_PHY_REG(HDMI_TX_PHY_CHANNEL_SWAP, 0x04c), 261 VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1, 0x050), 262 VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2, 0x054), 263 VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4, 0x05c), 264 265 VC5_RM_REG(HDMI_RM_CONTROL, 0x000), 266 VC5_RM_REG(HDMI_RM_OFFSET, 0x018), 267 VC5_RM_REG(HDMI_RM_FORMAT, 0x01c), 268 269 VC5_RAM_REG(HDMI_RAM_PACKET_START, 0x000), 270 271 VC5_CEC_REG(HDMI_CEC_CNTRL_1, 0x010), 272 VC5_CEC_REG(HDMI_CEC_CNTRL_2, 0x014), 273 VC5_CEC_REG(HDMI_CEC_CNTRL_3, 0x018), 274 VC5_CEC_REG(HDMI_CEC_CNTRL_4, 0x01c), 275 VC5_CEC_REG(HDMI_CEC_CNTRL_5, 0x020), 276 VC5_CEC_REG(HDMI_CEC_TX_DATA_1, 0x028), 277 VC5_CEC_REG(HDMI_CEC_TX_DATA_2, 0x02c), 278 VC5_CEC_REG(HDMI_CEC_TX_DATA_3, 0x030), 279 VC5_CEC_REG(HDMI_CEC_TX_DATA_4, 0x034), 280 VC5_CEC_REG(HDMI_CEC_RX_DATA_1, 0x038), 281 VC5_CEC_REG(HDMI_CEC_RX_DATA_2, 0x03c), 282 VC5_CEC_REG(HDMI_CEC_RX_DATA_3, 0x040), 283 VC5_CEC_REG(HDMI_CEC_RX_DATA_4, 0x044), 284 285 VC5_CSC_REG(HDMI_CSC_CTL, 0x000), 286 VC5_CSC_REG(HDMI_CSC_12_11, 0x004), 287 VC5_CSC_REG(HDMI_CSC_14_13, 0x008), 288 VC5_CSC_REG(HDMI_CSC_22_21, 0x00c), 289 VC5_CSC_REG(HDMI_CSC_24_23, 0x010), 290 VC5_CSC_REG(HDMI_CSC_32_31, 0x014), 291 VC5_CSC_REG(HDMI_CSC_34_33, 0x018), 292 }; 293 294 static const struct vc4_hdmi_register __maybe_unused vc5_hdmi_hdmi1_fields[] = { 295 VC4_HD_REG(HDMI_DVP_CTL, 0x0000), 296 VC4_HD_REG(HDMI_MAI_CTL, 0x0030), 297 VC4_HD_REG(HDMI_MAI_THR, 0x0034), 298 VC4_HD_REG(HDMI_MAI_FMT, 0x0038), 299 VC4_HD_REG(HDMI_MAI_DATA, 0x003c), 300 VC4_HD_REG(HDMI_MAI_SMP, 0x0040), 301 VC4_HD_REG(HDMI_VID_CTL, 0x0048), 302 VC4_HD_REG(HDMI_FRAME_COUNT, 0x0064), 303 304 VC4_HDMI_REG(HDMI_FIFO_CTL, 0x074), 305 VC4_HDMI_REG(HDMI_AUDIO_PACKET_CONFIG, 0x0b8), 306 VC4_HDMI_REG(HDMI_RAM_PACKET_CONFIG, 0x0bc), 307 VC4_HDMI_REG(HDMI_RAM_PACKET_STATUS, 0x0c4), 308 VC4_HDMI_REG(HDMI_CRP_CFG, 0x0c8), 309 VC4_HDMI_REG(HDMI_CTS_0, 0x0cc), 310 VC4_HDMI_REG(HDMI_CTS_1, 0x0d0), 311 VC4_HDMI_REG(HDMI_SCHEDULER_CONTROL, 0x0e0), 312 VC4_HDMI_REG(HDMI_HORZA, 0x0e4), 313 VC4_HDMI_REG(HDMI_HORZB, 0x0e8), 314 VC4_HDMI_REG(HDMI_VERTA0, 0x0ec), 315 VC4_HDMI_REG(HDMI_VERTB0, 0x0f0), 316 VC4_HDMI_REG(HDMI_VERTA1, 0x0f4), 317 VC4_HDMI_REG(HDMI_VERTB1, 0x0f8), 318 VC4_HDMI_REG(HDMI_MAI_CHANNEL_MAP, 0x09c), 319 VC4_HDMI_REG(HDMI_MAI_CONFIG, 0x0a0), 320 VC4_HDMI_REG(HDMI_DEEP_COLOR_CONFIG_1, 0x170), 321 VC4_HDMI_REG(HDMI_GCP_CONFIG, 0x178), 322 VC4_HDMI_REG(HDMI_GCP_WORD_1, 0x17c), 323 VC4_HDMI_REG(HDMI_HOTPLUG, 0x1a8), 324 VC4_HDMI_REG(HDMI_SCRAMBLER_CTL, 0x1c4), 325 326 VC5_DVP_REG(HDMI_CLOCK_STOP, 0x0bc), 327 VC5_DVP_REG(HDMI_VEC_INTERFACE_XBAR, 0x0f0), 328 329 VC5_PHY_REG(HDMI_TX_PHY_RESET_CTL, 0x000), 330 VC5_PHY_REG(HDMI_TX_PHY_POWERDOWN_CTL, 0x004), 331 VC5_PHY_REG(HDMI_TX_PHY_CTL_0, 0x008), 332 VC5_PHY_REG(HDMI_TX_PHY_CTL_1, 0x00c), 333 VC5_PHY_REG(HDMI_TX_PHY_CTL_2, 0x010), 334 VC5_PHY_REG(HDMI_TX_PHY_CTL_3, 0x014), 335 VC5_PHY_REG(HDMI_TX_PHY_PLL_CTL_0, 0x01c), 336 VC5_PHY_REG(HDMI_TX_PHY_PLL_CTL_1, 0x020), 337 VC5_PHY_REG(HDMI_TX_PHY_CLK_DIV, 0x028), 338 VC5_PHY_REG(HDMI_TX_PHY_PLL_CFG, 0x034), 339 VC5_PHY_REG(HDMI_TX_PHY_CHANNEL_SWAP, 0x04c), 340 VC5_PHY_REG(HDMI_TX_PHY_TMDS_CLK_WORD_SEL, 0x044), 341 VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1, 0x050), 342 VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2, 0x054), 343 VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4, 0x05c), 344 345 VC5_RM_REG(HDMI_RM_CONTROL, 0x000), 346 VC5_RM_REG(HDMI_RM_OFFSET, 0x018), 347 VC5_RM_REG(HDMI_RM_FORMAT, 0x01c), 348 349 VC5_RAM_REG(HDMI_RAM_PACKET_START, 0x000), 350 351 VC5_CEC_REG(HDMI_CEC_CNTRL_1, 0x010), 352 VC5_CEC_REG(HDMI_CEC_CNTRL_2, 0x014), 353 VC5_CEC_REG(HDMI_CEC_CNTRL_3, 0x018), 354 VC5_CEC_REG(HDMI_CEC_CNTRL_4, 0x01c), 355 VC5_CEC_REG(HDMI_CEC_CNTRL_5, 0x020), 356 VC5_CEC_REG(HDMI_CEC_TX_DATA_1, 0x028), 357 VC5_CEC_REG(HDMI_CEC_TX_DATA_2, 0x02c), 358 VC5_CEC_REG(HDMI_CEC_TX_DATA_3, 0x030), 359 VC5_CEC_REG(HDMI_CEC_TX_DATA_4, 0x034), 360 VC5_CEC_REG(HDMI_CEC_RX_DATA_1, 0x038), 361 VC5_CEC_REG(HDMI_CEC_RX_DATA_2, 0x03c), 362 VC5_CEC_REG(HDMI_CEC_RX_DATA_3, 0x040), 363 VC5_CEC_REG(HDMI_CEC_RX_DATA_4, 0x044), 364 365 VC5_CSC_REG(HDMI_CSC_CTL, 0x000), 366 VC5_CSC_REG(HDMI_CSC_12_11, 0x004), 367 VC5_CSC_REG(HDMI_CSC_14_13, 0x008), 368 VC5_CSC_REG(HDMI_CSC_22_21, 0x00c), 369 VC5_CSC_REG(HDMI_CSC_24_23, 0x010), 370 VC5_CSC_REG(HDMI_CSC_32_31, 0x014), 371 VC5_CSC_REG(HDMI_CSC_34_33, 0x018), 372 }; 373 374 static inline 375 void __iomem *__vc4_hdmi_get_field_base(struct vc4_hdmi *hdmi, 376 enum vc4_hdmi_regs reg) 377 { 378 switch (reg) { 379 case VC4_HD: 380 return hdmi->hd_regs; 381 382 case VC4_HDMI: 383 return hdmi->hdmicore_regs; 384 385 case VC5_CSC: 386 return hdmi->csc_regs; 387 388 case VC5_CEC: 389 return hdmi->cec_regs; 390 391 case VC5_DVP: 392 return hdmi->dvp_regs; 393 394 case VC5_PHY: 395 return hdmi->phy_regs; 396 397 case VC5_RAM: 398 return hdmi->ram_regs; 399 400 case VC5_RM: 401 return hdmi->rm_regs; 402 403 default: 404 return NULL; 405 } 406 407 return NULL; 408 } 409 410 static inline u32 vc4_hdmi_read(struct vc4_hdmi *hdmi, 411 enum vc4_hdmi_field reg) 412 { 413 const struct vc4_hdmi_register *field; 414 const struct vc4_hdmi_variant *variant = hdmi->variant; 415 void __iomem *base; 416 417 WARN_ON(!pm_runtime_active(&hdmi->pdev->dev)); 418 419 if (reg >= variant->num_registers) { 420 dev_warn(&hdmi->pdev->dev, 421 "Invalid register ID %u\n", reg); 422 return 0; 423 } 424 425 field = &variant->registers[reg]; 426 base = __vc4_hdmi_get_field_base(hdmi, field->reg); 427 if (!base) { 428 dev_warn(&hdmi->pdev->dev, 429 "Unknown register ID %u\n", reg); 430 return 0; 431 } 432 433 return readl(base + field->offset); 434 } 435 #define HDMI_READ(reg) vc4_hdmi_read(vc4_hdmi, reg) 436 437 static inline void vc4_hdmi_write(struct vc4_hdmi *hdmi, 438 enum vc4_hdmi_field reg, 439 u32 value) 440 { 441 const struct vc4_hdmi_register *field; 442 const struct vc4_hdmi_variant *variant = hdmi->variant; 443 void __iomem *base; 444 445 lockdep_assert_held(&hdmi->hw_lock); 446 447 WARN_ON(!pm_runtime_active(&hdmi->pdev->dev)); 448 449 if (reg >= variant->num_registers) { 450 dev_warn(&hdmi->pdev->dev, 451 "Invalid register ID %u\n", reg); 452 return; 453 } 454 455 field = &variant->registers[reg]; 456 base = __vc4_hdmi_get_field_base(hdmi, field->reg); 457 if (!base) 458 return; 459 460 writel(value, base + field->offset); 461 } 462 #define HDMI_WRITE(reg, val) vc4_hdmi_write(vc4_hdmi, reg, val) 463 464 #endif /* _VC4_HDMI_REGS_H_ */ 465