1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 Broadcom 4 * Copyright (c) 2014 The Linux Foundation. All rights reserved. 5 * Copyright (C) 2013 Red Hat 6 * Author: Rob Clark <robdclark@gmail.com> 7 */ 8 9 /** 10 * DOC: VC4 Falcon HDMI module 11 * 12 * The HDMI core has a state machine and a PHY. On BCM2835, most of 13 * the unit operates off of the HSM clock from CPRMAN. It also 14 * internally uses the PLLH_PIX clock for the PHY. 15 * 16 * HDMI infoframes are kept within a small packet ram, where each 17 * packet can be individually enabled for including in a frame. 18 * 19 * HDMI audio is implemented entirely within the HDMI IP block. A 20 * register in the HDMI encoder takes SPDIF frames from the DMA engine 21 * and transfers them over an internal MAI (multi-channel audio 22 * interconnect) bus to the encoder side for insertion into the video 23 * blank regions. 24 * 25 * The driver's HDMI encoder does not yet support power management. 26 * The HDMI encoder's power domain and the HSM/pixel clocks are kept 27 * continuously running, and only the HDMI logic and packet ram are 28 * powered off/on at disable/enable time. 29 * 30 * The driver does not yet support CEC control, though the HDMI 31 * encoder block has CEC support. 32 */ 33 34 #include <drm/drm_atomic_helper.h> 35 #include <drm/drm_edid.h> 36 #include <drm/drm_probe_helper.h> 37 #include <drm/drm_simple_kms_helper.h> 38 #include <drm/drm_scdc_helper.h> 39 #include <linux/clk.h> 40 #include <linux/component.h> 41 #include <linux/i2c.h> 42 #include <linux/of_address.h> 43 #include <linux/of_gpio.h> 44 #include <linux/of_platform.h> 45 #include <linux/pm_runtime.h> 46 #include <linux/rational.h> 47 #include <linux/reset.h> 48 #include <sound/dmaengine_pcm.h> 49 #include <sound/hdmi-codec.h> 50 #include <sound/pcm_drm_eld.h> 51 #include <sound/pcm_params.h> 52 #include <sound/soc.h> 53 #include "media/cec.h" 54 #include "vc4_drv.h" 55 #include "vc4_hdmi.h" 56 #include "vc4_hdmi_regs.h" 57 #include "vc4_regs.h" 58 59 #define VC5_HDMI_HORZA_HFP_SHIFT 16 60 #define VC5_HDMI_HORZA_HFP_MASK VC4_MASK(28, 16) 61 #define VC5_HDMI_HORZA_VPOS BIT(15) 62 #define VC5_HDMI_HORZA_HPOS BIT(14) 63 #define VC5_HDMI_HORZA_HAP_SHIFT 0 64 #define VC5_HDMI_HORZA_HAP_MASK VC4_MASK(13, 0) 65 66 #define VC5_HDMI_HORZB_HBP_SHIFT 16 67 #define VC5_HDMI_HORZB_HBP_MASK VC4_MASK(26, 16) 68 #define VC5_HDMI_HORZB_HSP_SHIFT 0 69 #define VC5_HDMI_HORZB_HSP_MASK VC4_MASK(10, 0) 70 71 #define VC5_HDMI_VERTA_VSP_SHIFT 24 72 #define VC5_HDMI_VERTA_VSP_MASK VC4_MASK(28, 24) 73 #define VC5_HDMI_VERTA_VFP_SHIFT 16 74 #define VC5_HDMI_VERTA_VFP_MASK VC4_MASK(22, 16) 75 #define VC5_HDMI_VERTA_VAL_SHIFT 0 76 #define VC5_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0) 77 78 #define VC5_HDMI_VERTB_VSPO_SHIFT 16 79 #define VC5_HDMI_VERTB_VSPO_MASK VC4_MASK(29, 16) 80 81 #define VC5_HDMI_SCRAMBLER_CTL_ENABLE BIT(0) 82 83 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT 8 84 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK VC4_MASK(10, 8) 85 86 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT 0 87 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK VC4_MASK(3, 0) 88 89 #define VC5_HDMI_GCP_CONFIG_GCP_ENABLE BIT(31) 90 91 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT 8 92 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK VC4_MASK(15, 8) 93 94 # define VC4_HD_M_SW_RST BIT(2) 95 # define VC4_HD_M_ENABLE BIT(0) 96 97 #define HSM_MIN_CLOCK_FREQ 120000000 98 #define CEC_CLOCK_FREQ 40000 99 100 #define HDMI_14_MAX_TMDS_CLK (340 * 1000 * 1000) 101 102 static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode) 103 { 104 return (mode->clock * 1000) > HDMI_14_MAX_TMDS_CLK; 105 } 106 107 static bool vc4_hdmi_is_full_range_rgb(struct vc4_hdmi *vc4_hdmi, 108 const struct drm_display_mode *mode) 109 { 110 struct vc4_hdmi_encoder *vc4_encoder = &vc4_hdmi->encoder; 111 112 return !vc4_encoder->hdmi_monitor || 113 drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_FULL; 114 } 115 116 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused) 117 { 118 struct drm_info_node *node = (struct drm_info_node *)m->private; 119 struct vc4_hdmi *vc4_hdmi = node->info_ent->data; 120 struct drm_printer p = drm_seq_file_printer(m); 121 122 drm_print_regset32(&p, &vc4_hdmi->hdmi_regset); 123 drm_print_regset32(&p, &vc4_hdmi->hd_regset); 124 125 return 0; 126 } 127 128 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi) 129 { 130 unsigned long flags; 131 132 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 133 134 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST); 135 udelay(1); 136 HDMI_WRITE(HDMI_M_CTL, 0); 137 138 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE); 139 140 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 141 VC4_HDMI_SW_RESET_HDMI | 142 VC4_HDMI_SW_RESET_FORMAT_DETECT); 143 144 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0); 145 146 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 147 } 148 149 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi) 150 { 151 unsigned long flags; 152 153 reset_control_reset(vc4_hdmi->reset); 154 155 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 156 157 HDMI_WRITE(HDMI_DVP_CTL, 0); 158 159 HDMI_WRITE(HDMI_CLOCK_STOP, 160 HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL); 161 162 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 163 } 164 165 #ifdef CONFIG_DRM_VC4_HDMI_CEC 166 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) 167 { 168 unsigned long cec_rate = clk_get_rate(vc4_hdmi->cec_clock); 169 unsigned long flags; 170 u16 clk_cnt; 171 u32 value; 172 173 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 174 175 value = HDMI_READ(HDMI_CEC_CNTRL_1); 176 value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK; 177 178 /* 179 * Set the clock divider: the hsm_clock rate and this divider 180 * setting will give a 40 kHz CEC clock. 181 */ 182 clk_cnt = cec_rate / CEC_CLOCK_FREQ; 183 value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT; 184 HDMI_WRITE(HDMI_CEC_CNTRL_1, value); 185 186 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 187 } 188 #else 189 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {} 190 #endif 191 192 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder); 193 194 static enum drm_connector_status 195 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force) 196 { 197 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 198 bool connected = false; 199 200 mutex_lock(&vc4_hdmi->mutex); 201 202 WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev)); 203 204 if (vc4_hdmi->hpd_gpio) { 205 if (gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio)) 206 connected = true; 207 } else { 208 unsigned long flags; 209 u32 hotplug; 210 211 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 212 hotplug = HDMI_READ(HDMI_HOTPLUG); 213 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 214 215 if (hotplug & VC4_HDMI_HOTPLUG_CONNECTED) 216 connected = true; 217 } 218 219 if (connected) { 220 if (connector->status != connector_status_connected) { 221 struct edid *edid = drm_get_edid(connector, vc4_hdmi->ddc); 222 223 if (edid) { 224 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid); 225 vc4_hdmi->encoder.hdmi_monitor = drm_detect_hdmi_monitor(edid); 226 kfree(edid); 227 } 228 } 229 230 vc4_hdmi_enable_scrambling(&vc4_hdmi->encoder.base.base); 231 pm_runtime_put(&vc4_hdmi->pdev->dev); 232 mutex_unlock(&vc4_hdmi->mutex); 233 return connector_status_connected; 234 } 235 236 cec_phys_addr_invalidate(vc4_hdmi->cec_adap); 237 pm_runtime_put(&vc4_hdmi->pdev->dev); 238 mutex_unlock(&vc4_hdmi->mutex); 239 return connector_status_disconnected; 240 } 241 242 static void vc4_hdmi_connector_destroy(struct drm_connector *connector) 243 { 244 drm_connector_unregister(connector); 245 drm_connector_cleanup(connector); 246 } 247 248 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector) 249 { 250 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 251 struct vc4_hdmi_encoder *vc4_encoder = &vc4_hdmi->encoder; 252 int ret = 0; 253 struct edid *edid; 254 255 mutex_lock(&vc4_hdmi->mutex); 256 257 edid = drm_get_edid(connector, vc4_hdmi->ddc); 258 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid); 259 if (!edid) { 260 ret = -ENODEV; 261 goto out; 262 } 263 264 vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid); 265 266 drm_connector_update_edid_property(connector, edid); 267 ret = drm_add_edid_modes(connector, edid); 268 kfree(edid); 269 270 if (vc4_hdmi->disable_4kp60) { 271 struct drm_device *drm = connector->dev; 272 struct drm_display_mode *mode; 273 274 list_for_each_entry(mode, &connector->probed_modes, head) { 275 if (vc4_hdmi_mode_needs_scrambling(mode)) { 276 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz."); 277 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60."); 278 } 279 } 280 } 281 282 out: 283 mutex_unlock(&vc4_hdmi->mutex); 284 285 return ret; 286 } 287 288 static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector, 289 struct drm_atomic_state *state) 290 { 291 struct drm_connector_state *old_state = 292 drm_atomic_get_old_connector_state(state, connector); 293 struct drm_connector_state *new_state = 294 drm_atomic_get_new_connector_state(state, connector); 295 struct drm_crtc *crtc = new_state->crtc; 296 297 if (!crtc) 298 return 0; 299 300 if (old_state->colorspace != new_state->colorspace || 301 !drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) { 302 struct drm_crtc_state *crtc_state; 303 304 crtc_state = drm_atomic_get_crtc_state(state, crtc); 305 if (IS_ERR(crtc_state)) 306 return PTR_ERR(crtc_state); 307 308 crtc_state->mode_changed = true; 309 } 310 311 return 0; 312 } 313 314 static void vc4_hdmi_connector_reset(struct drm_connector *connector) 315 { 316 struct vc4_hdmi_connector_state *old_state = 317 conn_state_to_vc4_hdmi_conn_state(connector->state); 318 struct vc4_hdmi_connector_state *new_state = 319 kzalloc(sizeof(*new_state), GFP_KERNEL); 320 321 if (connector->state) 322 __drm_atomic_helper_connector_destroy_state(connector->state); 323 324 kfree(old_state); 325 __drm_atomic_helper_connector_reset(connector, &new_state->base); 326 327 if (!new_state) 328 return; 329 330 new_state->base.max_bpc = 8; 331 new_state->base.max_requested_bpc = 8; 332 drm_atomic_helper_connector_tv_reset(connector); 333 } 334 335 static struct drm_connector_state * 336 vc4_hdmi_connector_duplicate_state(struct drm_connector *connector) 337 { 338 struct drm_connector_state *conn_state = connector->state; 339 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state); 340 struct vc4_hdmi_connector_state *new_state; 341 342 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL); 343 if (!new_state) 344 return NULL; 345 346 new_state->pixel_rate = vc4_state->pixel_rate; 347 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base); 348 349 return &new_state->base; 350 } 351 352 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = { 353 .detect = vc4_hdmi_connector_detect, 354 .fill_modes = drm_helper_probe_single_connector_modes, 355 .destroy = vc4_hdmi_connector_destroy, 356 .reset = vc4_hdmi_connector_reset, 357 .atomic_duplicate_state = vc4_hdmi_connector_duplicate_state, 358 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 359 }; 360 361 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = { 362 .get_modes = vc4_hdmi_connector_get_modes, 363 .atomic_check = vc4_hdmi_connector_atomic_check, 364 }; 365 366 static int vc4_hdmi_connector_init(struct drm_device *dev, 367 struct vc4_hdmi *vc4_hdmi) 368 { 369 struct drm_connector *connector = &vc4_hdmi->connector; 370 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base; 371 int ret; 372 373 drm_connector_init_with_ddc(dev, connector, 374 &vc4_hdmi_connector_funcs, 375 DRM_MODE_CONNECTOR_HDMIA, 376 vc4_hdmi->ddc); 377 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs); 378 379 /* 380 * Some of the properties below require access to state, like bpc. 381 * Allocate some default initial connector state with our reset helper. 382 */ 383 if (connector->funcs->reset) 384 connector->funcs->reset(connector); 385 386 /* Create and attach TV margin props to this connector. */ 387 ret = drm_mode_create_tv_margin_properties(dev); 388 if (ret) 389 return ret; 390 391 ret = drm_mode_create_hdmi_colorspace_property(connector); 392 if (ret) 393 return ret; 394 395 drm_connector_attach_colorspace_property(connector); 396 drm_connector_attach_tv_margin_properties(connector); 397 drm_connector_attach_max_bpc_property(connector, 8, 12); 398 399 connector->polled = (DRM_CONNECTOR_POLL_CONNECT | 400 DRM_CONNECTOR_POLL_DISCONNECT); 401 402 connector->interlace_allowed = 1; 403 connector->doublescan_allowed = 0; 404 405 if (vc4_hdmi->variant->supports_hdr) 406 drm_connector_attach_hdr_output_metadata_property(connector); 407 408 drm_connector_attach_encoder(connector, encoder); 409 410 return 0; 411 } 412 413 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder, 414 enum hdmi_infoframe_type type, 415 bool poll) 416 { 417 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 418 u32 packet_id = type - 0x80; 419 unsigned long flags; 420 421 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 422 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 423 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id)); 424 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 425 426 if (!poll) 427 return 0; 428 429 return wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) & 430 BIT(packet_id)), 100); 431 } 432 433 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder, 434 union hdmi_infoframe *frame) 435 { 436 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 437 u32 packet_id = frame->any.type - 0x80; 438 const struct vc4_hdmi_register *ram_packet_start = 439 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START]; 440 u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id; 441 void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi, 442 ram_packet_start->reg); 443 uint8_t buffer[VC4_HDMI_PACKET_STRIDE]; 444 unsigned long flags; 445 ssize_t len, i; 446 int ret; 447 448 WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) & 449 VC4_HDMI_RAM_PACKET_ENABLE), 450 "Packet RAM has to be on to store the packet."); 451 452 len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer)); 453 if (len < 0) 454 return; 455 456 ret = vc4_hdmi_stop_packet(encoder, frame->any.type, true); 457 if (ret) { 458 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret); 459 return; 460 } 461 462 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 463 464 for (i = 0; i < len; i += 7) { 465 writel(buffer[i + 0] << 0 | 466 buffer[i + 1] << 8 | 467 buffer[i + 2] << 16, 468 base + packet_reg); 469 packet_reg += 4; 470 471 writel(buffer[i + 3] << 0 | 472 buffer[i + 4] << 8 | 473 buffer[i + 5] << 16 | 474 buffer[i + 6] << 24, 475 base + packet_reg); 476 packet_reg += 4; 477 } 478 479 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 480 HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id)); 481 482 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 483 484 ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) & 485 BIT(packet_id)), 100); 486 if (ret) 487 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret); 488 } 489 490 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder) 491 { 492 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 493 struct drm_connector *connector = &vc4_hdmi->connector; 494 struct drm_connector_state *cstate = connector->state; 495 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 496 union hdmi_infoframe frame; 497 int ret; 498 499 lockdep_assert_held(&vc4_hdmi->mutex); 500 501 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, 502 connector, mode); 503 if (ret < 0) { 504 DRM_ERROR("couldn't fill AVI infoframe\n"); 505 return; 506 } 507 508 drm_hdmi_avi_infoframe_quant_range(&frame.avi, 509 connector, mode, 510 vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode) ? 511 HDMI_QUANTIZATION_RANGE_FULL : 512 HDMI_QUANTIZATION_RANGE_LIMITED); 513 drm_hdmi_avi_infoframe_colorimetry(&frame.avi, cstate); 514 drm_hdmi_avi_infoframe_bars(&frame.avi, cstate); 515 516 vc4_hdmi_write_infoframe(encoder, &frame); 517 } 518 519 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder) 520 { 521 union hdmi_infoframe frame; 522 int ret; 523 524 ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore"); 525 if (ret < 0) { 526 DRM_ERROR("couldn't fill SPD infoframe\n"); 527 return; 528 } 529 530 frame.spd.sdi = HDMI_SPD_SDI_PC; 531 532 vc4_hdmi_write_infoframe(encoder, &frame); 533 } 534 535 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder) 536 { 537 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 538 struct hdmi_audio_infoframe *audio = &vc4_hdmi->audio.infoframe; 539 union hdmi_infoframe frame; 540 541 memcpy(&frame.audio, audio, sizeof(*audio)); 542 vc4_hdmi_write_infoframe(encoder, &frame); 543 } 544 545 static void vc4_hdmi_set_hdr_infoframe(struct drm_encoder *encoder) 546 { 547 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 548 struct drm_connector *connector = &vc4_hdmi->connector; 549 struct drm_connector_state *conn_state = connector->state; 550 union hdmi_infoframe frame; 551 552 lockdep_assert_held(&vc4_hdmi->mutex); 553 554 if (!vc4_hdmi->variant->supports_hdr) 555 return; 556 557 if (!conn_state->hdr_output_metadata) 558 return; 559 560 if (drm_hdmi_infoframe_set_hdr_metadata(&frame.drm, conn_state)) 561 return; 562 563 vc4_hdmi_write_infoframe(encoder, &frame); 564 } 565 566 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder) 567 { 568 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 569 570 lockdep_assert_held(&vc4_hdmi->mutex); 571 572 vc4_hdmi_set_avi_infoframe(encoder); 573 vc4_hdmi_set_spd_infoframe(encoder); 574 /* 575 * If audio was streaming, then we need to reenabled the audio 576 * infoframe here during encoder_enable. 577 */ 578 if (vc4_hdmi->audio.streaming) 579 vc4_hdmi_set_audio_infoframe(encoder); 580 581 vc4_hdmi_set_hdr_infoframe(encoder); 582 } 583 584 static bool vc4_hdmi_supports_scrambling(struct drm_encoder *encoder, 585 struct drm_display_mode *mode) 586 { 587 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 588 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 589 struct drm_display_info *display = &vc4_hdmi->connector.display_info; 590 591 lockdep_assert_held(&vc4_hdmi->mutex); 592 593 if (!vc4_encoder->hdmi_monitor) 594 return false; 595 596 if (!display->hdmi.scdc.supported || 597 !display->hdmi.scdc.scrambling.supported) 598 return false; 599 600 return true; 601 } 602 603 #define SCRAMBLING_POLLING_DELAY_MS 1000 604 605 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder) 606 { 607 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 608 struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 609 unsigned long flags; 610 611 lockdep_assert_held(&vc4_hdmi->mutex); 612 613 if (!vc4_hdmi_supports_scrambling(encoder, mode)) 614 return; 615 616 if (!vc4_hdmi_mode_needs_scrambling(mode)) 617 return; 618 619 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true); 620 drm_scdc_set_scrambling(vc4_hdmi->ddc, true); 621 622 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 623 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) | 624 VC5_HDMI_SCRAMBLER_CTL_ENABLE); 625 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 626 627 vc4_hdmi->scdc_enabled = true; 628 629 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work, 630 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS)); 631 } 632 633 static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder) 634 { 635 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 636 unsigned long flags; 637 638 lockdep_assert_held(&vc4_hdmi->mutex); 639 640 if (!vc4_hdmi->scdc_enabled) 641 return; 642 643 vc4_hdmi->scdc_enabled = false; 644 645 if (delayed_work_pending(&vc4_hdmi->scrambling_work)) 646 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work); 647 648 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 649 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) & 650 ~VC5_HDMI_SCRAMBLER_CTL_ENABLE); 651 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 652 653 drm_scdc_set_scrambling(vc4_hdmi->ddc, false); 654 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, false); 655 } 656 657 static void vc4_hdmi_scrambling_wq(struct work_struct *work) 658 { 659 struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work), 660 struct vc4_hdmi, 661 scrambling_work); 662 663 if (drm_scdc_get_scrambling_status(vc4_hdmi->ddc)) 664 return; 665 666 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true); 667 drm_scdc_set_scrambling(vc4_hdmi->ddc, true); 668 669 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work, 670 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS)); 671 } 672 673 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder, 674 struct drm_atomic_state *state) 675 { 676 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 677 unsigned long flags; 678 679 mutex_lock(&vc4_hdmi->mutex); 680 681 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 682 683 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0); 684 685 HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB); 686 687 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 688 689 mdelay(1); 690 691 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 692 HDMI_WRITE(HDMI_VID_CTL, 693 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE); 694 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 695 696 vc4_hdmi_disable_scrambling(encoder); 697 698 mutex_unlock(&vc4_hdmi->mutex); 699 } 700 701 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder, 702 struct drm_atomic_state *state) 703 { 704 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 705 unsigned long flags; 706 int ret; 707 708 mutex_lock(&vc4_hdmi->mutex); 709 710 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 711 HDMI_WRITE(HDMI_VID_CTL, 712 HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX); 713 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 714 715 if (vc4_hdmi->variant->phy_disable) 716 vc4_hdmi->variant->phy_disable(vc4_hdmi); 717 718 clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock); 719 clk_disable_unprepare(vc4_hdmi->pixel_clock); 720 721 ret = pm_runtime_put(&vc4_hdmi->pdev->dev); 722 if (ret < 0) 723 DRM_ERROR("Failed to release power domain: %d\n", ret); 724 725 mutex_unlock(&vc4_hdmi->mutex); 726 } 727 728 static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder) 729 { 730 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 731 732 mutex_lock(&vc4_hdmi->mutex); 733 vc4_hdmi->output_enabled = false; 734 mutex_unlock(&vc4_hdmi->mutex); 735 } 736 737 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, 738 struct drm_connector_state *state, 739 const struct drm_display_mode *mode) 740 { 741 unsigned long flags; 742 u32 csc_ctl; 743 744 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 745 746 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR, 747 VC4_HD_CSC_CTL_ORDER); 748 749 if (!vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode)) { 750 /* CEA VICs other than #1 requre limited range RGB 751 * output unless overridden by an AVI infoframe. 752 * Apply a colorspace conversion to squash 0-255 down 753 * to 16-235. The matrix here is: 754 * 755 * [ 0 0 0.8594 16] 756 * [ 0 0.8594 0 16] 757 * [ 0.8594 0 0 16] 758 * [ 0 0 0 1] 759 */ 760 csc_ctl |= VC4_HD_CSC_CTL_ENABLE; 761 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC; 762 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM, 763 VC4_HD_CSC_CTL_MODE); 764 765 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000); 766 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0); 767 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000); 768 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000); 769 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0); 770 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000); 771 } 772 773 /* The RGB order applies even when CSC is disabled. */ 774 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl); 775 776 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 777 } 778 779 /* 780 * If we need to output Full Range RGB, then use the unity matrix 781 * 782 * [ 1 0 0 0] 783 * [ 0 1 0 0] 784 * [ 0 0 1 0] 785 * 786 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets 787 */ 788 static const u16 vc5_hdmi_csc_full_rgb_unity[3][4] = { 789 { 0x2000, 0x0000, 0x0000, 0x0000 }, 790 { 0x0000, 0x2000, 0x0000, 0x0000 }, 791 { 0x0000, 0x0000, 0x2000, 0x0000 }, 792 }; 793 794 /* 795 * CEA VICs other than #1 require limited range RGB output unless 796 * overridden by an AVI infoframe. Apply a colorspace conversion to 797 * squash 0-255 down to 16-235. The matrix here is: 798 * 799 * [ 0.8594 0 0 16] 800 * [ 0 0.8594 0 16] 801 * [ 0 0 0.8594 16] 802 * 803 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets 804 */ 805 static const u16 vc5_hdmi_csc_full_rgb_to_limited_rgb[3][4] = { 806 { 0x1b80, 0x0000, 0x0000, 0x0400 }, 807 { 0x0000, 0x1b80, 0x0000, 0x0400 }, 808 { 0x0000, 0x0000, 0x1b80, 0x0400 }, 809 }; 810 811 static void vc5_hdmi_set_csc_coeffs(struct vc4_hdmi *vc4_hdmi, 812 const u16 coeffs[3][4]) 813 { 814 lockdep_assert_held(&vc4_hdmi->hw_lock); 815 816 HDMI_WRITE(HDMI_CSC_12_11, (coeffs[0][1] << 16) | coeffs[0][0]); 817 HDMI_WRITE(HDMI_CSC_14_13, (coeffs[0][3] << 16) | coeffs[0][2]); 818 HDMI_WRITE(HDMI_CSC_22_21, (coeffs[1][1] << 16) | coeffs[1][0]); 819 HDMI_WRITE(HDMI_CSC_24_23, (coeffs[1][3] << 16) | coeffs[1][2]); 820 HDMI_WRITE(HDMI_CSC_32_31, (coeffs[2][1] << 16) | coeffs[2][0]); 821 HDMI_WRITE(HDMI_CSC_34_33, (coeffs[2][3] << 16) | coeffs[2][2]); 822 } 823 824 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, 825 struct drm_connector_state *state, 826 const struct drm_display_mode *mode) 827 { 828 unsigned long flags; 829 u32 csc_ctl = VC5_MT_CP_CSC_CTL_ENABLE | VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM, 830 VC5_MT_CP_CSC_CTL_MODE); 831 832 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 833 834 HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, 0x354021); 835 836 if (!vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode)) 837 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_limited_rgb); 838 else 839 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_unity); 840 841 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl); 842 843 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 844 } 845 846 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi, 847 struct drm_connector_state *state, 848 struct drm_display_mode *mode) 849 { 850 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 851 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 852 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 853 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 854 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 855 VC4_HDMI_VERTA_VSP) | 856 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 857 VC4_HDMI_VERTA_VFP) | 858 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL)); 859 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 860 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end, 861 VC4_HDMI_VERTB_VBP)); 862 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 863 VC4_SET_FIELD(mode->crtc_vtotal - 864 mode->crtc_vsync_end - 865 interlaced, 866 VC4_HDMI_VERTB_VBP)); 867 unsigned long flags; 868 869 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 870 871 HDMI_WRITE(HDMI_HORZA, 872 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) | 873 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) | 874 VC4_SET_FIELD(mode->hdisplay * pixel_rep, 875 VC4_HDMI_HORZA_HAP)); 876 877 HDMI_WRITE(HDMI_HORZB, 878 VC4_SET_FIELD((mode->htotal - 879 mode->hsync_end) * pixel_rep, 880 VC4_HDMI_HORZB_HBP) | 881 VC4_SET_FIELD((mode->hsync_end - 882 mode->hsync_start) * pixel_rep, 883 VC4_HDMI_HORZB_HSP) | 884 VC4_SET_FIELD((mode->hsync_start - 885 mode->hdisplay) * pixel_rep, 886 VC4_HDMI_HORZB_HFP)); 887 888 HDMI_WRITE(HDMI_VERTA0, verta); 889 HDMI_WRITE(HDMI_VERTA1, verta); 890 891 HDMI_WRITE(HDMI_VERTB0, vertb_even); 892 HDMI_WRITE(HDMI_VERTB1, vertb); 893 894 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 895 } 896 897 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi, 898 struct drm_connector_state *state, 899 struct drm_display_mode *mode) 900 { 901 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 902 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 903 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 904 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 905 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 906 VC5_HDMI_VERTA_VSP) | 907 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 908 VC5_HDMI_VERTA_VFP) | 909 VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL)); 910 u32 vertb = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) | 911 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end, 912 VC4_HDMI_VERTB_VBP)); 913 u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) | 914 VC4_SET_FIELD(mode->crtc_vtotal - 915 mode->crtc_vsync_end - 916 interlaced, 917 VC4_HDMI_VERTB_VBP)); 918 unsigned long flags; 919 unsigned char gcp; 920 bool gcp_en; 921 u32 reg; 922 923 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 924 925 HDMI_WRITE(HDMI_HORZA, 926 (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) | 927 (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) | 928 VC4_SET_FIELD(mode->hdisplay * pixel_rep, 929 VC5_HDMI_HORZA_HAP) | 930 VC4_SET_FIELD((mode->hsync_start - 931 mode->hdisplay) * pixel_rep, 932 VC5_HDMI_HORZA_HFP)); 933 934 HDMI_WRITE(HDMI_HORZB, 935 VC4_SET_FIELD((mode->htotal - 936 mode->hsync_end) * pixel_rep, 937 VC5_HDMI_HORZB_HBP) | 938 VC4_SET_FIELD((mode->hsync_end - 939 mode->hsync_start) * pixel_rep, 940 VC5_HDMI_HORZB_HSP)); 941 942 HDMI_WRITE(HDMI_VERTA0, verta); 943 HDMI_WRITE(HDMI_VERTA1, verta); 944 945 HDMI_WRITE(HDMI_VERTB0, vertb_even); 946 HDMI_WRITE(HDMI_VERTB1, vertb); 947 948 switch (state->max_bpc) { 949 case 12: 950 gcp = 6; 951 gcp_en = true; 952 break; 953 case 10: 954 gcp = 5; 955 gcp_en = true; 956 break; 957 case 8: 958 default: 959 gcp = 4; 960 gcp_en = false; 961 break; 962 } 963 964 reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1); 965 reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK | 966 VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK); 967 reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) | 968 VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH); 969 HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg); 970 971 reg = HDMI_READ(HDMI_GCP_WORD_1); 972 reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK; 973 reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1); 974 HDMI_WRITE(HDMI_GCP_WORD_1, reg); 975 976 reg = HDMI_READ(HDMI_GCP_CONFIG); 977 reg &= ~VC5_HDMI_GCP_CONFIG_GCP_ENABLE; 978 reg |= gcp_en ? VC5_HDMI_GCP_CONFIG_GCP_ENABLE : 0; 979 HDMI_WRITE(HDMI_GCP_CONFIG, reg); 980 981 HDMI_WRITE(HDMI_CLOCK_STOP, 0); 982 983 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 984 } 985 986 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi) 987 { 988 unsigned long flags; 989 u32 drift; 990 int ret; 991 992 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 993 994 drift = HDMI_READ(HDMI_FIFO_CTL); 995 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK; 996 997 HDMI_WRITE(HDMI_FIFO_CTL, 998 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 999 HDMI_WRITE(HDMI_FIFO_CTL, 1000 drift | VC4_HDMI_FIFO_CTL_RECENTER); 1001 1002 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1003 1004 usleep_range(1000, 1100); 1005 1006 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1007 1008 HDMI_WRITE(HDMI_FIFO_CTL, 1009 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 1010 HDMI_WRITE(HDMI_FIFO_CTL, 1011 drift | VC4_HDMI_FIFO_CTL_RECENTER); 1012 1013 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1014 1015 ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) & 1016 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1); 1017 WARN_ONCE(ret, "Timeout waiting for " 1018 "VC4_HDMI_FIFO_CTL_RECENTER_DONE"); 1019 } 1020 1021 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder, 1022 struct drm_atomic_state *state) 1023 { 1024 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1025 struct drm_connector *connector = &vc4_hdmi->connector; 1026 struct drm_connector_state *conn_state = 1027 drm_atomic_get_new_connector_state(state, connector); 1028 struct vc4_hdmi_connector_state *vc4_conn_state = 1029 conn_state_to_vc4_hdmi_conn_state(conn_state); 1030 struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1031 unsigned long pixel_rate = vc4_conn_state->pixel_rate; 1032 unsigned long bvb_rate, hsm_rate; 1033 unsigned long flags; 1034 int ret; 1035 1036 mutex_lock(&vc4_hdmi->mutex); 1037 1038 /* 1039 * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must 1040 * be faster than pixel clock, infinitesimally faster, tested in 1041 * simulation. Otherwise, exact value is unimportant for HDMI 1042 * operation." This conflicts with bcm2835's vc4 documentation, which 1043 * states HSM's clock has to be at least 108% of the pixel clock. 1044 * 1045 * Real life tests reveal that vc4's firmware statement holds up, and 1046 * users are able to use pixel clocks closer to HSM's, namely for 1047 * 1920x1200@60Hz. So it was decided to have leave a 1% margin between 1048 * both clocks. Which, for RPi0-3 implies a maximum pixel clock of 1049 * 162MHz. 1050 * 1051 * Additionally, the AXI clock needs to be at least 25% of 1052 * pixel clock, but HSM ends up being the limiting factor. 1053 */ 1054 hsm_rate = max_t(unsigned long, 120000000, (pixel_rate / 100) * 101); 1055 ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate); 1056 if (ret) { 1057 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret); 1058 goto out; 1059 } 1060 1061 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev); 1062 if (ret < 0) { 1063 DRM_ERROR("Failed to retain power domain: %d\n", ret); 1064 goto out; 1065 } 1066 1067 ret = clk_set_rate(vc4_hdmi->pixel_clock, pixel_rate); 1068 if (ret) { 1069 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret); 1070 goto err_put_runtime_pm; 1071 } 1072 1073 ret = clk_prepare_enable(vc4_hdmi->pixel_clock); 1074 if (ret) { 1075 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret); 1076 goto err_put_runtime_pm; 1077 } 1078 1079 1080 vc4_hdmi_cec_update_clk_div(vc4_hdmi); 1081 1082 if (pixel_rate > 297000000) 1083 bvb_rate = 300000000; 1084 else if (pixel_rate > 148500000) 1085 bvb_rate = 150000000; 1086 else 1087 bvb_rate = 75000000; 1088 1089 ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate); 1090 if (ret) { 1091 DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret); 1092 goto err_disable_pixel_clock; 1093 } 1094 1095 ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock); 1096 if (ret) { 1097 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret); 1098 goto err_disable_pixel_clock; 1099 } 1100 1101 if (vc4_hdmi->variant->phy_init) 1102 vc4_hdmi->variant->phy_init(vc4_hdmi, vc4_conn_state); 1103 1104 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1105 1106 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1107 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 1108 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT | 1109 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS); 1110 1111 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1112 1113 if (vc4_hdmi->variant->set_timings) 1114 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode); 1115 1116 mutex_unlock(&vc4_hdmi->mutex); 1117 1118 return; 1119 1120 err_disable_pixel_clock: 1121 clk_disable_unprepare(vc4_hdmi->pixel_clock); 1122 err_put_runtime_pm: 1123 pm_runtime_put(&vc4_hdmi->pdev->dev); 1124 out: 1125 mutex_unlock(&vc4_hdmi->mutex); 1126 return; 1127 } 1128 1129 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder, 1130 struct drm_atomic_state *state) 1131 { 1132 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1133 struct drm_connector *connector = &vc4_hdmi->connector; 1134 struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1135 struct drm_connector_state *conn_state = 1136 drm_atomic_get_new_connector_state(state, connector); 1137 unsigned long flags; 1138 1139 mutex_lock(&vc4_hdmi->mutex); 1140 1141 if (vc4_hdmi->variant->csc_setup) 1142 vc4_hdmi->variant->csc_setup(vc4_hdmi, conn_state, mode); 1143 1144 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1145 HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N); 1146 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1147 1148 mutex_unlock(&vc4_hdmi->mutex); 1149 } 1150 1151 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder, 1152 struct drm_atomic_state *state) 1153 { 1154 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1155 struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1156 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 1157 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 1158 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 1159 unsigned long flags; 1160 int ret; 1161 1162 mutex_lock(&vc4_hdmi->mutex); 1163 1164 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1165 1166 HDMI_WRITE(HDMI_VID_CTL, 1167 VC4_HD_VID_CTL_ENABLE | 1168 VC4_HD_VID_CTL_CLRRGB | 1169 VC4_HD_VID_CTL_UNDERFLOW_ENABLE | 1170 VC4_HD_VID_CTL_FRAME_COUNTER_RESET | 1171 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) | 1172 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW)); 1173 1174 HDMI_WRITE(HDMI_VID_CTL, 1175 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX); 1176 1177 if (vc4_encoder->hdmi_monitor) { 1178 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1179 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 1180 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 1181 1182 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1183 1184 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1185 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000); 1186 WARN_ONCE(ret, "Timeout waiting for " 1187 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 1188 } else { 1189 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 1190 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & 1191 ~(VC4_HDMI_RAM_PACKET_ENABLE)); 1192 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1193 HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1194 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 1195 1196 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1197 1198 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1199 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000); 1200 WARN_ONCE(ret, "Timeout waiting for " 1201 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 1202 } 1203 1204 if (vc4_encoder->hdmi_monitor) { 1205 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1206 1207 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1208 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE)); 1209 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1210 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 1211 VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT); 1212 1213 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 1214 VC4_HDMI_RAM_PACKET_ENABLE); 1215 1216 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1217 1218 vc4_hdmi_set_infoframes(encoder); 1219 } 1220 1221 vc4_hdmi_recenter_fifo(vc4_hdmi); 1222 vc4_hdmi_enable_scrambling(encoder); 1223 1224 mutex_unlock(&vc4_hdmi->mutex); 1225 } 1226 1227 static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder) 1228 { 1229 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1230 1231 mutex_lock(&vc4_hdmi->mutex); 1232 vc4_hdmi->output_enabled = true; 1233 mutex_unlock(&vc4_hdmi->mutex); 1234 } 1235 1236 static void vc4_hdmi_encoder_atomic_mode_set(struct drm_encoder *encoder, 1237 struct drm_crtc_state *crtc_state, 1238 struct drm_connector_state *conn_state) 1239 { 1240 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1241 1242 mutex_lock(&vc4_hdmi->mutex); 1243 memcpy(&vc4_hdmi->saved_adjusted_mode, 1244 &crtc_state->adjusted_mode, 1245 sizeof(vc4_hdmi->saved_adjusted_mode)); 1246 mutex_unlock(&vc4_hdmi->mutex); 1247 } 1248 1249 #define WIFI_2_4GHz_CH1_MIN_FREQ 2400000000ULL 1250 #define WIFI_2_4GHz_CH1_MAX_FREQ 2422000000ULL 1251 1252 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder, 1253 struct drm_crtc_state *crtc_state, 1254 struct drm_connector_state *conn_state) 1255 { 1256 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state); 1257 struct drm_display_mode *mode = &crtc_state->adjusted_mode; 1258 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1259 unsigned long long pixel_rate = mode->clock * 1000; 1260 unsigned long long tmds_rate; 1261 1262 if (vc4_hdmi->variant->unsupported_odd_h_timings && 1263 ((mode->hdisplay % 2) || (mode->hsync_start % 2) || 1264 (mode->hsync_end % 2) || (mode->htotal % 2))) 1265 return -EINVAL; 1266 1267 /* 1268 * The 1440p@60 pixel rate is in the same range than the first 1269 * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz 1270 * bandwidth). Slightly lower the frequency to bring it out of 1271 * the WiFi range. 1272 */ 1273 tmds_rate = pixel_rate * 10; 1274 if (vc4_hdmi->disable_wifi_frequencies && 1275 (tmds_rate >= WIFI_2_4GHz_CH1_MIN_FREQ && 1276 tmds_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) { 1277 mode->clock = 238560; 1278 pixel_rate = mode->clock * 1000; 1279 } 1280 1281 if (conn_state->max_bpc == 12) { 1282 pixel_rate = pixel_rate * 150; 1283 do_div(pixel_rate, 100); 1284 } else if (conn_state->max_bpc == 10) { 1285 pixel_rate = pixel_rate * 125; 1286 do_div(pixel_rate, 100); 1287 } 1288 1289 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 1290 pixel_rate = pixel_rate * 2; 1291 1292 if (pixel_rate > vc4_hdmi->variant->max_pixel_clock) 1293 return -EINVAL; 1294 1295 if (vc4_hdmi->disable_4kp60 && (pixel_rate > HDMI_14_MAX_TMDS_CLK)) 1296 return -EINVAL; 1297 1298 vc4_state->pixel_rate = pixel_rate; 1299 1300 return 0; 1301 } 1302 1303 static enum drm_mode_status 1304 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder, 1305 const struct drm_display_mode *mode) 1306 { 1307 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1308 1309 if (vc4_hdmi->variant->unsupported_odd_h_timings && 1310 ((mode->hdisplay % 2) || (mode->hsync_start % 2) || 1311 (mode->hsync_end % 2) || (mode->htotal % 2))) 1312 return MODE_H_ILLEGAL; 1313 1314 if ((mode->clock * 1000) > vc4_hdmi->variant->max_pixel_clock) 1315 return MODE_CLOCK_HIGH; 1316 1317 if (vc4_hdmi->disable_4kp60 && vc4_hdmi_mode_needs_scrambling(mode)) 1318 return MODE_CLOCK_HIGH; 1319 1320 return MODE_OK; 1321 } 1322 1323 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = { 1324 .atomic_check = vc4_hdmi_encoder_atomic_check, 1325 .atomic_mode_set = vc4_hdmi_encoder_atomic_mode_set, 1326 .mode_valid = vc4_hdmi_encoder_mode_valid, 1327 .disable = vc4_hdmi_encoder_disable, 1328 .enable = vc4_hdmi_encoder_enable, 1329 }; 1330 1331 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask) 1332 { 1333 int i; 1334 u32 channel_map = 0; 1335 1336 for (i = 0; i < 8; i++) { 1337 if (channel_mask & BIT(i)) 1338 channel_map |= i << (3 * i); 1339 } 1340 return channel_map; 1341 } 1342 1343 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask) 1344 { 1345 int i; 1346 u32 channel_map = 0; 1347 1348 for (i = 0; i < 8; i++) { 1349 if (channel_mask & BIT(i)) 1350 channel_map |= i << (4 * i); 1351 } 1352 return channel_map; 1353 } 1354 1355 /* HDMI audio codec callbacks */ 1356 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi, 1357 unsigned int samplerate) 1358 { 1359 u32 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock); 1360 unsigned long flags; 1361 unsigned long n, m; 1362 1363 rational_best_approximation(hsm_clock, samplerate, 1364 VC4_HD_MAI_SMP_N_MASK >> 1365 VC4_HD_MAI_SMP_N_SHIFT, 1366 (VC4_HD_MAI_SMP_M_MASK >> 1367 VC4_HD_MAI_SMP_M_SHIFT) + 1, 1368 &n, &m); 1369 1370 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1371 HDMI_WRITE(HDMI_MAI_SMP, 1372 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) | 1373 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M)); 1374 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1375 } 1376 1377 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi, unsigned int samplerate) 1378 { 1379 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1380 u32 n, cts; 1381 u64 tmp; 1382 1383 lockdep_assert_held(&vc4_hdmi->mutex); 1384 lockdep_assert_held(&vc4_hdmi->hw_lock); 1385 1386 n = 128 * samplerate / 1000; 1387 tmp = (u64)(mode->clock * 1000) * n; 1388 do_div(tmp, 128 * samplerate); 1389 cts = tmp; 1390 1391 HDMI_WRITE(HDMI_CRP_CFG, 1392 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN | 1393 VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N)); 1394 1395 /* 1396 * We could get slightly more accurate clocks in some cases by 1397 * providing a CTS_1 value. The two CTS values are alternated 1398 * between based on the period fields 1399 */ 1400 HDMI_WRITE(HDMI_CTS_0, cts); 1401 HDMI_WRITE(HDMI_CTS_1, cts); 1402 } 1403 1404 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai) 1405 { 1406 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai); 1407 1408 return snd_soc_card_get_drvdata(card); 1409 } 1410 1411 static bool vc4_hdmi_audio_can_stream(struct vc4_hdmi *vc4_hdmi) 1412 { 1413 lockdep_assert_held(&vc4_hdmi->mutex); 1414 1415 /* 1416 * If the controller is disabled, prevent any ALSA output. 1417 */ 1418 if (!vc4_hdmi->output_enabled) 1419 return false; 1420 1421 /* 1422 * If the encoder is currently in DVI mode, treat the codec DAI 1423 * as missing. 1424 */ 1425 if (!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) & VC4_HDMI_RAM_PACKET_ENABLE)) 1426 return false; 1427 1428 return true; 1429 } 1430 1431 static int vc4_hdmi_audio_startup(struct device *dev, void *data) 1432 { 1433 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 1434 unsigned long flags; 1435 1436 mutex_lock(&vc4_hdmi->mutex); 1437 1438 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) { 1439 mutex_unlock(&vc4_hdmi->mutex); 1440 return -ENODEV; 1441 } 1442 1443 vc4_hdmi->audio.streaming = true; 1444 1445 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1446 HDMI_WRITE(HDMI_MAI_CTL, 1447 VC4_HD_MAI_CTL_RESET | 1448 VC4_HD_MAI_CTL_FLUSH | 1449 VC4_HD_MAI_CTL_DLATE | 1450 VC4_HD_MAI_CTL_ERRORE | 1451 VC4_HD_MAI_CTL_ERRORF); 1452 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1453 1454 if (vc4_hdmi->variant->phy_rng_enable) 1455 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi); 1456 1457 mutex_unlock(&vc4_hdmi->mutex); 1458 1459 return 0; 1460 } 1461 1462 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi) 1463 { 1464 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base; 1465 struct device *dev = &vc4_hdmi->pdev->dev; 1466 unsigned long flags; 1467 int ret; 1468 1469 lockdep_assert_held(&vc4_hdmi->mutex); 1470 1471 vc4_hdmi->audio.streaming = false; 1472 ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO, false); 1473 if (ret) 1474 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret); 1475 1476 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1477 1478 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET); 1479 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF); 1480 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH); 1481 1482 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1483 } 1484 1485 static void vc4_hdmi_audio_shutdown(struct device *dev, void *data) 1486 { 1487 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 1488 unsigned long flags; 1489 1490 mutex_lock(&vc4_hdmi->mutex); 1491 1492 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1493 1494 HDMI_WRITE(HDMI_MAI_CTL, 1495 VC4_HD_MAI_CTL_DLATE | 1496 VC4_HD_MAI_CTL_ERRORE | 1497 VC4_HD_MAI_CTL_ERRORF); 1498 1499 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1500 1501 if (vc4_hdmi->variant->phy_rng_disable) 1502 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi); 1503 1504 vc4_hdmi->audio.streaming = false; 1505 vc4_hdmi_audio_reset(vc4_hdmi); 1506 1507 mutex_unlock(&vc4_hdmi->mutex); 1508 } 1509 1510 static int sample_rate_to_mai_fmt(int samplerate) 1511 { 1512 switch (samplerate) { 1513 case 8000: 1514 return VC4_HDMI_MAI_SAMPLE_RATE_8000; 1515 case 11025: 1516 return VC4_HDMI_MAI_SAMPLE_RATE_11025; 1517 case 12000: 1518 return VC4_HDMI_MAI_SAMPLE_RATE_12000; 1519 case 16000: 1520 return VC4_HDMI_MAI_SAMPLE_RATE_16000; 1521 case 22050: 1522 return VC4_HDMI_MAI_SAMPLE_RATE_22050; 1523 case 24000: 1524 return VC4_HDMI_MAI_SAMPLE_RATE_24000; 1525 case 32000: 1526 return VC4_HDMI_MAI_SAMPLE_RATE_32000; 1527 case 44100: 1528 return VC4_HDMI_MAI_SAMPLE_RATE_44100; 1529 case 48000: 1530 return VC4_HDMI_MAI_SAMPLE_RATE_48000; 1531 case 64000: 1532 return VC4_HDMI_MAI_SAMPLE_RATE_64000; 1533 case 88200: 1534 return VC4_HDMI_MAI_SAMPLE_RATE_88200; 1535 case 96000: 1536 return VC4_HDMI_MAI_SAMPLE_RATE_96000; 1537 case 128000: 1538 return VC4_HDMI_MAI_SAMPLE_RATE_128000; 1539 case 176400: 1540 return VC4_HDMI_MAI_SAMPLE_RATE_176400; 1541 case 192000: 1542 return VC4_HDMI_MAI_SAMPLE_RATE_192000; 1543 default: 1544 return VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED; 1545 } 1546 } 1547 1548 /* HDMI audio codec callbacks */ 1549 static int vc4_hdmi_audio_prepare(struct device *dev, void *data, 1550 struct hdmi_codec_daifmt *daifmt, 1551 struct hdmi_codec_params *params) 1552 { 1553 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 1554 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base; 1555 unsigned int sample_rate = params->sample_rate; 1556 unsigned int channels = params->channels; 1557 unsigned long flags; 1558 u32 audio_packet_config, channel_mask; 1559 u32 channel_map; 1560 u32 mai_audio_format; 1561 u32 mai_sample_rate; 1562 1563 dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__, 1564 sample_rate, params->sample_width, channels); 1565 1566 mutex_lock(&vc4_hdmi->mutex); 1567 1568 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) { 1569 mutex_unlock(&vc4_hdmi->mutex); 1570 return -EINVAL; 1571 } 1572 1573 vc4_hdmi_audio_set_mai_clock(vc4_hdmi, sample_rate); 1574 1575 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1576 HDMI_WRITE(HDMI_MAI_CTL, 1577 VC4_SET_FIELD(channels, VC4_HD_MAI_CTL_CHNUM) | 1578 VC4_HD_MAI_CTL_WHOLSMP | 1579 VC4_HD_MAI_CTL_CHALIGN | 1580 VC4_HD_MAI_CTL_ENABLE); 1581 1582 mai_sample_rate = sample_rate_to_mai_fmt(sample_rate); 1583 if (params->iec.status[0] & IEC958_AES0_NONAUDIO && 1584 params->channels == 8) 1585 mai_audio_format = VC4_HDMI_MAI_FORMAT_HBR; 1586 else 1587 mai_audio_format = VC4_HDMI_MAI_FORMAT_PCM; 1588 HDMI_WRITE(HDMI_MAI_FMT, 1589 VC4_SET_FIELD(mai_sample_rate, 1590 VC4_HDMI_MAI_FORMAT_SAMPLE_RATE) | 1591 VC4_SET_FIELD(mai_audio_format, 1592 VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT)); 1593 1594 /* The B frame identifier should match the value used by alsa-lib (8) */ 1595 audio_packet_config = 1596 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT | 1597 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS | 1598 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER); 1599 1600 channel_mask = GENMASK(channels - 1, 0); 1601 audio_packet_config |= VC4_SET_FIELD(channel_mask, 1602 VC4_HDMI_AUDIO_PACKET_CEA_MASK); 1603 1604 /* Set the MAI threshold */ 1605 HDMI_WRITE(HDMI_MAI_THR, 1606 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) | 1607 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) | 1608 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQHIGH) | 1609 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQLOW)); 1610 1611 HDMI_WRITE(HDMI_MAI_CONFIG, 1612 VC4_HDMI_MAI_CONFIG_BIT_REVERSE | 1613 VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE | 1614 VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK)); 1615 1616 channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask); 1617 HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map); 1618 HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config); 1619 1620 vc4_hdmi_set_n_cts(vc4_hdmi, sample_rate); 1621 1622 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1623 1624 memcpy(&vc4_hdmi->audio.infoframe, ¶ms->cea, sizeof(params->cea)); 1625 vc4_hdmi_set_audio_infoframe(encoder); 1626 1627 mutex_unlock(&vc4_hdmi->mutex); 1628 1629 return 0; 1630 } 1631 1632 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = { 1633 .name = "vc4-hdmi-cpu-dai-component", 1634 }; 1635 1636 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai) 1637 { 1638 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai); 1639 1640 snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL); 1641 1642 return 0; 1643 } 1644 1645 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = { 1646 .name = "vc4-hdmi-cpu-dai", 1647 .probe = vc4_hdmi_audio_cpu_dai_probe, 1648 .playback = { 1649 .stream_name = "Playback", 1650 .channels_min = 1, 1651 .channels_max = 8, 1652 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 1653 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 1654 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 1655 SNDRV_PCM_RATE_192000, 1656 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 1657 }, 1658 }; 1659 1660 static const struct snd_dmaengine_pcm_config pcm_conf = { 1661 .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx", 1662 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 1663 }; 1664 1665 static int vc4_hdmi_audio_get_eld(struct device *dev, void *data, 1666 uint8_t *buf, size_t len) 1667 { 1668 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 1669 struct drm_connector *connector = &vc4_hdmi->connector; 1670 1671 mutex_lock(&vc4_hdmi->mutex); 1672 memcpy(buf, connector->eld, min(sizeof(connector->eld), len)); 1673 mutex_unlock(&vc4_hdmi->mutex); 1674 1675 return 0; 1676 } 1677 1678 static const struct hdmi_codec_ops vc4_hdmi_codec_ops = { 1679 .get_eld = vc4_hdmi_audio_get_eld, 1680 .prepare = vc4_hdmi_audio_prepare, 1681 .audio_shutdown = vc4_hdmi_audio_shutdown, 1682 .audio_startup = vc4_hdmi_audio_startup, 1683 }; 1684 1685 static struct hdmi_codec_pdata vc4_hdmi_codec_pdata = { 1686 .ops = &vc4_hdmi_codec_ops, 1687 .max_i2s_channels = 8, 1688 .i2s = 1, 1689 }; 1690 1691 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi) 1692 { 1693 const struct vc4_hdmi_register *mai_data = 1694 &vc4_hdmi->variant->registers[HDMI_MAI_DATA]; 1695 struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link; 1696 struct snd_soc_card *card = &vc4_hdmi->audio.card; 1697 struct device *dev = &vc4_hdmi->pdev->dev; 1698 struct platform_device *codec_pdev; 1699 const __be32 *addr; 1700 int index; 1701 int ret; 1702 1703 if (!of_find_property(dev->of_node, "dmas", NULL)) { 1704 dev_warn(dev, 1705 "'dmas' DT property is missing, no HDMI audio\n"); 1706 return 0; 1707 } 1708 1709 if (mai_data->reg != VC4_HD) { 1710 WARN_ONCE(true, "MAI isn't in the HD block\n"); 1711 return -EINVAL; 1712 } 1713 1714 /* 1715 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve 1716 * the bus address specified in the DT, because the physical address 1717 * (the one returned by platform_get_resource()) is not appropriate 1718 * for DMA transfers. 1719 * This VC/MMU should probably be exposed to avoid this kind of hacks. 1720 */ 1721 index = of_property_match_string(dev->of_node, "reg-names", "hd"); 1722 /* Before BCM2711, we don't have a named register range */ 1723 if (index < 0) 1724 index = 1; 1725 1726 addr = of_get_address(dev->of_node, index, NULL, NULL); 1727 1728 vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset; 1729 vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1730 vc4_hdmi->audio.dma_data.maxburst = 2; 1731 1732 ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0); 1733 if (ret) { 1734 dev_err(dev, "Could not register PCM component: %d\n", ret); 1735 return ret; 1736 } 1737 1738 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp, 1739 &vc4_hdmi_audio_cpu_dai_drv, 1); 1740 if (ret) { 1741 dev_err(dev, "Could not register CPU DAI: %d\n", ret); 1742 return ret; 1743 } 1744 1745 codec_pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME, 1746 PLATFORM_DEVID_AUTO, 1747 &vc4_hdmi_codec_pdata, 1748 sizeof(vc4_hdmi_codec_pdata)); 1749 if (IS_ERR(codec_pdev)) { 1750 dev_err(dev, "Couldn't register the HDMI codec: %ld\n", PTR_ERR(codec_pdev)); 1751 return PTR_ERR(codec_pdev); 1752 } 1753 1754 dai_link->cpus = &vc4_hdmi->audio.cpu; 1755 dai_link->codecs = &vc4_hdmi->audio.codec; 1756 dai_link->platforms = &vc4_hdmi->audio.platform; 1757 1758 dai_link->num_cpus = 1; 1759 dai_link->num_codecs = 1; 1760 dai_link->num_platforms = 1; 1761 1762 dai_link->name = "MAI"; 1763 dai_link->stream_name = "MAI PCM"; 1764 dai_link->codecs->dai_name = "i2s-hifi"; 1765 dai_link->cpus->dai_name = dev_name(dev); 1766 dai_link->codecs->name = dev_name(&codec_pdev->dev); 1767 dai_link->platforms->name = dev_name(dev); 1768 1769 card->dai_link = dai_link; 1770 card->num_links = 1; 1771 card->name = vc4_hdmi->variant->card_name; 1772 card->driver_name = "vc4-hdmi"; 1773 card->dev = dev; 1774 card->owner = THIS_MODULE; 1775 1776 /* 1777 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and 1778 * stores a pointer to the snd card object in dev->driver_data. This 1779 * means we cannot use it for something else. The hdmi back-pointer is 1780 * now stored in card->drvdata and should be retrieved with 1781 * snd_soc_card_get_drvdata() if needed. 1782 */ 1783 snd_soc_card_set_drvdata(card, vc4_hdmi); 1784 ret = devm_snd_soc_register_card(dev, card); 1785 if (ret) 1786 dev_err_probe(dev, ret, "Could not register sound card\n"); 1787 1788 return ret; 1789 1790 } 1791 1792 static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv) 1793 { 1794 struct vc4_hdmi *vc4_hdmi = priv; 1795 struct drm_connector *connector = &vc4_hdmi->connector; 1796 struct drm_device *dev = connector->dev; 1797 1798 if (dev && dev->registered) 1799 drm_connector_helper_hpd_irq_event(connector); 1800 1801 return IRQ_HANDLED; 1802 } 1803 1804 static int vc4_hdmi_hotplug_init(struct vc4_hdmi *vc4_hdmi) 1805 { 1806 struct drm_connector *connector = &vc4_hdmi->connector; 1807 struct platform_device *pdev = vc4_hdmi->pdev; 1808 int ret; 1809 1810 if (vc4_hdmi->variant->external_irq_controller) { 1811 unsigned int hpd_con = platform_get_irq_byname(pdev, "hpd-connected"); 1812 unsigned int hpd_rm = platform_get_irq_byname(pdev, "hpd-removed"); 1813 1814 ret = request_threaded_irq(hpd_con, 1815 NULL, 1816 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT, 1817 "vc4 hdmi hpd connected", vc4_hdmi); 1818 if (ret) 1819 return ret; 1820 1821 ret = request_threaded_irq(hpd_rm, 1822 NULL, 1823 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT, 1824 "vc4 hdmi hpd disconnected", vc4_hdmi); 1825 if (ret) { 1826 free_irq(hpd_con, vc4_hdmi); 1827 return ret; 1828 } 1829 1830 connector->polled = DRM_CONNECTOR_POLL_HPD; 1831 } 1832 1833 return 0; 1834 } 1835 1836 static void vc4_hdmi_hotplug_exit(struct vc4_hdmi *vc4_hdmi) 1837 { 1838 struct platform_device *pdev = vc4_hdmi->pdev; 1839 1840 if (vc4_hdmi->variant->external_irq_controller) { 1841 free_irq(platform_get_irq_byname(pdev, "hpd-connected"), vc4_hdmi); 1842 free_irq(platform_get_irq_byname(pdev, "hpd-removed"), vc4_hdmi); 1843 } 1844 } 1845 1846 #ifdef CONFIG_DRM_VC4_HDMI_CEC 1847 static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv) 1848 { 1849 struct vc4_hdmi *vc4_hdmi = priv; 1850 1851 if (vc4_hdmi->cec_rx_msg.len) 1852 cec_received_msg(vc4_hdmi->cec_adap, 1853 &vc4_hdmi->cec_rx_msg); 1854 1855 return IRQ_HANDLED; 1856 } 1857 1858 static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv) 1859 { 1860 struct vc4_hdmi *vc4_hdmi = priv; 1861 1862 if (vc4_hdmi->cec_tx_ok) { 1863 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK, 1864 0, 0, 0, 0); 1865 } else { 1866 /* 1867 * This CEC implementation makes 1 retry, so if we 1868 * get a NACK, then that means it made 2 attempts. 1869 */ 1870 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK, 1871 0, 2, 0, 0); 1872 } 1873 return IRQ_HANDLED; 1874 } 1875 1876 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv) 1877 { 1878 struct vc4_hdmi *vc4_hdmi = priv; 1879 irqreturn_t ret; 1880 1881 if (vc4_hdmi->cec_irq_was_rx) 1882 ret = vc4_cec_irq_handler_rx_thread(irq, priv); 1883 else 1884 ret = vc4_cec_irq_handler_tx_thread(irq, priv); 1885 1886 return ret; 1887 } 1888 1889 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1) 1890 { 1891 struct drm_device *dev = vc4_hdmi->connector.dev; 1892 struct cec_msg *msg = &vc4_hdmi->cec_rx_msg; 1893 unsigned int i; 1894 1895 lockdep_assert_held(&vc4_hdmi->hw_lock); 1896 1897 msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >> 1898 VC4_HDMI_CEC_REC_WRD_CNT_SHIFT); 1899 1900 if (msg->len > 16) { 1901 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len); 1902 return; 1903 } 1904 1905 for (i = 0; i < msg->len; i += 4) { 1906 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2)); 1907 1908 msg->msg[i] = val & 0xff; 1909 msg->msg[i + 1] = (val >> 8) & 0xff; 1910 msg->msg[i + 2] = (val >> 16) & 0xff; 1911 msg->msg[i + 3] = (val >> 24) & 0xff; 1912 } 1913 } 1914 1915 static irqreturn_t vc4_cec_irq_handler_tx_bare_locked(struct vc4_hdmi *vc4_hdmi) 1916 { 1917 u32 cntrl1; 1918 1919 lockdep_assert_held(&vc4_hdmi->hw_lock); 1920 1921 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1); 1922 vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD; 1923 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 1924 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 1925 1926 return IRQ_WAKE_THREAD; 1927 } 1928 1929 static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv) 1930 { 1931 struct vc4_hdmi *vc4_hdmi = priv; 1932 irqreturn_t ret; 1933 1934 spin_lock(&vc4_hdmi->hw_lock); 1935 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi); 1936 spin_unlock(&vc4_hdmi->hw_lock); 1937 1938 return ret; 1939 } 1940 1941 static irqreturn_t vc4_cec_irq_handler_rx_bare_locked(struct vc4_hdmi *vc4_hdmi) 1942 { 1943 u32 cntrl1; 1944 1945 lockdep_assert_held(&vc4_hdmi->hw_lock); 1946 1947 vc4_hdmi->cec_rx_msg.len = 0; 1948 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1); 1949 vc4_cec_read_msg(vc4_hdmi, cntrl1); 1950 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 1951 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 1952 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 1953 1954 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 1955 1956 return IRQ_WAKE_THREAD; 1957 } 1958 1959 static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv) 1960 { 1961 struct vc4_hdmi *vc4_hdmi = priv; 1962 irqreturn_t ret; 1963 1964 spin_lock(&vc4_hdmi->hw_lock); 1965 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi); 1966 spin_unlock(&vc4_hdmi->hw_lock); 1967 1968 return ret; 1969 } 1970 1971 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv) 1972 { 1973 struct vc4_hdmi *vc4_hdmi = priv; 1974 u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS); 1975 irqreturn_t ret; 1976 u32 cntrl5; 1977 1978 if (!(stat & VC4_HDMI_CPU_CEC)) 1979 return IRQ_NONE; 1980 1981 spin_lock(&vc4_hdmi->hw_lock); 1982 cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5); 1983 vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT; 1984 if (vc4_hdmi->cec_irq_was_rx) 1985 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi); 1986 else 1987 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi); 1988 1989 HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC); 1990 spin_unlock(&vc4_hdmi->hw_lock); 1991 1992 return ret; 1993 } 1994 1995 static int vc4_hdmi_cec_enable(struct cec_adapter *adap) 1996 { 1997 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 1998 /* clock period in microseconds */ 1999 const u32 usecs = 1000000 / CEC_CLOCK_FREQ; 2000 unsigned long flags; 2001 u32 val; 2002 int ret; 2003 2004 /* 2005 * NOTE: This function should really take vc4_hdmi->mutex, but doing so 2006 * results in a reentrancy since cec_s_phys_addr_from_edid() called in 2007 * .detect or .get_modes might call .adap_enable, which leads to this 2008 * function being called with that mutex held. 2009 * 2010 * Concurrency is not an issue for the moment since we don't share any 2011 * state with KMS, so we can ignore the lock for now, but we need to 2012 * keep it in mind if we were to change that assumption. 2013 */ 2014 2015 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev); 2016 if (ret) 2017 return ret; 2018 2019 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2020 2021 val = HDMI_READ(HDMI_CEC_CNTRL_5); 2022 val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET | 2023 VC4_HDMI_CEC_CNT_TO_4700_US_MASK | 2024 VC4_HDMI_CEC_CNT_TO_4500_US_MASK); 2025 val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) | 2026 ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT); 2027 2028 HDMI_WRITE(HDMI_CEC_CNTRL_5, val | 2029 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 2030 HDMI_WRITE(HDMI_CEC_CNTRL_5, val); 2031 HDMI_WRITE(HDMI_CEC_CNTRL_2, 2032 ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) | 2033 ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) | 2034 ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) | 2035 ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) | 2036 ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT)); 2037 HDMI_WRITE(HDMI_CEC_CNTRL_3, 2038 ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) | 2039 ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) | 2040 ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) | 2041 ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT)); 2042 HDMI_WRITE(HDMI_CEC_CNTRL_4, 2043 ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) | 2044 ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) | 2045 ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) | 2046 ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT)); 2047 2048 if (!vc4_hdmi->variant->external_irq_controller) 2049 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC); 2050 2051 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2052 2053 return 0; 2054 } 2055 2056 static int vc4_hdmi_cec_disable(struct cec_adapter *adap) 2057 { 2058 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 2059 unsigned long flags; 2060 2061 /* 2062 * NOTE: This function should really take vc4_hdmi->mutex, but doing so 2063 * results in a reentrancy since cec_s_phys_addr_from_edid() called in 2064 * .detect or .get_modes might call .adap_enable, which leads to this 2065 * function being called with that mutex held. 2066 * 2067 * Concurrency is not an issue for the moment since we don't share any 2068 * state with KMS, so we can ignore the lock for now, but we need to 2069 * keep it in mind if we were to change that assumption. 2070 */ 2071 2072 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2073 2074 if (!vc4_hdmi->variant->external_irq_controller) 2075 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC); 2076 2077 HDMI_WRITE(HDMI_CEC_CNTRL_5, HDMI_READ(HDMI_CEC_CNTRL_5) | 2078 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 2079 2080 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2081 2082 pm_runtime_put(&vc4_hdmi->pdev->dev); 2083 2084 return 0; 2085 } 2086 2087 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable) 2088 { 2089 if (enable) 2090 return vc4_hdmi_cec_enable(adap); 2091 else 2092 return vc4_hdmi_cec_disable(adap); 2093 } 2094 2095 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr) 2096 { 2097 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 2098 unsigned long flags; 2099 2100 /* 2101 * NOTE: This function should really take vc4_hdmi->mutex, but doing so 2102 * results in a reentrancy since cec_s_phys_addr_from_edid() called in 2103 * .detect or .get_modes might call .adap_enable, which leads to this 2104 * function being called with that mutex held. 2105 * 2106 * Concurrency is not an issue for the moment since we don't share any 2107 * state with KMS, so we can ignore the lock for now, but we need to 2108 * keep it in mind if we were to change that assumption. 2109 */ 2110 2111 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2112 HDMI_WRITE(HDMI_CEC_CNTRL_1, 2113 (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) | 2114 (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT); 2115 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2116 2117 return 0; 2118 } 2119 2120 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts, 2121 u32 signal_free_time, struct cec_msg *msg) 2122 { 2123 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 2124 struct drm_device *dev = vc4_hdmi->connector.dev; 2125 unsigned long flags; 2126 u32 val; 2127 unsigned int i; 2128 2129 /* 2130 * NOTE: This function should really take vc4_hdmi->mutex, but doing so 2131 * results in a reentrancy since cec_s_phys_addr_from_edid() called in 2132 * .detect or .get_modes might call .adap_enable, which leads to this 2133 * function being called with that mutex held. 2134 * 2135 * Concurrency is not an issue for the moment since we don't share any 2136 * state with KMS, so we can ignore the lock for now, but we need to 2137 * keep it in mind if we were to change that assumption. 2138 */ 2139 2140 if (msg->len > 16) { 2141 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len); 2142 return -ENOMEM; 2143 } 2144 2145 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2146 2147 for (i = 0; i < msg->len; i += 4) 2148 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2), 2149 (msg->msg[i]) | 2150 (msg->msg[i + 1] << 8) | 2151 (msg->msg[i + 2] << 16) | 2152 (msg->msg[i + 3] << 24)); 2153 2154 val = HDMI_READ(HDMI_CEC_CNTRL_1); 2155 val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 2156 HDMI_WRITE(HDMI_CEC_CNTRL_1, val); 2157 val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK; 2158 val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT; 2159 val |= VC4_HDMI_CEC_START_XMIT_BEGIN; 2160 2161 HDMI_WRITE(HDMI_CEC_CNTRL_1, val); 2162 2163 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2164 2165 return 0; 2166 } 2167 2168 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = { 2169 .adap_enable = vc4_hdmi_cec_adap_enable, 2170 .adap_log_addr = vc4_hdmi_cec_adap_log_addr, 2171 .adap_transmit = vc4_hdmi_cec_adap_transmit, 2172 }; 2173 2174 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi) 2175 { 2176 struct cec_connector_info conn_info; 2177 struct platform_device *pdev = vc4_hdmi->pdev; 2178 struct device *dev = &pdev->dev; 2179 unsigned long flags; 2180 u32 value; 2181 int ret; 2182 2183 if (!of_find_property(dev->of_node, "interrupts", NULL)) { 2184 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n"); 2185 return 0; 2186 } 2187 2188 vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops, 2189 vc4_hdmi, "vc4", 2190 CEC_CAP_DEFAULTS | 2191 CEC_CAP_CONNECTOR_INFO, 1); 2192 ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap); 2193 if (ret < 0) 2194 return ret; 2195 2196 cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector); 2197 cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info); 2198 2199 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2200 value = HDMI_READ(HDMI_CEC_CNTRL_1); 2201 /* Set the logical address to Unregistered */ 2202 value |= VC4_HDMI_CEC_ADDR_MASK; 2203 HDMI_WRITE(HDMI_CEC_CNTRL_1, value); 2204 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2205 2206 vc4_hdmi_cec_update_clk_div(vc4_hdmi); 2207 2208 if (vc4_hdmi->variant->external_irq_controller) { 2209 ret = request_threaded_irq(platform_get_irq_byname(pdev, "cec-rx"), 2210 vc4_cec_irq_handler_rx_bare, 2211 vc4_cec_irq_handler_rx_thread, 0, 2212 "vc4 hdmi cec rx", vc4_hdmi); 2213 if (ret) 2214 goto err_delete_cec_adap; 2215 2216 ret = request_threaded_irq(platform_get_irq_byname(pdev, "cec-tx"), 2217 vc4_cec_irq_handler_tx_bare, 2218 vc4_cec_irq_handler_tx_thread, 0, 2219 "vc4 hdmi cec tx", vc4_hdmi); 2220 if (ret) 2221 goto err_remove_cec_rx_handler; 2222 } else { 2223 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2224 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff); 2225 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2226 2227 ret = request_threaded_irq(platform_get_irq(pdev, 0), 2228 vc4_cec_irq_handler, 2229 vc4_cec_irq_handler_thread, 0, 2230 "vc4 hdmi cec", vc4_hdmi); 2231 if (ret) 2232 goto err_delete_cec_adap; 2233 } 2234 2235 ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev); 2236 if (ret < 0) 2237 goto err_remove_handlers; 2238 2239 return 0; 2240 2241 err_remove_handlers: 2242 if (vc4_hdmi->variant->external_irq_controller) 2243 free_irq(platform_get_irq_byname(pdev, "cec-tx"), vc4_hdmi); 2244 else 2245 free_irq(platform_get_irq(pdev, 0), vc4_hdmi); 2246 2247 err_remove_cec_rx_handler: 2248 if (vc4_hdmi->variant->external_irq_controller) 2249 free_irq(platform_get_irq_byname(pdev, "cec-rx"), vc4_hdmi); 2250 2251 err_delete_cec_adap: 2252 cec_delete_adapter(vc4_hdmi->cec_adap); 2253 2254 return ret; 2255 } 2256 2257 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi) 2258 { 2259 struct platform_device *pdev = vc4_hdmi->pdev; 2260 2261 if (vc4_hdmi->variant->external_irq_controller) { 2262 free_irq(platform_get_irq_byname(pdev, "cec-rx"), vc4_hdmi); 2263 free_irq(platform_get_irq_byname(pdev, "cec-tx"), vc4_hdmi); 2264 } else { 2265 free_irq(platform_get_irq(pdev, 0), vc4_hdmi); 2266 } 2267 2268 cec_unregister_adapter(vc4_hdmi->cec_adap); 2269 } 2270 #else 2271 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi) 2272 { 2273 return 0; 2274 } 2275 2276 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi) {}; 2277 2278 #endif 2279 2280 static int vc4_hdmi_build_regset(struct vc4_hdmi *vc4_hdmi, 2281 struct debugfs_regset32 *regset, 2282 enum vc4_hdmi_regs reg) 2283 { 2284 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant; 2285 struct debugfs_reg32 *regs, *new_regs; 2286 unsigned int count = 0; 2287 unsigned int i; 2288 2289 regs = kcalloc(variant->num_registers, sizeof(*regs), 2290 GFP_KERNEL); 2291 if (!regs) 2292 return -ENOMEM; 2293 2294 for (i = 0; i < variant->num_registers; i++) { 2295 const struct vc4_hdmi_register *field = &variant->registers[i]; 2296 2297 if (field->reg != reg) 2298 continue; 2299 2300 regs[count].name = field->name; 2301 regs[count].offset = field->offset; 2302 count++; 2303 } 2304 2305 new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL); 2306 if (!new_regs) 2307 return -ENOMEM; 2308 2309 regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg); 2310 regset->regs = new_regs; 2311 regset->nregs = count; 2312 2313 return 0; 2314 } 2315 2316 static int vc4_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi) 2317 { 2318 struct platform_device *pdev = vc4_hdmi->pdev; 2319 struct device *dev = &pdev->dev; 2320 int ret; 2321 2322 vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0); 2323 if (IS_ERR(vc4_hdmi->hdmicore_regs)) 2324 return PTR_ERR(vc4_hdmi->hdmicore_regs); 2325 2326 vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1); 2327 if (IS_ERR(vc4_hdmi->hd_regs)) 2328 return PTR_ERR(vc4_hdmi->hd_regs); 2329 2330 ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD); 2331 if (ret) 2332 return ret; 2333 2334 ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI); 2335 if (ret) 2336 return ret; 2337 2338 vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel"); 2339 if (IS_ERR(vc4_hdmi->pixel_clock)) { 2340 ret = PTR_ERR(vc4_hdmi->pixel_clock); 2341 if (ret != -EPROBE_DEFER) 2342 DRM_ERROR("Failed to get pixel clock\n"); 2343 return ret; 2344 } 2345 2346 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); 2347 if (IS_ERR(vc4_hdmi->hsm_clock)) { 2348 DRM_ERROR("Failed to get HDMI state machine clock\n"); 2349 return PTR_ERR(vc4_hdmi->hsm_clock); 2350 } 2351 vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock; 2352 vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock; 2353 2354 return 0; 2355 } 2356 2357 static int vc5_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi) 2358 { 2359 struct platform_device *pdev = vc4_hdmi->pdev; 2360 struct device *dev = &pdev->dev; 2361 struct resource *res; 2362 2363 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi"); 2364 if (!res) 2365 return -ENODEV; 2366 2367 vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start, 2368 resource_size(res)); 2369 if (!vc4_hdmi->hdmicore_regs) 2370 return -ENOMEM; 2371 2372 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd"); 2373 if (!res) 2374 return -ENODEV; 2375 2376 vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res)); 2377 if (!vc4_hdmi->hd_regs) 2378 return -ENOMEM; 2379 2380 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec"); 2381 if (!res) 2382 return -ENODEV; 2383 2384 vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res)); 2385 if (!vc4_hdmi->cec_regs) 2386 return -ENOMEM; 2387 2388 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc"); 2389 if (!res) 2390 return -ENODEV; 2391 2392 vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res)); 2393 if (!vc4_hdmi->csc_regs) 2394 return -ENOMEM; 2395 2396 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp"); 2397 if (!res) 2398 return -ENODEV; 2399 2400 vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res)); 2401 if (!vc4_hdmi->dvp_regs) 2402 return -ENOMEM; 2403 2404 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy"); 2405 if (!res) 2406 return -ENODEV; 2407 2408 vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res)); 2409 if (!vc4_hdmi->phy_regs) 2410 return -ENOMEM; 2411 2412 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet"); 2413 if (!res) 2414 return -ENODEV; 2415 2416 vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res)); 2417 if (!vc4_hdmi->ram_regs) 2418 return -ENOMEM; 2419 2420 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm"); 2421 if (!res) 2422 return -ENODEV; 2423 2424 vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res)); 2425 if (!vc4_hdmi->rm_regs) 2426 return -ENOMEM; 2427 2428 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); 2429 if (IS_ERR(vc4_hdmi->hsm_clock)) { 2430 DRM_ERROR("Failed to get HDMI state machine clock\n"); 2431 return PTR_ERR(vc4_hdmi->hsm_clock); 2432 } 2433 2434 vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb"); 2435 if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) { 2436 DRM_ERROR("Failed to get pixel bvb clock\n"); 2437 return PTR_ERR(vc4_hdmi->pixel_bvb_clock); 2438 } 2439 2440 vc4_hdmi->audio_clock = devm_clk_get(dev, "audio"); 2441 if (IS_ERR(vc4_hdmi->audio_clock)) { 2442 DRM_ERROR("Failed to get audio clock\n"); 2443 return PTR_ERR(vc4_hdmi->audio_clock); 2444 } 2445 2446 vc4_hdmi->cec_clock = devm_clk_get(dev, "cec"); 2447 if (IS_ERR(vc4_hdmi->cec_clock)) { 2448 DRM_ERROR("Failed to get CEC clock\n"); 2449 return PTR_ERR(vc4_hdmi->cec_clock); 2450 } 2451 2452 vc4_hdmi->reset = devm_reset_control_get(dev, NULL); 2453 if (IS_ERR(vc4_hdmi->reset)) { 2454 DRM_ERROR("Failed to get HDMI reset line\n"); 2455 return PTR_ERR(vc4_hdmi->reset); 2456 } 2457 2458 return 0; 2459 } 2460 2461 static int __maybe_unused vc4_hdmi_runtime_suspend(struct device *dev) 2462 { 2463 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 2464 2465 clk_disable_unprepare(vc4_hdmi->hsm_clock); 2466 2467 return 0; 2468 } 2469 2470 static int vc4_hdmi_runtime_resume(struct device *dev) 2471 { 2472 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 2473 int ret; 2474 2475 ret = clk_prepare_enable(vc4_hdmi->hsm_clock); 2476 if (ret) 2477 return ret; 2478 2479 return 0; 2480 } 2481 2482 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data) 2483 { 2484 const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev); 2485 struct platform_device *pdev = to_platform_device(dev); 2486 struct drm_device *drm = dev_get_drvdata(master); 2487 struct vc4_hdmi *vc4_hdmi; 2488 struct drm_encoder *encoder; 2489 struct device_node *ddc_node; 2490 int ret; 2491 2492 vc4_hdmi = devm_kzalloc(dev, sizeof(*vc4_hdmi), GFP_KERNEL); 2493 if (!vc4_hdmi) 2494 return -ENOMEM; 2495 mutex_init(&vc4_hdmi->mutex); 2496 spin_lock_init(&vc4_hdmi->hw_lock); 2497 INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq); 2498 2499 dev_set_drvdata(dev, vc4_hdmi); 2500 encoder = &vc4_hdmi->encoder.base.base; 2501 vc4_hdmi->encoder.base.type = variant->encoder_type; 2502 vc4_hdmi->encoder.base.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure; 2503 vc4_hdmi->encoder.base.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable; 2504 vc4_hdmi->encoder.base.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable; 2505 vc4_hdmi->encoder.base.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable; 2506 vc4_hdmi->encoder.base.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown; 2507 vc4_hdmi->pdev = pdev; 2508 vc4_hdmi->variant = variant; 2509 2510 /* 2511 * Since we don't know the state of the controller and its 2512 * display (if any), let's assume it's always enabled. 2513 * vc4_hdmi_disable_scrambling() will thus run at boot, make 2514 * sure it's disabled, and avoid any inconsistency. 2515 */ 2516 vc4_hdmi->scdc_enabled = true; 2517 2518 ret = variant->init_resources(vc4_hdmi); 2519 if (ret) 2520 return ret; 2521 2522 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0); 2523 if (!ddc_node) { 2524 DRM_ERROR("Failed to find ddc node in device tree\n"); 2525 return -ENODEV; 2526 } 2527 2528 vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node); 2529 of_node_put(ddc_node); 2530 if (!vc4_hdmi->ddc) { 2531 DRM_DEBUG("Failed to get ddc i2c adapter by node\n"); 2532 return -EPROBE_DEFER; 2533 } 2534 2535 /* Only use the GPIO HPD pin if present in the DT, otherwise 2536 * we'll use the HDMI core's register. 2537 */ 2538 vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN); 2539 if (IS_ERR(vc4_hdmi->hpd_gpio)) { 2540 ret = PTR_ERR(vc4_hdmi->hpd_gpio); 2541 goto err_put_ddc; 2542 } 2543 2544 vc4_hdmi->disable_wifi_frequencies = 2545 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence"); 2546 2547 if (variant->max_pixel_clock == 600000000) { 2548 struct vc4_dev *vc4 = to_vc4_dev(drm); 2549 long max_rate = clk_round_rate(vc4->hvs->core_clk, 550000000); 2550 2551 if (max_rate < 550000000) 2552 vc4_hdmi->disable_4kp60 = true; 2553 } 2554 2555 /* 2556 * If we boot without any cable connected to the HDMI connector, 2557 * the firmware will skip the HSM initialization and leave it 2558 * with a rate of 0, resulting in a bus lockup when we're 2559 * accessing the registers even if it's enabled. 2560 * 2561 * Let's put a sensible default at runtime_resume so that we 2562 * don't end up in this situation. 2563 */ 2564 ret = clk_set_min_rate(vc4_hdmi->hsm_clock, HSM_MIN_CLOCK_FREQ); 2565 if (ret) 2566 goto err_put_ddc; 2567 2568 /* 2569 * We need to have the device powered up at this point to call 2570 * our reset hook and for the CEC init. 2571 */ 2572 ret = vc4_hdmi_runtime_resume(dev); 2573 if (ret) 2574 goto err_put_ddc; 2575 2576 pm_runtime_get_noresume(dev); 2577 pm_runtime_set_active(dev); 2578 pm_runtime_enable(dev); 2579 2580 if (vc4_hdmi->variant->reset) 2581 vc4_hdmi->variant->reset(vc4_hdmi); 2582 2583 if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") || 2584 of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1")) && 2585 HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) { 2586 clk_prepare_enable(vc4_hdmi->pixel_clock); 2587 clk_prepare_enable(vc4_hdmi->hsm_clock); 2588 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock); 2589 } 2590 2591 drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS); 2592 drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs); 2593 2594 ret = vc4_hdmi_connector_init(drm, vc4_hdmi); 2595 if (ret) 2596 goto err_destroy_encoder; 2597 2598 ret = vc4_hdmi_hotplug_init(vc4_hdmi); 2599 if (ret) 2600 goto err_destroy_conn; 2601 2602 ret = vc4_hdmi_cec_init(vc4_hdmi); 2603 if (ret) 2604 goto err_free_hotplug; 2605 2606 ret = vc4_hdmi_audio_init(vc4_hdmi); 2607 if (ret) 2608 goto err_free_cec; 2609 2610 vc4_debugfs_add_file(drm, variant->debugfs_name, 2611 vc4_hdmi_debugfs_regs, 2612 vc4_hdmi); 2613 2614 pm_runtime_put_sync(dev); 2615 2616 return 0; 2617 2618 err_free_cec: 2619 vc4_hdmi_cec_exit(vc4_hdmi); 2620 err_free_hotplug: 2621 vc4_hdmi_hotplug_exit(vc4_hdmi); 2622 err_destroy_conn: 2623 vc4_hdmi_connector_destroy(&vc4_hdmi->connector); 2624 err_destroy_encoder: 2625 drm_encoder_cleanup(encoder); 2626 pm_runtime_put_sync(dev); 2627 pm_runtime_disable(dev); 2628 err_put_ddc: 2629 put_device(&vc4_hdmi->ddc->dev); 2630 2631 return ret; 2632 } 2633 2634 static void vc4_hdmi_unbind(struct device *dev, struct device *master, 2635 void *data) 2636 { 2637 struct vc4_hdmi *vc4_hdmi; 2638 2639 /* 2640 * ASoC makes it a bit hard to retrieve a pointer to the 2641 * vc4_hdmi structure. Registering the card will overwrite our 2642 * device drvdata with a pointer to the snd_soc_card structure, 2643 * which can then be used to retrieve whatever drvdata we want 2644 * to associate. 2645 * 2646 * However, that doesn't fly in the case where we wouldn't 2647 * register an ASoC card (because of an old DT that is missing 2648 * the dmas properties for example), then the card isn't 2649 * registered and the device drvdata wouldn't be set. 2650 * 2651 * We can deal with both cases by making sure a snd_soc_card 2652 * pointer and a vc4_hdmi structure are pointing to the same 2653 * memory address, so we can treat them indistinctly without any 2654 * issue. 2655 */ 2656 BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0); 2657 BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0); 2658 vc4_hdmi = dev_get_drvdata(dev); 2659 2660 kfree(vc4_hdmi->hdmi_regset.regs); 2661 kfree(vc4_hdmi->hd_regset.regs); 2662 2663 vc4_hdmi_cec_exit(vc4_hdmi); 2664 vc4_hdmi_hotplug_exit(vc4_hdmi); 2665 vc4_hdmi_connector_destroy(&vc4_hdmi->connector); 2666 drm_encoder_cleanup(&vc4_hdmi->encoder.base.base); 2667 2668 pm_runtime_disable(dev); 2669 2670 put_device(&vc4_hdmi->ddc->dev); 2671 } 2672 2673 static const struct component_ops vc4_hdmi_ops = { 2674 .bind = vc4_hdmi_bind, 2675 .unbind = vc4_hdmi_unbind, 2676 }; 2677 2678 static int vc4_hdmi_dev_probe(struct platform_device *pdev) 2679 { 2680 return component_add(&pdev->dev, &vc4_hdmi_ops); 2681 } 2682 2683 static int vc4_hdmi_dev_remove(struct platform_device *pdev) 2684 { 2685 component_del(&pdev->dev, &vc4_hdmi_ops); 2686 return 0; 2687 } 2688 2689 static const struct vc4_hdmi_variant bcm2835_variant = { 2690 .encoder_type = VC4_ENCODER_TYPE_HDMI0, 2691 .debugfs_name = "hdmi_regs", 2692 .card_name = "vc4-hdmi", 2693 .max_pixel_clock = 162000000, 2694 .registers = vc4_hdmi_fields, 2695 .num_registers = ARRAY_SIZE(vc4_hdmi_fields), 2696 2697 .init_resources = vc4_hdmi_init_resources, 2698 .csc_setup = vc4_hdmi_csc_setup, 2699 .reset = vc4_hdmi_reset, 2700 .set_timings = vc4_hdmi_set_timings, 2701 .phy_init = vc4_hdmi_phy_init, 2702 .phy_disable = vc4_hdmi_phy_disable, 2703 .phy_rng_enable = vc4_hdmi_phy_rng_enable, 2704 .phy_rng_disable = vc4_hdmi_phy_rng_disable, 2705 .channel_map = vc4_hdmi_channel_map, 2706 .supports_hdr = false, 2707 }; 2708 2709 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = { 2710 .encoder_type = VC4_ENCODER_TYPE_HDMI0, 2711 .debugfs_name = "hdmi0_regs", 2712 .card_name = "vc4-hdmi-0", 2713 .max_pixel_clock = 600000000, 2714 .registers = vc5_hdmi_hdmi0_fields, 2715 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi0_fields), 2716 .phy_lane_mapping = { 2717 PHY_LANE_0, 2718 PHY_LANE_1, 2719 PHY_LANE_2, 2720 PHY_LANE_CK, 2721 }, 2722 .unsupported_odd_h_timings = true, 2723 .external_irq_controller = true, 2724 2725 .init_resources = vc5_hdmi_init_resources, 2726 .csc_setup = vc5_hdmi_csc_setup, 2727 .reset = vc5_hdmi_reset, 2728 .set_timings = vc5_hdmi_set_timings, 2729 .phy_init = vc5_hdmi_phy_init, 2730 .phy_disable = vc5_hdmi_phy_disable, 2731 .phy_rng_enable = vc5_hdmi_phy_rng_enable, 2732 .phy_rng_disable = vc5_hdmi_phy_rng_disable, 2733 .channel_map = vc5_hdmi_channel_map, 2734 .supports_hdr = true, 2735 }; 2736 2737 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = { 2738 .encoder_type = VC4_ENCODER_TYPE_HDMI1, 2739 .debugfs_name = "hdmi1_regs", 2740 .card_name = "vc4-hdmi-1", 2741 .max_pixel_clock = HDMI_14_MAX_TMDS_CLK, 2742 .registers = vc5_hdmi_hdmi1_fields, 2743 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi1_fields), 2744 .phy_lane_mapping = { 2745 PHY_LANE_1, 2746 PHY_LANE_0, 2747 PHY_LANE_CK, 2748 PHY_LANE_2, 2749 }, 2750 .unsupported_odd_h_timings = true, 2751 .external_irq_controller = true, 2752 2753 .init_resources = vc5_hdmi_init_resources, 2754 .csc_setup = vc5_hdmi_csc_setup, 2755 .reset = vc5_hdmi_reset, 2756 .set_timings = vc5_hdmi_set_timings, 2757 .phy_init = vc5_hdmi_phy_init, 2758 .phy_disable = vc5_hdmi_phy_disable, 2759 .phy_rng_enable = vc5_hdmi_phy_rng_enable, 2760 .phy_rng_disable = vc5_hdmi_phy_rng_disable, 2761 .channel_map = vc5_hdmi_channel_map, 2762 .supports_hdr = true, 2763 }; 2764 2765 static const struct of_device_id vc4_hdmi_dt_match[] = { 2766 { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant }, 2767 { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant }, 2768 { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant }, 2769 {} 2770 }; 2771 2772 static const struct dev_pm_ops vc4_hdmi_pm_ops = { 2773 SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend, 2774 vc4_hdmi_runtime_resume, 2775 NULL) 2776 }; 2777 2778 struct platform_driver vc4_hdmi_driver = { 2779 .probe = vc4_hdmi_dev_probe, 2780 .remove = vc4_hdmi_dev_remove, 2781 .driver = { 2782 .name = "vc4_hdmi", 2783 .of_match_table = vc4_hdmi_dt_match, 2784 .pm = &vc4_hdmi_pm_ops, 2785 }, 2786 }; 2787