1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 Broadcom 4 * Copyright (c) 2014 The Linux Foundation. All rights reserved. 5 * Copyright (C) 2013 Red Hat 6 * Author: Rob Clark <robdclark@gmail.com> 7 */ 8 9 /** 10 * DOC: VC4 Falcon HDMI module 11 * 12 * The HDMI core has a state machine and a PHY. On BCM2835, most of 13 * the unit operates off of the HSM clock from CPRMAN. It also 14 * internally uses the PLLH_PIX clock for the PHY. 15 * 16 * HDMI infoframes are kept within a small packet ram, where each 17 * packet can be individually enabled for including in a frame. 18 * 19 * HDMI audio is implemented entirely within the HDMI IP block. A 20 * register in the HDMI encoder takes SPDIF frames from the DMA engine 21 * and transfers them over an internal MAI (multi-channel audio 22 * interconnect) bus to the encoder side for insertion into the video 23 * blank regions. 24 * 25 * The driver's HDMI encoder does not yet support power management. 26 * The HDMI encoder's power domain and the HSM/pixel clocks are kept 27 * continuously running, and only the HDMI logic and packet ram are 28 * powered off/on at disable/enable time. 29 * 30 * The driver does not yet support CEC control, though the HDMI 31 * encoder block has CEC support. 32 */ 33 34 #include <drm/drm_atomic_helper.h> 35 #include <drm/drm_edid.h> 36 #include <drm/drm_probe_helper.h> 37 #include <drm/drm_simple_kms_helper.h> 38 #include <linux/clk.h> 39 #include <linux/component.h> 40 #include <linux/i2c.h> 41 #include <linux/of_address.h> 42 #include <linux/of_gpio.h> 43 #include <linux/of_platform.h> 44 #include <linux/pm_runtime.h> 45 #include <linux/rational.h> 46 #include <linux/reset.h> 47 #include <sound/dmaengine_pcm.h> 48 #include <sound/pcm_drm_eld.h> 49 #include <sound/pcm_params.h> 50 #include <sound/soc.h> 51 #include "media/cec.h" 52 #include "vc4_drv.h" 53 #include "vc4_hdmi.h" 54 #include "vc4_hdmi_regs.h" 55 #include "vc4_regs.h" 56 57 #define VC5_HDMI_HORZA_HFP_SHIFT 16 58 #define VC5_HDMI_HORZA_HFP_MASK VC4_MASK(28, 16) 59 #define VC5_HDMI_HORZA_VPOS BIT(15) 60 #define VC5_HDMI_HORZA_HPOS BIT(14) 61 #define VC5_HDMI_HORZA_HAP_SHIFT 0 62 #define VC5_HDMI_HORZA_HAP_MASK VC4_MASK(13, 0) 63 64 #define VC5_HDMI_HORZB_HBP_SHIFT 16 65 #define VC5_HDMI_HORZB_HBP_MASK VC4_MASK(26, 16) 66 #define VC5_HDMI_HORZB_HSP_SHIFT 0 67 #define VC5_HDMI_HORZB_HSP_MASK VC4_MASK(10, 0) 68 69 #define VC5_HDMI_VERTA_VSP_SHIFT 24 70 #define VC5_HDMI_VERTA_VSP_MASK VC4_MASK(28, 24) 71 #define VC5_HDMI_VERTA_VFP_SHIFT 16 72 #define VC5_HDMI_VERTA_VFP_MASK VC4_MASK(22, 16) 73 #define VC5_HDMI_VERTA_VAL_SHIFT 0 74 #define VC5_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0) 75 76 #define VC5_HDMI_VERTB_VSPO_SHIFT 16 77 #define VC5_HDMI_VERTB_VSPO_MASK VC4_MASK(29, 16) 78 79 # define VC4_HD_M_SW_RST BIT(2) 80 # define VC4_HD_M_ENABLE BIT(0) 81 82 #define CEC_CLOCK_FREQ 40000 83 #define VC4_HSM_MID_CLOCK 149985000 84 85 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused) 86 { 87 struct drm_info_node *node = (struct drm_info_node *)m->private; 88 struct vc4_hdmi *vc4_hdmi = node->info_ent->data; 89 struct drm_printer p = drm_seq_file_printer(m); 90 91 drm_print_regset32(&p, &vc4_hdmi->hdmi_regset); 92 drm_print_regset32(&p, &vc4_hdmi->hd_regset); 93 94 return 0; 95 } 96 97 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi) 98 { 99 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST); 100 udelay(1); 101 HDMI_WRITE(HDMI_M_CTL, 0); 102 103 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE); 104 105 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 106 VC4_HDMI_SW_RESET_HDMI | 107 VC4_HDMI_SW_RESET_FORMAT_DETECT); 108 109 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0); 110 } 111 112 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi) 113 { 114 reset_control_reset(vc4_hdmi->reset); 115 116 HDMI_WRITE(HDMI_DVP_CTL, 0); 117 118 HDMI_WRITE(HDMI_CLOCK_STOP, 119 HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL); 120 } 121 122 static enum drm_connector_status 123 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force) 124 { 125 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 126 127 if (vc4_hdmi->hpd_gpio) { 128 if (gpio_get_value_cansleep(vc4_hdmi->hpd_gpio) ^ 129 vc4_hdmi->hpd_active_low) 130 return connector_status_connected; 131 cec_phys_addr_invalidate(vc4_hdmi->cec_adap); 132 return connector_status_disconnected; 133 } 134 135 if (drm_probe_ddc(vc4_hdmi->ddc)) 136 return connector_status_connected; 137 138 if (HDMI_READ(HDMI_HOTPLUG) & VC4_HDMI_HOTPLUG_CONNECTED) 139 return connector_status_connected; 140 cec_phys_addr_invalidate(vc4_hdmi->cec_adap); 141 return connector_status_disconnected; 142 } 143 144 static void vc4_hdmi_connector_destroy(struct drm_connector *connector) 145 { 146 drm_connector_unregister(connector); 147 drm_connector_cleanup(connector); 148 } 149 150 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector) 151 { 152 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 153 struct vc4_hdmi_encoder *vc4_encoder = &vc4_hdmi->encoder; 154 int ret = 0; 155 struct edid *edid; 156 157 edid = drm_get_edid(connector, vc4_hdmi->ddc); 158 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid); 159 if (!edid) 160 return -ENODEV; 161 162 vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid); 163 164 drm_connector_update_edid_property(connector, edid); 165 ret = drm_add_edid_modes(connector, edid); 166 kfree(edid); 167 168 return ret; 169 } 170 171 static void vc4_hdmi_connector_reset(struct drm_connector *connector) 172 { 173 drm_atomic_helper_connector_reset(connector); 174 drm_atomic_helper_connector_tv_reset(connector); 175 } 176 177 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = { 178 .detect = vc4_hdmi_connector_detect, 179 .fill_modes = drm_helper_probe_single_connector_modes, 180 .destroy = vc4_hdmi_connector_destroy, 181 .reset = vc4_hdmi_connector_reset, 182 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 183 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 184 }; 185 186 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = { 187 .get_modes = vc4_hdmi_connector_get_modes, 188 }; 189 190 static int vc4_hdmi_connector_init(struct drm_device *dev, 191 struct vc4_hdmi *vc4_hdmi) 192 { 193 struct drm_connector *connector = &vc4_hdmi->connector; 194 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base; 195 int ret; 196 197 drm_connector_init_with_ddc(dev, connector, 198 &vc4_hdmi_connector_funcs, 199 DRM_MODE_CONNECTOR_HDMIA, 200 vc4_hdmi->ddc); 201 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs); 202 203 /* Create and attach TV margin props to this connector. */ 204 ret = drm_mode_create_tv_margin_properties(dev); 205 if (ret) 206 return ret; 207 208 drm_connector_attach_tv_margin_properties(connector); 209 210 connector->polled = (DRM_CONNECTOR_POLL_CONNECT | 211 DRM_CONNECTOR_POLL_DISCONNECT); 212 213 connector->interlace_allowed = 1; 214 connector->doublescan_allowed = 0; 215 216 drm_connector_attach_encoder(connector, encoder); 217 218 return 0; 219 } 220 221 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder, 222 enum hdmi_infoframe_type type) 223 { 224 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 225 u32 packet_id = type - 0x80; 226 227 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 228 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id)); 229 230 return wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) & 231 BIT(packet_id)), 100); 232 } 233 234 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder, 235 union hdmi_infoframe *frame) 236 { 237 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 238 u32 packet_id = frame->any.type - 0x80; 239 const struct vc4_hdmi_register *ram_packet_start = 240 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START]; 241 u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id; 242 void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi, 243 ram_packet_start->reg); 244 uint8_t buffer[VC4_HDMI_PACKET_STRIDE]; 245 ssize_t len, i; 246 int ret; 247 248 WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) & 249 VC4_HDMI_RAM_PACKET_ENABLE), 250 "Packet RAM has to be on to store the packet."); 251 252 len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer)); 253 if (len < 0) 254 return; 255 256 ret = vc4_hdmi_stop_packet(encoder, frame->any.type); 257 if (ret) { 258 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret); 259 return; 260 } 261 262 for (i = 0; i < len; i += 7) { 263 writel(buffer[i + 0] << 0 | 264 buffer[i + 1] << 8 | 265 buffer[i + 2] << 16, 266 base + packet_reg); 267 packet_reg += 4; 268 269 writel(buffer[i + 3] << 0 | 270 buffer[i + 4] << 8 | 271 buffer[i + 5] << 16 | 272 buffer[i + 6] << 24, 273 base + packet_reg); 274 packet_reg += 4; 275 } 276 277 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 278 HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id)); 279 ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) & 280 BIT(packet_id)), 100); 281 if (ret) 282 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret); 283 } 284 285 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder) 286 { 287 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 288 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 289 struct drm_connector *connector = &vc4_hdmi->connector; 290 struct drm_connector_state *cstate = connector->state; 291 struct drm_crtc *crtc = encoder->crtc; 292 const struct drm_display_mode *mode = &crtc->state->adjusted_mode; 293 union hdmi_infoframe frame; 294 int ret; 295 296 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, 297 connector, mode); 298 if (ret < 0) { 299 DRM_ERROR("couldn't fill AVI infoframe\n"); 300 return; 301 } 302 303 drm_hdmi_avi_infoframe_quant_range(&frame.avi, 304 connector, mode, 305 vc4_encoder->limited_rgb_range ? 306 HDMI_QUANTIZATION_RANGE_LIMITED : 307 HDMI_QUANTIZATION_RANGE_FULL); 308 309 drm_hdmi_avi_infoframe_bars(&frame.avi, cstate); 310 311 vc4_hdmi_write_infoframe(encoder, &frame); 312 } 313 314 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder) 315 { 316 union hdmi_infoframe frame; 317 int ret; 318 319 ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore"); 320 if (ret < 0) { 321 DRM_ERROR("couldn't fill SPD infoframe\n"); 322 return; 323 } 324 325 frame.spd.sdi = HDMI_SPD_SDI_PC; 326 327 vc4_hdmi_write_infoframe(encoder, &frame); 328 } 329 330 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder) 331 { 332 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 333 union hdmi_infoframe frame; 334 335 hdmi_audio_infoframe_init(&frame.audio); 336 337 frame.audio.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM; 338 frame.audio.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM; 339 frame.audio.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM; 340 frame.audio.channels = vc4_hdmi->audio.channels; 341 342 vc4_hdmi_write_infoframe(encoder, &frame); 343 } 344 345 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder) 346 { 347 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 348 349 vc4_hdmi_set_avi_infoframe(encoder); 350 vc4_hdmi_set_spd_infoframe(encoder); 351 /* 352 * If audio was streaming, then we need to reenabled the audio 353 * infoframe here during encoder_enable. 354 */ 355 if (vc4_hdmi->audio.streaming) 356 vc4_hdmi_set_audio_infoframe(encoder); 357 } 358 359 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder) 360 { 361 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 362 363 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0); 364 365 HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | 366 VC4_HD_VID_CTL_CLRRGB | VC4_HD_VID_CTL_CLRSYNC); 367 368 HDMI_WRITE(HDMI_VID_CTL, 369 HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX); 370 } 371 372 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder) 373 { 374 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 375 int ret; 376 377 if (vc4_hdmi->variant->phy_disable) 378 vc4_hdmi->variant->phy_disable(vc4_hdmi); 379 380 HDMI_WRITE(HDMI_VID_CTL, 381 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE); 382 383 clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock); 384 clk_disable_unprepare(vc4_hdmi->hsm_clock); 385 clk_disable_unprepare(vc4_hdmi->pixel_clock); 386 387 ret = pm_runtime_put(&vc4_hdmi->pdev->dev); 388 if (ret < 0) 389 DRM_ERROR("Failed to release power domain: %d\n", ret); 390 } 391 392 static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder) 393 { 394 } 395 396 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable) 397 { 398 u32 csc_ctl; 399 400 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR, 401 VC4_HD_CSC_CTL_ORDER); 402 403 if (enable) { 404 /* CEA VICs other than #1 requre limited range RGB 405 * output unless overridden by an AVI infoframe. 406 * Apply a colorspace conversion to squash 0-255 down 407 * to 16-235. The matrix here is: 408 * 409 * [ 0 0 0.8594 16] 410 * [ 0 0.8594 0 16] 411 * [ 0.8594 0 0 16] 412 * [ 0 0 0 1] 413 */ 414 csc_ctl |= VC4_HD_CSC_CTL_ENABLE; 415 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC; 416 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM, 417 VC4_HD_CSC_CTL_MODE); 418 419 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000); 420 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0); 421 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000); 422 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000); 423 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0); 424 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000); 425 } 426 427 /* The RGB order applies even when CSC is disabled. */ 428 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl); 429 } 430 431 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable) 432 { 433 u32 csc_ctl; 434 435 csc_ctl = 0x07; /* RGB_CONVERT_MODE = custom matrix, || USE_RGB_TO_YCBCR */ 436 437 if (enable) { 438 /* CEA VICs other than #1 requre limited range RGB 439 * output unless overridden by an AVI infoframe. 440 * Apply a colorspace conversion to squash 0-255 down 441 * to 16-235. The matrix here is: 442 * 443 * [ 0.8594 0 0 16] 444 * [ 0 0.8594 0 16] 445 * [ 0 0 0.8594 16] 446 * [ 0 0 0 1] 447 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets 448 */ 449 HDMI_WRITE(HDMI_CSC_12_11, (0x0000 << 16) | 0x1b80); 450 HDMI_WRITE(HDMI_CSC_14_13, (0x0400 << 16) | 0x0000); 451 HDMI_WRITE(HDMI_CSC_22_21, (0x1b80 << 16) | 0x0000); 452 HDMI_WRITE(HDMI_CSC_24_23, (0x0400 << 16) | 0x0000); 453 HDMI_WRITE(HDMI_CSC_32_31, (0x0000 << 16) | 0x0000); 454 HDMI_WRITE(HDMI_CSC_34_33, (0x0400 << 16) | 0x1b80); 455 } else { 456 /* Still use the matrix for full range, but make it unity. 457 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets 458 */ 459 HDMI_WRITE(HDMI_CSC_12_11, (0x0000 << 16) | 0x2000); 460 HDMI_WRITE(HDMI_CSC_14_13, (0x0000 << 16) | 0x0000); 461 HDMI_WRITE(HDMI_CSC_22_21, (0x2000 << 16) | 0x0000); 462 HDMI_WRITE(HDMI_CSC_24_23, (0x0000 << 16) | 0x0000); 463 HDMI_WRITE(HDMI_CSC_32_31, (0x0000 << 16) | 0x0000); 464 HDMI_WRITE(HDMI_CSC_34_33, (0x0000 << 16) | 0x2000); 465 } 466 467 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl); 468 } 469 470 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi, 471 struct drm_display_mode *mode) 472 { 473 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 474 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 475 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 476 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 477 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 478 VC4_HDMI_VERTA_VSP) | 479 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 480 VC4_HDMI_VERTA_VFP) | 481 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL)); 482 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 483 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end, 484 VC4_HDMI_VERTB_VBP)); 485 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 486 VC4_SET_FIELD(mode->crtc_vtotal - 487 mode->crtc_vsync_end - 488 interlaced, 489 VC4_HDMI_VERTB_VBP)); 490 491 HDMI_WRITE(HDMI_HORZA, 492 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) | 493 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) | 494 VC4_SET_FIELD(mode->hdisplay * pixel_rep, 495 VC4_HDMI_HORZA_HAP)); 496 497 HDMI_WRITE(HDMI_HORZB, 498 VC4_SET_FIELD((mode->htotal - 499 mode->hsync_end) * pixel_rep, 500 VC4_HDMI_HORZB_HBP) | 501 VC4_SET_FIELD((mode->hsync_end - 502 mode->hsync_start) * pixel_rep, 503 VC4_HDMI_HORZB_HSP) | 504 VC4_SET_FIELD((mode->hsync_start - 505 mode->hdisplay) * pixel_rep, 506 VC4_HDMI_HORZB_HFP)); 507 508 HDMI_WRITE(HDMI_VERTA0, verta); 509 HDMI_WRITE(HDMI_VERTA1, verta); 510 511 HDMI_WRITE(HDMI_VERTB0, vertb_even); 512 HDMI_WRITE(HDMI_VERTB1, vertb); 513 } 514 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi, 515 struct drm_display_mode *mode) 516 { 517 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 518 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 519 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 520 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 521 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 522 VC5_HDMI_VERTA_VSP) | 523 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 524 VC5_HDMI_VERTA_VFP) | 525 VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL)); 526 u32 vertb = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) | 527 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end, 528 VC4_HDMI_VERTB_VBP)); 529 u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) | 530 VC4_SET_FIELD(mode->crtc_vtotal - 531 mode->crtc_vsync_end - 532 interlaced, 533 VC4_HDMI_VERTB_VBP)); 534 535 HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, 0x354021); 536 HDMI_WRITE(HDMI_HORZA, 537 (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) | 538 (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) | 539 VC4_SET_FIELD(mode->hdisplay * pixel_rep, 540 VC5_HDMI_HORZA_HAP) | 541 VC4_SET_FIELD((mode->hsync_start - 542 mode->hdisplay) * pixel_rep, 543 VC5_HDMI_HORZA_HFP)); 544 545 HDMI_WRITE(HDMI_HORZB, 546 VC4_SET_FIELD((mode->htotal - 547 mode->hsync_end) * pixel_rep, 548 VC5_HDMI_HORZB_HBP) | 549 VC4_SET_FIELD((mode->hsync_end - 550 mode->hsync_start) * pixel_rep, 551 VC5_HDMI_HORZB_HSP)); 552 553 HDMI_WRITE(HDMI_VERTA0, verta); 554 HDMI_WRITE(HDMI_VERTA1, verta); 555 556 HDMI_WRITE(HDMI_VERTB0, vertb_even); 557 HDMI_WRITE(HDMI_VERTB1, vertb); 558 559 HDMI_WRITE(HDMI_CLOCK_STOP, 0); 560 } 561 562 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi) 563 { 564 u32 drift; 565 int ret; 566 567 drift = HDMI_READ(HDMI_FIFO_CTL); 568 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK; 569 570 HDMI_WRITE(HDMI_FIFO_CTL, 571 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 572 HDMI_WRITE(HDMI_FIFO_CTL, 573 drift | VC4_HDMI_FIFO_CTL_RECENTER); 574 usleep_range(1000, 1100); 575 HDMI_WRITE(HDMI_FIFO_CTL, 576 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 577 HDMI_WRITE(HDMI_FIFO_CTL, 578 drift | VC4_HDMI_FIFO_CTL_RECENTER); 579 580 ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) & 581 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1); 582 WARN_ONCE(ret, "Timeout waiting for " 583 "VC4_HDMI_FIFO_CTL_RECENTER_DONE"); 584 } 585 586 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder) 587 { 588 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; 589 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 590 unsigned long pixel_rate, hsm_rate; 591 int ret; 592 593 ret = pm_runtime_get_sync(&vc4_hdmi->pdev->dev); 594 if (ret < 0) { 595 DRM_ERROR("Failed to retain power domain: %d\n", ret); 596 return; 597 } 598 599 pixel_rate = mode->clock * 1000 * ((mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1); 600 ret = clk_set_rate(vc4_hdmi->pixel_clock, pixel_rate); 601 if (ret) { 602 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret); 603 return; 604 } 605 606 ret = clk_prepare_enable(vc4_hdmi->pixel_clock); 607 if (ret) { 608 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret); 609 return; 610 } 611 612 /* 613 * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must 614 * be faster than pixel clock, infinitesimally faster, tested in 615 * simulation. Otherwise, exact value is unimportant for HDMI 616 * operation." This conflicts with bcm2835's vc4 documentation, which 617 * states HSM's clock has to be at least 108% of the pixel clock. 618 * 619 * Real life tests reveal that vc4's firmware statement holds up, and 620 * users are able to use pixel clocks closer to HSM's, namely for 621 * 1920x1200@60Hz. So it was decided to have leave a 1% margin between 622 * both clocks. Which, for RPi0-3 implies a maximum pixel clock of 623 * 162MHz. 624 * 625 * Additionally, the AXI clock needs to be at least 25% of 626 * pixel clock, but HSM ends up being the limiting factor. 627 */ 628 hsm_rate = max_t(unsigned long, 120000000, (pixel_rate / 100) * 101); 629 ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate); 630 if (ret) { 631 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret); 632 return; 633 } 634 635 ret = clk_prepare_enable(vc4_hdmi->hsm_clock); 636 if (ret) { 637 DRM_ERROR("Failed to turn on HSM clock: %d\n", ret); 638 clk_disable_unprepare(vc4_hdmi->pixel_clock); 639 return; 640 } 641 642 /* 643 * FIXME: When the pixel freq is 594MHz (4k60), this needs to be setup 644 * at 300MHz. 645 */ 646 ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, 647 (hsm_rate > VC4_HSM_MID_CLOCK ? 150000000 : 75000000)); 648 if (ret) { 649 DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret); 650 clk_disable_unprepare(vc4_hdmi->hsm_clock); 651 clk_disable_unprepare(vc4_hdmi->pixel_clock); 652 return; 653 } 654 655 ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock); 656 if (ret) { 657 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret); 658 clk_disable_unprepare(vc4_hdmi->hsm_clock); 659 clk_disable_unprepare(vc4_hdmi->pixel_clock); 660 return; 661 } 662 663 if (vc4_hdmi->variant->reset) 664 vc4_hdmi->variant->reset(vc4_hdmi); 665 666 if (vc4_hdmi->variant->phy_init) 667 vc4_hdmi->variant->phy_init(vc4_hdmi, mode); 668 669 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 670 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 671 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT | 672 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS); 673 674 if (vc4_hdmi->variant->set_timings) 675 vc4_hdmi->variant->set_timings(vc4_hdmi, mode); 676 } 677 678 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder) 679 { 680 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; 681 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 682 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 683 684 if (vc4_encoder->hdmi_monitor && 685 drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_LIMITED) { 686 if (vc4_hdmi->variant->csc_setup) 687 vc4_hdmi->variant->csc_setup(vc4_hdmi, true); 688 689 vc4_encoder->limited_rgb_range = true; 690 } else { 691 if (vc4_hdmi->variant->csc_setup) 692 vc4_hdmi->variant->csc_setup(vc4_hdmi, false); 693 694 vc4_encoder->limited_rgb_range = false; 695 } 696 697 HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N); 698 } 699 700 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder) 701 { 702 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; 703 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 704 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 705 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 706 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 707 int ret; 708 709 HDMI_WRITE(HDMI_VID_CTL, 710 VC4_HD_VID_CTL_ENABLE | 711 VC4_HD_VID_CTL_UNDERFLOW_ENABLE | 712 VC4_HD_VID_CTL_FRAME_COUNTER_RESET | 713 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) | 714 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW)); 715 716 HDMI_WRITE(HDMI_VID_CTL, 717 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX); 718 719 if (vc4_encoder->hdmi_monitor) { 720 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 721 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 722 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 723 724 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 725 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000); 726 WARN_ONCE(ret, "Timeout waiting for " 727 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 728 } else { 729 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 730 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & 731 ~(VC4_HDMI_RAM_PACKET_ENABLE)); 732 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 733 HDMI_READ(HDMI_SCHEDULER_CONTROL) & 734 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 735 736 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 737 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000); 738 WARN_ONCE(ret, "Timeout waiting for " 739 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 740 } 741 742 if (vc4_encoder->hdmi_monitor) { 743 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 744 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE)); 745 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 746 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 747 VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT); 748 749 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 750 VC4_HDMI_RAM_PACKET_ENABLE); 751 752 vc4_hdmi_set_infoframes(encoder); 753 } 754 755 vc4_hdmi_recenter_fifo(vc4_hdmi); 756 } 757 758 static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder) 759 { 760 } 761 762 static enum drm_mode_status 763 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder, 764 const struct drm_display_mode *mode) 765 { 766 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 767 768 if ((mode->clock * 1000) > vc4_hdmi->variant->max_pixel_clock) 769 return MODE_CLOCK_HIGH; 770 771 return MODE_OK; 772 } 773 774 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = { 775 .mode_valid = vc4_hdmi_encoder_mode_valid, 776 .disable = vc4_hdmi_encoder_disable, 777 .enable = vc4_hdmi_encoder_enable, 778 }; 779 780 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask) 781 { 782 int i; 783 u32 channel_map = 0; 784 785 for (i = 0; i < 8; i++) { 786 if (channel_mask & BIT(i)) 787 channel_map |= i << (3 * i); 788 } 789 return channel_map; 790 } 791 792 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask) 793 { 794 int i; 795 u32 channel_map = 0; 796 797 for (i = 0; i < 8; i++) { 798 if (channel_mask & BIT(i)) 799 channel_map |= i << (4 * i); 800 } 801 return channel_map; 802 } 803 804 /* HDMI audio codec callbacks */ 805 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi) 806 { 807 u32 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock); 808 unsigned long n, m; 809 810 rational_best_approximation(hsm_clock, vc4_hdmi->audio.samplerate, 811 VC4_HD_MAI_SMP_N_MASK >> 812 VC4_HD_MAI_SMP_N_SHIFT, 813 (VC4_HD_MAI_SMP_M_MASK >> 814 VC4_HD_MAI_SMP_M_SHIFT) + 1, 815 &n, &m); 816 817 HDMI_WRITE(HDMI_MAI_SMP, 818 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) | 819 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M)); 820 } 821 822 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi) 823 { 824 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base; 825 struct drm_crtc *crtc = encoder->crtc; 826 const struct drm_display_mode *mode = &crtc->state->adjusted_mode; 827 u32 samplerate = vc4_hdmi->audio.samplerate; 828 u32 n, cts; 829 u64 tmp; 830 831 n = 128 * samplerate / 1000; 832 tmp = (u64)(mode->clock * 1000) * n; 833 do_div(tmp, 128 * samplerate); 834 cts = tmp; 835 836 HDMI_WRITE(HDMI_CRP_CFG, 837 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN | 838 VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N)); 839 840 /* 841 * We could get slightly more accurate clocks in some cases by 842 * providing a CTS_1 value. The two CTS values are alternated 843 * between based on the period fields 844 */ 845 HDMI_WRITE(HDMI_CTS_0, cts); 846 HDMI_WRITE(HDMI_CTS_1, cts); 847 } 848 849 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai) 850 { 851 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai); 852 853 return snd_soc_card_get_drvdata(card); 854 } 855 856 static int vc4_hdmi_audio_startup(struct snd_pcm_substream *substream, 857 struct snd_soc_dai *dai) 858 { 859 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai); 860 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base; 861 struct drm_connector *connector = &vc4_hdmi->connector; 862 int ret; 863 864 if (vc4_hdmi->audio.substream && vc4_hdmi->audio.substream != substream) 865 return -EINVAL; 866 867 vc4_hdmi->audio.substream = substream; 868 869 /* 870 * If the HDMI encoder hasn't probed, or the encoder is 871 * currently in DVI mode, treat the codec dai as missing. 872 */ 873 if (!encoder->crtc || !(HDMI_READ(HDMI_RAM_PACKET_CONFIG) & 874 VC4_HDMI_RAM_PACKET_ENABLE)) 875 return -ENODEV; 876 877 ret = snd_pcm_hw_constraint_eld(substream->runtime, connector->eld); 878 if (ret) 879 return ret; 880 881 return 0; 882 } 883 884 static int vc4_hdmi_audio_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 885 { 886 return 0; 887 } 888 889 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi) 890 { 891 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base; 892 struct device *dev = &vc4_hdmi->pdev->dev; 893 int ret; 894 895 vc4_hdmi->audio.streaming = false; 896 ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO); 897 if (ret) 898 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret); 899 900 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET); 901 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF); 902 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH); 903 } 904 905 static void vc4_hdmi_audio_shutdown(struct snd_pcm_substream *substream, 906 struct snd_soc_dai *dai) 907 { 908 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai); 909 910 if (substream != vc4_hdmi->audio.substream) 911 return; 912 913 vc4_hdmi_audio_reset(vc4_hdmi); 914 915 vc4_hdmi->audio.substream = NULL; 916 } 917 918 /* HDMI audio codec callbacks */ 919 static int vc4_hdmi_audio_hw_params(struct snd_pcm_substream *substream, 920 struct snd_pcm_hw_params *params, 921 struct snd_soc_dai *dai) 922 { 923 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai); 924 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base; 925 struct device *dev = &vc4_hdmi->pdev->dev; 926 u32 audio_packet_config, channel_mask; 927 u32 channel_map; 928 929 if (substream != vc4_hdmi->audio.substream) 930 return -EINVAL; 931 932 dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__, 933 params_rate(params), params_width(params), 934 params_channels(params)); 935 936 vc4_hdmi->audio.channels = params_channels(params); 937 vc4_hdmi->audio.samplerate = params_rate(params); 938 939 HDMI_WRITE(HDMI_MAI_CTL, 940 VC4_HD_MAI_CTL_RESET | 941 VC4_HD_MAI_CTL_FLUSH | 942 VC4_HD_MAI_CTL_DLATE | 943 VC4_HD_MAI_CTL_ERRORE | 944 VC4_HD_MAI_CTL_ERRORF); 945 946 vc4_hdmi_audio_set_mai_clock(vc4_hdmi); 947 948 /* The B frame identifier should match the value used by alsa-lib (8) */ 949 audio_packet_config = 950 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT | 951 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS | 952 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER); 953 954 channel_mask = GENMASK(vc4_hdmi->audio.channels - 1, 0); 955 audio_packet_config |= VC4_SET_FIELD(channel_mask, 956 VC4_HDMI_AUDIO_PACKET_CEA_MASK); 957 958 /* Set the MAI threshold. This logic mimics the firmware's. */ 959 if (vc4_hdmi->audio.samplerate > 96000) { 960 HDMI_WRITE(HDMI_MAI_THR, 961 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQHIGH) | 962 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW)); 963 } else if (vc4_hdmi->audio.samplerate > 48000) { 964 HDMI_WRITE(HDMI_MAI_THR, 965 VC4_SET_FIELD(0x14, VC4_HD_MAI_THR_DREQHIGH) | 966 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW)); 967 } else { 968 HDMI_WRITE(HDMI_MAI_THR, 969 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) | 970 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) | 971 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQHIGH) | 972 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQLOW)); 973 } 974 975 HDMI_WRITE(HDMI_MAI_CONFIG, 976 VC4_HDMI_MAI_CONFIG_BIT_REVERSE | 977 VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK)); 978 979 channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask); 980 HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map); 981 HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config); 982 vc4_hdmi_set_n_cts(vc4_hdmi); 983 984 vc4_hdmi_set_audio_infoframe(encoder); 985 986 return 0; 987 } 988 989 static int vc4_hdmi_audio_trigger(struct snd_pcm_substream *substream, int cmd, 990 struct snd_soc_dai *dai) 991 { 992 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai); 993 994 switch (cmd) { 995 case SNDRV_PCM_TRIGGER_START: 996 vc4_hdmi->audio.streaming = true; 997 998 if (vc4_hdmi->variant->phy_rng_enable) 999 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi); 1000 1001 HDMI_WRITE(HDMI_MAI_CTL, 1002 VC4_SET_FIELD(vc4_hdmi->audio.channels, 1003 VC4_HD_MAI_CTL_CHNUM) | 1004 VC4_HD_MAI_CTL_ENABLE); 1005 break; 1006 case SNDRV_PCM_TRIGGER_STOP: 1007 HDMI_WRITE(HDMI_MAI_CTL, 1008 VC4_HD_MAI_CTL_DLATE | 1009 VC4_HD_MAI_CTL_ERRORE | 1010 VC4_HD_MAI_CTL_ERRORF); 1011 1012 if (vc4_hdmi->variant->phy_rng_disable) 1013 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi); 1014 1015 vc4_hdmi->audio.streaming = false; 1016 1017 break; 1018 default: 1019 break; 1020 } 1021 1022 return 0; 1023 } 1024 1025 static inline struct vc4_hdmi * 1026 snd_component_to_hdmi(struct snd_soc_component *component) 1027 { 1028 struct snd_soc_card *card = snd_soc_component_get_drvdata(component); 1029 1030 return snd_soc_card_get_drvdata(card); 1031 } 1032 1033 static int vc4_hdmi_audio_eld_ctl_info(struct snd_kcontrol *kcontrol, 1034 struct snd_ctl_elem_info *uinfo) 1035 { 1036 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1037 struct vc4_hdmi *vc4_hdmi = snd_component_to_hdmi(component); 1038 struct drm_connector *connector = &vc4_hdmi->connector; 1039 1040 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 1041 uinfo->count = sizeof(connector->eld); 1042 1043 return 0; 1044 } 1045 1046 static int vc4_hdmi_audio_eld_ctl_get(struct snd_kcontrol *kcontrol, 1047 struct snd_ctl_elem_value *ucontrol) 1048 { 1049 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1050 struct vc4_hdmi *vc4_hdmi = snd_component_to_hdmi(component); 1051 struct drm_connector *connector = &vc4_hdmi->connector; 1052 1053 memcpy(ucontrol->value.bytes.data, connector->eld, 1054 sizeof(connector->eld)); 1055 1056 return 0; 1057 } 1058 1059 static const struct snd_kcontrol_new vc4_hdmi_audio_controls[] = { 1060 { 1061 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1062 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1063 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1064 .name = "ELD", 1065 .info = vc4_hdmi_audio_eld_ctl_info, 1066 .get = vc4_hdmi_audio_eld_ctl_get, 1067 }, 1068 }; 1069 1070 static const struct snd_soc_dapm_widget vc4_hdmi_audio_widgets[] = { 1071 SND_SOC_DAPM_OUTPUT("TX"), 1072 }; 1073 1074 static const struct snd_soc_dapm_route vc4_hdmi_audio_routes[] = { 1075 { "TX", NULL, "Playback" }, 1076 }; 1077 1078 static const struct snd_soc_component_driver vc4_hdmi_audio_component_drv = { 1079 .name = "vc4-hdmi-codec-dai-component", 1080 .controls = vc4_hdmi_audio_controls, 1081 .num_controls = ARRAY_SIZE(vc4_hdmi_audio_controls), 1082 .dapm_widgets = vc4_hdmi_audio_widgets, 1083 .num_dapm_widgets = ARRAY_SIZE(vc4_hdmi_audio_widgets), 1084 .dapm_routes = vc4_hdmi_audio_routes, 1085 .num_dapm_routes = ARRAY_SIZE(vc4_hdmi_audio_routes), 1086 .idle_bias_on = 1, 1087 .use_pmdown_time = 1, 1088 .endianness = 1, 1089 .non_legacy_dai_naming = 1, 1090 }; 1091 1092 static const struct snd_soc_dai_ops vc4_hdmi_audio_dai_ops = { 1093 .startup = vc4_hdmi_audio_startup, 1094 .shutdown = vc4_hdmi_audio_shutdown, 1095 .hw_params = vc4_hdmi_audio_hw_params, 1096 .set_fmt = vc4_hdmi_audio_set_fmt, 1097 .trigger = vc4_hdmi_audio_trigger, 1098 }; 1099 1100 static struct snd_soc_dai_driver vc4_hdmi_audio_codec_dai_drv = { 1101 .name = "vc4-hdmi-hifi", 1102 .playback = { 1103 .stream_name = "Playback", 1104 .channels_min = 2, 1105 .channels_max = 8, 1106 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 1107 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 1108 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 1109 SNDRV_PCM_RATE_192000, 1110 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 1111 }, 1112 }; 1113 1114 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = { 1115 .name = "vc4-hdmi-cpu-dai-component", 1116 }; 1117 1118 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai) 1119 { 1120 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai); 1121 1122 snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL); 1123 1124 return 0; 1125 } 1126 1127 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = { 1128 .name = "vc4-hdmi-cpu-dai", 1129 .probe = vc4_hdmi_audio_cpu_dai_probe, 1130 .playback = { 1131 .stream_name = "Playback", 1132 .channels_min = 1, 1133 .channels_max = 8, 1134 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 1135 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 1136 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 1137 SNDRV_PCM_RATE_192000, 1138 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 1139 }, 1140 .ops = &vc4_hdmi_audio_dai_ops, 1141 }; 1142 1143 static const struct snd_dmaengine_pcm_config pcm_conf = { 1144 .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx", 1145 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 1146 }; 1147 1148 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi) 1149 { 1150 const struct vc4_hdmi_register *mai_data = 1151 &vc4_hdmi->variant->registers[HDMI_MAI_DATA]; 1152 struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link; 1153 struct snd_soc_card *card = &vc4_hdmi->audio.card; 1154 struct device *dev = &vc4_hdmi->pdev->dev; 1155 const __be32 *addr; 1156 int index; 1157 int ret; 1158 1159 if (!of_find_property(dev->of_node, "dmas", NULL)) { 1160 dev_warn(dev, 1161 "'dmas' DT property is missing, no HDMI audio\n"); 1162 return 0; 1163 } 1164 1165 if (mai_data->reg != VC4_HD) { 1166 WARN_ONCE(true, "MAI isn't in the HD block\n"); 1167 return -EINVAL; 1168 } 1169 1170 /* 1171 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve 1172 * the bus address specified in the DT, because the physical address 1173 * (the one returned by platform_get_resource()) is not appropriate 1174 * for DMA transfers. 1175 * This VC/MMU should probably be exposed to avoid this kind of hacks. 1176 */ 1177 index = of_property_match_string(dev->of_node, "reg-names", "hd"); 1178 /* Before BCM2711, we don't have a named register range */ 1179 if (index < 0) 1180 index = 1; 1181 1182 addr = of_get_address(dev->of_node, index, NULL, NULL); 1183 1184 vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset; 1185 vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1186 vc4_hdmi->audio.dma_data.maxburst = 2; 1187 1188 ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0); 1189 if (ret) { 1190 dev_err(dev, "Could not register PCM component: %d\n", ret); 1191 return ret; 1192 } 1193 1194 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp, 1195 &vc4_hdmi_audio_cpu_dai_drv, 1); 1196 if (ret) { 1197 dev_err(dev, "Could not register CPU DAI: %d\n", ret); 1198 return ret; 1199 } 1200 1201 /* register component and codec dai */ 1202 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_component_drv, 1203 &vc4_hdmi_audio_codec_dai_drv, 1); 1204 if (ret) { 1205 dev_err(dev, "Could not register component: %d\n", ret); 1206 return ret; 1207 } 1208 1209 dai_link->cpus = &vc4_hdmi->audio.cpu; 1210 dai_link->codecs = &vc4_hdmi->audio.codec; 1211 dai_link->platforms = &vc4_hdmi->audio.platform; 1212 1213 dai_link->num_cpus = 1; 1214 dai_link->num_codecs = 1; 1215 dai_link->num_platforms = 1; 1216 1217 dai_link->name = "MAI"; 1218 dai_link->stream_name = "MAI PCM"; 1219 dai_link->codecs->dai_name = vc4_hdmi_audio_codec_dai_drv.name; 1220 dai_link->cpus->dai_name = dev_name(dev); 1221 dai_link->codecs->name = dev_name(dev); 1222 dai_link->platforms->name = dev_name(dev); 1223 1224 card->dai_link = dai_link; 1225 card->num_links = 1; 1226 card->name = vc4_hdmi->variant->card_name; 1227 card->dev = dev; 1228 card->owner = THIS_MODULE; 1229 1230 /* 1231 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and 1232 * stores a pointer to the snd card object in dev->driver_data. This 1233 * means we cannot use it for something else. The hdmi back-pointer is 1234 * now stored in card->drvdata and should be retrieved with 1235 * snd_soc_card_get_drvdata() if needed. 1236 */ 1237 snd_soc_card_set_drvdata(card, vc4_hdmi); 1238 ret = devm_snd_soc_register_card(dev, card); 1239 if (ret) 1240 dev_err(dev, "Could not register sound card: %d\n", ret); 1241 1242 return ret; 1243 1244 } 1245 1246 #ifdef CONFIG_DRM_VC4_HDMI_CEC 1247 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv) 1248 { 1249 struct vc4_hdmi *vc4_hdmi = priv; 1250 1251 if (vc4_hdmi->cec_irq_was_rx) { 1252 if (vc4_hdmi->cec_rx_msg.len) 1253 cec_received_msg(vc4_hdmi->cec_adap, 1254 &vc4_hdmi->cec_rx_msg); 1255 } else if (vc4_hdmi->cec_tx_ok) { 1256 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK, 1257 0, 0, 0, 0); 1258 } else { 1259 /* 1260 * This CEC implementation makes 1 retry, so if we 1261 * get a NACK, then that means it made 2 attempts. 1262 */ 1263 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK, 1264 0, 2, 0, 0); 1265 } 1266 return IRQ_HANDLED; 1267 } 1268 1269 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1) 1270 { 1271 struct cec_msg *msg = &vc4_hdmi->cec_rx_msg; 1272 unsigned int i; 1273 1274 msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >> 1275 VC4_HDMI_CEC_REC_WRD_CNT_SHIFT); 1276 for (i = 0; i < msg->len; i += 4) { 1277 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + i); 1278 1279 msg->msg[i] = val & 0xff; 1280 msg->msg[i + 1] = (val >> 8) & 0xff; 1281 msg->msg[i + 2] = (val >> 16) & 0xff; 1282 msg->msg[i + 3] = (val >> 24) & 0xff; 1283 } 1284 } 1285 1286 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv) 1287 { 1288 struct vc4_hdmi *vc4_hdmi = priv; 1289 u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS); 1290 u32 cntrl1, cntrl5; 1291 1292 if (!(stat & VC4_HDMI_CPU_CEC)) 1293 return IRQ_NONE; 1294 vc4_hdmi->cec_rx_msg.len = 0; 1295 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1); 1296 cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5); 1297 vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT; 1298 if (vc4_hdmi->cec_irq_was_rx) { 1299 vc4_cec_read_msg(vc4_hdmi, cntrl1); 1300 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 1301 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 1302 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 1303 } else { 1304 vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD; 1305 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 1306 } 1307 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 1308 HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC); 1309 1310 return IRQ_WAKE_THREAD; 1311 } 1312 1313 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable) 1314 { 1315 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 1316 /* clock period in microseconds */ 1317 const u32 usecs = 1000000 / CEC_CLOCK_FREQ; 1318 u32 val = HDMI_READ(HDMI_CEC_CNTRL_5); 1319 1320 val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET | 1321 VC4_HDMI_CEC_CNT_TO_4700_US_MASK | 1322 VC4_HDMI_CEC_CNT_TO_4500_US_MASK); 1323 val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) | 1324 ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT); 1325 1326 if (enable) { 1327 HDMI_WRITE(HDMI_CEC_CNTRL_5, val | 1328 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 1329 HDMI_WRITE(HDMI_CEC_CNTRL_5, val); 1330 HDMI_WRITE(HDMI_CEC_CNTRL_2, 1331 ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) | 1332 ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) | 1333 ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) | 1334 ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) | 1335 ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT)); 1336 HDMI_WRITE(HDMI_CEC_CNTRL_3, 1337 ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) | 1338 ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) | 1339 ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) | 1340 ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT)); 1341 HDMI_WRITE(HDMI_CEC_CNTRL_4, 1342 ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) | 1343 ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) | 1344 ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) | 1345 ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT)); 1346 1347 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC); 1348 } else { 1349 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC); 1350 HDMI_WRITE(HDMI_CEC_CNTRL_5, val | 1351 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 1352 } 1353 return 0; 1354 } 1355 1356 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr) 1357 { 1358 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 1359 1360 HDMI_WRITE(HDMI_CEC_CNTRL_1, 1361 (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) | 1362 (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT); 1363 return 0; 1364 } 1365 1366 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts, 1367 u32 signal_free_time, struct cec_msg *msg) 1368 { 1369 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 1370 u32 val; 1371 unsigned int i; 1372 1373 for (i = 0; i < msg->len; i += 4) 1374 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + i, 1375 (msg->msg[i]) | 1376 (msg->msg[i + 1] << 8) | 1377 (msg->msg[i + 2] << 16) | 1378 (msg->msg[i + 3] << 24)); 1379 1380 val = HDMI_READ(HDMI_CEC_CNTRL_1); 1381 val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 1382 HDMI_WRITE(HDMI_CEC_CNTRL_1, val); 1383 val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK; 1384 val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT; 1385 val |= VC4_HDMI_CEC_START_XMIT_BEGIN; 1386 1387 HDMI_WRITE(HDMI_CEC_CNTRL_1, val); 1388 return 0; 1389 } 1390 1391 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = { 1392 .adap_enable = vc4_hdmi_cec_adap_enable, 1393 .adap_log_addr = vc4_hdmi_cec_adap_log_addr, 1394 .adap_transmit = vc4_hdmi_cec_adap_transmit, 1395 }; 1396 1397 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi) 1398 { 1399 struct cec_connector_info conn_info; 1400 struct platform_device *pdev = vc4_hdmi->pdev; 1401 u32 value; 1402 int ret; 1403 1404 if (!vc4_hdmi->variant->cec_available) 1405 return 0; 1406 1407 vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops, 1408 vc4_hdmi, "vc4", 1409 CEC_CAP_DEFAULTS | 1410 CEC_CAP_CONNECTOR_INFO, 1); 1411 ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap); 1412 if (ret < 0) 1413 return ret; 1414 1415 cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector); 1416 cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info); 1417 1418 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff); 1419 value = HDMI_READ(HDMI_CEC_CNTRL_1); 1420 value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK; 1421 /* 1422 * Set the logical address to Unregistered and set the clock 1423 * divider: the hsm_clock rate and this divider setting will 1424 * give a 40 kHz CEC clock. 1425 */ 1426 value |= VC4_HDMI_CEC_ADDR_MASK | 1427 (4091 << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT); 1428 HDMI_WRITE(HDMI_CEC_CNTRL_1, value); 1429 ret = devm_request_threaded_irq(&pdev->dev, platform_get_irq(pdev, 0), 1430 vc4_cec_irq_handler, 1431 vc4_cec_irq_handler_thread, 0, 1432 "vc4 hdmi cec", vc4_hdmi); 1433 if (ret) 1434 goto err_delete_cec_adap; 1435 1436 ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev); 1437 if (ret < 0) 1438 goto err_delete_cec_adap; 1439 1440 return 0; 1441 1442 err_delete_cec_adap: 1443 cec_delete_adapter(vc4_hdmi->cec_adap); 1444 1445 return ret; 1446 } 1447 1448 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi) 1449 { 1450 cec_unregister_adapter(vc4_hdmi->cec_adap); 1451 } 1452 #else 1453 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi) 1454 { 1455 return 0; 1456 } 1457 1458 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi) {}; 1459 1460 #endif 1461 1462 static int vc4_hdmi_build_regset(struct vc4_hdmi *vc4_hdmi, 1463 struct debugfs_regset32 *regset, 1464 enum vc4_hdmi_regs reg) 1465 { 1466 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant; 1467 struct debugfs_reg32 *regs, *new_regs; 1468 unsigned int count = 0; 1469 unsigned int i; 1470 1471 regs = kcalloc(variant->num_registers, sizeof(*regs), 1472 GFP_KERNEL); 1473 if (!regs) 1474 return -ENOMEM; 1475 1476 for (i = 0; i < variant->num_registers; i++) { 1477 const struct vc4_hdmi_register *field = &variant->registers[i]; 1478 1479 if (field->reg != reg) 1480 continue; 1481 1482 regs[count].name = field->name; 1483 regs[count].offset = field->offset; 1484 count++; 1485 } 1486 1487 new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL); 1488 if (!new_regs) 1489 return -ENOMEM; 1490 1491 regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg); 1492 regset->regs = new_regs; 1493 regset->nregs = count; 1494 1495 return 0; 1496 } 1497 1498 static int vc4_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi) 1499 { 1500 struct platform_device *pdev = vc4_hdmi->pdev; 1501 struct device *dev = &pdev->dev; 1502 int ret; 1503 1504 vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0); 1505 if (IS_ERR(vc4_hdmi->hdmicore_regs)) 1506 return PTR_ERR(vc4_hdmi->hdmicore_regs); 1507 1508 vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1); 1509 if (IS_ERR(vc4_hdmi->hd_regs)) 1510 return PTR_ERR(vc4_hdmi->hd_regs); 1511 1512 ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD); 1513 if (ret) 1514 return ret; 1515 1516 ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI); 1517 if (ret) 1518 return ret; 1519 1520 vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel"); 1521 if (IS_ERR(vc4_hdmi->pixel_clock)) { 1522 ret = PTR_ERR(vc4_hdmi->pixel_clock); 1523 if (ret != -EPROBE_DEFER) 1524 DRM_ERROR("Failed to get pixel clock\n"); 1525 return ret; 1526 } 1527 1528 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); 1529 if (IS_ERR(vc4_hdmi->hsm_clock)) { 1530 DRM_ERROR("Failed to get HDMI state machine clock\n"); 1531 return PTR_ERR(vc4_hdmi->hsm_clock); 1532 } 1533 vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock; 1534 1535 return 0; 1536 } 1537 1538 static int vc5_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi) 1539 { 1540 struct platform_device *pdev = vc4_hdmi->pdev; 1541 struct device *dev = &pdev->dev; 1542 struct resource *res; 1543 1544 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi"); 1545 if (!res) 1546 return -ENODEV; 1547 1548 vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start, 1549 resource_size(res)); 1550 if (!vc4_hdmi->hdmicore_regs) 1551 return -ENOMEM; 1552 1553 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd"); 1554 if (!res) 1555 return -ENODEV; 1556 1557 vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res)); 1558 if (!vc4_hdmi->hd_regs) 1559 return -ENOMEM; 1560 1561 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec"); 1562 if (!res) 1563 return -ENODEV; 1564 1565 vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res)); 1566 if (!vc4_hdmi->cec_regs) 1567 return -ENOMEM; 1568 1569 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc"); 1570 if (!res) 1571 return -ENODEV; 1572 1573 vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res)); 1574 if (!vc4_hdmi->csc_regs) 1575 return -ENOMEM; 1576 1577 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp"); 1578 if (!res) 1579 return -ENODEV; 1580 1581 vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res)); 1582 if (!vc4_hdmi->dvp_regs) 1583 return -ENOMEM; 1584 1585 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy"); 1586 if (!res) 1587 return -ENODEV; 1588 1589 vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res)); 1590 if (!vc4_hdmi->phy_regs) 1591 return -ENOMEM; 1592 1593 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet"); 1594 if (!res) 1595 return -ENODEV; 1596 1597 vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res)); 1598 if (!vc4_hdmi->ram_regs) 1599 return -ENOMEM; 1600 1601 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm"); 1602 if (!res) 1603 return -ENODEV; 1604 1605 vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res)); 1606 if (!vc4_hdmi->rm_regs) 1607 return -ENOMEM; 1608 1609 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); 1610 if (IS_ERR(vc4_hdmi->hsm_clock)) { 1611 DRM_ERROR("Failed to get HDMI state machine clock\n"); 1612 return PTR_ERR(vc4_hdmi->hsm_clock); 1613 } 1614 1615 vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb"); 1616 if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) { 1617 DRM_ERROR("Failed to get pixel bvb clock\n"); 1618 return PTR_ERR(vc4_hdmi->pixel_bvb_clock); 1619 } 1620 1621 vc4_hdmi->audio_clock = devm_clk_get(dev, "audio"); 1622 if (IS_ERR(vc4_hdmi->audio_clock)) { 1623 DRM_ERROR("Failed to get audio clock\n"); 1624 return PTR_ERR(vc4_hdmi->audio_clock); 1625 } 1626 1627 vc4_hdmi->reset = devm_reset_control_get(dev, NULL); 1628 if (IS_ERR(vc4_hdmi->reset)) { 1629 DRM_ERROR("Failed to get HDMI reset line\n"); 1630 return PTR_ERR(vc4_hdmi->reset); 1631 } 1632 1633 return 0; 1634 } 1635 1636 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data) 1637 { 1638 const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev); 1639 struct platform_device *pdev = to_platform_device(dev); 1640 struct drm_device *drm = dev_get_drvdata(master); 1641 struct vc4_hdmi *vc4_hdmi; 1642 struct drm_encoder *encoder; 1643 struct device_node *ddc_node; 1644 u32 value; 1645 int ret; 1646 1647 vc4_hdmi = devm_kzalloc(dev, sizeof(*vc4_hdmi), GFP_KERNEL); 1648 if (!vc4_hdmi) 1649 return -ENOMEM; 1650 1651 dev_set_drvdata(dev, vc4_hdmi); 1652 encoder = &vc4_hdmi->encoder.base.base; 1653 vc4_hdmi->encoder.base.type = variant->encoder_type; 1654 vc4_hdmi->encoder.base.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure; 1655 vc4_hdmi->encoder.base.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable; 1656 vc4_hdmi->encoder.base.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable; 1657 vc4_hdmi->encoder.base.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable; 1658 vc4_hdmi->encoder.base.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown; 1659 vc4_hdmi->pdev = pdev; 1660 vc4_hdmi->variant = variant; 1661 1662 ret = variant->init_resources(vc4_hdmi); 1663 if (ret) 1664 return ret; 1665 1666 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0); 1667 if (!ddc_node) { 1668 DRM_ERROR("Failed to find ddc node in device tree\n"); 1669 return -ENODEV; 1670 } 1671 1672 vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node); 1673 of_node_put(ddc_node); 1674 if (!vc4_hdmi->ddc) { 1675 DRM_DEBUG("Failed to get ddc i2c adapter by node\n"); 1676 return -EPROBE_DEFER; 1677 } 1678 1679 /* Only use the GPIO HPD pin if present in the DT, otherwise 1680 * we'll use the HDMI core's register. 1681 */ 1682 if (of_find_property(dev->of_node, "hpd-gpios", &value)) { 1683 enum of_gpio_flags hpd_gpio_flags; 1684 1685 vc4_hdmi->hpd_gpio = of_get_named_gpio_flags(dev->of_node, 1686 "hpd-gpios", 0, 1687 &hpd_gpio_flags); 1688 if (vc4_hdmi->hpd_gpio < 0) { 1689 ret = vc4_hdmi->hpd_gpio; 1690 goto err_unprepare_hsm; 1691 } 1692 1693 vc4_hdmi->hpd_active_low = hpd_gpio_flags & OF_GPIO_ACTIVE_LOW; 1694 } 1695 1696 pm_runtime_enable(dev); 1697 1698 drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS); 1699 drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs); 1700 1701 ret = vc4_hdmi_connector_init(drm, vc4_hdmi); 1702 if (ret) 1703 goto err_destroy_encoder; 1704 1705 ret = vc4_hdmi_cec_init(vc4_hdmi); 1706 if (ret) 1707 goto err_destroy_conn; 1708 1709 ret = vc4_hdmi_audio_init(vc4_hdmi); 1710 if (ret) 1711 goto err_free_cec; 1712 1713 vc4_debugfs_add_file(drm, variant->debugfs_name, 1714 vc4_hdmi_debugfs_regs, 1715 vc4_hdmi); 1716 1717 return 0; 1718 1719 err_free_cec: 1720 vc4_hdmi_cec_exit(vc4_hdmi); 1721 err_destroy_conn: 1722 vc4_hdmi_connector_destroy(&vc4_hdmi->connector); 1723 err_destroy_encoder: 1724 drm_encoder_cleanup(encoder); 1725 err_unprepare_hsm: 1726 pm_runtime_disable(dev); 1727 put_device(&vc4_hdmi->ddc->dev); 1728 1729 return ret; 1730 } 1731 1732 static void vc4_hdmi_unbind(struct device *dev, struct device *master, 1733 void *data) 1734 { 1735 struct vc4_hdmi *vc4_hdmi; 1736 1737 /* 1738 * ASoC makes it a bit hard to retrieve a pointer to the 1739 * vc4_hdmi structure. Registering the card will overwrite our 1740 * device drvdata with a pointer to the snd_soc_card structure, 1741 * which can then be used to retrieve whatever drvdata we want 1742 * to associate. 1743 * 1744 * However, that doesn't fly in the case where we wouldn't 1745 * register an ASoC card (because of an old DT that is missing 1746 * the dmas properties for example), then the card isn't 1747 * registered and the device drvdata wouldn't be set. 1748 * 1749 * We can deal with both cases by making sure a snd_soc_card 1750 * pointer and a vc4_hdmi structure are pointing to the same 1751 * memory address, so we can treat them indistinctly without any 1752 * issue. 1753 */ 1754 BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0); 1755 BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0); 1756 vc4_hdmi = dev_get_drvdata(dev); 1757 1758 kfree(vc4_hdmi->hdmi_regset.regs); 1759 kfree(vc4_hdmi->hd_regset.regs); 1760 1761 vc4_hdmi_cec_exit(vc4_hdmi); 1762 vc4_hdmi_connector_destroy(&vc4_hdmi->connector); 1763 drm_encoder_cleanup(&vc4_hdmi->encoder.base.base); 1764 1765 pm_runtime_disable(dev); 1766 1767 put_device(&vc4_hdmi->ddc->dev); 1768 } 1769 1770 static const struct component_ops vc4_hdmi_ops = { 1771 .bind = vc4_hdmi_bind, 1772 .unbind = vc4_hdmi_unbind, 1773 }; 1774 1775 static int vc4_hdmi_dev_probe(struct platform_device *pdev) 1776 { 1777 return component_add(&pdev->dev, &vc4_hdmi_ops); 1778 } 1779 1780 static int vc4_hdmi_dev_remove(struct platform_device *pdev) 1781 { 1782 component_del(&pdev->dev, &vc4_hdmi_ops); 1783 return 0; 1784 } 1785 1786 static const struct vc4_hdmi_variant bcm2835_variant = { 1787 .encoder_type = VC4_ENCODER_TYPE_HDMI0, 1788 .debugfs_name = "hdmi_regs", 1789 .card_name = "vc4-hdmi", 1790 .max_pixel_clock = 162000000, 1791 .cec_available = true, 1792 .registers = vc4_hdmi_fields, 1793 .num_registers = ARRAY_SIZE(vc4_hdmi_fields), 1794 1795 .init_resources = vc4_hdmi_init_resources, 1796 .csc_setup = vc4_hdmi_csc_setup, 1797 .reset = vc4_hdmi_reset, 1798 .set_timings = vc4_hdmi_set_timings, 1799 .phy_init = vc4_hdmi_phy_init, 1800 .phy_disable = vc4_hdmi_phy_disable, 1801 .phy_rng_enable = vc4_hdmi_phy_rng_enable, 1802 .phy_rng_disable = vc4_hdmi_phy_rng_disable, 1803 .channel_map = vc4_hdmi_channel_map, 1804 }; 1805 1806 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = { 1807 .encoder_type = VC4_ENCODER_TYPE_HDMI0, 1808 .debugfs_name = "hdmi0_regs", 1809 .card_name = "vc4-hdmi-0", 1810 .max_pixel_clock = 297000000, 1811 .registers = vc5_hdmi_hdmi0_fields, 1812 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi0_fields), 1813 .phy_lane_mapping = { 1814 PHY_LANE_0, 1815 PHY_LANE_1, 1816 PHY_LANE_2, 1817 PHY_LANE_CK, 1818 }, 1819 1820 .init_resources = vc5_hdmi_init_resources, 1821 .csc_setup = vc5_hdmi_csc_setup, 1822 .reset = vc5_hdmi_reset, 1823 .set_timings = vc5_hdmi_set_timings, 1824 .phy_init = vc5_hdmi_phy_init, 1825 .phy_disable = vc5_hdmi_phy_disable, 1826 .phy_rng_enable = vc5_hdmi_phy_rng_enable, 1827 .phy_rng_disable = vc5_hdmi_phy_rng_disable, 1828 .channel_map = vc5_hdmi_channel_map, 1829 }; 1830 1831 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = { 1832 .encoder_type = VC4_ENCODER_TYPE_HDMI1, 1833 .debugfs_name = "hdmi1_regs", 1834 .card_name = "vc4-hdmi-1", 1835 .max_pixel_clock = 297000000, 1836 .registers = vc5_hdmi_hdmi1_fields, 1837 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi1_fields), 1838 .phy_lane_mapping = { 1839 PHY_LANE_1, 1840 PHY_LANE_0, 1841 PHY_LANE_CK, 1842 PHY_LANE_2, 1843 }, 1844 1845 .init_resources = vc5_hdmi_init_resources, 1846 .csc_setup = vc5_hdmi_csc_setup, 1847 .reset = vc5_hdmi_reset, 1848 .set_timings = vc5_hdmi_set_timings, 1849 .phy_init = vc5_hdmi_phy_init, 1850 .phy_disable = vc5_hdmi_phy_disable, 1851 .phy_rng_enable = vc5_hdmi_phy_rng_enable, 1852 .phy_rng_disable = vc5_hdmi_phy_rng_disable, 1853 .channel_map = vc5_hdmi_channel_map, 1854 }; 1855 1856 static const struct of_device_id vc4_hdmi_dt_match[] = { 1857 { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant }, 1858 { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant }, 1859 { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant }, 1860 {} 1861 }; 1862 1863 struct platform_driver vc4_hdmi_driver = { 1864 .probe = vc4_hdmi_dev_probe, 1865 .remove = vc4_hdmi_dev_remove, 1866 .driver = { 1867 .name = "vc4_hdmi", 1868 .of_match_table = vc4_hdmi_dt_match, 1869 }, 1870 }; 1871