1 /* 2 * Copyright (C) 2015 Broadcom 3 * Copyright (c) 2014 The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License version 2 as published by 9 * the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 /** 21 * DOC: VC4 Falcon HDMI module 22 * 23 * The HDMI core has a state machine and a PHY. On BCM2835, most of 24 * the unit operates off of the HSM clock from CPRMAN. It also 25 * internally uses the PLLH_PIX clock for the PHY. 26 * 27 * HDMI infoframes are kept within a small packet ram, where each 28 * packet can be individually enabled for including in a frame. 29 * 30 * HDMI audio is implemented entirely within the HDMI IP block. A 31 * register in the HDMI encoder takes SPDIF frames from the DMA engine 32 * and transfers them over an internal MAI (multi-channel audio 33 * interconnect) bus to the encoder side for insertion into the video 34 * blank regions. 35 * 36 * The driver's HDMI encoder does not yet support power management. 37 * The HDMI encoder's power domain and the HSM/pixel clocks are kept 38 * continuously running, and only the HDMI logic and packet ram are 39 * powered off/on at disable/enable time. 40 * 41 * The driver does not yet support CEC control, though the HDMI 42 * encoder block has CEC support. 43 */ 44 45 #include "drm_atomic_helper.h" 46 #include "drm_crtc_helper.h" 47 #include "drm_edid.h" 48 #include "linux/clk.h" 49 #include "linux/component.h" 50 #include "linux/i2c.h" 51 #include "linux/of_address.h" 52 #include "linux/of_gpio.h" 53 #include "linux/of_platform.h" 54 #include "linux/rational.h" 55 #include "sound/dmaengine_pcm.h" 56 #include "sound/pcm_drm_eld.h" 57 #include "sound/pcm_params.h" 58 #include "sound/soc.h" 59 #include "vc4_drv.h" 60 #include "vc4_regs.h" 61 62 /* HDMI audio information */ 63 struct vc4_hdmi_audio { 64 struct snd_soc_card card; 65 struct snd_soc_dai_link link; 66 int samplerate; 67 int channels; 68 struct snd_dmaengine_dai_dma_data dma_data; 69 struct snd_pcm_substream *substream; 70 }; 71 72 /* General HDMI hardware state. */ 73 struct vc4_hdmi { 74 struct platform_device *pdev; 75 76 struct drm_encoder *encoder; 77 struct drm_connector *connector; 78 79 struct vc4_hdmi_audio audio; 80 81 struct i2c_adapter *ddc; 82 void __iomem *hdmicore_regs; 83 void __iomem *hd_regs; 84 int hpd_gpio; 85 bool hpd_active_low; 86 87 struct clk *pixel_clock; 88 struct clk *hsm_clock; 89 }; 90 91 #define HDMI_READ(offset) readl(vc4->hdmi->hdmicore_regs + offset) 92 #define HDMI_WRITE(offset, val) writel(val, vc4->hdmi->hdmicore_regs + offset) 93 #define HD_READ(offset) readl(vc4->hdmi->hd_regs + offset) 94 #define HD_WRITE(offset, val) writel(val, vc4->hdmi->hd_regs + offset) 95 96 /* VC4 HDMI encoder KMS struct */ 97 struct vc4_hdmi_encoder { 98 struct vc4_encoder base; 99 bool hdmi_monitor; 100 bool limited_rgb_range; 101 bool rgb_range_selectable; 102 }; 103 104 static inline struct vc4_hdmi_encoder * 105 to_vc4_hdmi_encoder(struct drm_encoder *encoder) 106 { 107 return container_of(encoder, struct vc4_hdmi_encoder, base.base); 108 } 109 110 /* VC4 HDMI connector KMS struct */ 111 struct vc4_hdmi_connector { 112 struct drm_connector base; 113 114 /* Since the connector is attached to just the one encoder, 115 * this is the reference to it so we can do the best_encoder() 116 * hook. 117 */ 118 struct drm_encoder *encoder; 119 }; 120 121 static inline struct vc4_hdmi_connector * 122 to_vc4_hdmi_connector(struct drm_connector *connector) 123 { 124 return container_of(connector, struct vc4_hdmi_connector, base); 125 } 126 127 #define HDMI_REG(reg) { reg, #reg } 128 static const struct { 129 u32 reg; 130 const char *name; 131 } hdmi_regs[] = { 132 HDMI_REG(VC4_HDMI_CORE_REV), 133 HDMI_REG(VC4_HDMI_SW_RESET_CONTROL), 134 HDMI_REG(VC4_HDMI_HOTPLUG_INT), 135 HDMI_REG(VC4_HDMI_HOTPLUG), 136 HDMI_REG(VC4_HDMI_MAI_CHANNEL_MAP), 137 HDMI_REG(VC4_HDMI_MAI_CONFIG), 138 HDMI_REG(VC4_HDMI_MAI_FORMAT), 139 HDMI_REG(VC4_HDMI_AUDIO_PACKET_CONFIG), 140 HDMI_REG(VC4_HDMI_RAM_PACKET_CONFIG), 141 HDMI_REG(VC4_HDMI_HORZA), 142 HDMI_REG(VC4_HDMI_HORZB), 143 HDMI_REG(VC4_HDMI_FIFO_CTL), 144 HDMI_REG(VC4_HDMI_SCHEDULER_CONTROL), 145 HDMI_REG(VC4_HDMI_VERTA0), 146 HDMI_REG(VC4_HDMI_VERTA1), 147 HDMI_REG(VC4_HDMI_VERTB0), 148 HDMI_REG(VC4_HDMI_VERTB1), 149 HDMI_REG(VC4_HDMI_TX_PHY_RESET_CTL), 150 HDMI_REG(VC4_HDMI_TX_PHY_CTL0), 151 }; 152 153 static const struct { 154 u32 reg; 155 const char *name; 156 } hd_regs[] = { 157 HDMI_REG(VC4_HD_M_CTL), 158 HDMI_REG(VC4_HD_MAI_CTL), 159 HDMI_REG(VC4_HD_MAI_THR), 160 HDMI_REG(VC4_HD_MAI_FMT), 161 HDMI_REG(VC4_HD_MAI_SMP), 162 HDMI_REG(VC4_HD_VID_CTL), 163 HDMI_REG(VC4_HD_CSC_CTL), 164 HDMI_REG(VC4_HD_FRAME_COUNT), 165 }; 166 167 #ifdef CONFIG_DEBUG_FS 168 int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused) 169 { 170 struct drm_info_node *node = (struct drm_info_node *)m->private; 171 struct drm_device *dev = node->minor->dev; 172 struct vc4_dev *vc4 = to_vc4_dev(dev); 173 int i; 174 175 for (i = 0; i < ARRAY_SIZE(hdmi_regs); i++) { 176 seq_printf(m, "%s (0x%04x): 0x%08x\n", 177 hdmi_regs[i].name, hdmi_regs[i].reg, 178 HDMI_READ(hdmi_regs[i].reg)); 179 } 180 181 for (i = 0; i < ARRAY_SIZE(hd_regs); i++) { 182 seq_printf(m, "%s (0x%04x): 0x%08x\n", 183 hd_regs[i].name, hd_regs[i].reg, 184 HD_READ(hd_regs[i].reg)); 185 } 186 187 return 0; 188 } 189 #endif /* CONFIG_DEBUG_FS */ 190 191 static void vc4_hdmi_dump_regs(struct drm_device *dev) 192 { 193 struct vc4_dev *vc4 = to_vc4_dev(dev); 194 int i; 195 196 for (i = 0; i < ARRAY_SIZE(hdmi_regs); i++) { 197 DRM_INFO("0x%04x (%s): 0x%08x\n", 198 hdmi_regs[i].reg, hdmi_regs[i].name, 199 HDMI_READ(hdmi_regs[i].reg)); 200 } 201 for (i = 0; i < ARRAY_SIZE(hd_regs); i++) { 202 DRM_INFO("0x%04x (%s): 0x%08x\n", 203 hd_regs[i].reg, hd_regs[i].name, 204 HD_READ(hd_regs[i].reg)); 205 } 206 } 207 208 static enum drm_connector_status 209 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force) 210 { 211 struct drm_device *dev = connector->dev; 212 struct vc4_dev *vc4 = to_vc4_dev(dev); 213 214 if (vc4->hdmi->hpd_gpio) { 215 if (gpio_get_value_cansleep(vc4->hdmi->hpd_gpio) ^ 216 vc4->hdmi->hpd_active_low) 217 return connector_status_connected; 218 else 219 return connector_status_disconnected; 220 } 221 222 if (drm_probe_ddc(vc4->hdmi->ddc)) 223 return connector_status_connected; 224 225 if (HDMI_READ(VC4_HDMI_HOTPLUG) & VC4_HDMI_HOTPLUG_CONNECTED) 226 return connector_status_connected; 227 else 228 return connector_status_disconnected; 229 } 230 231 static void vc4_hdmi_connector_destroy(struct drm_connector *connector) 232 { 233 drm_connector_unregister(connector); 234 drm_connector_cleanup(connector); 235 } 236 237 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector) 238 { 239 struct vc4_hdmi_connector *vc4_connector = 240 to_vc4_hdmi_connector(connector); 241 struct drm_encoder *encoder = vc4_connector->encoder; 242 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 243 struct drm_device *dev = connector->dev; 244 struct vc4_dev *vc4 = to_vc4_dev(dev); 245 int ret = 0; 246 struct edid *edid; 247 248 edid = drm_get_edid(connector, vc4->hdmi->ddc); 249 if (!edid) 250 return -ENODEV; 251 252 vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid); 253 254 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) { 255 vc4_encoder->rgb_range_selectable = 256 drm_rgb_quant_range_selectable(edid); 257 } 258 259 drm_mode_connector_update_edid_property(connector, edid); 260 ret = drm_add_edid_modes(connector, edid); 261 drm_edid_to_eld(connector, edid); 262 263 return ret; 264 } 265 266 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = { 267 .dpms = drm_atomic_helper_connector_dpms, 268 .detect = vc4_hdmi_connector_detect, 269 .fill_modes = drm_helper_probe_single_connector_modes, 270 .destroy = vc4_hdmi_connector_destroy, 271 .reset = drm_atomic_helper_connector_reset, 272 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 273 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 274 }; 275 276 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = { 277 .get_modes = vc4_hdmi_connector_get_modes, 278 }; 279 280 static struct drm_connector *vc4_hdmi_connector_init(struct drm_device *dev, 281 struct drm_encoder *encoder) 282 { 283 struct drm_connector *connector = NULL; 284 struct vc4_hdmi_connector *hdmi_connector; 285 int ret = 0; 286 287 hdmi_connector = devm_kzalloc(dev->dev, sizeof(*hdmi_connector), 288 GFP_KERNEL); 289 if (!hdmi_connector) { 290 ret = -ENOMEM; 291 goto fail; 292 } 293 connector = &hdmi_connector->base; 294 295 hdmi_connector->encoder = encoder; 296 297 drm_connector_init(dev, connector, &vc4_hdmi_connector_funcs, 298 DRM_MODE_CONNECTOR_HDMIA); 299 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs); 300 301 connector->polled = (DRM_CONNECTOR_POLL_CONNECT | 302 DRM_CONNECTOR_POLL_DISCONNECT); 303 304 connector->interlace_allowed = 1; 305 connector->doublescan_allowed = 0; 306 307 drm_mode_connector_attach_encoder(connector, encoder); 308 309 return connector; 310 311 fail: 312 if (connector) 313 vc4_hdmi_connector_destroy(connector); 314 315 return ERR_PTR(ret); 316 } 317 318 static void vc4_hdmi_encoder_destroy(struct drm_encoder *encoder) 319 { 320 drm_encoder_cleanup(encoder); 321 } 322 323 static const struct drm_encoder_funcs vc4_hdmi_encoder_funcs = { 324 .destroy = vc4_hdmi_encoder_destroy, 325 }; 326 327 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder, 328 enum hdmi_infoframe_type type) 329 { 330 struct drm_device *dev = encoder->dev; 331 struct vc4_dev *vc4 = to_vc4_dev(dev); 332 u32 packet_id = type - 0x80; 333 334 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, 335 HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id)); 336 337 return wait_for(!(HDMI_READ(VC4_HDMI_RAM_PACKET_STATUS) & 338 BIT(packet_id)), 100); 339 } 340 341 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder, 342 union hdmi_infoframe *frame) 343 { 344 struct drm_device *dev = encoder->dev; 345 struct vc4_dev *vc4 = to_vc4_dev(dev); 346 u32 packet_id = frame->any.type - 0x80; 347 u32 packet_reg = VC4_HDMI_RAM_PACKET(packet_id); 348 uint8_t buffer[VC4_HDMI_PACKET_STRIDE]; 349 ssize_t len, i; 350 int ret; 351 352 WARN_ONCE(!(HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) & 353 VC4_HDMI_RAM_PACKET_ENABLE), 354 "Packet RAM has to be on to store the packet."); 355 356 len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer)); 357 if (len < 0) 358 return; 359 360 ret = vc4_hdmi_stop_packet(encoder, frame->any.type); 361 if (ret) { 362 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret); 363 return; 364 } 365 366 for (i = 0; i < len; i += 7) { 367 HDMI_WRITE(packet_reg, 368 buffer[i + 0] << 0 | 369 buffer[i + 1] << 8 | 370 buffer[i + 2] << 16); 371 packet_reg += 4; 372 373 HDMI_WRITE(packet_reg, 374 buffer[i + 3] << 0 | 375 buffer[i + 4] << 8 | 376 buffer[i + 5] << 16 | 377 buffer[i + 6] << 24); 378 packet_reg += 4; 379 } 380 381 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, 382 HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) | BIT(packet_id)); 383 ret = wait_for((HDMI_READ(VC4_HDMI_RAM_PACKET_STATUS) & 384 BIT(packet_id)), 100); 385 if (ret) 386 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret); 387 } 388 389 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder) 390 { 391 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 392 struct drm_crtc *crtc = encoder->crtc; 393 const struct drm_display_mode *mode = &crtc->state->adjusted_mode; 394 union hdmi_infoframe frame; 395 int ret; 396 397 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, mode); 398 if (ret < 0) { 399 DRM_ERROR("couldn't fill AVI infoframe\n"); 400 return; 401 } 402 403 drm_hdmi_avi_infoframe_quant_range(&frame.avi, mode, 404 vc4_encoder->limited_rgb_range ? 405 HDMI_QUANTIZATION_RANGE_LIMITED : 406 HDMI_QUANTIZATION_RANGE_FULL, 407 vc4_encoder->rgb_range_selectable); 408 409 vc4_hdmi_write_infoframe(encoder, &frame); 410 } 411 412 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder) 413 { 414 union hdmi_infoframe frame; 415 int ret; 416 417 ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore"); 418 if (ret < 0) { 419 DRM_ERROR("couldn't fill SPD infoframe\n"); 420 return; 421 } 422 423 frame.spd.sdi = HDMI_SPD_SDI_PC; 424 425 vc4_hdmi_write_infoframe(encoder, &frame); 426 } 427 428 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder) 429 { 430 struct drm_device *drm = encoder->dev; 431 struct vc4_dev *vc4 = drm->dev_private; 432 struct vc4_hdmi *hdmi = vc4->hdmi; 433 union hdmi_infoframe frame; 434 int ret; 435 436 ret = hdmi_audio_infoframe_init(&frame.audio); 437 438 frame.audio.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM; 439 frame.audio.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM; 440 frame.audio.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM; 441 frame.audio.channels = hdmi->audio.channels; 442 443 vc4_hdmi_write_infoframe(encoder, &frame); 444 } 445 446 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder) 447 { 448 vc4_hdmi_set_avi_infoframe(encoder); 449 vc4_hdmi_set_spd_infoframe(encoder); 450 } 451 452 static void vc4_hdmi_encoder_mode_set(struct drm_encoder *encoder, 453 struct drm_display_mode *unadjusted_mode, 454 struct drm_display_mode *mode) 455 { 456 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 457 struct drm_device *dev = encoder->dev; 458 struct vc4_dev *vc4 = to_vc4_dev(dev); 459 bool debug_dump_regs = false; 460 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 461 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 462 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 463 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 464 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 465 VC4_HDMI_VERTA_VSP) | 466 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 467 VC4_HDMI_VERTA_VFP) | 468 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL)); 469 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 470 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end, 471 VC4_HDMI_VERTB_VBP)); 472 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 473 VC4_SET_FIELD(mode->crtc_vtotal - 474 mode->crtc_vsync_end - 475 interlaced, 476 VC4_HDMI_VERTB_VBP)); 477 u32 csc_ctl; 478 479 if (debug_dump_regs) { 480 DRM_INFO("HDMI regs before:\n"); 481 vc4_hdmi_dump_regs(dev); 482 } 483 484 HD_WRITE(VC4_HD_VID_CTL, 0); 485 486 clk_set_rate(vc4->hdmi->pixel_clock, mode->clock * 1000 * 487 ((mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1)); 488 489 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL, 490 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) | 491 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT | 492 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS); 493 494 HDMI_WRITE(VC4_HDMI_HORZA, 495 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) | 496 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) | 497 VC4_SET_FIELD(mode->hdisplay * pixel_rep, 498 VC4_HDMI_HORZA_HAP)); 499 500 HDMI_WRITE(VC4_HDMI_HORZB, 501 VC4_SET_FIELD((mode->htotal - 502 mode->hsync_end) * pixel_rep, 503 VC4_HDMI_HORZB_HBP) | 504 VC4_SET_FIELD((mode->hsync_end - 505 mode->hsync_start) * pixel_rep, 506 VC4_HDMI_HORZB_HSP) | 507 VC4_SET_FIELD((mode->hsync_start - 508 mode->hdisplay) * pixel_rep, 509 VC4_HDMI_HORZB_HFP)); 510 511 HDMI_WRITE(VC4_HDMI_VERTA0, verta); 512 HDMI_WRITE(VC4_HDMI_VERTA1, verta); 513 514 HDMI_WRITE(VC4_HDMI_VERTB0, vertb_even); 515 HDMI_WRITE(VC4_HDMI_VERTB1, vertb); 516 517 HD_WRITE(VC4_HD_VID_CTL, 518 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) | 519 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW)); 520 521 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR, 522 VC4_HD_CSC_CTL_ORDER); 523 524 if (vc4_encoder->hdmi_monitor && 525 drm_default_rgb_quant_range(mode) == 526 HDMI_QUANTIZATION_RANGE_LIMITED) { 527 /* CEA VICs other than #1 requre limited range RGB 528 * output unless overridden by an AVI infoframe. 529 * Apply a colorspace conversion to squash 0-255 down 530 * to 16-235. The matrix here is: 531 * 532 * [ 0 0 0.8594 16] 533 * [ 0 0.8594 0 16] 534 * [ 0.8594 0 0 16] 535 * [ 0 0 0 1] 536 */ 537 csc_ctl |= VC4_HD_CSC_CTL_ENABLE; 538 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC; 539 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM, 540 VC4_HD_CSC_CTL_MODE); 541 542 HD_WRITE(VC4_HD_CSC_12_11, (0x000 << 16) | 0x000); 543 HD_WRITE(VC4_HD_CSC_14_13, (0x100 << 16) | 0x6e0); 544 HD_WRITE(VC4_HD_CSC_22_21, (0x6e0 << 16) | 0x000); 545 HD_WRITE(VC4_HD_CSC_24_23, (0x100 << 16) | 0x000); 546 HD_WRITE(VC4_HD_CSC_32_31, (0x000 << 16) | 0x6e0); 547 HD_WRITE(VC4_HD_CSC_34_33, (0x100 << 16) | 0x000); 548 vc4_encoder->limited_rgb_range = true; 549 } else { 550 vc4_encoder->limited_rgb_range = false; 551 } 552 553 /* The RGB order applies even when CSC is disabled. */ 554 HD_WRITE(VC4_HD_CSC_CTL, csc_ctl); 555 556 HDMI_WRITE(VC4_HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N); 557 558 if (debug_dump_regs) { 559 DRM_INFO("HDMI regs after:\n"); 560 vc4_hdmi_dump_regs(dev); 561 } 562 } 563 564 static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder) 565 { 566 struct drm_device *dev = encoder->dev; 567 struct vc4_dev *vc4 = to_vc4_dev(dev); 568 569 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, 0); 570 571 HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16); 572 HD_WRITE(VC4_HD_VID_CTL, 573 HD_READ(VC4_HD_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE); 574 } 575 576 static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder) 577 { 578 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 579 struct drm_device *dev = encoder->dev; 580 struct vc4_dev *vc4 = to_vc4_dev(dev); 581 int ret; 582 583 HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0); 584 585 HD_WRITE(VC4_HD_VID_CTL, 586 HD_READ(VC4_HD_VID_CTL) | 587 VC4_HD_VID_CTL_ENABLE | 588 VC4_HD_VID_CTL_UNDERFLOW_ENABLE | 589 VC4_HD_VID_CTL_FRAME_COUNTER_RESET); 590 591 if (vc4_encoder->hdmi_monitor) { 592 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL, 593 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) | 594 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 595 596 ret = wait_for(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) & 597 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000); 598 WARN_ONCE(ret, "Timeout waiting for " 599 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 600 } else { 601 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, 602 HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) & 603 ~(VC4_HDMI_RAM_PACKET_ENABLE)); 604 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL, 605 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) & 606 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 607 608 ret = wait_for(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) & 609 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000); 610 WARN_ONCE(ret, "Timeout waiting for " 611 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 612 } 613 614 if (vc4_encoder->hdmi_monitor) { 615 u32 drift; 616 617 WARN_ON(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) & 618 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE)); 619 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL, 620 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) | 621 VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT); 622 623 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, 624 VC4_HDMI_RAM_PACKET_ENABLE); 625 626 vc4_hdmi_set_infoframes(encoder); 627 628 drift = HDMI_READ(VC4_HDMI_FIFO_CTL); 629 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK; 630 631 HDMI_WRITE(VC4_HDMI_FIFO_CTL, 632 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 633 HDMI_WRITE(VC4_HDMI_FIFO_CTL, 634 drift | VC4_HDMI_FIFO_CTL_RECENTER); 635 udelay(1000); 636 HDMI_WRITE(VC4_HDMI_FIFO_CTL, 637 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 638 HDMI_WRITE(VC4_HDMI_FIFO_CTL, 639 drift | VC4_HDMI_FIFO_CTL_RECENTER); 640 641 ret = wait_for(HDMI_READ(VC4_HDMI_FIFO_CTL) & 642 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1); 643 WARN_ONCE(ret, "Timeout waiting for " 644 "VC4_HDMI_FIFO_CTL_RECENTER_DONE"); 645 } 646 } 647 648 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = { 649 .mode_set = vc4_hdmi_encoder_mode_set, 650 .disable = vc4_hdmi_encoder_disable, 651 .enable = vc4_hdmi_encoder_enable, 652 }; 653 654 /* HDMI audio codec callbacks */ 655 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *hdmi) 656 { 657 struct drm_device *drm = hdmi->encoder->dev; 658 struct vc4_dev *vc4 = to_vc4_dev(drm); 659 u32 hsm_clock = clk_get_rate(hdmi->hsm_clock); 660 unsigned long n, m; 661 662 rational_best_approximation(hsm_clock, hdmi->audio.samplerate, 663 VC4_HD_MAI_SMP_N_MASK >> 664 VC4_HD_MAI_SMP_N_SHIFT, 665 (VC4_HD_MAI_SMP_M_MASK >> 666 VC4_HD_MAI_SMP_M_SHIFT) + 1, 667 &n, &m); 668 669 HD_WRITE(VC4_HD_MAI_SMP, 670 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) | 671 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M)); 672 } 673 674 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *hdmi) 675 { 676 struct drm_encoder *encoder = hdmi->encoder; 677 struct drm_crtc *crtc = encoder->crtc; 678 struct drm_device *drm = encoder->dev; 679 struct vc4_dev *vc4 = to_vc4_dev(drm); 680 const struct drm_display_mode *mode = &crtc->state->adjusted_mode; 681 u32 samplerate = hdmi->audio.samplerate; 682 u32 n, cts; 683 u64 tmp; 684 685 n = 128 * samplerate / 1000; 686 tmp = (u64)(mode->clock * 1000) * n; 687 do_div(tmp, 128 * samplerate); 688 cts = tmp; 689 690 HDMI_WRITE(VC4_HDMI_CRP_CFG, 691 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN | 692 VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N)); 693 694 /* 695 * We could get slightly more accurate clocks in some cases by 696 * providing a CTS_1 value. The two CTS values are alternated 697 * between based on the period fields 698 */ 699 HDMI_WRITE(VC4_HDMI_CTS_0, cts); 700 HDMI_WRITE(VC4_HDMI_CTS_1, cts); 701 } 702 703 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai) 704 { 705 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai); 706 707 return snd_soc_card_get_drvdata(card); 708 } 709 710 static int vc4_hdmi_audio_startup(struct snd_pcm_substream *substream, 711 struct snd_soc_dai *dai) 712 { 713 struct vc4_hdmi *hdmi = dai_to_hdmi(dai); 714 struct drm_encoder *encoder = hdmi->encoder; 715 struct vc4_dev *vc4 = to_vc4_dev(encoder->dev); 716 int ret; 717 718 if (hdmi->audio.substream && hdmi->audio.substream != substream) 719 return -EINVAL; 720 721 hdmi->audio.substream = substream; 722 723 /* 724 * If the HDMI encoder hasn't probed, or the encoder is 725 * currently in DVI mode, treat the codec dai as missing. 726 */ 727 if (!encoder->crtc || !(HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) & 728 VC4_HDMI_RAM_PACKET_ENABLE)) 729 return -ENODEV; 730 731 ret = snd_pcm_hw_constraint_eld(substream->runtime, 732 hdmi->connector->eld); 733 if (ret) 734 return ret; 735 736 return 0; 737 } 738 739 static int vc4_hdmi_audio_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 740 { 741 return 0; 742 } 743 744 static void vc4_hdmi_audio_reset(struct vc4_hdmi *hdmi) 745 { 746 struct drm_encoder *encoder = hdmi->encoder; 747 struct drm_device *drm = encoder->dev; 748 struct device *dev = &hdmi->pdev->dev; 749 struct vc4_dev *vc4 = to_vc4_dev(drm); 750 int ret; 751 752 ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO); 753 if (ret) 754 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret); 755 756 HD_WRITE(VC4_HD_MAI_CTL, VC4_HD_MAI_CTL_RESET); 757 HD_WRITE(VC4_HD_MAI_CTL, VC4_HD_MAI_CTL_ERRORF); 758 HD_WRITE(VC4_HD_MAI_CTL, VC4_HD_MAI_CTL_FLUSH); 759 } 760 761 static void vc4_hdmi_audio_shutdown(struct snd_pcm_substream *substream, 762 struct snd_soc_dai *dai) 763 { 764 struct vc4_hdmi *hdmi = dai_to_hdmi(dai); 765 766 if (substream != hdmi->audio.substream) 767 return; 768 769 vc4_hdmi_audio_reset(hdmi); 770 771 hdmi->audio.substream = NULL; 772 } 773 774 /* HDMI audio codec callbacks */ 775 static int vc4_hdmi_audio_hw_params(struct snd_pcm_substream *substream, 776 struct snd_pcm_hw_params *params, 777 struct snd_soc_dai *dai) 778 { 779 struct vc4_hdmi *hdmi = dai_to_hdmi(dai); 780 struct drm_encoder *encoder = hdmi->encoder; 781 struct drm_device *drm = encoder->dev; 782 struct device *dev = &hdmi->pdev->dev; 783 struct vc4_dev *vc4 = to_vc4_dev(drm); 784 u32 audio_packet_config, channel_mask; 785 u32 channel_map, i; 786 787 if (substream != hdmi->audio.substream) 788 return -EINVAL; 789 790 dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__, 791 params_rate(params), params_width(params), 792 params_channels(params)); 793 794 hdmi->audio.channels = params_channels(params); 795 hdmi->audio.samplerate = params_rate(params); 796 797 HD_WRITE(VC4_HD_MAI_CTL, 798 VC4_HD_MAI_CTL_RESET | 799 VC4_HD_MAI_CTL_FLUSH | 800 VC4_HD_MAI_CTL_DLATE | 801 VC4_HD_MAI_CTL_ERRORE | 802 VC4_HD_MAI_CTL_ERRORF); 803 804 vc4_hdmi_audio_set_mai_clock(hdmi); 805 806 audio_packet_config = 807 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT | 808 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS | 809 VC4_SET_FIELD(0xf, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER); 810 811 channel_mask = GENMASK(hdmi->audio.channels - 1, 0); 812 audio_packet_config |= VC4_SET_FIELD(channel_mask, 813 VC4_HDMI_AUDIO_PACKET_CEA_MASK); 814 815 /* Set the MAI threshold. This logic mimics the firmware's. */ 816 if (hdmi->audio.samplerate > 96000) { 817 HD_WRITE(VC4_HD_MAI_THR, 818 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQHIGH) | 819 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW)); 820 } else if (hdmi->audio.samplerate > 48000) { 821 HD_WRITE(VC4_HD_MAI_THR, 822 VC4_SET_FIELD(0x14, VC4_HD_MAI_THR_DREQHIGH) | 823 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW)); 824 } else { 825 HD_WRITE(VC4_HD_MAI_THR, 826 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) | 827 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) | 828 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQHIGH) | 829 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQLOW)); 830 } 831 832 HDMI_WRITE(VC4_HDMI_MAI_CONFIG, 833 VC4_HDMI_MAI_CONFIG_BIT_REVERSE | 834 VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK)); 835 836 channel_map = 0; 837 for (i = 0; i < 8; i++) { 838 if (channel_mask & BIT(i)) 839 channel_map |= i << (3 * i); 840 } 841 842 HDMI_WRITE(VC4_HDMI_MAI_CHANNEL_MAP, channel_map); 843 HDMI_WRITE(VC4_HDMI_AUDIO_PACKET_CONFIG, audio_packet_config); 844 vc4_hdmi_set_n_cts(hdmi); 845 846 return 0; 847 } 848 849 static int vc4_hdmi_audio_trigger(struct snd_pcm_substream *substream, int cmd, 850 struct snd_soc_dai *dai) 851 { 852 struct vc4_hdmi *hdmi = dai_to_hdmi(dai); 853 struct drm_encoder *encoder = hdmi->encoder; 854 struct drm_device *drm = encoder->dev; 855 struct vc4_dev *vc4 = to_vc4_dev(drm); 856 857 switch (cmd) { 858 case SNDRV_PCM_TRIGGER_START: 859 vc4_hdmi_set_audio_infoframe(encoder); 860 HDMI_WRITE(VC4_HDMI_TX_PHY_CTL0, 861 HDMI_READ(VC4_HDMI_TX_PHY_CTL0) & 862 ~VC4_HDMI_TX_PHY_RNG_PWRDN); 863 HD_WRITE(VC4_HD_MAI_CTL, 864 VC4_SET_FIELD(hdmi->audio.channels, 865 VC4_HD_MAI_CTL_CHNUM) | 866 VC4_HD_MAI_CTL_ENABLE); 867 break; 868 case SNDRV_PCM_TRIGGER_STOP: 869 HD_WRITE(VC4_HD_MAI_CTL, 870 VC4_HD_MAI_CTL_DLATE | 871 VC4_HD_MAI_CTL_ERRORE | 872 VC4_HD_MAI_CTL_ERRORF); 873 HDMI_WRITE(VC4_HDMI_TX_PHY_CTL0, 874 HDMI_READ(VC4_HDMI_TX_PHY_CTL0) | 875 VC4_HDMI_TX_PHY_RNG_PWRDN); 876 break; 877 default: 878 break; 879 } 880 881 return 0; 882 } 883 884 static inline struct vc4_hdmi * 885 snd_component_to_hdmi(struct snd_soc_component *component) 886 { 887 struct snd_soc_card *card = snd_soc_component_get_drvdata(component); 888 889 return snd_soc_card_get_drvdata(card); 890 } 891 892 static int vc4_hdmi_audio_eld_ctl_info(struct snd_kcontrol *kcontrol, 893 struct snd_ctl_elem_info *uinfo) 894 { 895 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 896 struct vc4_hdmi *hdmi = snd_component_to_hdmi(component); 897 898 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 899 uinfo->count = sizeof(hdmi->connector->eld); 900 901 return 0; 902 } 903 904 static int vc4_hdmi_audio_eld_ctl_get(struct snd_kcontrol *kcontrol, 905 struct snd_ctl_elem_value *ucontrol) 906 { 907 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 908 struct vc4_hdmi *hdmi = snd_component_to_hdmi(component); 909 910 memcpy(ucontrol->value.bytes.data, hdmi->connector->eld, 911 sizeof(hdmi->connector->eld)); 912 913 return 0; 914 } 915 916 static const struct snd_kcontrol_new vc4_hdmi_audio_controls[] = { 917 { 918 .access = SNDRV_CTL_ELEM_ACCESS_READ | 919 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 920 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 921 .name = "ELD", 922 .info = vc4_hdmi_audio_eld_ctl_info, 923 .get = vc4_hdmi_audio_eld_ctl_get, 924 }, 925 }; 926 927 static const struct snd_soc_dapm_widget vc4_hdmi_audio_widgets[] = { 928 SND_SOC_DAPM_OUTPUT("TX"), 929 }; 930 931 static const struct snd_soc_dapm_route vc4_hdmi_audio_routes[] = { 932 { "TX", NULL, "Playback" }, 933 }; 934 935 static const struct snd_soc_codec_driver vc4_hdmi_audio_codec_drv = { 936 .component_driver = { 937 .controls = vc4_hdmi_audio_controls, 938 .num_controls = ARRAY_SIZE(vc4_hdmi_audio_controls), 939 .dapm_widgets = vc4_hdmi_audio_widgets, 940 .num_dapm_widgets = ARRAY_SIZE(vc4_hdmi_audio_widgets), 941 .dapm_routes = vc4_hdmi_audio_routes, 942 .num_dapm_routes = ARRAY_SIZE(vc4_hdmi_audio_routes), 943 }, 944 }; 945 946 static const struct snd_soc_dai_ops vc4_hdmi_audio_dai_ops = { 947 .startup = vc4_hdmi_audio_startup, 948 .shutdown = vc4_hdmi_audio_shutdown, 949 .hw_params = vc4_hdmi_audio_hw_params, 950 .set_fmt = vc4_hdmi_audio_set_fmt, 951 .trigger = vc4_hdmi_audio_trigger, 952 }; 953 954 static struct snd_soc_dai_driver vc4_hdmi_audio_codec_dai_drv = { 955 .name = "vc4-hdmi-hifi", 956 .playback = { 957 .stream_name = "Playback", 958 .channels_min = 2, 959 .channels_max = 8, 960 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 961 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 962 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 963 SNDRV_PCM_RATE_192000, 964 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 965 }, 966 }; 967 968 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = { 969 .name = "vc4-hdmi-cpu-dai-component", 970 }; 971 972 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai) 973 { 974 struct vc4_hdmi *hdmi = dai_to_hdmi(dai); 975 976 snd_soc_dai_init_dma_data(dai, &hdmi->audio.dma_data, NULL); 977 978 return 0; 979 } 980 981 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = { 982 .name = "vc4-hdmi-cpu-dai", 983 .probe = vc4_hdmi_audio_cpu_dai_probe, 984 .playback = { 985 .stream_name = "Playback", 986 .channels_min = 1, 987 .channels_max = 8, 988 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 989 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 990 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 991 SNDRV_PCM_RATE_192000, 992 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 993 }, 994 .ops = &vc4_hdmi_audio_dai_ops, 995 }; 996 997 static const struct snd_dmaengine_pcm_config pcm_conf = { 998 .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx", 999 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 1000 }; 1001 1002 static int vc4_hdmi_audio_init(struct vc4_hdmi *hdmi) 1003 { 1004 struct snd_soc_dai_link *dai_link = &hdmi->audio.link; 1005 struct snd_soc_card *card = &hdmi->audio.card; 1006 struct device *dev = &hdmi->pdev->dev; 1007 const __be32 *addr; 1008 int ret; 1009 1010 if (!of_find_property(dev->of_node, "dmas", NULL)) { 1011 dev_warn(dev, 1012 "'dmas' DT property is missing, no HDMI audio\n"); 1013 return 0; 1014 } 1015 1016 /* 1017 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve 1018 * the bus address specified in the DT, because the physical address 1019 * (the one returned by platform_get_resource()) is not appropriate 1020 * for DMA transfers. 1021 * This VC/MMU should probably be exposed to avoid this kind of hacks. 1022 */ 1023 addr = of_get_address(dev->of_node, 1, NULL, NULL); 1024 hdmi->audio.dma_data.addr = be32_to_cpup(addr) + VC4_HD_MAI_DATA; 1025 hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1026 hdmi->audio.dma_data.maxburst = 2; 1027 1028 ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0); 1029 if (ret) { 1030 dev_err(dev, "Could not register PCM component: %d\n", ret); 1031 return ret; 1032 } 1033 1034 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp, 1035 &vc4_hdmi_audio_cpu_dai_drv, 1); 1036 if (ret) { 1037 dev_err(dev, "Could not register CPU DAI: %d\n", ret); 1038 return ret; 1039 } 1040 1041 /* register codec and codec dai */ 1042 ret = snd_soc_register_codec(dev, &vc4_hdmi_audio_codec_drv, 1043 &vc4_hdmi_audio_codec_dai_drv, 1); 1044 if (ret) { 1045 dev_err(dev, "Could not register codec: %d\n", ret); 1046 return ret; 1047 } 1048 1049 dai_link->name = "MAI"; 1050 dai_link->stream_name = "MAI PCM"; 1051 dai_link->codec_dai_name = vc4_hdmi_audio_codec_dai_drv.name; 1052 dai_link->cpu_dai_name = dev_name(dev); 1053 dai_link->codec_name = dev_name(dev); 1054 dai_link->platform_name = dev_name(dev); 1055 1056 card->dai_link = dai_link; 1057 card->num_links = 1; 1058 card->name = "vc4-hdmi"; 1059 card->dev = dev; 1060 1061 /* 1062 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and 1063 * stores a pointer to the snd card object in dev->driver_data. This 1064 * means we cannot use it for something else. The hdmi back-pointer is 1065 * now stored in card->drvdata and should be retrieved with 1066 * snd_soc_card_get_drvdata() if needed. 1067 */ 1068 snd_soc_card_set_drvdata(card, hdmi); 1069 ret = devm_snd_soc_register_card(dev, card); 1070 if (ret) { 1071 dev_err(dev, "Could not register sound card: %d\n", ret); 1072 goto unregister_codec; 1073 } 1074 1075 return 0; 1076 1077 unregister_codec: 1078 snd_soc_unregister_codec(dev); 1079 1080 return ret; 1081 } 1082 1083 static void vc4_hdmi_audio_cleanup(struct vc4_hdmi *hdmi) 1084 { 1085 struct device *dev = &hdmi->pdev->dev; 1086 1087 /* 1088 * If drvdata is not set this means the audio card was not 1089 * registered, just skip codec unregistration in this case. 1090 */ 1091 if (dev_get_drvdata(dev)) 1092 snd_soc_unregister_codec(dev); 1093 } 1094 1095 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data) 1096 { 1097 struct platform_device *pdev = to_platform_device(dev); 1098 struct drm_device *drm = dev_get_drvdata(master); 1099 struct vc4_dev *vc4 = drm->dev_private; 1100 struct vc4_hdmi *hdmi; 1101 struct vc4_hdmi_encoder *vc4_hdmi_encoder; 1102 struct device_node *ddc_node; 1103 u32 value; 1104 int ret; 1105 1106 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); 1107 if (!hdmi) 1108 return -ENOMEM; 1109 1110 vc4_hdmi_encoder = devm_kzalloc(dev, sizeof(*vc4_hdmi_encoder), 1111 GFP_KERNEL); 1112 if (!vc4_hdmi_encoder) 1113 return -ENOMEM; 1114 vc4_hdmi_encoder->base.type = VC4_ENCODER_TYPE_HDMI; 1115 hdmi->encoder = &vc4_hdmi_encoder->base.base; 1116 1117 hdmi->pdev = pdev; 1118 hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0); 1119 if (IS_ERR(hdmi->hdmicore_regs)) 1120 return PTR_ERR(hdmi->hdmicore_regs); 1121 1122 hdmi->hd_regs = vc4_ioremap_regs(pdev, 1); 1123 if (IS_ERR(hdmi->hd_regs)) 1124 return PTR_ERR(hdmi->hd_regs); 1125 1126 hdmi->pixel_clock = devm_clk_get(dev, "pixel"); 1127 if (IS_ERR(hdmi->pixel_clock)) { 1128 DRM_ERROR("Failed to get pixel clock\n"); 1129 return PTR_ERR(hdmi->pixel_clock); 1130 } 1131 hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); 1132 if (IS_ERR(hdmi->hsm_clock)) { 1133 DRM_ERROR("Failed to get HDMI state machine clock\n"); 1134 return PTR_ERR(hdmi->hsm_clock); 1135 } 1136 1137 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0); 1138 if (!ddc_node) { 1139 DRM_ERROR("Failed to find ddc node in device tree\n"); 1140 return -ENODEV; 1141 } 1142 1143 hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node); 1144 of_node_put(ddc_node); 1145 if (!hdmi->ddc) { 1146 DRM_DEBUG("Failed to get ddc i2c adapter by node\n"); 1147 return -EPROBE_DEFER; 1148 } 1149 1150 /* Enable the clocks at startup. We can't quite recover from 1151 * turning off the pixel clock during disable/enables yet, so 1152 * it's always running. 1153 */ 1154 ret = clk_prepare_enable(hdmi->pixel_clock); 1155 if (ret) { 1156 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret); 1157 goto err_put_i2c; 1158 } 1159 1160 /* This is the rate that is set by the firmware. The number 1161 * needs to be a bit higher than the pixel clock rate 1162 * (generally 148.5Mhz). 1163 */ 1164 ret = clk_set_rate(hdmi->hsm_clock, 163682864); 1165 if (ret) { 1166 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret); 1167 goto err_unprepare_pix; 1168 } 1169 1170 ret = clk_prepare_enable(hdmi->hsm_clock); 1171 if (ret) { 1172 DRM_ERROR("Failed to turn on HDMI state machine clock: %d\n", 1173 ret); 1174 goto err_unprepare_pix; 1175 } 1176 1177 /* Only use the GPIO HPD pin if present in the DT, otherwise 1178 * we'll use the HDMI core's register. 1179 */ 1180 if (of_find_property(dev->of_node, "hpd-gpios", &value)) { 1181 enum of_gpio_flags hpd_gpio_flags; 1182 1183 hdmi->hpd_gpio = of_get_named_gpio_flags(dev->of_node, 1184 "hpd-gpios", 0, 1185 &hpd_gpio_flags); 1186 if (hdmi->hpd_gpio < 0) { 1187 ret = hdmi->hpd_gpio; 1188 goto err_unprepare_hsm; 1189 } 1190 1191 hdmi->hpd_active_low = hpd_gpio_flags & OF_GPIO_ACTIVE_LOW; 1192 } 1193 1194 vc4->hdmi = hdmi; 1195 1196 /* HDMI core must be enabled. */ 1197 if (!(HD_READ(VC4_HD_M_CTL) & VC4_HD_M_ENABLE)) { 1198 HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_SW_RST); 1199 udelay(1); 1200 HD_WRITE(VC4_HD_M_CTL, 0); 1201 1202 HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_ENABLE); 1203 1204 HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL, 1205 VC4_HDMI_SW_RESET_HDMI | 1206 VC4_HDMI_SW_RESET_FORMAT_DETECT); 1207 1208 HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL, 0); 1209 1210 /* PHY should be in reset, like 1211 * vc4_hdmi_encoder_disable() does. 1212 */ 1213 HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16); 1214 } 1215 1216 drm_encoder_init(drm, hdmi->encoder, &vc4_hdmi_encoder_funcs, 1217 DRM_MODE_ENCODER_TMDS, NULL); 1218 drm_encoder_helper_add(hdmi->encoder, &vc4_hdmi_encoder_helper_funcs); 1219 1220 hdmi->connector = vc4_hdmi_connector_init(drm, hdmi->encoder); 1221 if (IS_ERR(hdmi->connector)) { 1222 ret = PTR_ERR(hdmi->connector); 1223 goto err_destroy_encoder; 1224 } 1225 1226 ret = vc4_hdmi_audio_init(hdmi); 1227 if (ret) 1228 goto err_destroy_encoder; 1229 1230 return 0; 1231 1232 err_destroy_encoder: 1233 vc4_hdmi_encoder_destroy(hdmi->encoder); 1234 err_unprepare_hsm: 1235 clk_disable_unprepare(hdmi->hsm_clock); 1236 err_unprepare_pix: 1237 clk_disable_unprepare(hdmi->pixel_clock); 1238 err_put_i2c: 1239 put_device(&hdmi->ddc->dev); 1240 1241 return ret; 1242 } 1243 1244 static void vc4_hdmi_unbind(struct device *dev, struct device *master, 1245 void *data) 1246 { 1247 struct drm_device *drm = dev_get_drvdata(master); 1248 struct vc4_dev *vc4 = drm->dev_private; 1249 struct vc4_hdmi *hdmi = vc4->hdmi; 1250 1251 vc4_hdmi_audio_cleanup(hdmi); 1252 1253 vc4_hdmi_connector_destroy(hdmi->connector); 1254 vc4_hdmi_encoder_destroy(hdmi->encoder); 1255 1256 clk_disable_unprepare(hdmi->pixel_clock); 1257 clk_disable_unprepare(hdmi->hsm_clock); 1258 put_device(&hdmi->ddc->dev); 1259 1260 vc4->hdmi = NULL; 1261 } 1262 1263 static const struct component_ops vc4_hdmi_ops = { 1264 .bind = vc4_hdmi_bind, 1265 .unbind = vc4_hdmi_unbind, 1266 }; 1267 1268 static int vc4_hdmi_dev_probe(struct platform_device *pdev) 1269 { 1270 return component_add(&pdev->dev, &vc4_hdmi_ops); 1271 } 1272 1273 static int vc4_hdmi_dev_remove(struct platform_device *pdev) 1274 { 1275 component_del(&pdev->dev, &vc4_hdmi_ops); 1276 return 0; 1277 } 1278 1279 static const struct of_device_id vc4_hdmi_dt_match[] = { 1280 { .compatible = "brcm,bcm2835-hdmi" }, 1281 {} 1282 }; 1283 1284 struct platform_driver vc4_hdmi_driver = { 1285 .probe = vc4_hdmi_dev_probe, 1286 .remove = vc4_hdmi_dev_remove, 1287 .driver = { 1288 .name = "vc4_hdmi", 1289 .of_match_table = vc4_hdmi_dt_match, 1290 }, 1291 }; 1292