1 /* 2 * Copyright (C) 2015 Broadcom 3 * Copyright (c) 2014 The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License version 2 as published by 9 * the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 /** 21 * DOC: VC4 Falcon HDMI module 22 * 23 * The HDMI core has a state machine and a PHY. Most of the unit 24 * operates off of the HSM clock from CPRMAN. It also internally uses 25 * the PLLH_PIX clock for the PHY. 26 */ 27 28 #include "drm_atomic_helper.h" 29 #include "drm_crtc_helper.h" 30 #include "drm_edid.h" 31 #include "linux/clk.h" 32 #include "linux/component.h" 33 #include "linux/i2c.h" 34 #include "linux/of_gpio.h" 35 #include "linux/of_platform.h" 36 #include "vc4_drv.h" 37 #include "vc4_regs.h" 38 39 /* General HDMI hardware state. */ 40 struct vc4_hdmi { 41 struct platform_device *pdev; 42 43 struct drm_encoder *encoder; 44 struct drm_connector *connector; 45 46 struct i2c_adapter *ddc; 47 void __iomem *hdmicore_regs; 48 void __iomem *hd_regs; 49 int hpd_gpio; 50 bool hpd_active_low; 51 52 struct clk *pixel_clock; 53 struct clk *hsm_clock; 54 }; 55 56 #define HDMI_READ(offset) readl(vc4->hdmi->hdmicore_regs + offset) 57 #define HDMI_WRITE(offset, val) writel(val, vc4->hdmi->hdmicore_regs + offset) 58 #define HD_READ(offset) readl(vc4->hdmi->hd_regs + offset) 59 #define HD_WRITE(offset, val) writel(val, vc4->hdmi->hd_regs + offset) 60 61 /* VC4 HDMI encoder KMS struct */ 62 struct vc4_hdmi_encoder { 63 struct vc4_encoder base; 64 bool hdmi_monitor; 65 bool limited_rgb_range; 66 bool rgb_range_selectable; 67 }; 68 69 static inline struct vc4_hdmi_encoder * 70 to_vc4_hdmi_encoder(struct drm_encoder *encoder) 71 { 72 return container_of(encoder, struct vc4_hdmi_encoder, base.base); 73 } 74 75 /* VC4 HDMI connector KMS struct */ 76 struct vc4_hdmi_connector { 77 struct drm_connector base; 78 79 /* Since the connector is attached to just the one encoder, 80 * this is the reference to it so we can do the best_encoder() 81 * hook. 82 */ 83 struct drm_encoder *encoder; 84 }; 85 86 static inline struct vc4_hdmi_connector * 87 to_vc4_hdmi_connector(struct drm_connector *connector) 88 { 89 return container_of(connector, struct vc4_hdmi_connector, base); 90 } 91 92 #define HDMI_REG(reg) { reg, #reg } 93 static const struct { 94 u32 reg; 95 const char *name; 96 } hdmi_regs[] = { 97 HDMI_REG(VC4_HDMI_CORE_REV), 98 HDMI_REG(VC4_HDMI_SW_RESET_CONTROL), 99 HDMI_REG(VC4_HDMI_HOTPLUG_INT), 100 HDMI_REG(VC4_HDMI_HOTPLUG), 101 HDMI_REG(VC4_HDMI_RAM_PACKET_CONFIG), 102 HDMI_REG(VC4_HDMI_HORZA), 103 HDMI_REG(VC4_HDMI_HORZB), 104 HDMI_REG(VC4_HDMI_FIFO_CTL), 105 HDMI_REG(VC4_HDMI_SCHEDULER_CONTROL), 106 HDMI_REG(VC4_HDMI_VERTA0), 107 HDMI_REG(VC4_HDMI_VERTA1), 108 HDMI_REG(VC4_HDMI_VERTB0), 109 HDMI_REG(VC4_HDMI_VERTB1), 110 HDMI_REG(VC4_HDMI_TX_PHY_RESET_CTL), 111 }; 112 113 static const struct { 114 u32 reg; 115 const char *name; 116 } hd_regs[] = { 117 HDMI_REG(VC4_HD_M_CTL), 118 HDMI_REG(VC4_HD_MAI_CTL), 119 HDMI_REG(VC4_HD_VID_CTL), 120 HDMI_REG(VC4_HD_CSC_CTL), 121 HDMI_REG(VC4_HD_FRAME_COUNT), 122 }; 123 124 #ifdef CONFIG_DEBUG_FS 125 int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused) 126 { 127 struct drm_info_node *node = (struct drm_info_node *)m->private; 128 struct drm_device *dev = node->minor->dev; 129 struct vc4_dev *vc4 = to_vc4_dev(dev); 130 int i; 131 132 for (i = 0; i < ARRAY_SIZE(hdmi_regs); i++) { 133 seq_printf(m, "%s (0x%04x): 0x%08x\n", 134 hdmi_regs[i].name, hdmi_regs[i].reg, 135 HDMI_READ(hdmi_regs[i].reg)); 136 } 137 138 for (i = 0; i < ARRAY_SIZE(hd_regs); i++) { 139 seq_printf(m, "%s (0x%04x): 0x%08x\n", 140 hd_regs[i].name, hd_regs[i].reg, 141 HD_READ(hd_regs[i].reg)); 142 } 143 144 return 0; 145 } 146 #endif /* CONFIG_DEBUG_FS */ 147 148 static void vc4_hdmi_dump_regs(struct drm_device *dev) 149 { 150 struct vc4_dev *vc4 = to_vc4_dev(dev); 151 int i; 152 153 for (i = 0; i < ARRAY_SIZE(hdmi_regs); i++) { 154 DRM_INFO("0x%04x (%s): 0x%08x\n", 155 hdmi_regs[i].reg, hdmi_regs[i].name, 156 HDMI_READ(hdmi_regs[i].reg)); 157 } 158 for (i = 0; i < ARRAY_SIZE(hd_regs); i++) { 159 DRM_INFO("0x%04x (%s): 0x%08x\n", 160 hd_regs[i].reg, hd_regs[i].name, 161 HD_READ(hd_regs[i].reg)); 162 } 163 } 164 165 static enum drm_connector_status 166 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force) 167 { 168 struct drm_device *dev = connector->dev; 169 struct vc4_dev *vc4 = to_vc4_dev(dev); 170 171 if (vc4->hdmi->hpd_gpio) { 172 if (gpio_get_value_cansleep(vc4->hdmi->hpd_gpio) ^ 173 vc4->hdmi->hpd_active_low) 174 return connector_status_connected; 175 else 176 return connector_status_disconnected; 177 } 178 179 if (drm_probe_ddc(vc4->hdmi->ddc)) 180 return connector_status_connected; 181 182 if (HDMI_READ(VC4_HDMI_HOTPLUG) & VC4_HDMI_HOTPLUG_CONNECTED) 183 return connector_status_connected; 184 else 185 return connector_status_disconnected; 186 } 187 188 static void vc4_hdmi_connector_destroy(struct drm_connector *connector) 189 { 190 drm_connector_unregister(connector); 191 drm_connector_cleanup(connector); 192 } 193 194 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector) 195 { 196 struct vc4_hdmi_connector *vc4_connector = 197 to_vc4_hdmi_connector(connector); 198 struct drm_encoder *encoder = vc4_connector->encoder; 199 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 200 struct drm_device *dev = connector->dev; 201 struct vc4_dev *vc4 = to_vc4_dev(dev); 202 int ret = 0; 203 struct edid *edid; 204 205 edid = drm_get_edid(connector, vc4->hdmi->ddc); 206 if (!edid) 207 return -ENODEV; 208 209 vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid); 210 211 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) { 212 vc4_encoder->rgb_range_selectable = 213 drm_rgb_quant_range_selectable(edid); 214 } 215 216 drm_mode_connector_update_edid_property(connector, edid); 217 ret = drm_add_edid_modes(connector, edid); 218 219 return ret; 220 } 221 222 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = { 223 .dpms = drm_atomic_helper_connector_dpms, 224 .detect = vc4_hdmi_connector_detect, 225 .fill_modes = drm_helper_probe_single_connector_modes, 226 .destroy = vc4_hdmi_connector_destroy, 227 .reset = drm_atomic_helper_connector_reset, 228 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 229 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 230 }; 231 232 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = { 233 .get_modes = vc4_hdmi_connector_get_modes, 234 }; 235 236 static struct drm_connector *vc4_hdmi_connector_init(struct drm_device *dev, 237 struct drm_encoder *encoder) 238 { 239 struct drm_connector *connector = NULL; 240 struct vc4_hdmi_connector *hdmi_connector; 241 int ret = 0; 242 243 hdmi_connector = devm_kzalloc(dev->dev, sizeof(*hdmi_connector), 244 GFP_KERNEL); 245 if (!hdmi_connector) { 246 ret = -ENOMEM; 247 goto fail; 248 } 249 connector = &hdmi_connector->base; 250 251 hdmi_connector->encoder = encoder; 252 253 drm_connector_init(dev, connector, &vc4_hdmi_connector_funcs, 254 DRM_MODE_CONNECTOR_HDMIA); 255 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs); 256 257 connector->polled = (DRM_CONNECTOR_POLL_CONNECT | 258 DRM_CONNECTOR_POLL_DISCONNECT); 259 260 connector->interlace_allowed = 1; 261 connector->doublescan_allowed = 0; 262 263 drm_mode_connector_attach_encoder(connector, encoder); 264 265 return connector; 266 267 fail: 268 if (connector) 269 vc4_hdmi_connector_destroy(connector); 270 271 return ERR_PTR(ret); 272 } 273 274 static void vc4_hdmi_encoder_destroy(struct drm_encoder *encoder) 275 { 276 drm_encoder_cleanup(encoder); 277 } 278 279 static const struct drm_encoder_funcs vc4_hdmi_encoder_funcs = { 280 .destroy = vc4_hdmi_encoder_destroy, 281 }; 282 283 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder, 284 enum hdmi_infoframe_type type) 285 { 286 struct drm_device *dev = encoder->dev; 287 struct vc4_dev *vc4 = to_vc4_dev(dev); 288 u32 packet_id = type - 0x80; 289 290 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, 291 HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id)); 292 293 return wait_for(!(HDMI_READ(VC4_HDMI_RAM_PACKET_STATUS) & 294 BIT(packet_id)), 100); 295 } 296 297 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder, 298 union hdmi_infoframe *frame) 299 { 300 struct drm_device *dev = encoder->dev; 301 struct vc4_dev *vc4 = to_vc4_dev(dev); 302 u32 packet_id = frame->any.type - 0x80; 303 u32 packet_reg = VC4_HDMI_GCP_0 + VC4_HDMI_PACKET_STRIDE * packet_id; 304 uint8_t buffer[VC4_HDMI_PACKET_STRIDE]; 305 ssize_t len, i; 306 int ret; 307 308 WARN_ONCE(!(HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) & 309 VC4_HDMI_RAM_PACKET_ENABLE), 310 "Packet RAM has to be on to store the packet."); 311 312 len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer)); 313 if (len < 0) 314 return; 315 316 ret = vc4_hdmi_stop_packet(encoder, frame->any.type); 317 if (ret) { 318 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret); 319 return; 320 } 321 322 for (i = 0; i < len; i += 7) { 323 HDMI_WRITE(packet_reg, 324 buffer[i + 0] << 0 | 325 buffer[i + 1] << 8 | 326 buffer[i + 2] << 16); 327 packet_reg += 4; 328 329 HDMI_WRITE(packet_reg, 330 buffer[i + 3] << 0 | 331 buffer[i + 4] << 8 | 332 buffer[i + 5] << 16 | 333 buffer[i + 6] << 24); 334 packet_reg += 4; 335 } 336 337 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, 338 HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) | BIT(packet_id)); 339 ret = wait_for((HDMI_READ(VC4_HDMI_RAM_PACKET_STATUS) & 340 BIT(packet_id)), 100); 341 if (ret) 342 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret); 343 } 344 345 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder) 346 { 347 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 348 struct drm_crtc *crtc = encoder->crtc; 349 const struct drm_display_mode *mode = &crtc->state->adjusted_mode; 350 union hdmi_infoframe frame; 351 int ret; 352 353 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, mode); 354 if (ret < 0) { 355 DRM_ERROR("couldn't fill AVI infoframe\n"); 356 return; 357 } 358 359 drm_hdmi_avi_infoframe_quant_range(&frame.avi, mode, 360 vc4_encoder->limited_rgb_range ? 361 HDMI_QUANTIZATION_RANGE_LIMITED : 362 HDMI_QUANTIZATION_RANGE_FULL, 363 vc4_encoder->rgb_range_selectable); 364 365 vc4_hdmi_write_infoframe(encoder, &frame); 366 } 367 368 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder) 369 { 370 union hdmi_infoframe frame; 371 int ret; 372 373 ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore"); 374 if (ret < 0) { 375 DRM_ERROR("couldn't fill SPD infoframe\n"); 376 return; 377 } 378 379 frame.spd.sdi = HDMI_SPD_SDI_PC; 380 381 vc4_hdmi_write_infoframe(encoder, &frame); 382 } 383 384 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder) 385 { 386 vc4_hdmi_set_avi_infoframe(encoder); 387 vc4_hdmi_set_spd_infoframe(encoder); 388 } 389 390 static void vc4_hdmi_encoder_mode_set(struct drm_encoder *encoder, 391 struct drm_display_mode *unadjusted_mode, 392 struct drm_display_mode *mode) 393 { 394 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 395 struct drm_device *dev = encoder->dev; 396 struct vc4_dev *vc4 = to_vc4_dev(dev); 397 bool debug_dump_regs = false; 398 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 399 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 400 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 401 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 402 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 403 VC4_HDMI_VERTA_VSP) | 404 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 405 VC4_HDMI_VERTA_VFP) | 406 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL)); 407 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 408 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end, 409 VC4_HDMI_VERTB_VBP)); 410 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 411 VC4_SET_FIELD(mode->crtc_vtotal - 412 mode->crtc_vsync_end - 413 interlaced, 414 VC4_HDMI_VERTB_VBP)); 415 u32 csc_ctl; 416 417 if (debug_dump_regs) { 418 DRM_INFO("HDMI regs before:\n"); 419 vc4_hdmi_dump_regs(dev); 420 } 421 422 HD_WRITE(VC4_HD_VID_CTL, 0); 423 424 clk_set_rate(vc4->hdmi->pixel_clock, mode->clock * 1000 * 425 ((mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1)); 426 427 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL, 428 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) | 429 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT | 430 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS); 431 432 HDMI_WRITE(VC4_HDMI_HORZA, 433 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) | 434 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) | 435 VC4_SET_FIELD(mode->hdisplay * pixel_rep, 436 VC4_HDMI_HORZA_HAP)); 437 438 HDMI_WRITE(VC4_HDMI_HORZB, 439 VC4_SET_FIELD((mode->htotal - 440 mode->hsync_end) * pixel_rep, 441 VC4_HDMI_HORZB_HBP) | 442 VC4_SET_FIELD((mode->hsync_end - 443 mode->hsync_start) * pixel_rep, 444 VC4_HDMI_HORZB_HSP) | 445 VC4_SET_FIELD((mode->hsync_start - 446 mode->hdisplay) * pixel_rep, 447 VC4_HDMI_HORZB_HFP)); 448 449 HDMI_WRITE(VC4_HDMI_VERTA0, verta); 450 HDMI_WRITE(VC4_HDMI_VERTA1, verta); 451 452 HDMI_WRITE(VC4_HDMI_VERTB0, vertb_even); 453 HDMI_WRITE(VC4_HDMI_VERTB1, vertb); 454 455 HD_WRITE(VC4_HD_VID_CTL, 456 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) | 457 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW)); 458 459 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR, 460 VC4_HD_CSC_CTL_ORDER); 461 462 if (vc4_encoder->hdmi_monitor && 463 drm_default_rgb_quant_range(mode) == 464 HDMI_QUANTIZATION_RANGE_LIMITED) { 465 /* CEA VICs other than #1 requre limited range RGB 466 * output unless overridden by an AVI infoframe. 467 * Apply a colorspace conversion to squash 0-255 down 468 * to 16-235. The matrix here is: 469 * 470 * [ 0 0 0.8594 16] 471 * [ 0 0.8594 0 16] 472 * [ 0.8594 0 0 16] 473 * [ 0 0 0 1] 474 */ 475 csc_ctl |= VC4_HD_CSC_CTL_ENABLE; 476 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC; 477 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM, 478 VC4_HD_CSC_CTL_MODE); 479 480 HD_WRITE(VC4_HD_CSC_12_11, (0x000 << 16) | 0x000); 481 HD_WRITE(VC4_HD_CSC_14_13, (0x100 << 16) | 0x6e0); 482 HD_WRITE(VC4_HD_CSC_22_21, (0x6e0 << 16) | 0x000); 483 HD_WRITE(VC4_HD_CSC_24_23, (0x100 << 16) | 0x000); 484 HD_WRITE(VC4_HD_CSC_32_31, (0x000 << 16) | 0x6e0); 485 HD_WRITE(VC4_HD_CSC_34_33, (0x100 << 16) | 0x000); 486 vc4_encoder->limited_rgb_range = true; 487 } else { 488 vc4_encoder->limited_rgb_range = false; 489 } 490 491 /* The RGB order applies even when CSC is disabled. */ 492 HD_WRITE(VC4_HD_CSC_CTL, csc_ctl); 493 494 HDMI_WRITE(VC4_HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N); 495 496 if (debug_dump_regs) { 497 DRM_INFO("HDMI regs after:\n"); 498 vc4_hdmi_dump_regs(dev); 499 } 500 } 501 502 static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder) 503 { 504 struct drm_device *dev = encoder->dev; 505 struct vc4_dev *vc4 = to_vc4_dev(dev); 506 507 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, 0); 508 509 HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16); 510 HD_WRITE(VC4_HD_VID_CTL, 511 HD_READ(VC4_HD_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE); 512 } 513 514 static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder) 515 { 516 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 517 struct drm_device *dev = encoder->dev; 518 struct vc4_dev *vc4 = to_vc4_dev(dev); 519 int ret; 520 521 HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0); 522 523 HD_WRITE(VC4_HD_VID_CTL, 524 HD_READ(VC4_HD_VID_CTL) | 525 VC4_HD_VID_CTL_ENABLE | 526 VC4_HD_VID_CTL_UNDERFLOW_ENABLE | 527 VC4_HD_VID_CTL_FRAME_COUNTER_RESET); 528 529 if (vc4_encoder->hdmi_monitor) { 530 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL, 531 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) | 532 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 533 534 ret = wait_for(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) & 535 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000); 536 WARN_ONCE(ret, "Timeout waiting for " 537 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 538 } else { 539 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, 540 HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) & 541 ~(VC4_HDMI_RAM_PACKET_ENABLE)); 542 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL, 543 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) & 544 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 545 546 ret = wait_for(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) & 547 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000); 548 WARN_ONCE(ret, "Timeout waiting for " 549 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 550 } 551 552 if (vc4_encoder->hdmi_monitor) { 553 u32 drift; 554 555 WARN_ON(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) & 556 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE)); 557 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL, 558 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) | 559 VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT); 560 561 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, 562 VC4_HDMI_RAM_PACKET_ENABLE); 563 564 vc4_hdmi_set_infoframes(encoder); 565 566 drift = HDMI_READ(VC4_HDMI_FIFO_CTL); 567 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK; 568 569 HDMI_WRITE(VC4_HDMI_FIFO_CTL, 570 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 571 HDMI_WRITE(VC4_HDMI_FIFO_CTL, 572 drift | VC4_HDMI_FIFO_CTL_RECENTER); 573 udelay(1000); 574 HDMI_WRITE(VC4_HDMI_FIFO_CTL, 575 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 576 HDMI_WRITE(VC4_HDMI_FIFO_CTL, 577 drift | VC4_HDMI_FIFO_CTL_RECENTER); 578 579 ret = wait_for(HDMI_READ(VC4_HDMI_FIFO_CTL) & 580 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1); 581 WARN_ONCE(ret, "Timeout waiting for " 582 "VC4_HDMI_FIFO_CTL_RECENTER_DONE"); 583 } 584 } 585 586 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = { 587 .mode_set = vc4_hdmi_encoder_mode_set, 588 .disable = vc4_hdmi_encoder_disable, 589 .enable = vc4_hdmi_encoder_enable, 590 }; 591 592 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data) 593 { 594 struct platform_device *pdev = to_platform_device(dev); 595 struct drm_device *drm = dev_get_drvdata(master); 596 struct vc4_dev *vc4 = drm->dev_private; 597 struct vc4_hdmi *hdmi; 598 struct vc4_hdmi_encoder *vc4_hdmi_encoder; 599 struct device_node *ddc_node; 600 u32 value; 601 int ret; 602 603 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); 604 if (!hdmi) 605 return -ENOMEM; 606 607 vc4_hdmi_encoder = devm_kzalloc(dev, sizeof(*vc4_hdmi_encoder), 608 GFP_KERNEL); 609 if (!vc4_hdmi_encoder) 610 return -ENOMEM; 611 vc4_hdmi_encoder->base.type = VC4_ENCODER_TYPE_HDMI; 612 hdmi->encoder = &vc4_hdmi_encoder->base.base; 613 614 hdmi->pdev = pdev; 615 hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0); 616 if (IS_ERR(hdmi->hdmicore_regs)) 617 return PTR_ERR(hdmi->hdmicore_regs); 618 619 hdmi->hd_regs = vc4_ioremap_regs(pdev, 1); 620 if (IS_ERR(hdmi->hd_regs)) 621 return PTR_ERR(hdmi->hd_regs); 622 623 hdmi->pixel_clock = devm_clk_get(dev, "pixel"); 624 if (IS_ERR(hdmi->pixel_clock)) { 625 DRM_ERROR("Failed to get pixel clock\n"); 626 return PTR_ERR(hdmi->pixel_clock); 627 } 628 hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); 629 if (IS_ERR(hdmi->hsm_clock)) { 630 DRM_ERROR("Failed to get HDMI state machine clock\n"); 631 return PTR_ERR(hdmi->hsm_clock); 632 } 633 634 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0); 635 if (!ddc_node) { 636 DRM_ERROR("Failed to find ddc node in device tree\n"); 637 return -ENODEV; 638 } 639 640 hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node); 641 of_node_put(ddc_node); 642 if (!hdmi->ddc) { 643 DRM_DEBUG("Failed to get ddc i2c adapter by node\n"); 644 return -EPROBE_DEFER; 645 } 646 647 /* Enable the clocks at startup. We can't quite recover from 648 * turning off the pixel clock during disable/enables yet, so 649 * it's always running. 650 */ 651 ret = clk_prepare_enable(hdmi->pixel_clock); 652 if (ret) { 653 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret); 654 goto err_put_i2c; 655 } 656 657 /* This is the rate that is set by the firmware. The number 658 * needs to be a bit higher than the pixel clock rate 659 * (generally 148.5Mhz). 660 */ 661 ret = clk_set_rate(hdmi->hsm_clock, 163682864); 662 if (ret) { 663 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret); 664 goto err_unprepare_pix; 665 } 666 667 ret = clk_prepare_enable(hdmi->hsm_clock); 668 if (ret) { 669 DRM_ERROR("Failed to turn on HDMI state machine clock: %d\n", 670 ret); 671 goto err_unprepare_pix; 672 } 673 674 /* Only use the GPIO HPD pin if present in the DT, otherwise 675 * we'll use the HDMI core's register. 676 */ 677 if (of_find_property(dev->of_node, "hpd-gpios", &value)) { 678 enum of_gpio_flags hpd_gpio_flags; 679 680 hdmi->hpd_gpio = of_get_named_gpio_flags(dev->of_node, 681 "hpd-gpios", 0, 682 &hpd_gpio_flags); 683 if (hdmi->hpd_gpio < 0) { 684 ret = hdmi->hpd_gpio; 685 goto err_unprepare_hsm; 686 } 687 688 hdmi->hpd_active_low = hpd_gpio_flags & OF_GPIO_ACTIVE_LOW; 689 } 690 691 vc4->hdmi = hdmi; 692 693 /* HDMI core must be enabled. */ 694 if (!(HD_READ(VC4_HD_M_CTL) & VC4_HD_M_ENABLE)) { 695 HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_SW_RST); 696 udelay(1); 697 HD_WRITE(VC4_HD_M_CTL, 0); 698 699 HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_ENABLE); 700 701 HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL, 702 VC4_HDMI_SW_RESET_HDMI | 703 VC4_HDMI_SW_RESET_FORMAT_DETECT); 704 705 HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL, 0); 706 707 /* PHY should be in reset, like 708 * vc4_hdmi_encoder_disable() does. 709 */ 710 HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16); 711 } 712 713 drm_encoder_init(drm, hdmi->encoder, &vc4_hdmi_encoder_funcs, 714 DRM_MODE_ENCODER_TMDS, NULL); 715 drm_encoder_helper_add(hdmi->encoder, &vc4_hdmi_encoder_helper_funcs); 716 717 hdmi->connector = vc4_hdmi_connector_init(drm, hdmi->encoder); 718 if (IS_ERR(hdmi->connector)) { 719 ret = PTR_ERR(hdmi->connector); 720 goto err_destroy_encoder; 721 } 722 723 return 0; 724 725 err_destroy_encoder: 726 vc4_hdmi_encoder_destroy(hdmi->encoder); 727 err_unprepare_hsm: 728 clk_disable_unprepare(hdmi->hsm_clock); 729 err_unprepare_pix: 730 clk_disable_unprepare(hdmi->pixel_clock); 731 err_put_i2c: 732 put_device(&hdmi->ddc->dev); 733 734 return ret; 735 } 736 737 static void vc4_hdmi_unbind(struct device *dev, struct device *master, 738 void *data) 739 { 740 struct drm_device *drm = dev_get_drvdata(master); 741 struct vc4_dev *vc4 = drm->dev_private; 742 struct vc4_hdmi *hdmi = vc4->hdmi; 743 744 vc4_hdmi_connector_destroy(hdmi->connector); 745 vc4_hdmi_encoder_destroy(hdmi->encoder); 746 747 clk_disable_unprepare(hdmi->pixel_clock); 748 clk_disable_unprepare(hdmi->hsm_clock); 749 put_device(&hdmi->ddc->dev); 750 751 vc4->hdmi = NULL; 752 } 753 754 static const struct component_ops vc4_hdmi_ops = { 755 .bind = vc4_hdmi_bind, 756 .unbind = vc4_hdmi_unbind, 757 }; 758 759 static int vc4_hdmi_dev_probe(struct platform_device *pdev) 760 { 761 return component_add(&pdev->dev, &vc4_hdmi_ops); 762 } 763 764 static int vc4_hdmi_dev_remove(struct platform_device *pdev) 765 { 766 component_del(&pdev->dev, &vc4_hdmi_ops); 767 return 0; 768 } 769 770 static const struct of_device_id vc4_hdmi_dt_match[] = { 771 { .compatible = "brcm,bcm2835-hdmi" }, 772 {} 773 }; 774 775 struct platform_driver vc4_hdmi_driver = { 776 .probe = vc4_hdmi_dev_probe, 777 .remove = vc4_hdmi_dev_remove, 778 .driver = { 779 .name = "vc4_hdmi", 780 .of_match_table = vc4_hdmi_dt_match, 781 }, 782 }; 783