1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 Broadcom 4 * Copyright (c) 2014 The Linux Foundation. All rights reserved. 5 * Copyright (C) 2013 Red Hat 6 * Author: Rob Clark <robdclark@gmail.com> 7 */ 8 9 /** 10 * DOC: VC4 Falcon HDMI module 11 * 12 * The HDMI core has a state machine and a PHY. On BCM2835, most of 13 * the unit operates off of the HSM clock from CPRMAN. It also 14 * internally uses the PLLH_PIX clock for the PHY. 15 * 16 * HDMI infoframes are kept within a small packet ram, where each 17 * packet can be individually enabled for including in a frame. 18 * 19 * HDMI audio is implemented entirely within the HDMI IP block. A 20 * register in the HDMI encoder takes SPDIF frames from the DMA engine 21 * and transfers them over an internal MAI (multi-channel audio 22 * interconnect) bus to the encoder side for insertion into the video 23 * blank regions. 24 * 25 * The driver's HDMI encoder does not yet support power management. 26 * The HDMI encoder's power domain and the HSM/pixel clocks are kept 27 * continuously running, and only the HDMI logic and packet ram are 28 * powered off/on at disable/enable time. 29 * 30 * The driver does not yet support CEC control, though the HDMI 31 * encoder block has CEC support. 32 */ 33 34 #include <drm/display/drm_hdmi_helper.h> 35 #include <drm/display/drm_scdc_helper.h> 36 #include <drm/drm_atomic_helper.h> 37 #include <drm/drm_drv.h> 38 #include <drm/drm_probe_helper.h> 39 #include <drm/drm_simple_kms_helper.h> 40 #include <linux/clk.h> 41 #include <linux/component.h> 42 #include <linux/gpio/consumer.h> 43 #include <linux/i2c.h> 44 #include <linux/of_address.h> 45 #include <linux/of_platform.h> 46 #include <linux/pm_runtime.h> 47 #include <linux/rational.h> 48 #include <linux/reset.h> 49 #include <sound/dmaengine_pcm.h> 50 #include <sound/hdmi-codec.h> 51 #include <sound/pcm_drm_eld.h> 52 #include <sound/pcm_params.h> 53 #include <sound/soc.h> 54 #include "media/cec.h" 55 #include "vc4_drv.h" 56 #include "vc4_hdmi.h" 57 #include "vc4_hdmi_regs.h" 58 #include "vc4_regs.h" 59 60 #define VC5_HDMI_HORZA_HFP_SHIFT 16 61 #define VC5_HDMI_HORZA_HFP_MASK VC4_MASK(28, 16) 62 #define VC5_HDMI_HORZA_VPOS BIT(15) 63 #define VC5_HDMI_HORZA_HPOS BIT(14) 64 #define VC5_HDMI_HORZA_HAP_SHIFT 0 65 #define VC5_HDMI_HORZA_HAP_MASK VC4_MASK(13, 0) 66 67 #define VC5_HDMI_HORZB_HBP_SHIFT 16 68 #define VC5_HDMI_HORZB_HBP_MASK VC4_MASK(26, 16) 69 #define VC5_HDMI_HORZB_HSP_SHIFT 0 70 #define VC5_HDMI_HORZB_HSP_MASK VC4_MASK(10, 0) 71 72 #define VC5_HDMI_VERTA_VSP_SHIFT 24 73 #define VC5_HDMI_VERTA_VSP_MASK VC4_MASK(28, 24) 74 #define VC5_HDMI_VERTA_VFP_SHIFT 16 75 #define VC5_HDMI_VERTA_VFP_MASK VC4_MASK(22, 16) 76 #define VC5_HDMI_VERTA_VAL_SHIFT 0 77 #define VC5_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0) 78 79 #define VC5_HDMI_VERTB_VSPO_SHIFT 16 80 #define VC5_HDMI_VERTB_VSPO_MASK VC4_MASK(29, 16) 81 82 #define VC4_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT 0 83 #define VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK VC4_MASK(3, 0) 84 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT 0 85 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK VC4_MASK(3, 0) 86 87 #define VC5_HDMI_SCRAMBLER_CTL_ENABLE BIT(0) 88 89 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT 8 90 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK VC4_MASK(10, 8) 91 92 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT 0 93 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK VC4_MASK(3, 0) 94 95 #define VC5_HDMI_GCP_CONFIG_GCP_ENABLE BIT(31) 96 97 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT 8 98 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK VC4_MASK(15, 8) 99 100 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_MASK VC4_MASK(7, 0) 101 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_SET_AVMUTE BIT(0) 102 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_CLEAR_AVMUTE BIT(4) 103 104 # define VC4_HD_M_SW_RST BIT(2) 105 # define VC4_HD_M_ENABLE BIT(0) 106 107 #define HSM_MIN_CLOCK_FREQ 120000000 108 #define CEC_CLOCK_FREQ 40000 109 110 #define HDMI_14_MAX_TMDS_CLK (340 * 1000 * 1000) 111 112 static const char * const output_format_str[] = { 113 [VC4_HDMI_OUTPUT_RGB] = "RGB", 114 [VC4_HDMI_OUTPUT_YUV420] = "YUV 4:2:0", 115 [VC4_HDMI_OUTPUT_YUV422] = "YUV 4:2:2", 116 [VC4_HDMI_OUTPUT_YUV444] = "YUV 4:4:4", 117 }; 118 119 static const char *vc4_hdmi_output_fmt_str(enum vc4_hdmi_output_format fmt) 120 { 121 if (fmt >= ARRAY_SIZE(output_format_str)) 122 return "invalid"; 123 124 return output_format_str[fmt]; 125 } 126 127 static unsigned long long 128 vc4_hdmi_encoder_compute_mode_clock(const struct drm_display_mode *mode, 129 unsigned int bpc, enum vc4_hdmi_output_format fmt); 130 131 static bool vc4_hdmi_supports_scrambling(struct vc4_hdmi *vc4_hdmi) 132 { 133 struct drm_display_info *display = &vc4_hdmi->connector.display_info; 134 135 lockdep_assert_held(&vc4_hdmi->mutex); 136 137 if (!display->is_hdmi) 138 return false; 139 140 if (!display->hdmi.scdc.supported || 141 !display->hdmi.scdc.scrambling.supported) 142 return false; 143 144 return true; 145 } 146 147 static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode, 148 unsigned int bpc, 149 enum vc4_hdmi_output_format fmt) 150 { 151 unsigned long long clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc, fmt); 152 153 return clock > HDMI_14_MAX_TMDS_CLK; 154 } 155 156 static bool vc4_hdmi_is_full_range(struct vc4_hdmi *vc4_hdmi, 157 struct vc4_hdmi_connector_state *vc4_state) 158 { 159 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 160 struct drm_display_info *display = &vc4_hdmi->connector.display_info; 161 162 if (vc4_state->broadcast_rgb == VC4_HDMI_BROADCAST_RGB_LIMITED) 163 return false; 164 else if (vc4_state->broadcast_rgb == VC4_HDMI_BROADCAST_RGB_FULL) 165 return true; 166 167 return !display->is_hdmi || 168 drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_FULL; 169 } 170 171 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused) 172 { 173 struct drm_debugfs_entry *entry = m->private; 174 struct vc4_hdmi *vc4_hdmi = entry->file.data; 175 struct drm_device *drm = vc4_hdmi->connector.dev; 176 struct drm_printer p = drm_seq_file_printer(m); 177 int idx; 178 179 if (!drm_dev_enter(drm, &idx)) 180 return -ENODEV; 181 182 drm_print_regset32(&p, &vc4_hdmi->hdmi_regset); 183 drm_print_regset32(&p, &vc4_hdmi->hd_regset); 184 drm_print_regset32(&p, &vc4_hdmi->cec_regset); 185 drm_print_regset32(&p, &vc4_hdmi->csc_regset); 186 drm_print_regset32(&p, &vc4_hdmi->dvp_regset); 187 drm_print_regset32(&p, &vc4_hdmi->phy_regset); 188 drm_print_regset32(&p, &vc4_hdmi->ram_regset); 189 drm_print_regset32(&p, &vc4_hdmi->rm_regset); 190 191 drm_dev_exit(idx); 192 193 return 0; 194 } 195 196 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi) 197 { 198 struct drm_device *drm = vc4_hdmi->connector.dev; 199 unsigned long flags; 200 int idx; 201 202 /* 203 * We can be called by our bind callback, when the 204 * connector->dev pointer might not be initialised yet. 205 */ 206 if (drm && !drm_dev_enter(drm, &idx)) 207 return; 208 209 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 210 211 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST); 212 udelay(1); 213 HDMI_WRITE(HDMI_M_CTL, 0); 214 215 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE); 216 217 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 218 VC4_HDMI_SW_RESET_HDMI | 219 VC4_HDMI_SW_RESET_FORMAT_DETECT); 220 221 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0); 222 223 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 224 225 if (drm) 226 drm_dev_exit(idx); 227 } 228 229 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi) 230 { 231 struct drm_device *drm = vc4_hdmi->connector.dev; 232 unsigned long flags; 233 int idx; 234 235 /* 236 * We can be called by our bind callback, when the 237 * connector->dev pointer might not be initialised yet. 238 */ 239 if (drm && !drm_dev_enter(drm, &idx)) 240 return; 241 242 reset_control_reset(vc4_hdmi->reset); 243 244 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 245 246 HDMI_WRITE(HDMI_DVP_CTL, 0); 247 248 HDMI_WRITE(HDMI_CLOCK_STOP, 249 HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL); 250 251 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 252 253 if (drm) 254 drm_dev_exit(idx); 255 } 256 257 #ifdef CONFIG_DRM_VC4_HDMI_CEC 258 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) 259 { 260 struct drm_device *drm = vc4_hdmi->connector.dev; 261 unsigned long cec_rate; 262 unsigned long flags; 263 u16 clk_cnt; 264 u32 value; 265 int idx; 266 267 /* 268 * This function is called by our runtime_resume implementation 269 * and thus at bind time, when we haven't registered our 270 * connector yet and thus don't have a pointer to the DRM 271 * device. 272 */ 273 if (drm && !drm_dev_enter(drm, &idx)) 274 return; 275 276 cec_rate = clk_get_rate(vc4_hdmi->cec_clock); 277 278 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 279 280 value = HDMI_READ(HDMI_CEC_CNTRL_1); 281 value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK; 282 283 /* 284 * Set the clock divider: the hsm_clock rate and this divider 285 * setting will give a 40 kHz CEC clock. 286 */ 287 clk_cnt = cec_rate / CEC_CLOCK_FREQ; 288 value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT; 289 HDMI_WRITE(HDMI_CEC_CNTRL_1, value); 290 291 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 292 293 if (drm) 294 drm_dev_exit(idx); 295 } 296 #else 297 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {} 298 #endif 299 300 static int reset_pipe(struct drm_crtc *crtc, 301 struct drm_modeset_acquire_ctx *ctx) 302 { 303 struct drm_atomic_state *state; 304 struct drm_crtc_state *crtc_state; 305 int ret; 306 307 state = drm_atomic_state_alloc(crtc->dev); 308 if (!state) 309 return -ENOMEM; 310 311 state->acquire_ctx = ctx; 312 313 crtc_state = drm_atomic_get_crtc_state(state, crtc); 314 if (IS_ERR(crtc_state)) { 315 ret = PTR_ERR(crtc_state); 316 goto out; 317 } 318 319 crtc_state->connectors_changed = true; 320 321 ret = drm_atomic_commit(state); 322 out: 323 drm_atomic_state_put(state); 324 325 return ret; 326 } 327 328 static int vc4_hdmi_reset_link(struct drm_connector *connector, 329 struct drm_modeset_acquire_ctx *ctx) 330 { 331 struct drm_device *drm; 332 struct vc4_hdmi *vc4_hdmi; 333 struct drm_connector_state *conn_state; 334 struct drm_crtc_state *crtc_state; 335 struct drm_crtc *crtc; 336 bool scrambling_needed; 337 u8 config; 338 int ret; 339 340 if (!connector) 341 return 0; 342 343 drm = connector->dev; 344 ret = drm_modeset_lock(&drm->mode_config.connection_mutex, ctx); 345 if (ret) 346 return ret; 347 348 conn_state = connector->state; 349 crtc = conn_state->crtc; 350 if (!crtc) 351 return 0; 352 353 ret = drm_modeset_lock(&crtc->mutex, ctx); 354 if (ret) 355 return ret; 356 357 crtc_state = crtc->state; 358 if (!crtc_state->active) 359 return 0; 360 361 vc4_hdmi = connector_to_vc4_hdmi(connector); 362 mutex_lock(&vc4_hdmi->mutex); 363 364 if (!vc4_hdmi_supports_scrambling(vc4_hdmi)) { 365 mutex_unlock(&vc4_hdmi->mutex); 366 return 0; 367 } 368 369 scrambling_needed = vc4_hdmi_mode_needs_scrambling(&vc4_hdmi->saved_adjusted_mode, 370 vc4_hdmi->output_bpc, 371 vc4_hdmi->output_format); 372 if (!scrambling_needed) { 373 mutex_unlock(&vc4_hdmi->mutex); 374 return 0; 375 } 376 377 if (conn_state->commit && 378 !try_wait_for_completion(&conn_state->commit->hw_done)) { 379 mutex_unlock(&vc4_hdmi->mutex); 380 return 0; 381 } 382 383 ret = drm_scdc_readb(connector->ddc, SCDC_TMDS_CONFIG, &config); 384 if (ret < 0) { 385 drm_err(drm, "Failed to read TMDS config: %d\n", ret); 386 mutex_unlock(&vc4_hdmi->mutex); 387 return 0; 388 } 389 390 if (!!(config & SCDC_SCRAMBLING_ENABLE) == scrambling_needed) { 391 mutex_unlock(&vc4_hdmi->mutex); 392 return 0; 393 } 394 395 mutex_unlock(&vc4_hdmi->mutex); 396 397 /* 398 * HDMI 2.0 says that one should not send scrambled data 399 * prior to configuring the sink scrambling, and that 400 * TMDS clock/data transmission should be suspended when 401 * changing the TMDS clock rate in the sink. So let's 402 * just do a full modeset here, even though some sinks 403 * would be perfectly happy if were to just reconfigure 404 * the SCDC settings on the fly. 405 */ 406 return reset_pipe(crtc, ctx); 407 } 408 409 static void vc4_hdmi_handle_hotplug(struct vc4_hdmi *vc4_hdmi, 410 struct drm_modeset_acquire_ctx *ctx, 411 enum drm_connector_status status) 412 { 413 struct drm_connector *connector = &vc4_hdmi->connector; 414 struct edid *edid; 415 int ret; 416 417 /* 418 * NOTE: This function should really be called with 419 * vc4_hdmi->mutex held, but doing so results in reentrancy 420 * issues since cec_s_phys_addr_from_edid might call 421 * .adap_enable, which leads to that funtion being called with 422 * our mutex held. 423 * 424 * A similar situation occurs with vc4_hdmi_reset_link() that 425 * will call into our KMS hooks if the scrambling was enabled. 426 * 427 * Concurrency isn't an issue at the moment since we don't share 428 * any state with any of the other frameworks so we can ignore 429 * the lock for now. 430 */ 431 432 if (status == connector_status_disconnected) { 433 cec_phys_addr_invalidate(vc4_hdmi->cec_adap); 434 return; 435 } 436 437 edid = drm_get_edid(connector, vc4_hdmi->ddc); 438 if (!edid) 439 return; 440 441 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid); 442 kfree(edid); 443 444 for (;;) { 445 ret = vc4_hdmi_reset_link(connector, ctx); 446 if (ret == -EDEADLK) { 447 drm_modeset_backoff(ctx); 448 continue; 449 } 450 451 break; 452 } 453 } 454 455 static int vc4_hdmi_connector_detect_ctx(struct drm_connector *connector, 456 struct drm_modeset_acquire_ctx *ctx, 457 bool force) 458 { 459 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 460 enum drm_connector_status status = connector_status_disconnected; 461 462 /* 463 * NOTE: This function should really take vc4_hdmi->mutex, but 464 * doing so results in reentrancy issues since 465 * vc4_hdmi_handle_hotplug() can call into other functions that 466 * would take the mutex while it's held here. 467 * 468 * Concurrency isn't an issue at the moment since we don't share 469 * any state with any of the other frameworks so we can ignore 470 * the lock for now. 471 */ 472 473 WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev)); 474 475 if (vc4_hdmi->hpd_gpio) { 476 if (gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio)) 477 status = connector_status_connected; 478 } else { 479 if (vc4_hdmi->variant->hp_detect && 480 vc4_hdmi->variant->hp_detect(vc4_hdmi)) 481 status = connector_status_connected; 482 } 483 484 vc4_hdmi_handle_hotplug(vc4_hdmi, ctx, status); 485 pm_runtime_put(&vc4_hdmi->pdev->dev); 486 487 return status; 488 } 489 490 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector) 491 { 492 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 493 struct vc4_dev *vc4 = to_vc4_dev(connector->dev); 494 int ret = 0; 495 struct edid *edid; 496 497 /* 498 * NOTE: This function should really take vc4_hdmi->mutex, but 499 * doing so results in reentrancy issues since 500 * cec_s_phys_addr_from_edid might call .adap_enable, which 501 * leads to that funtion being called with our mutex held. 502 * 503 * Concurrency isn't an issue at the moment since we don't share 504 * any state with any of the other frameworks so we can ignore 505 * the lock for now. 506 */ 507 508 edid = drm_get_edid(connector, vc4_hdmi->ddc); 509 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid); 510 if (!edid) 511 return -ENODEV; 512 513 drm_connector_update_edid_property(connector, edid); 514 ret = drm_add_edid_modes(connector, edid); 515 kfree(edid); 516 517 if (!vc4->hvs->vc5_hdmi_enable_hdmi_20) { 518 struct drm_device *drm = connector->dev; 519 const struct drm_display_mode *mode; 520 521 list_for_each_entry(mode, &connector->probed_modes, head) { 522 if (vc4_hdmi_mode_needs_scrambling(mode, 8, VC4_HDMI_OUTPUT_RGB)) { 523 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz."); 524 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60."); 525 } 526 } 527 } 528 529 return ret; 530 } 531 532 static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector, 533 struct drm_atomic_state *state) 534 { 535 struct drm_connector_state *old_state = 536 drm_atomic_get_old_connector_state(state, connector); 537 struct vc4_hdmi_connector_state *old_vc4_state = 538 conn_state_to_vc4_hdmi_conn_state(old_state); 539 struct drm_connector_state *new_state = 540 drm_atomic_get_new_connector_state(state, connector); 541 struct vc4_hdmi_connector_state *new_vc4_state = 542 conn_state_to_vc4_hdmi_conn_state(new_state); 543 struct drm_crtc *crtc = new_state->crtc; 544 545 if (!crtc) 546 return 0; 547 548 if (old_state->tv.margins.left != new_state->tv.margins.left || 549 old_state->tv.margins.right != new_state->tv.margins.right || 550 old_state->tv.margins.top != new_state->tv.margins.top || 551 old_state->tv.margins.bottom != new_state->tv.margins.bottom) { 552 struct drm_crtc_state *crtc_state; 553 int ret; 554 555 crtc_state = drm_atomic_get_crtc_state(state, crtc); 556 if (IS_ERR(crtc_state)) 557 return PTR_ERR(crtc_state); 558 559 /* 560 * Strictly speaking, we should be calling 561 * drm_atomic_helper_check_planes() after our call to 562 * drm_atomic_add_affected_planes(). However, the 563 * connector atomic_check is called as part of 564 * drm_atomic_helper_check_modeset() that already 565 * happens before a call to 566 * drm_atomic_helper_check_planes() in 567 * drm_atomic_helper_check(). 568 */ 569 ret = drm_atomic_add_affected_planes(state, crtc); 570 if (ret) 571 return ret; 572 } 573 574 if (old_state->colorspace != new_state->colorspace || 575 old_vc4_state->broadcast_rgb != new_vc4_state->broadcast_rgb || 576 !drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) { 577 struct drm_crtc_state *crtc_state; 578 579 crtc_state = drm_atomic_get_crtc_state(state, crtc); 580 if (IS_ERR(crtc_state)) 581 return PTR_ERR(crtc_state); 582 583 crtc_state->mode_changed = true; 584 } 585 586 return 0; 587 } 588 589 static int vc4_hdmi_connector_get_property(struct drm_connector *connector, 590 const struct drm_connector_state *state, 591 struct drm_property *property, 592 uint64_t *val) 593 { 594 struct drm_device *drm = connector->dev; 595 struct vc4_hdmi *vc4_hdmi = 596 connector_to_vc4_hdmi(connector); 597 const struct vc4_hdmi_connector_state *vc4_conn_state = 598 conn_state_to_vc4_hdmi_conn_state(state); 599 600 if (property == vc4_hdmi->broadcast_rgb_property) { 601 *val = vc4_conn_state->broadcast_rgb; 602 } else { 603 drm_dbg(drm, "Unknown property [PROP:%d:%s]\n", 604 property->base.id, property->name); 605 return -EINVAL; 606 } 607 608 return 0; 609 } 610 611 static int vc4_hdmi_connector_set_property(struct drm_connector *connector, 612 struct drm_connector_state *state, 613 struct drm_property *property, 614 uint64_t val) 615 { 616 struct drm_device *drm = connector->dev; 617 struct vc4_hdmi *vc4_hdmi = 618 connector_to_vc4_hdmi(connector); 619 struct vc4_hdmi_connector_state *vc4_conn_state = 620 conn_state_to_vc4_hdmi_conn_state(state); 621 622 if (property == vc4_hdmi->broadcast_rgb_property) { 623 vc4_conn_state->broadcast_rgb = val; 624 return 0; 625 } 626 627 drm_dbg(drm, "Unknown property [PROP:%d:%s]\n", 628 property->base.id, property->name); 629 return -EINVAL; 630 } 631 632 static void vc4_hdmi_connector_reset(struct drm_connector *connector) 633 { 634 struct vc4_hdmi_connector_state *old_state = 635 conn_state_to_vc4_hdmi_conn_state(connector->state); 636 struct vc4_hdmi_connector_state *new_state = 637 kzalloc(sizeof(*new_state), GFP_KERNEL); 638 639 if (connector->state) 640 __drm_atomic_helper_connector_destroy_state(connector->state); 641 642 kfree(old_state); 643 __drm_atomic_helper_connector_reset(connector, &new_state->base); 644 645 if (!new_state) 646 return; 647 648 new_state->base.max_bpc = 8; 649 new_state->base.max_requested_bpc = 8; 650 new_state->output_format = VC4_HDMI_OUTPUT_RGB; 651 new_state->broadcast_rgb = VC4_HDMI_BROADCAST_RGB_AUTO; 652 drm_atomic_helper_connector_tv_margins_reset(connector); 653 } 654 655 static struct drm_connector_state * 656 vc4_hdmi_connector_duplicate_state(struct drm_connector *connector) 657 { 658 struct drm_connector_state *conn_state = connector->state; 659 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state); 660 struct vc4_hdmi_connector_state *new_state; 661 662 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL); 663 if (!new_state) 664 return NULL; 665 666 new_state->tmds_char_rate = vc4_state->tmds_char_rate; 667 new_state->output_bpc = vc4_state->output_bpc; 668 new_state->output_format = vc4_state->output_format; 669 new_state->broadcast_rgb = vc4_state->broadcast_rgb; 670 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base); 671 672 return &new_state->base; 673 } 674 675 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = { 676 .fill_modes = drm_helper_probe_single_connector_modes, 677 .reset = vc4_hdmi_connector_reset, 678 .atomic_duplicate_state = vc4_hdmi_connector_duplicate_state, 679 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 680 .atomic_get_property = vc4_hdmi_connector_get_property, 681 .atomic_set_property = vc4_hdmi_connector_set_property, 682 }; 683 684 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = { 685 .detect_ctx = vc4_hdmi_connector_detect_ctx, 686 .get_modes = vc4_hdmi_connector_get_modes, 687 .atomic_check = vc4_hdmi_connector_atomic_check, 688 }; 689 690 static const struct drm_prop_enum_list broadcast_rgb_names[] = { 691 { VC4_HDMI_BROADCAST_RGB_AUTO, "Automatic" }, 692 { VC4_HDMI_BROADCAST_RGB_FULL, "Full" }, 693 { VC4_HDMI_BROADCAST_RGB_LIMITED, "Limited 16:235" }, 694 }; 695 696 static void 697 vc4_hdmi_attach_broadcast_rgb_property(struct drm_device *dev, 698 struct vc4_hdmi *vc4_hdmi) 699 { 700 struct drm_property *prop = vc4_hdmi->broadcast_rgb_property; 701 702 if (!prop) { 703 prop = drm_property_create_enum(dev, DRM_MODE_PROP_ENUM, 704 "Broadcast RGB", 705 broadcast_rgb_names, 706 ARRAY_SIZE(broadcast_rgb_names)); 707 if (!prop) 708 return; 709 710 vc4_hdmi->broadcast_rgb_property = prop; 711 } 712 713 drm_object_attach_property(&vc4_hdmi->connector.base, prop, 714 VC4_HDMI_BROADCAST_RGB_AUTO); 715 } 716 717 static int vc4_hdmi_connector_init(struct drm_device *dev, 718 struct vc4_hdmi *vc4_hdmi) 719 { 720 struct drm_connector *connector = &vc4_hdmi->connector; 721 struct drm_encoder *encoder = &vc4_hdmi->encoder.base; 722 int ret; 723 724 ret = drmm_connector_init(dev, connector, 725 &vc4_hdmi_connector_funcs, 726 DRM_MODE_CONNECTOR_HDMIA, 727 vc4_hdmi->ddc); 728 if (ret) 729 return ret; 730 731 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs); 732 733 /* 734 * Some of the properties below require access to state, like bpc. 735 * Allocate some default initial connector state with our reset helper. 736 */ 737 if (connector->funcs->reset) 738 connector->funcs->reset(connector); 739 740 /* Create and attach TV margin props to this connector. */ 741 ret = drm_mode_create_tv_margin_properties(dev); 742 if (ret) 743 return ret; 744 745 ret = drm_mode_create_hdmi_colorspace_property(connector, 0); 746 if (ret) 747 return ret; 748 749 drm_connector_attach_colorspace_property(connector); 750 drm_connector_attach_tv_margin_properties(connector); 751 drm_connector_attach_max_bpc_property(connector, 8, 12); 752 753 connector->polled = (DRM_CONNECTOR_POLL_CONNECT | 754 DRM_CONNECTOR_POLL_DISCONNECT); 755 756 connector->interlace_allowed = 1; 757 connector->doublescan_allowed = 0; 758 connector->stereo_allowed = 1; 759 760 if (vc4_hdmi->variant->supports_hdr) 761 drm_connector_attach_hdr_output_metadata_property(connector); 762 763 vc4_hdmi_attach_broadcast_rgb_property(dev, vc4_hdmi); 764 765 drm_connector_attach_encoder(connector, encoder); 766 767 return 0; 768 } 769 770 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder, 771 enum hdmi_infoframe_type type, 772 bool poll) 773 { 774 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 775 struct drm_device *drm = vc4_hdmi->connector.dev; 776 u32 packet_id = type - 0x80; 777 unsigned long flags; 778 int ret = 0; 779 int idx; 780 781 if (!drm_dev_enter(drm, &idx)) 782 return -ENODEV; 783 784 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 785 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 786 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id)); 787 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 788 789 if (poll) { 790 ret = wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) & 791 BIT(packet_id)), 100); 792 } 793 794 drm_dev_exit(idx); 795 return ret; 796 } 797 798 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder, 799 union hdmi_infoframe *frame) 800 { 801 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 802 struct drm_device *drm = vc4_hdmi->connector.dev; 803 u32 packet_id = frame->any.type - 0x80; 804 const struct vc4_hdmi_register *ram_packet_start = 805 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START]; 806 u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id; 807 u32 packet_reg_next = ram_packet_start->offset + 808 VC4_HDMI_PACKET_STRIDE * (packet_id + 1); 809 void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi, 810 ram_packet_start->reg); 811 uint8_t buffer[VC4_HDMI_PACKET_STRIDE] = {}; 812 unsigned long flags; 813 ssize_t len, i; 814 int ret; 815 int idx; 816 817 if (!drm_dev_enter(drm, &idx)) 818 return; 819 820 WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) & 821 VC4_HDMI_RAM_PACKET_ENABLE), 822 "Packet RAM has to be on to store the packet."); 823 824 len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer)); 825 if (len < 0) 826 goto out; 827 828 ret = vc4_hdmi_stop_packet(encoder, frame->any.type, true); 829 if (ret) { 830 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret); 831 goto out; 832 } 833 834 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 835 836 for (i = 0; i < len; i += 7) { 837 writel(buffer[i + 0] << 0 | 838 buffer[i + 1] << 8 | 839 buffer[i + 2] << 16, 840 base + packet_reg); 841 packet_reg += 4; 842 843 writel(buffer[i + 3] << 0 | 844 buffer[i + 4] << 8 | 845 buffer[i + 5] << 16 | 846 buffer[i + 6] << 24, 847 base + packet_reg); 848 packet_reg += 4; 849 } 850 851 /* 852 * clear remainder of packet ram as it's included in the 853 * infoframe and triggers a checksum error on hdmi analyser 854 */ 855 for (; packet_reg < packet_reg_next; packet_reg += 4) 856 writel(0, base + packet_reg); 857 858 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 859 HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id)); 860 861 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 862 863 ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) & 864 BIT(packet_id)), 100); 865 if (ret) 866 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret); 867 868 out: 869 drm_dev_exit(idx); 870 } 871 872 static void vc4_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame, 873 enum vc4_hdmi_output_format fmt) 874 { 875 switch (fmt) { 876 case VC4_HDMI_OUTPUT_RGB: 877 frame->colorspace = HDMI_COLORSPACE_RGB; 878 break; 879 880 case VC4_HDMI_OUTPUT_YUV420: 881 frame->colorspace = HDMI_COLORSPACE_YUV420; 882 break; 883 884 case VC4_HDMI_OUTPUT_YUV422: 885 frame->colorspace = HDMI_COLORSPACE_YUV422; 886 break; 887 888 case VC4_HDMI_OUTPUT_YUV444: 889 frame->colorspace = HDMI_COLORSPACE_YUV444; 890 break; 891 892 default: 893 break; 894 } 895 } 896 897 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder) 898 { 899 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 900 struct drm_connector *connector = &vc4_hdmi->connector; 901 struct drm_connector_state *cstate = connector->state; 902 struct vc4_hdmi_connector_state *vc4_state = 903 conn_state_to_vc4_hdmi_conn_state(cstate); 904 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 905 union hdmi_infoframe frame; 906 int ret; 907 908 lockdep_assert_held(&vc4_hdmi->mutex); 909 910 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, 911 connector, mode); 912 if (ret < 0) { 913 DRM_ERROR("couldn't fill AVI infoframe\n"); 914 return; 915 } 916 917 drm_hdmi_avi_infoframe_quant_range(&frame.avi, 918 connector, mode, 919 vc4_hdmi_is_full_range(vc4_hdmi, vc4_state) ? 920 HDMI_QUANTIZATION_RANGE_FULL : 921 HDMI_QUANTIZATION_RANGE_LIMITED); 922 drm_hdmi_avi_infoframe_colorimetry(&frame.avi, cstate); 923 vc4_hdmi_avi_infoframe_colorspace(&frame.avi, vc4_state->output_format); 924 drm_hdmi_avi_infoframe_bars(&frame.avi, cstate); 925 926 vc4_hdmi_write_infoframe(encoder, &frame); 927 } 928 929 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder) 930 { 931 union hdmi_infoframe frame; 932 int ret; 933 934 ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore"); 935 if (ret < 0) { 936 DRM_ERROR("couldn't fill SPD infoframe\n"); 937 return; 938 } 939 940 frame.spd.sdi = HDMI_SPD_SDI_PC; 941 942 vc4_hdmi_write_infoframe(encoder, &frame); 943 } 944 945 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder) 946 { 947 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 948 struct hdmi_audio_infoframe *audio = &vc4_hdmi->audio.infoframe; 949 union hdmi_infoframe frame; 950 951 memcpy(&frame.audio, audio, sizeof(*audio)); 952 953 if (vc4_hdmi->packet_ram_enabled) 954 vc4_hdmi_write_infoframe(encoder, &frame); 955 } 956 957 static void vc4_hdmi_set_hdr_infoframe(struct drm_encoder *encoder) 958 { 959 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 960 struct drm_connector *connector = &vc4_hdmi->connector; 961 struct drm_connector_state *conn_state = connector->state; 962 union hdmi_infoframe frame; 963 964 lockdep_assert_held(&vc4_hdmi->mutex); 965 966 if (!vc4_hdmi->variant->supports_hdr) 967 return; 968 969 if (!conn_state->hdr_output_metadata) 970 return; 971 972 if (drm_hdmi_infoframe_set_hdr_metadata(&frame.drm, conn_state)) 973 return; 974 975 vc4_hdmi_write_infoframe(encoder, &frame); 976 } 977 978 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder) 979 { 980 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 981 982 lockdep_assert_held(&vc4_hdmi->mutex); 983 984 vc4_hdmi_set_avi_infoframe(encoder); 985 vc4_hdmi_set_spd_infoframe(encoder); 986 /* 987 * If audio was streaming, then we need to reenabled the audio 988 * infoframe here during encoder_enable. 989 */ 990 if (vc4_hdmi->audio.streaming) 991 vc4_hdmi_set_audio_infoframe(encoder); 992 993 vc4_hdmi_set_hdr_infoframe(encoder); 994 } 995 996 #define SCRAMBLING_POLLING_DELAY_MS 1000 997 998 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder) 999 { 1000 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1001 struct drm_connector *connector = &vc4_hdmi->connector; 1002 struct drm_device *drm = connector->dev; 1003 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1004 unsigned long flags; 1005 int idx; 1006 1007 lockdep_assert_held(&vc4_hdmi->mutex); 1008 1009 if (!vc4_hdmi_supports_scrambling(vc4_hdmi)) 1010 return; 1011 1012 if (!vc4_hdmi_mode_needs_scrambling(mode, 1013 vc4_hdmi->output_bpc, 1014 vc4_hdmi->output_format)) 1015 return; 1016 1017 if (!drm_dev_enter(drm, &idx)) 1018 return; 1019 1020 drm_scdc_set_high_tmds_clock_ratio(connector, true); 1021 drm_scdc_set_scrambling(connector, true); 1022 1023 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1024 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) | 1025 VC5_HDMI_SCRAMBLER_CTL_ENABLE); 1026 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1027 1028 drm_dev_exit(idx); 1029 1030 vc4_hdmi->scdc_enabled = true; 1031 1032 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work, 1033 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS)); 1034 } 1035 1036 static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder) 1037 { 1038 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1039 struct drm_connector *connector = &vc4_hdmi->connector; 1040 struct drm_device *drm = connector->dev; 1041 unsigned long flags; 1042 int idx; 1043 1044 lockdep_assert_held(&vc4_hdmi->mutex); 1045 1046 if (!vc4_hdmi->scdc_enabled) 1047 return; 1048 1049 vc4_hdmi->scdc_enabled = false; 1050 1051 if (delayed_work_pending(&vc4_hdmi->scrambling_work)) 1052 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work); 1053 1054 if (!drm_dev_enter(drm, &idx)) 1055 return; 1056 1057 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1058 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) & 1059 ~VC5_HDMI_SCRAMBLER_CTL_ENABLE); 1060 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1061 1062 drm_scdc_set_scrambling(connector, false); 1063 drm_scdc_set_high_tmds_clock_ratio(connector, false); 1064 1065 drm_dev_exit(idx); 1066 } 1067 1068 static void vc4_hdmi_scrambling_wq(struct work_struct *work) 1069 { 1070 struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work), 1071 struct vc4_hdmi, 1072 scrambling_work); 1073 struct drm_connector *connector = &vc4_hdmi->connector; 1074 1075 if (drm_scdc_get_scrambling_status(connector)) 1076 return; 1077 1078 drm_scdc_set_high_tmds_clock_ratio(connector, true); 1079 drm_scdc_set_scrambling(connector, true); 1080 1081 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work, 1082 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS)); 1083 } 1084 1085 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder, 1086 struct drm_atomic_state *state) 1087 { 1088 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1089 struct drm_device *drm = vc4_hdmi->connector.dev; 1090 unsigned long flags; 1091 int idx; 1092 1093 mutex_lock(&vc4_hdmi->mutex); 1094 1095 vc4_hdmi->packet_ram_enabled = false; 1096 1097 if (!drm_dev_enter(drm, &idx)) 1098 goto out; 1099 1100 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1101 1102 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0); 1103 1104 HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB); 1105 1106 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1107 1108 mdelay(1); 1109 1110 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1111 HDMI_WRITE(HDMI_VID_CTL, 1112 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE); 1113 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1114 1115 vc4_hdmi_disable_scrambling(encoder); 1116 1117 drm_dev_exit(idx); 1118 1119 out: 1120 mutex_unlock(&vc4_hdmi->mutex); 1121 } 1122 1123 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder, 1124 struct drm_atomic_state *state) 1125 { 1126 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1127 struct drm_device *drm = vc4_hdmi->connector.dev; 1128 unsigned long flags; 1129 int ret; 1130 int idx; 1131 1132 mutex_lock(&vc4_hdmi->mutex); 1133 1134 if (!drm_dev_enter(drm, &idx)) 1135 goto out; 1136 1137 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1138 HDMI_WRITE(HDMI_VID_CTL, 1139 HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX); 1140 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1141 1142 if (vc4_hdmi->variant->phy_disable) 1143 vc4_hdmi->variant->phy_disable(vc4_hdmi); 1144 1145 clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock); 1146 clk_disable_unprepare(vc4_hdmi->pixel_clock); 1147 1148 ret = pm_runtime_put(&vc4_hdmi->pdev->dev); 1149 if (ret < 0) 1150 DRM_ERROR("Failed to release power domain: %d\n", ret); 1151 1152 drm_dev_exit(idx); 1153 1154 out: 1155 mutex_unlock(&vc4_hdmi->mutex); 1156 } 1157 1158 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, 1159 struct drm_connector_state *state, 1160 const struct drm_display_mode *mode) 1161 { 1162 struct vc4_hdmi_connector_state *vc4_state = 1163 conn_state_to_vc4_hdmi_conn_state(state); 1164 struct drm_device *drm = vc4_hdmi->connector.dev; 1165 unsigned long flags; 1166 u32 csc_ctl; 1167 int idx; 1168 1169 if (!drm_dev_enter(drm, &idx)) 1170 return; 1171 1172 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1173 1174 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR, 1175 VC4_HD_CSC_CTL_ORDER); 1176 1177 if (!vc4_hdmi_is_full_range(vc4_hdmi, vc4_state)) { 1178 /* CEA VICs other than #1 requre limited range RGB 1179 * output unless overridden by an AVI infoframe. 1180 * Apply a colorspace conversion to squash 0-255 down 1181 * to 16-235. The matrix here is: 1182 * 1183 * [ 0 0 0.8594 16] 1184 * [ 0 0.8594 0 16] 1185 * [ 0.8594 0 0 16] 1186 * [ 0 0 0 1] 1187 */ 1188 csc_ctl |= VC4_HD_CSC_CTL_ENABLE; 1189 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC; 1190 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM, 1191 VC4_HD_CSC_CTL_MODE); 1192 1193 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000); 1194 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0); 1195 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000); 1196 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000); 1197 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0); 1198 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000); 1199 } 1200 1201 /* The RGB order applies even when CSC is disabled. */ 1202 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl); 1203 1204 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1205 1206 drm_dev_exit(idx); 1207 } 1208 1209 /* 1210 * Matrices for (internal) RGB to RGB output. 1211 * 1212 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets 1213 */ 1214 static const u16 vc5_hdmi_csc_full_rgb_to_rgb[2][3][4] = { 1215 { 1216 /* 1217 * Full range - unity 1218 * 1219 * [ 1 0 0 0] 1220 * [ 0 1 0 0] 1221 * [ 0 0 1 0] 1222 */ 1223 { 0x2000, 0x0000, 0x0000, 0x0000 }, 1224 { 0x0000, 0x2000, 0x0000, 0x0000 }, 1225 { 0x0000, 0x0000, 0x2000, 0x0000 }, 1226 }, 1227 { 1228 /* 1229 * Limited range 1230 * 1231 * CEA VICs other than #1 require limited range RGB 1232 * output unless overridden by an AVI infoframe. Apply a 1233 * colorspace conversion to squash 0-255 down to 16-235. 1234 * The matrix here is: 1235 * 1236 * [ 0.8594 0 0 16] 1237 * [ 0 0.8594 0 16] 1238 * [ 0 0 0.8594 16] 1239 */ 1240 { 0x1b80, 0x0000, 0x0000, 0x0400 }, 1241 { 0x0000, 0x1b80, 0x0000, 0x0400 }, 1242 { 0x0000, 0x0000, 0x1b80, 0x0400 }, 1243 }, 1244 }; 1245 1246 /* 1247 * Conversion between Full Range RGB and YUV using the BT.601 Colorspace 1248 * 1249 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets 1250 */ 1251 static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt601[2][3][4] = { 1252 { 1253 /* 1254 * Full Range 1255 * 1256 * [ 0.299000 0.587000 0.114000 0 ] 1257 * [ -0.168736 -0.331264 0.500000 128 ] 1258 * [ 0.500000 -0.418688 -0.081312 128 ] 1259 */ 1260 { 0x0991, 0x12c9, 0x03a6, 0x0000 }, 1261 { 0xfa9b, 0xf567, 0x1000, 0x2000 }, 1262 { 0x1000, 0xf29b, 0xfd67, 0x2000 }, 1263 }, 1264 { 1265 /* Limited Range 1266 * 1267 * [ 0.255785 0.502160 0.097523 16 ] 1268 * [ -0.147644 -0.289856 0.437500 128 ] 1269 * [ 0.437500 -0.366352 -0.071148 128 ] 1270 */ 1271 { 0x082f, 0x1012, 0x031f, 0x0400 }, 1272 { 0xfb48, 0xf6ba, 0x0e00, 0x2000 }, 1273 { 0x0e00, 0xf448, 0xfdba, 0x2000 }, 1274 }, 1275 }; 1276 1277 /* 1278 * Conversion between Full Range RGB and YUV using the BT.709 Colorspace 1279 * 1280 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets 1281 */ 1282 static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt709[2][3][4] = { 1283 { 1284 /* 1285 * Full Range 1286 * 1287 * [ 0.212600 0.715200 0.072200 0 ] 1288 * [ -0.114572 -0.385428 0.500000 128 ] 1289 * [ 0.500000 -0.454153 -0.045847 128 ] 1290 */ 1291 { 0x06ce, 0x16e3, 0x024f, 0x0000 }, 1292 { 0xfc56, 0xf3ac, 0x1000, 0x2000 }, 1293 { 0x1000, 0xf179, 0xfe89, 0x2000 }, 1294 }, 1295 { 1296 /* 1297 * Limited Range 1298 * 1299 * [ 0.181906 0.611804 0.061758 16 ] 1300 * [ -0.100268 -0.337232 0.437500 128 ] 1301 * [ 0.437500 -0.397386 -0.040114 128 ] 1302 */ 1303 { 0x05d2, 0x1394, 0x01fa, 0x0400 }, 1304 { 0xfccc, 0xf536, 0x0e00, 0x2000 }, 1305 { 0x0e00, 0xf34a, 0xfeb8, 0x2000 }, 1306 }, 1307 }; 1308 1309 /* 1310 * Conversion between Full Range RGB and YUV using the BT.2020 Colorspace 1311 * 1312 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets 1313 */ 1314 static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt2020[2][3][4] = { 1315 { 1316 /* 1317 * Full Range 1318 * 1319 * [ 0.262700 0.678000 0.059300 0 ] 1320 * [ -0.139630 -0.360370 0.500000 128 ] 1321 * [ 0.500000 -0.459786 -0.040214 128 ] 1322 */ 1323 { 0x0868, 0x15b2, 0x01e6, 0x0000 }, 1324 { 0xfb89, 0xf479, 0x1000, 0x2000 }, 1325 { 0x1000, 0xf14a, 0xfeb8, 0x2000 }, 1326 }, 1327 { 1328 /* Limited Range 1329 * 1330 * [ 0.224732 0.580008 0.050729 16 ] 1331 * [ -0.122176 -0.315324 0.437500 128 ] 1332 * [ 0.437500 -0.402312 -0.035188 128 ] 1333 */ 1334 { 0x082f, 0x1012, 0x031f, 0x0400 }, 1335 { 0xfb48, 0xf6ba, 0x0e00, 0x2000 }, 1336 { 0x0e00, 0xf448, 0xfdba, 0x2000 }, 1337 }, 1338 }; 1339 1340 static void vc5_hdmi_set_csc_coeffs(struct vc4_hdmi *vc4_hdmi, 1341 const u16 coeffs[3][4]) 1342 { 1343 lockdep_assert_held(&vc4_hdmi->hw_lock); 1344 1345 HDMI_WRITE(HDMI_CSC_12_11, (coeffs[0][1] << 16) | coeffs[0][0]); 1346 HDMI_WRITE(HDMI_CSC_14_13, (coeffs[0][3] << 16) | coeffs[0][2]); 1347 HDMI_WRITE(HDMI_CSC_22_21, (coeffs[1][1] << 16) | coeffs[1][0]); 1348 HDMI_WRITE(HDMI_CSC_24_23, (coeffs[1][3] << 16) | coeffs[1][2]); 1349 HDMI_WRITE(HDMI_CSC_32_31, (coeffs[2][1] << 16) | coeffs[2][0]); 1350 HDMI_WRITE(HDMI_CSC_34_33, (coeffs[2][3] << 16) | coeffs[2][2]); 1351 } 1352 1353 static void vc5_hdmi_set_csc_coeffs_swap(struct vc4_hdmi *vc4_hdmi, 1354 const u16 coeffs[3][4]) 1355 { 1356 lockdep_assert_held(&vc4_hdmi->hw_lock); 1357 1358 /* YUV444 needs the CSC matrices using the channels in a different order */ 1359 HDMI_WRITE(HDMI_CSC_12_11, (coeffs[1][1] << 16) | coeffs[1][0]); 1360 HDMI_WRITE(HDMI_CSC_14_13, (coeffs[1][3] << 16) | coeffs[1][2]); 1361 HDMI_WRITE(HDMI_CSC_22_21, (coeffs[2][1] << 16) | coeffs[2][0]); 1362 HDMI_WRITE(HDMI_CSC_24_23, (coeffs[2][3] << 16) | coeffs[2][2]); 1363 HDMI_WRITE(HDMI_CSC_32_31, (coeffs[0][1] << 16) | coeffs[0][0]); 1364 HDMI_WRITE(HDMI_CSC_34_33, (coeffs[0][3] << 16) | coeffs[0][2]); 1365 } 1366 1367 static const u16 1368 (*vc5_hdmi_find_yuv_csc_coeffs(struct vc4_hdmi *vc4_hdmi, u32 colorspace, bool limited))[4] 1369 { 1370 switch (colorspace) { 1371 case DRM_MODE_COLORIMETRY_SMPTE_170M_YCC: 1372 case DRM_MODE_COLORIMETRY_XVYCC_601: 1373 case DRM_MODE_COLORIMETRY_SYCC_601: 1374 case DRM_MODE_COLORIMETRY_OPYCC_601: 1375 case DRM_MODE_COLORIMETRY_BT601_YCC: 1376 return vc5_hdmi_csc_full_rgb_to_yuv_bt601[limited]; 1377 1378 default: 1379 case DRM_MODE_COLORIMETRY_NO_DATA: 1380 case DRM_MODE_COLORIMETRY_BT709_YCC: 1381 case DRM_MODE_COLORIMETRY_XVYCC_709: 1382 case DRM_MODE_COLORIMETRY_RGB_WIDE_FIXED: 1383 case DRM_MODE_COLORIMETRY_RGB_WIDE_FLOAT: 1384 return vc5_hdmi_csc_full_rgb_to_yuv_bt709[limited]; 1385 1386 case DRM_MODE_COLORIMETRY_BT2020_CYCC: 1387 case DRM_MODE_COLORIMETRY_BT2020_YCC: 1388 case DRM_MODE_COLORIMETRY_BT2020_RGB: 1389 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65: 1390 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER: 1391 return vc5_hdmi_csc_full_rgb_to_yuv_bt2020[limited]; 1392 } 1393 } 1394 1395 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, 1396 struct drm_connector_state *state, 1397 const struct drm_display_mode *mode) 1398 { 1399 struct drm_device *drm = vc4_hdmi->connector.dev; 1400 struct vc4_hdmi_connector_state *vc4_state = 1401 conn_state_to_vc4_hdmi_conn_state(state); 1402 unsigned int lim_range = vc4_hdmi_is_full_range(vc4_hdmi, vc4_state) ? 0 : 1; 1403 unsigned long flags; 1404 const u16 (*csc)[4]; 1405 u32 if_cfg = 0; 1406 u32 if_xbar = 0x543210; 1407 u32 csc_chan_ctl = 0; 1408 u32 csc_ctl = VC5_MT_CP_CSC_CTL_ENABLE | VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM, 1409 VC5_MT_CP_CSC_CTL_MODE); 1410 int idx; 1411 1412 if (!drm_dev_enter(drm, &idx)) 1413 return; 1414 1415 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1416 1417 switch (vc4_state->output_format) { 1418 case VC4_HDMI_OUTPUT_YUV444: 1419 csc = vc5_hdmi_find_yuv_csc_coeffs(vc4_hdmi, state->colorspace, !!lim_range); 1420 1421 vc5_hdmi_set_csc_coeffs_swap(vc4_hdmi, csc); 1422 break; 1423 1424 case VC4_HDMI_OUTPUT_YUV422: 1425 csc = vc5_hdmi_find_yuv_csc_coeffs(vc4_hdmi, state->colorspace, !!lim_range); 1426 1427 csc_ctl |= VC4_SET_FIELD(VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422_STANDARD, 1428 VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422) | 1429 VC5_MT_CP_CSC_CTL_USE_444_TO_422 | 1430 VC5_MT_CP_CSC_CTL_USE_RNG_SUPPRESSION; 1431 1432 csc_chan_ctl |= VC4_SET_FIELD(VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP_LEGACY_STYLE, 1433 VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP); 1434 1435 if_cfg |= VC4_SET_FIELD(VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422_FORMAT_422_LEGACY, 1436 VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422); 1437 1438 vc5_hdmi_set_csc_coeffs(vc4_hdmi, csc); 1439 break; 1440 1441 case VC4_HDMI_OUTPUT_RGB: 1442 if_xbar = 0x354021; 1443 1444 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_rgb[lim_range]); 1445 break; 1446 1447 default: 1448 break; 1449 } 1450 1451 HDMI_WRITE(HDMI_VEC_INTERFACE_CFG, if_cfg); 1452 HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, if_xbar); 1453 HDMI_WRITE(HDMI_CSC_CHANNEL_CTL, csc_chan_ctl); 1454 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl); 1455 1456 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1457 1458 drm_dev_exit(idx); 1459 } 1460 1461 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi, 1462 struct drm_connector_state *state, 1463 const struct drm_display_mode *mode) 1464 { 1465 struct drm_device *drm = vc4_hdmi->connector.dev; 1466 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 1467 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 1468 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 1469 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 1470 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 1471 VC4_HDMI_VERTA_VSP) | 1472 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 1473 VC4_HDMI_VERTA_VFP) | 1474 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL)); 1475 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 1476 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end + 1477 interlaced, 1478 VC4_HDMI_VERTB_VBP)); 1479 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 1480 VC4_SET_FIELD(mode->crtc_vtotal - 1481 mode->crtc_vsync_end, 1482 VC4_HDMI_VERTB_VBP)); 1483 unsigned long flags; 1484 u32 reg; 1485 int idx; 1486 1487 if (!drm_dev_enter(drm, &idx)) 1488 return; 1489 1490 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1491 1492 HDMI_WRITE(HDMI_HORZA, 1493 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) | 1494 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) | 1495 VC4_SET_FIELD(mode->hdisplay * pixel_rep, 1496 VC4_HDMI_HORZA_HAP)); 1497 1498 HDMI_WRITE(HDMI_HORZB, 1499 VC4_SET_FIELD((mode->htotal - 1500 mode->hsync_end) * pixel_rep, 1501 VC4_HDMI_HORZB_HBP) | 1502 VC4_SET_FIELD((mode->hsync_end - 1503 mode->hsync_start) * pixel_rep, 1504 VC4_HDMI_HORZB_HSP) | 1505 VC4_SET_FIELD((mode->hsync_start - 1506 mode->hdisplay) * pixel_rep, 1507 VC4_HDMI_HORZB_HFP)); 1508 1509 HDMI_WRITE(HDMI_VERTA0, verta); 1510 HDMI_WRITE(HDMI_VERTA1, verta); 1511 1512 HDMI_WRITE(HDMI_VERTB0, vertb_even); 1513 HDMI_WRITE(HDMI_VERTB1, vertb); 1514 1515 reg = HDMI_READ(HDMI_MISC_CONTROL); 1516 reg &= ~VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK; 1517 reg |= VC4_SET_FIELD(pixel_rep - 1, VC4_HDMI_MISC_CONTROL_PIXEL_REP); 1518 HDMI_WRITE(HDMI_MISC_CONTROL, reg); 1519 1520 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1521 1522 drm_dev_exit(idx); 1523 } 1524 1525 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi, 1526 struct drm_connector_state *state, 1527 const struct drm_display_mode *mode) 1528 { 1529 struct drm_device *drm = vc4_hdmi->connector.dev; 1530 const struct vc4_hdmi_connector_state *vc4_state = 1531 conn_state_to_vc4_hdmi_conn_state(state); 1532 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 1533 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 1534 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 1535 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 1536 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 1537 VC5_HDMI_VERTA_VSP) | 1538 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 1539 VC5_HDMI_VERTA_VFP) | 1540 VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL)); 1541 u32 vertb = (VC4_SET_FIELD(mode->htotal >> (2 - pixel_rep), 1542 VC5_HDMI_VERTB_VSPO) | 1543 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end + 1544 interlaced, 1545 VC4_HDMI_VERTB_VBP)); 1546 u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) | 1547 VC4_SET_FIELD(mode->crtc_vtotal - 1548 mode->crtc_vsync_end, 1549 VC4_HDMI_VERTB_VBP)); 1550 unsigned long flags; 1551 unsigned char gcp; 1552 u32 reg; 1553 int idx; 1554 1555 if (!drm_dev_enter(drm, &idx)) 1556 return; 1557 1558 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1559 1560 HDMI_WRITE(HDMI_HORZA, 1561 (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) | 1562 (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) | 1563 VC4_SET_FIELD(mode->hdisplay * pixel_rep, 1564 VC5_HDMI_HORZA_HAP) | 1565 VC4_SET_FIELD((mode->hsync_start - 1566 mode->hdisplay) * pixel_rep, 1567 VC5_HDMI_HORZA_HFP)); 1568 1569 HDMI_WRITE(HDMI_HORZB, 1570 VC4_SET_FIELD((mode->htotal - 1571 mode->hsync_end) * pixel_rep, 1572 VC5_HDMI_HORZB_HBP) | 1573 VC4_SET_FIELD((mode->hsync_end - 1574 mode->hsync_start) * pixel_rep, 1575 VC5_HDMI_HORZB_HSP)); 1576 1577 HDMI_WRITE(HDMI_VERTA0, verta); 1578 HDMI_WRITE(HDMI_VERTA1, verta); 1579 1580 HDMI_WRITE(HDMI_VERTB0, vertb_even); 1581 HDMI_WRITE(HDMI_VERTB1, vertb); 1582 1583 switch (vc4_state->output_bpc) { 1584 case 12: 1585 gcp = 6; 1586 break; 1587 case 10: 1588 gcp = 5; 1589 break; 1590 case 8: 1591 default: 1592 gcp = 0; 1593 break; 1594 } 1595 1596 /* 1597 * YCC422 is always 36-bit and not considered deep colour so 1598 * doesn't signal in GCP. 1599 */ 1600 if (vc4_state->output_format == VC4_HDMI_OUTPUT_YUV422) { 1601 gcp = 0; 1602 } 1603 1604 reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1); 1605 reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK | 1606 VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK); 1607 reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) | 1608 VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH); 1609 HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg); 1610 1611 reg = HDMI_READ(HDMI_GCP_WORD_1); 1612 reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK; 1613 reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1); 1614 reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_MASK; 1615 reg |= VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_CLEAR_AVMUTE; 1616 HDMI_WRITE(HDMI_GCP_WORD_1, reg); 1617 1618 reg = HDMI_READ(HDMI_GCP_CONFIG); 1619 reg |= VC5_HDMI_GCP_CONFIG_GCP_ENABLE; 1620 HDMI_WRITE(HDMI_GCP_CONFIG, reg); 1621 1622 reg = HDMI_READ(HDMI_MISC_CONTROL); 1623 reg &= ~VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK; 1624 reg |= VC4_SET_FIELD(pixel_rep - 1, VC5_HDMI_MISC_CONTROL_PIXEL_REP); 1625 HDMI_WRITE(HDMI_MISC_CONTROL, reg); 1626 1627 HDMI_WRITE(HDMI_CLOCK_STOP, 0); 1628 1629 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1630 1631 drm_dev_exit(idx); 1632 } 1633 1634 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi) 1635 { 1636 struct drm_device *drm = vc4_hdmi->connector.dev; 1637 unsigned long flags; 1638 u32 drift; 1639 int ret; 1640 int idx; 1641 1642 if (!drm_dev_enter(drm, &idx)) 1643 return; 1644 1645 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1646 1647 drift = HDMI_READ(HDMI_FIFO_CTL); 1648 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK; 1649 1650 HDMI_WRITE(HDMI_FIFO_CTL, 1651 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 1652 HDMI_WRITE(HDMI_FIFO_CTL, 1653 drift | VC4_HDMI_FIFO_CTL_RECENTER); 1654 1655 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1656 1657 usleep_range(1000, 1100); 1658 1659 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1660 1661 HDMI_WRITE(HDMI_FIFO_CTL, 1662 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 1663 HDMI_WRITE(HDMI_FIFO_CTL, 1664 drift | VC4_HDMI_FIFO_CTL_RECENTER); 1665 1666 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1667 1668 ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) & 1669 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1); 1670 WARN_ONCE(ret, "Timeout waiting for " 1671 "VC4_HDMI_FIFO_CTL_RECENTER_DONE"); 1672 1673 drm_dev_exit(idx); 1674 } 1675 1676 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder, 1677 struct drm_atomic_state *state) 1678 { 1679 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1680 struct drm_device *drm = vc4_hdmi->connector.dev; 1681 struct drm_connector *connector = &vc4_hdmi->connector; 1682 struct drm_connector_state *conn_state = 1683 drm_atomic_get_new_connector_state(state, connector); 1684 struct vc4_hdmi_connector_state *vc4_conn_state = 1685 conn_state_to_vc4_hdmi_conn_state(conn_state); 1686 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1687 unsigned long tmds_char_rate = vc4_conn_state->tmds_char_rate; 1688 unsigned long bvb_rate, hsm_rate; 1689 unsigned long flags; 1690 int ret; 1691 int idx; 1692 1693 mutex_lock(&vc4_hdmi->mutex); 1694 1695 if (!drm_dev_enter(drm, &idx)) 1696 goto out; 1697 1698 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev); 1699 if (ret < 0) { 1700 DRM_ERROR("Failed to retain power domain: %d\n", ret); 1701 goto err_dev_exit; 1702 } 1703 1704 /* 1705 * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must 1706 * be faster than pixel clock, infinitesimally faster, tested in 1707 * simulation. Otherwise, exact value is unimportant for HDMI 1708 * operation." This conflicts with bcm2835's vc4 documentation, which 1709 * states HSM's clock has to be at least 108% of the pixel clock. 1710 * 1711 * Real life tests reveal that vc4's firmware statement holds up, and 1712 * users are able to use pixel clocks closer to HSM's, namely for 1713 * 1920x1200@60Hz. So it was decided to have leave a 1% margin between 1714 * both clocks. Which, for RPi0-3 implies a maximum pixel clock of 1715 * 162MHz. 1716 * 1717 * Additionally, the AXI clock needs to be at least 25% of 1718 * pixel clock, but HSM ends up being the limiting factor. 1719 */ 1720 hsm_rate = max_t(unsigned long, 1721 HSM_MIN_CLOCK_FREQ, 1722 (tmds_char_rate / 100) * 101); 1723 ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate); 1724 if (ret) { 1725 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret); 1726 goto err_put_runtime_pm; 1727 } 1728 1729 ret = clk_set_rate(vc4_hdmi->pixel_clock, tmds_char_rate); 1730 if (ret) { 1731 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret); 1732 goto err_put_runtime_pm; 1733 } 1734 1735 ret = clk_prepare_enable(vc4_hdmi->pixel_clock); 1736 if (ret) { 1737 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret); 1738 goto err_put_runtime_pm; 1739 } 1740 1741 1742 vc4_hdmi_cec_update_clk_div(vc4_hdmi); 1743 1744 if (tmds_char_rate > 297000000) 1745 bvb_rate = 300000000; 1746 else if (tmds_char_rate > 148500000) 1747 bvb_rate = 150000000; 1748 else 1749 bvb_rate = 75000000; 1750 1751 ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate); 1752 if (ret) { 1753 DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret); 1754 goto err_disable_pixel_clock; 1755 } 1756 1757 ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock); 1758 if (ret) { 1759 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret); 1760 goto err_disable_pixel_clock; 1761 } 1762 1763 if (vc4_hdmi->variant->phy_init) 1764 vc4_hdmi->variant->phy_init(vc4_hdmi, vc4_conn_state); 1765 1766 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1767 1768 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1769 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 1770 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT | 1771 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS); 1772 1773 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1774 1775 if (vc4_hdmi->variant->set_timings) 1776 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode); 1777 1778 drm_dev_exit(idx); 1779 1780 mutex_unlock(&vc4_hdmi->mutex); 1781 1782 return; 1783 1784 err_disable_pixel_clock: 1785 clk_disable_unprepare(vc4_hdmi->pixel_clock); 1786 err_put_runtime_pm: 1787 pm_runtime_put(&vc4_hdmi->pdev->dev); 1788 err_dev_exit: 1789 drm_dev_exit(idx); 1790 out: 1791 mutex_unlock(&vc4_hdmi->mutex); 1792 return; 1793 } 1794 1795 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder, 1796 struct drm_atomic_state *state) 1797 { 1798 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1799 struct drm_device *drm = vc4_hdmi->connector.dev; 1800 struct drm_connector *connector = &vc4_hdmi->connector; 1801 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1802 struct drm_connector_state *conn_state = 1803 drm_atomic_get_new_connector_state(state, connector); 1804 unsigned long flags; 1805 int idx; 1806 1807 mutex_lock(&vc4_hdmi->mutex); 1808 1809 if (!drm_dev_enter(drm, &idx)) 1810 goto out; 1811 1812 if (vc4_hdmi->variant->csc_setup) 1813 vc4_hdmi->variant->csc_setup(vc4_hdmi, conn_state, mode); 1814 1815 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1816 HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N); 1817 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1818 1819 drm_dev_exit(idx); 1820 1821 out: 1822 mutex_unlock(&vc4_hdmi->mutex); 1823 } 1824 1825 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder, 1826 struct drm_atomic_state *state) 1827 { 1828 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1829 struct drm_device *drm = vc4_hdmi->connector.dev; 1830 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1831 struct drm_display_info *display = &vc4_hdmi->connector.display_info; 1832 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 1833 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 1834 unsigned long flags; 1835 int ret; 1836 int idx; 1837 1838 mutex_lock(&vc4_hdmi->mutex); 1839 1840 if (!drm_dev_enter(drm, &idx)) 1841 goto out; 1842 1843 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1844 1845 HDMI_WRITE(HDMI_VID_CTL, 1846 VC4_HD_VID_CTL_ENABLE | 1847 VC4_HD_VID_CTL_CLRRGB | 1848 VC4_HD_VID_CTL_UNDERFLOW_ENABLE | 1849 VC4_HD_VID_CTL_FRAME_COUNTER_RESET | 1850 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) | 1851 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW)); 1852 1853 HDMI_WRITE(HDMI_VID_CTL, 1854 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX); 1855 1856 if (display->is_hdmi) { 1857 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1858 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 1859 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 1860 1861 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1862 1863 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1864 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000); 1865 WARN_ONCE(ret, "Timeout waiting for " 1866 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 1867 } else { 1868 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 1869 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & 1870 ~(VC4_HDMI_RAM_PACKET_ENABLE)); 1871 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1872 HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1873 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 1874 1875 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1876 1877 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1878 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000); 1879 WARN_ONCE(ret, "Timeout waiting for " 1880 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 1881 } 1882 1883 if (display->is_hdmi) { 1884 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1885 1886 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1887 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE)); 1888 1889 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 1890 VC4_HDMI_RAM_PACKET_ENABLE); 1891 1892 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1893 vc4_hdmi->packet_ram_enabled = true; 1894 1895 vc4_hdmi_set_infoframes(encoder); 1896 } 1897 1898 vc4_hdmi_recenter_fifo(vc4_hdmi); 1899 vc4_hdmi_enable_scrambling(encoder); 1900 1901 drm_dev_exit(idx); 1902 1903 out: 1904 mutex_unlock(&vc4_hdmi->mutex); 1905 } 1906 1907 static void vc4_hdmi_encoder_atomic_mode_set(struct drm_encoder *encoder, 1908 struct drm_crtc_state *crtc_state, 1909 struct drm_connector_state *conn_state) 1910 { 1911 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1912 struct vc4_hdmi_connector_state *vc4_state = 1913 conn_state_to_vc4_hdmi_conn_state(conn_state); 1914 1915 mutex_lock(&vc4_hdmi->mutex); 1916 drm_mode_copy(&vc4_hdmi->saved_adjusted_mode, 1917 &crtc_state->adjusted_mode); 1918 vc4_hdmi->output_bpc = vc4_state->output_bpc; 1919 vc4_hdmi->output_format = vc4_state->output_format; 1920 mutex_unlock(&vc4_hdmi->mutex); 1921 } 1922 1923 static bool 1924 vc4_hdmi_sink_supports_format_bpc(const struct vc4_hdmi *vc4_hdmi, 1925 const struct drm_display_info *info, 1926 const struct drm_display_mode *mode, 1927 unsigned int format, unsigned int bpc) 1928 { 1929 struct drm_device *dev = vc4_hdmi->connector.dev; 1930 u8 vic = drm_match_cea_mode(mode); 1931 1932 if (vic == 1 && bpc != 8) { 1933 drm_dbg(dev, "VIC1 requires a bpc of 8, got %u\n", bpc); 1934 return false; 1935 } 1936 1937 if (!info->is_hdmi && 1938 (format != VC4_HDMI_OUTPUT_RGB || bpc != 8)) { 1939 drm_dbg(dev, "DVI Monitors require an RGB output at 8 bpc\n"); 1940 return false; 1941 } 1942 1943 switch (format) { 1944 case VC4_HDMI_OUTPUT_RGB: 1945 drm_dbg(dev, "RGB Format, checking the constraints.\n"); 1946 1947 if (!(info->color_formats & DRM_COLOR_FORMAT_RGB444)) 1948 return false; 1949 1950 if (bpc == 10 && !(info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30)) { 1951 drm_dbg(dev, "10 BPC but sink doesn't support Deep Color 30.\n"); 1952 return false; 1953 } 1954 1955 if (bpc == 12 && !(info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36)) { 1956 drm_dbg(dev, "12 BPC but sink doesn't support Deep Color 36.\n"); 1957 return false; 1958 } 1959 1960 drm_dbg(dev, "RGB format supported in that configuration.\n"); 1961 1962 return true; 1963 1964 case VC4_HDMI_OUTPUT_YUV422: 1965 drm_dbg(dev, "YUV422 format, checking the constraints.\n"); 1966 1967 if (!(info->color_formats & DRM_COLOR_FORMAT_YCBCR422)) { 1968 drm_dbg(dev, "Sink doesn't support YUV422.\n"); 1969 return false; 1970 } 1971 1972 if (bpc != 12) { 1973 drm_dbg(dev, "YUV422 only supports 12 bpc.\n"); 1974 return false; 1975 } 1976 1977 drm_dbg(dev, "YUV422 format supported in that configuration.\n"); 1978 1979 return true; 1980 1981 case VC4_HDMI_OUTPUT_YUV444: 1982 drm_dbg(dev, "YUV444 format, checking the constraints.\n"); 1983 1984 if (!(info->color_formats & DRM_COLOR_FORMAT_YCBCR444)) { 1985 drm_dbg(dev, "Sink doesn't support YUV444.\n"); 1986 return false; 1987 } 1988 1989 if (bpc == 10 && !(info->edid_hdmi_ycbcr444_dc_modes & DRM_EDID_HDMI_DC_30)) { 1990 drm_dbg(dev, "10 BPC but sink doesn't support Deep Color 30.\n"); 1991 return false; 1992 } 1993 1994 if (bpc == 12 && !(info->edid_hdmi_ycbcr444_dc_modes & DRM_EDID_HDMI_DC_36)) { 1995 drm_dbg(dev, "12 BPC but sink doesn't support Deep Color 36.\n"); 1996 return false; 1997 } 1998 1999 drm_dbg(dev, "YUV444 format supported in that configuration.\n"); 2000 2001 return true; 2002 } 2003 2004 return false; 2005 } 2006 2007 static enum drm_mode_status 2008 vc4_hdmi_encoder_clock_valid(const struct vc4_hdmi *vc4_hdmi, 2009 const struct drm_display_mode *mode, 2010 unsigned long long clock) 2011 { 2012 const struct drm_connector *connector = &vc4_hdmi->connector; 2013 const struct drm_display_info *info = &connector->display_info; 2014 struct vc4_dev *vc4 = to_vc4_dev(connector->dev); 2015 2016 if (clock > vc4_hdmi->variant->max_pixel_clock) 2017 return MODE_CLOCK_HIGH; 2018 2019 if (!vc4->hvs->vc5_hdmi_enable_hdmi_20 && clock > HDMI_14_MAX_TMDS_CLK) 2020 return MODE_CLOCK_HIGH; 2021 2022 /* 4096x2160@60 is not reliable without overclocking core */ 2023 if (!vc4->hvs->vc5_hdmi_enable_4096by2160 && 2024 mode->hdisplay > 3840 && mode->vdisplay >= 2160 && 2025 drm_mode_vrefresh(mode) >= 50) 2026 return MODE_CLOCK_HIGH; 2027 2028 if (info->max_tmds_clock && clock > (info->max_tmds_clock * 1000)) 2029 return MODE_CLOCK_HIGH; 2030 2031 return MODE_OK; 2032 } 2033 2034 static unsigned long long 2035 vc4_hdmi_encoder_compute_mode_clock(const struct drm_display_mode *mode, 2036 unsigned int bpc, 2037 enum vc4_hdmi_output_format fmt) 2038 { 2039 unsigned long long clock = mode->clock * 1000ULL; 2040 2041 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 2042 clock = clock * 2; 2043 2044 if (fmt == VC4_HDMI_OUTPUT_YUV422) 2045 bpc = 8; 2046 2047 clock = clock * bpc; 2048 do_div(clock, 8); 2049 2050 return clock; 2051 } 2052 2053 static int 2054 vc4_hdmi_encoder_compute_clock(const struct vc4_hdmi *vc4_hdmi, 2055 struct vc4_hdmi_connector_state *vc4_state, 2056 const struct drm_display_mode *mode, 2057 unsigned int bpc, unsigned int fmt) 2058 { 2059 unsigned long long clock; 2060 2061 clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc, fmt); 2062 if (vc4_hdmi_encoder_clock_valid(vc4_hdmi, mode, clock) != MODE_OK) 2063 return -EINVAL; 2064 2065 vc4_state->tmds_char_rate = clock; 2066 2067 return 0; 2068 } 2069 2070 static int 2071 vc4_hdmi_encoder_compute_format(const struct vc4_hdmi *vc4_hdmi, 2072 struct vc4_hdmi_connector_state *vc4_state, 2073 const struct drm_display_mode *mode, 2074 unsigned int bpc) 2075 { 2076 struct drm_device *dev = vc4_hdmi->connector.dev; 2077 const struct drm_connector *connector = &vc4_hdmi->connector; 2078 const struct drm_display_info *info = &connector->display_info; 2079 unsigned int format; 2080 2081 drm_dbg(dev, "Trying with an RGB output\n"); 2082 2083 format = VC4_HDMI_OUTPUT_RGB; 2084 if (vc4_hdmi_sink_supports_format_bpc(vc4_hdmi, info, mode, format, bpc)) { 2085 int ret; 2086 2087 ret = vc4_hdmi_encoder_compute_clock(vc4_hdmi, vc4_state, 2088 mode, bpc, format); 2089 if (!ret) { 2090 vc4_state->output_format = format; 2091 return 0; 2092 } 2093 } 2094 2095 drm_dbg(dev, "Failed, Trying with an YUV422 output\n"); 2096 2097 format = VC4_HDMI_OUTPUT_YUV422; 2098 if (vc4_hdmi_sink_supports_format_bpc(vc4_hdmi, info, mode, format, bpc)) { 2099 int ret; 2100 2101 ret = vc4_hdmi_encoder_compute_clock(vc4_hdmi, vc4_state, 2102 mode, bpc, format); 2103 if (!ret) { 2104 vc4_state->output_format = format; 2105 return 0; 2106 } 2107 } 2108 2109 drm_dbg(dev, "Failed. No Format Supported for that bpc count.\n"); 2110 2111 return -EINVAL; 2112 } 2113 2114 static int 2115 vc4_hdmi_encoder_compute_config(const struct vc4_hdmi *vc4_hdmi, 2116 struct vc4_hdmi_connector_state *vc4_state, 2117 const struct drm_display_mode *mode) 2118 { 2119 struct drm_device *dev = vc4_hdmi->connector.dev; 2120 struct drm_connector_state *conn_state = &vc4_state->base; 2121 unsigned int max_bpc = clamp_t(unsigned int, conn_state->max_bpc, 8, 12); 2122 unsigned int bpc; 2123 int ret; 2124 2125 for (bpc = max_bpc; bpc >= 8; bpc -= 2) { 2126 drm_dbg(dev, "Trying with a %d bpc output\n", bpc); 2127 2128 ret = vc4_hdmi_encoder_compute_format(vc4_hdmi, vc4_state, 2129 mode, bpc); 2130 if (ret) 2131 continue; 2132 2133 vc4_state->output_bpc = bpc; 2134 2135 drm_dbg(dev, 2136 "Mode %ux%u @ %uHz: Found configuration: bpc: %u, fmt: %s, clock: %llu\n", 2137 mode->hdisplay, mode->vdisplay, drm_mode_vrefresh(mode), 2138 vc4_state->output_bpc, 2139 vc4_hdmi_output_fmt_str(vc4_state->output_format), 2140 vc4_state->tmds_char_rate); 2141 2142 break; 2143 } 2144 2145 return ret; 2146 } 2147 2148 #define WIFI_2_4GHz_CH1_MIN_FREQ 2400000000ULL 2149 #define WIFI_2_4GHz_CH1_MAX_FREQ 2422000000ULL 2150 2151 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder, 2152 struct drm_crtc_state *crtc_state, 2153 struct drm_connector_state *conn_state) 2154 { 2155 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 2156 struct drm_connector *connector = &vc4_hdmi->connector; 2157 struct drm_connector_state *old_conn_state = 2158 drm_atomic_get_old_connector_state(conn_state->state, connector); 2159 struct vc4_hdmi_connector_state *old_vc4_state = 2160 conn_state_to_vc4_hdmi_conn_state(old_conn_state); 2161 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state); 2162 struct drm_display_mode *mode = &crtc_state->adjusted_mode; 2163 unsigned long long tmds_char_rate = mode->clock * 1000; 2164 unsigned long long tmds_bit_rate; 2165 int ret; 2166 2167 if (vc4_hdmi->variant->unsupported_odd_h_timings) { 2168 if (mode->flags & DRM_MODE_FLAG_DBLCLK) { 2169 /* Only try to fixup DBLCLK modes to get 480i and 576i 2170 * working. 2171 * A generic solution for all modes with odd horizontal 2172 * timing values seems impossible based on trying to 2173 * solve it for 1366x768 monitors. 2174 */ 2175 if ((mode->hsync_start - mode->hdisplay) & 1) 2176 mode->hsync_start--; 2177 if ((mode->hsync_end - mode->hsync_start) & 1) 2178 mode->hsync_end--; 2179 } 2180 2181 /* Now check whether we still have odd values remaining */ 2182 if ((mode->hdisplay % 2) || (mode->hsync_start % 2) || 2183 (mode->hsync_end % 2) || (mode->htotal % 2)) 2184 return -EINVAL; 2185 } 2186 2187 /* 2188 * The 1440p@60 pixel rate is in the same range than the first 2189 * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz 2190 * bandwidth). Slightly lower the frequency to bring it out of 2191 * the WiFi range. 2192 */ 2193 tmds_bit_rate = tmds_char_rate * 10; 2194 if (vc4_hdmi->disable_wifi_frequencies && 2195 (tmds_bit_rate >= WIFI_2_4GHz_CH1_MIN_FREQ && 2196 tmds_bit_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) { 2197 mode->clock = 238560; 2198 tmds_char_rate = mode->clock * 1000; 2199 } 2200 2201 ret = vc4_hdmi_encoder_compute_config(vc4_hdmi, vc4_state, mode); 2202 if (ret) 2203 return ret; 2204 2205 /* vc4_hdmi_encoder_compute_config may have changed output_bpc and/or output_format */ 2206 if (vc4_state->output_bpc != old_vc4_state->output_bpc || 2207 vc4_state->output_format != old_vc4_state->output_format) 2208 crtc_state->mode_changed = true; 2209 2210 return 0; 2211 } 2212 2213 static enum drm_mode_status 2214 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder, 2215 const struct drm_display_mode *mode) 2216 { 2217 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 2218 2219 if (vc4_hdmi->variant->unsupported_odd_h_timings && 2220 !(mode->flags & DRM_MODE_FLAG_DBLCLK) && 2221 ((mode->hdisplay % 2) || (mode->hsync_start % 2) || 2222 (mode->hsync_end % 2) || (mode->htotal % 2))) 2223 return MODE_H_ILLEGAL; 2224 2225 return vc4_hdmi_encoder_clock_valid(vc4_hdmi, mode, mode->clock * 1000); 2226 } 2227 2228 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = { 2229 .atomic_check = vc4_hdmi_encoder_atomic_check, 2230 .atomic_mode_set = vc4_hdmi_encoder_atomic_mode_set, 2231 .mode_valid = vc4_hdmi_encoder_mode_valid, 2232 }; 2233 2234 static int vc4_hdmi_late_register(struct drm_encoder *encoder) 2235 { 2236 struct drm_device *drm = encoder->dev; 2237 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 2238 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant; 2239 2240 drm_debugfs_add_file(drm, variant->debugfs_name, 2241 vc4_hdmi_debugfs_regs, vc4_hdmi); 2242 2243 return 0; 2244 } 2245 2246 static const struct drm_encoder_funcs vc4_hdmi_encoder_funcs = { 2247 .late_register = vc4_hdmi_late_register, 2248 }; 2249 2250 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask) 2251 { 2252 int i; 2253 u32 channel_map = 0; 2254 2255 for (i = 0; i < 8; i++) { 2256 if (channel_mask & BIT(i)) 2257 channel_map |= i << (3 * i); 2258 } 2259 return channel_map; 2260 } 2261 2262 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask) 2263 { 2264 int i; 2265 u32 channel_map = 0; 2266 2267 for (i = 0; i < 8; i++) { 2268 if (channel_mask & BIT(i)) 2269 channel_map |= i << (4 * i); 2270 } 2271 return channel_map; 2272 } 2273 2274 static bool vc5_hdmi_hp_detect(struct vc4_hdmi *vc4_hdmi) 2275 { 2276 struct drm_device *drm = vc4_hdmi->connector.dev; 2277 unsigned long flags; 2278 u32 hotplug; 2279 int idx; 2280 2281 if (!drm_dev_enter(drm, &idx)) 2282 return false; 2283 2284 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2285 hotplug = HDMI_READ(HDMI_HOTPLUG); 2286 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2287 2288 drm_dev_exit(idx); 2289 2290 return !!(hotplug & VC4_HDMI_HOTPLUG_CONNECTED); 2291 } 2292 2293 /* HDMI audio codec callbacks */ 2294 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi, 2295 unsigned int samplerate) 2296 { 2297 struct drm_device *drm = vc4_hdmi->connector.dev; 2298 u32 hsm_clock; 2299 unsigned long flags; 2300 unsigned long n, m; 2301 int idx; 2302 2303 if (!drm_dev_enter(drm, &idx)) 2304 return; 2305 2306 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock); 2307 rational_best_approximation(hsm_clock, samplerate, 2308 VC4_HD_MAI_SMP_N_MASK >> 2309 VC4_HD_MAI_SMP_N_SHIFT, 2310 (VC4_HD_MAI_SMP_M_MASK >> 2311 VC4_HD_MAI_SMP_M_SHIFT) + 1, 2312 &n, &m); 2313 2314 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2315 HDMI_WRITE(HDMI_MAI_SMP, 2316 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) | 2317 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M)); 2318 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2319 2320 drm_dev_exit(idx); 2321 } 2322 2323 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi, unsigned int samplerate) 2324 { 2325 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 2326 u32 n, cts; 2327 u64 tmp; 2328 2329 lockdep_assert_held(&vc4_hdmi->mutex); 2330 lockdep_assert_held(&vc4_hdmi->hw_lock); 2331 2332 n = 128 * samplerate / 1000; 2333 tmp = (u64)(mode->clock * 1000) * n; 2334 do_div(tmp, 128 * samplerate); 2335 cts = tmp; 2336 2337 HDMI_WRITE(HDMI_CRP_CFG, 2338 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN | 2339 VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N)); 2340 2341 /* 2342 * We could get slightly more accurate clocks in some cases by 2343 * providing a CTS_1 value. The two CTS values are alternated 2344 * between based on the period fields 2345 */ 2346 HDMI_WRITE(HDMI_CTS_0, cts); 2347 HDMI_WRITE(HDMI_CTS_1, cts); 2348 } 2349 2350 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai) 2351 { 2352 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai); 2353 2354 return snd_soc_card_get_drvdata(card); 2355 } 2356 2357 static bool vc4_hdmi_audio_can_stream(struct vc4_hdmi *vc4_hdmi) 2358 { 2359 struct drm_display_info *display = &vc4_hdmi->connector.display_info; 2360 2361 lockdep_assert_held(&vc4_hdmi->mutex); 2362 2363 /* 2364 * If the encoder is currently in DVI mode, treat the codec DAI 2365 * as missing. 2366 */ 2367 if (!display->is_hdmi) 2368 return false; 2369 2370 return true; 2371 } 2372 2373 static int vc4_hdmi_audio_startup(struct device *dev, void *data) 2374 { 2375 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 2376 struct drm_device *drm = vc4_hdmi->connector.dev; 2377 unsigned long flags; 2378 int ret = 0; 2379 int idx; 2380 2381 mutex_lock(&vc4_hdmi->mutex); 2382 2383 if (!drm_dev_enter(drm, &idx)) { 2384 ret = -ENODEV; 2385 goto out; 2386 } 2387 2388 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) { 2389 ret = -ENODEV; 2390 goto out_dev_exit; 2391 } 2392 2393 vc4_hdmi->audio.streaming = true; 2394 2395 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2396 HDMI_WRITE(HDMI_MAI_CTL, 2397 VC4_HD_MAI_CTL_RESET | 2398 VC4_HD_MAI_CTL_FLUSH | 2399 VC4_HD_MAI_CTL_DLATE | 2400 VC4_HD_MAI_CTL_ERRORE | 2401 VC4_HD_MAI_CTL_ERRORF); 2402 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2403 2404 if (vc4_hdmi->variant->phy_rng_enable) 2405 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi); 2406 2407 out_dev_exit: 2408 drm_dev_exit(idx); 2409 out: 2410 mutex_unlock(&vc4_hdmi->mutex); 2411 2412 return ret; 2413 } 2414 2415 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi) 2416 { 2417 struct drm_encoder *encoder = &vc4_hdmi->encoder.base; 2418 struct device *dev = &vc4_hdmi->pdev->dev; 2419 unsigned long flags; 2420 int ret; 2421 2422 lockdep_assert_held(&vc4_hdmi->mutex); 2423 2424 vc4_hdmi->audio.streaming = false; 2425 ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO, false); 2426 if (ret) 2427 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret); 2428 2429 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2430 2431 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET); 2432 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF); 2433 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH); 2434 2435 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2436 } 2437 2438 static void vc4_hdmi_audio_shutdown(struct device *dev, void *data) 2439 { 2440 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 2441 struct drm_device *drm = vc4_hdmi->connector.dev; 2442 unsigned long flags; 2443 int idx; 2444 2445 mutex_lock(&vc4_hdmi->mutex); 2446 2447 if (!drm_dev_enter(drm, &idx)) 2448 goto out; 2449 2450 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2451 2452 HDMI_WRITE(HDMI_MAI_CTL, 2453 VC4_HD_MAI_CTL_DLATE | 2454 VC4_HD_MAI_CTL_ERRORE | 2455 VC4_HD_MAI_CTL_ERRORF); 2456 2457 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2458 2459 if (vc4_hdmi->variant->phy_rng_disable) 2460 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi); 2461 2462 vc4_hdmi->audio.streaming = false; 2463 vc4_hdmi_audio_reset(vc4_hdmi); 2464 2465 drm_dev_exit(idx); 2466 2467 out: 2468 mutex_unlock(&vc4_hdmi->mutex); 2469 } 2470 2471 static int sample_rate_to_mai_fmt(int samplerate) 2472 { 2473 switch (samplerate) { 2474 case 8000: 2475 return VC4_HDMI_MAI_SAMPLE_RATE_8000; 2476 case 11025: 2477 return VC4_HDMI_MAI_SAMPLE_RATE_11025; 2478 case 12000: 2479 return VC4_HDMI_MAI_SAMPLE_RATE_12000; 2480 case 16000: 2481 return VC4_HDMI_MAI_SAMPLE_RATE_16000; 2482 case 22050: 2483 return VC4_HDMI_MAI_SAMPLE_RATE_22050; 2484 case 24000: 2485 return VC4_HDMI_MAI_SAMPLE_RATE_24000; 2486 case 32000: 2487 return VC4_HDMI_MAI_SAMPLE_RATE_32000; 2488 case 44100: 2489 return VC4_HDMI_MAI_SAMPLE_RATE_44100; 2490 case 48000: 2491 return VC4_HDMI_MAI_SAMPLE_RATE_48000; 2492 case 64000: 2493 return VC4_HDMI_MAI_SAMPLE_RATE_64000; 2494 case 88200: 2495 return VC4_HDMI_MAI_SAMPLE_RATE_88200; 2496 case 96000: 2497 return VC4_HDMI_MAI_SAMPLE_RATE_96000; 2498 case 128000: 2499 return VC4_HDMI_MAI_SAMPLE_RATE_128000; 2500 case 176400: 2501 return VC4_HDMI_MAI_SAMPLE_RATE_176400; 2502 case 192000: 2503 return VC4_HDMI_MAI_SAMPLE_RATE_192000; 2504 default: 2505 return VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED; 2506 } 2507 } 2508 2509 /* HDMI audio codec callbacks */ 2510 static int vc4_hdmi_audio_prepare(struct device *dev, void *data, 2511 struct hdmi_codec_daifmt *daifmt, 2512 struct hdmi_codec_params *params) 2513 { 2514 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 2515 struct drm_device *drm = vc4_hdmi->connector.dev; 2516 struct drm_encoder *encoder = &vc4_hdmi->encoder.base; 2517 unsigned int sample_rate = params->sample_rate; 2518 unsigned int channels = params->channels; 2519 unsigned long flags; 2520 u32 audio_packet_config, channel_mask; 2521 u32 channel_map; 2522 u32 mai_audio_format; 2523 u32 mai_sample_rate; 2524 int ret = 0; 2525 int idx; 2526 2527 dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__, 2528 sample_rate, params->sample_width, channels); 2529 2530 mutex_lock(&vc4_hdmi->mutex); 2531 2532 if (!drm_dev_enter(drm, &idx)) { 2533 ret = -ENODEV; 2534 goto out; 2535 } 2536 2537 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) { 2538 ret = -EINVAL; 2539 goto out_dev_exit; 2540 } 2541 2542 vc4_hdmi_audio_set_mai_clock(vc4_hdmi, sample_rate); 2543 2544 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2545 HDMI_WRITE(HDMI_MAI_CTL, 2546 VC4_SET_FIELD(channels, VC4_HD_MAI_CTL_CHNUM) | 2547 VC4_HD_MAI_CTL_WHOLSMP | 2548 VC4_HD_MAI_CTL_CHALIGN | 2549 VC4_HD_MAI_CTL_ENABLE); 2550 2551 mai_sample_rate = sample_rate_to_mai_fmt(sample_rate); 2552 if (params->iec.status[0] & IEC958_AES0_NONAUDIO && 2553 params->channels == 8) 2554 mai_audio_format = VC4_HDMI_MAI_FORMAT_HBR; 2555 else 2556 mai_audio_format = VC4_HDMI_MAI_FORMAT_PCM; 2557 HDMI_WRITE(HDMI_MAI_FMT, 2558 VC4_SET_FIELD(mai_sample_rate, 2559 VC4_HDMI_MAI_FORMAT_SAMPLE_RATE) | 2560 VC4_SET_FIELD(mai_audio_format, 2561 VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT)); 2562 2563 /* The B frame identifier should match the value used by alsa-lib (8) */ 2564 audio_packet_config = 2565 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT | 2566 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS | 2567 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER); 2568 2569 channel_mask = GENMASK(channels - 1, 0); 2570 audio_packet_config |= VC4_SET_FIELD(channel_mask, 2571 VC4_HDMI_AUDIO_PACKET_CEA_MASK); 2572 2573 /* Set the MAI threshold */ 2574 HDMI_WRITE(HDMI_MAI_THR, 2575 VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICHIGH) | 2576 VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICLOW) | 2577 VC4_SET_FIELD(0x06, VC4_HD_MAI_THR_DREQHIGH) | 2578 VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_DREQLOW)); 2579 2580 HDMI_WRITE(HDMI_MAI_CONFIG, 2581 VC4_HDMI_MAI_CONFIG_BIT_REVERSE | 2582 VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE | 2583 VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK)); 2584 2585 channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask); 2586 HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map); 2587 HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config); 2588 2589 vc4_hdmi_set_n_cts(vc4_hdmi, sample_rate); 2590 2591 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2592 2593 memcpy(&vc4_hdmi->audio.infoframe, ¶ms->cea, sizeof(params->cea)); 2594 vc4_hdmi_set_audio_infoframe(encoder); 2595 2596 out_dev_exit: 2597 drm_dev_exit(idx); 2598 out: 2599 mutex_unlock(&vc4_hdmi->mutex); 2600 2601 return ret; 2602 } 2603 2604 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = { 2605 .name = "vc4-hdmi-cpu-dai-component", 2606 .legacy_dai_naming = 1, 2607 }; 2608 2609 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai) 2610 { 2611 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai); 2612 2613 snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL); 2614 2615 return 0; 2616 } 2617 2618 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = { 2619 .name = "vc4-hdmi-cpu-dai", 2620 .probe = vc4_hdmi_audio_cpu_dai_probe, 2621 .playback = { 2622 .stream_name = "Playback", 2623 .channels_min = 1, 2624 .channels_max = 8, 2625 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 2626 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 2627 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 2628 SNDRV_PCM_RATE_192000, 2629 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 2630 }, 2631 }; 2632 2633 static const struct snd_dmaengine_pcm_config pcm_conf = { 2634 .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx", 2635 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 2636 }; 2637 2638 static int vc4_hdmi_audio_get_eld(struct device *dev, void *data, 2639 uint8_t *buf, size_t len) 2640 { 2641 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 2642 struct drm_connector *connector = &vc4_hdmi->connector; 2643 2644 mutex_lock(&vc4_hdmi->mutex); 2645 memcpy(buf, connector->eld, min(sizeof(connector->eld), len)); 2646 mutex_unlock(&vc4_hdmi->mutex); 2647 2648 return 0; 2649 } 2650 2651 static const struct hdmi_codec_ops vc4_hdmi_codec_ops = { 2652 .get_eld = vc4_hdmi_audio_get_eld, 2653 .prepare = vc4_hdmi_audio_prepare, 2654 .audio_shutdown = vc4_hdmi_audio_shutdown, 2655 .audio_startup = vc4_hdmi_audio_startup, 2656 }; 2657 2658 static struct hdmi_codec_pdata vc4_hdmi_codec_pdata = { 2659 .ops = &vc4_hdmi_codec_ops, 2660 .max_i2s_channels = 8, 2661 .i2s = 1, 2662 }; 2663 2664 static void vc4_hdmi_audio_codec_release(void *ptr) 2665 { 2666 struct vc4_hdmi *vc4_hdmi = ptr; 2667 2668 platform_device_unregister(vc4_hdmi->audio.codec_pdev); 2669 vc4_hdmi->audio.codec_pdev = NULL; 2670 } 2671 2672 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi) 2673 { 2674 const struct vc4_hdmi_register *mai_data = 2675 &vc4_hdmi->variant->registers[HDMI_MAI_DATA]; 2676 struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link; 2677 struct snd_soc_card *card = &vc4_hdmi->audio.card; 2678 struct device *dev = &vc4_hdmi->pdev->dev; 2679 struct platform_device *codec_pdev; 2680 const __be32 *addr; 2681 int index, len; 2682 int ret; 2683 2684 /* 2685 * ASoC makes it a bit hard to retrieve a pointer to the 2686 * vc4_hdmi structure. Registering the card will overwrite our 2687 * device drvdata with a pointer to the snd_soc_card structure, 2688 * which can then be used to retrieve whatever drvdata we want 2689 * to associate. 2690 * 2691 * However, that doesn't fly in the case where we wouldn't 2692 * register an ASoC card (because of an old DT that is missing 2693 * the dmas properties for example), then the card isn't 2694 * registered and the device drvdata wouldn't be set. 2695 * 2696 * We can deal with both cases by making sure a snd_soc_card 2697 * pointer and a vc4_hdmi structure are pointing to the same 2698 * memory address, so we can treat them indistinctly without any 2699 * issue. 2700 */ 2701 BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0); 2702 BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0); 2703 2704 if (!of_find_property(dev->of_node, "dmas", &len) || !len) { 2705 dev_warn(dev, 2706 "'dmas' DT property is missing or empty, no HDMI audio\n"); 2707 return 0; 2708 } 2709 2710 if (mai_data->reg != VC4_HD) { 2711 WARN_ONCE(true, "MAI isn't in the HD block\n"); 2712 return -EINVAL; 2713 } 2714 2715 /* 2716 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve 2717 * the bus address specified in the DT, because the physical address 2718 * (the one returned by platform_get_resource()) is not appropriate 2719 * for DMA transfers. 2720 * This VC/MMU should probably be exposed to avoid this kind of hacks. 2721 */ 2722 index = of_property_match_string(dev->of_node, "reg-names", "hd"); 2723 /* Before BCM2711, we don't have a named register range */ 2724 if (index < 0) 2725 index = 1; 2726 2727 addr = of_get_address(dev->of_node, index, NULL, NULL); 2728 2729 vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset; 2730 vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 2731 vc4_hdmi->audio.dma_data.maxburst = 2; 2732 2733 /* 2734 * NOTE: Strictly speaking, we should probably use a DRM-managed 2735 * registration there to avoid removing all the audio components 2736 * by the time the driver doesn't have any user anymore. 2737 * 2738 * However, the ASoC core uses a number of devm_kzalloc calls 2739 * when registering, even when using non-device-managed 2740 * functions (such as in snd_soc_register_component()). 2741 * 2742 * If we call snd_soc_unregister_component() in a DRM-managed 2743 * action, the device-managed actions have already been executed 2744 * and thus we would access memory that has been freed. 2745 * 2746 * Using device-managed hooks here probably leaves us open to a 2747 * bunch of issues if userspace still has a handle on the ALSA 2748 * device when the device is removed. However, this is mitigated 2749 * by the use of drm_dev_enter()/drm_dev_exit() in the audio 2750 * path to prevent the access to the device resources if it 2751 * isn't there anymore. 2752 * 2753 * Then, the vc4_hdmi structure is DRM-managed and thus only 2754 * freed whenever the last user has closed the DRM device file. 2755 * It should thus outlive ALSA in most situations. 2756 */ 2757 ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0); 2758 if (ret) { 2759 dev_err(dev, "Could not register PCM component: %d\n", ret); 2760 return ret; 2761 } 2762 2763 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp, 2764 &vc4_hdmi_audio_cpu_dai_drv, 1); 2765 if (ret) { 2766 dev_err(dev, "Could not register CPU DAI: %d\n", ret); 2767 return ret; 2768 } 2769 2770 codec_pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME, 2771 PLATFORM_DEVID_AUTO, 2772 &vc4_hdmi_codec_pdata, 2773 sizeof(vc4_hdmi_codec_pdata)); 2774 if (IS_ERR(codec_pdev)) { 2775 dev_err(dev, "Couldn't register the HDMI codec: %ld\n", PTR_ERR(codec_pdev)); 2776 return PTR_ERR(codec_pdev); 2777 } 2778 vc4_hdmi->audio.codec_pdev = codec_pdev; 2779 2780 ret = devm_add_action_or_reset(dev, vc4_hdmi_audio_codec_release, vc4_hdmi); 2781 if (ret) 2782 return ret; 2783 2784 dai_link->cpus = &vc4_hdmi->audio.cpu; 2785 dai_link->codecs = &vc4_hdmi->audio.codec; 2786 dai_link->platforms = &vc4_hdmi->audio.platform; 2787 2788 dai_link->num_cpus = 1; 2789 dai_link->num_codecs = 1; 2790 dai_link->num_platforms = 1; 2791 2792 dai_link->name = "MAI"; 2793 dai_link->stream_name = "MAI PCM"; 2794 dai_link->codecs->dai_name = "i2s-hifi"; 2795 dai_link->cpus->dai_name = dev_name(dev); 2796 dai_link->codecs->name = dev_name(&codec_pdev->dev); 2797 dai_link->platforms->name = dev_name(dev); 2798 2799 card->dai_link = dai_link; 2800 card->num_links = 1; 2801 card->name = vc4_hdmi->variant->card_name; 2802 card->driver_name = "vc4-hdmi"; 2803 card->dev = dev; 2804 card->owner = THIS_MODULE; 2805 2806 /* 2807 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and 2808 * stores a pointer to the snd card object in dev->driver_data. This 2809 * means we cannot use it for something else. The hdmi back-pointer is 2810 * now stored in card->drvdata and should be retrieved with 2811 * snd_soc_card_get_drvdata() if needed. 2812 */ 2813 snd_soc_card_set_drvdata(card, vc4_hdmi); 2814 ret = devm_snd_soc_register_card(dev, card); 2815 if (ret) 2816 dev_err_probe(dev, ret, "Could not register sound card\n"); 2817 2818 return ret; 2819 2820 } 2821 2822 static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv) 2823 { 2824 struct vc4_hdmi *vc4_hdmi = priv; 2825 struct drm_connector *connector = &vc4_hdmi->connector; 2826 struct drm_device *dev = connector->dev; 2827 2828 if (dev && dev->registered) 2829 drm_connector_helper_hpd_irq_event(connector); 2830 2831 return IRQ_HANDLED; 2832 } 2833 2834 static int vc4_hdmi_hotplug_init(struct vc4_hdmi *vc4_hdmi) 2835 { 2836 struct drm_connector *connector = &vc4_hdmi->connector; 2837 struct platform_device *pdev = vc4_hdmi->pdev; 2838 int ret; 2839 2840 if (vc4_hdmi->variant->external_irq_controller) { 2841 unsigned int hpd_con = platform_get_irq_byname(pdev, "hpd-connected"); 2842 unsigned int hpd_rm = platform_get_irq_byname(pdev, "hpd-removed"); 2843 2844 ret = devm_request_threaded_irq(&pdev->dev, hpd_con, 2845 NULL, 2846 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT, 2847 "vc4 hdmi hpd connected", vc4_hdmi); 2848 if (ret) 2849 return ret; 2850 2851 ret = devm_request_threaded_irq(&pdev->dev, hpd_rm, 2852 NULL, 2853 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT, 2854 "vc4 hdmi hpd disconnected", vc4_hdmi); 2855 if (ret) 2856 return ret; 2857 2858 connector->polled = DRM_CONNECTOR_POLL_HPD; 2859 } 2860 2861 return 0; 2862 } 2863 2864 #ifdef CONFIG_DRM_VC4_HDMI_CEC 2865 static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv) 2866 { 2867 struct vc4_hdmi *vc4_hdmi = priv; 2868 2869 if (vc4_hdmi->cec_rx_msg.len) 2870 cec_received_msg(vc4_hdmi->cec_adap, 2871 &vc4_hdmi->cec_rx_msg); 2872 2873 return IRQ_HANDLED; 2874 } 2875 2876 static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv) 2877 { 2878 struct vc4_hdmi *vc4_hdmi = priv; 2879 2880 if (vc4_hdmi->cec_tx_ok) { 2881 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK, 2882 0, 0, 0, 0); 2883 } else { 2884 /* 2885 * This CEC implementation makes 1 retry, so if we 2886 * get a NACK, then that means it made 2 attempts. 2887 */ 2888 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK, 2889 0, 2, 0, 0); 2890 } 2891 return IRQ_HANDLED; 2892 } 2893 2894 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv) 2895 { 2896 struct vc4_hdmi *vc4_hdmi = priv; 2897 irqreturn_t ret; 2898 2899 if (vc4_hdmi->cec_irq_was_rx) 2900 ret = vc4_cec_irq_handler_rx_thread(irq, priv); 2901 else 2902 ret = vc4_cec_irq_handler_tx_thread(irq, priv); 2903 2904 return ret; 2905 } 2906 2907 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1) 2908 { 2909 struct drm_device *dev = vc4_hdmi->connector.dev; 2910 struct cec_msg *msg = &vc4_hdmi->cec_rx_msg; 2911 unsigned int i; 2912 2913 lockdep_assert_held(&vc4_hdmi->hw_lock); 2914 2915 msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >> 2916 VC4_HDMI_CEC_REC_WRD_CNT_SHIFT); 2917 2918 if (msg->len > 16) { 2919 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len); 2920 return; 2921 } 2922 2923 for (i = 0; i < msg->len; i += 4) { 2924 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2)); 2925 2926 msg->msg[i] = val & 0xff; 2927 msg->msg[i + 1] = (val >> 8) & 0xff; 2928 msg->msg[i + 2] = (val >> 16) & 0xff; 2929 msg->msg[i + 3] = (val >> 24) & 0xff; 2930 } 2931 } 2932 2933 static irqreturn_t vc4_cec_irq_handler_tx_bare_locked(struct vc4_hdmi *vc4_hdmi) 2934 { 2935 u32 cntrl1; 2936 2937 /* 2938 * We don't need to protect the register access using 2939 * drm_dev_enter() there because the interrupt handler lifetime 2940 * is tied to the device itself, and not to the DRM device. 2941 * 2942 * So when the device will be gone, one of the first thing we 2943 * will be doing will be to unregister the interrupt handler, 2944 * and then unregister the DRM device. drm_dev_enter() would 2945 * thus always succeed if we are here. 2946 */ 2947 2948 lockdep_assert_held(&vc4_hdmi->hw_lock); 2949 2950 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1); 2951 vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD; 2952 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 2953 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 2954 2955 return IRQ_WAKE_THREAD; 2956 } 2957 2958 static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv) 2959 { 2960 struct vc4_hdmi *vc4_hdmi = priv; 2961 irqreturn_t ret; 2962 2963 spin_lock(&vc4_hdmi->hw_lock); 2964 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi); 2965 spin_unlock(&vc4_hdmi->hw_lock); 2966 2967 return ret; 2968 } 2969 2970 static irqreturn_t vc4_cec_irq_handler_rx_bare_locked(struct vc4_hdmi *vc4_hdmi) 2971 { 2972 u32 cntrl1; 2973 2974 lockdep_assert_held(&vc4_hdmi->hw_lock); 2975 2976 /* 2977 * We don't need to protect the register access using 2978 * drm_dev_enter() there because the interrupt handler lifetime 2979 * is tied to the device itself, and not to the DRM device. 2980 * 2981 * So when the device will be gone, one of the first thing we 2982 * will be doing will be to unregister the interrupt handler, 2983 * and then unregister the DRM device. drm_dev_enter() would 2984 * thus always succeed if we are here. 2985 */ 2986 2987 vc4_hdmi->cec_rx_msg.len = 0; 2988 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1); 2989 vc4_cec_read_msg(vc4_hdmi, cntrl1); 2990 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 2991 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 2992 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 2993 2994 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 2995 2996 return IRQ_WAKE_THREAD; 2997 } 2998 2999 static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv) 3000 { 3001 struct vc4_hdmi *vc4_hdmi = priv; 3002 irqreturn_t ret; 3003 3004 spin_lock(&vc4_hdmi->hw_lock); 3005 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi); 3006 spin_unlock(&vc4_hdmi->hw_lock); 3007 3008 return ret; 3009 } 3010 3011 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv) 3012 { 3013 struct vc4_hdmi *vc4_hdmi = priv; 3014 u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS); 3015 irqreturn_t ret; 3016 u32 cntrl5; 3017 3018 /* 3019 * We don't need to protect the register access using 3020 * drm_dev_enter() there because the interrupt handler lifetime 3021 * is tied to the device itself, and not to the DRM device. 3022 * 3023 * So when the device will be gone, one of the first thing we 3024 * will be doing will be to unregister the interrupt handler, 3025 * and then unregister the DRM device. drm_dev_enter() would 3026 * thus always succeed if we are here. 3027 */ 3028 3029 if (!(stat & VC4_HDMI_CPU_CEC)) 3030 return IRQ_NONE; 3031 3032 spin_lock(&vc4_hdmi->hw_lock); 3033 cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5); 3034 vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT; 3035 if (vc4_hdmi->cec_irq_was_rx) 3036 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi); 3037 else 3038 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi); 3039 3040 HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC); 3041 spin_unlock(&vc4_hdmi->hw_lock); 3042 3043 return ret; 3044 } 3045 3046 static int vc4_hdmi_cec_enable(struct cec_adapter *adap) 3047 { 3048 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 3049 struct drm_device *drm = vc4_hdmi->connector.dev; 3050 /* clock period in microseconds */ 3051 const u32 usecs = 1000000 / CEC_CLOCK_FREQ; 3052 unsigned long flags; 3053 u32 val; 3054 int ret; 3055 int idx; 3056 3057 if (!drm_dev_enter(drm, &idx)) 3058 /* 3059 * We can't return an error code, because the CEC 3060 * framework will emit WARN_ON messages at unbind 3061 * otherwise. 3062 */ 3063 return 0; 3064 3065 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev); 3066 if (ret) { 3067 drm_dev_exit(idx); 3068 return ret; 3069 } 3070 3071 mutex_lock(&vc4_hdmi->mutex); 3072 3073 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 3074 3075 val = HDMI_READ(HDMI_CEC_CNTRL_5); 3076 val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET | 3077 VC4_HDMI_CEC_CNT_TO_4700_US_MASK | 3078 VC4_HDMI_CEC_CNT_TO_4500_US_MASK); 3079 val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) | 3080 ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT); 3081 3082 HDMI_WRITE(HDMI_CEC_CNTRL_5, val | 3083 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 3084 HDMI_WRITE(HDMI_CEC_CNTRL_5, val); 3085 HDMI_WRITE(HDMI_CEC_CNTRL_2, 3086 ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) | 3087 ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) | 3088 ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) | 3089 ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) | 3090 ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT)); 3091 HDMI_WRITE(HDMI_CEC_CNTRL_3, 3092 ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) | 3093 ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) | 3094 ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) | 3095 ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT)); 3096 HDMI_WRITE(HDMI_CEC_CNTRL_4, 3097 ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) | 3098 ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) | 3099 ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) | 3100 ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT)); 3101 3102 if (!vc4_hdmi->variant->external_irq_controller) 3103 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC); 3104 3105 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 3106 3107 mutex_unlock(&vc4_hdmi->mutex); 3108 drm_dev_exit(idx); 3109 3110 return 0; 3111 } 3112 3113 static int vc4_hdmi_cec_disable(struct cec_adapter *adap) 3114 { 3115 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 3116 struct drm_device *drm = vc4_hdmi->connector.dev; 3117 unsigned long flags; 3118 int idx; 3119 3120 if (!drm_dev_enter(drm, &idx)) 3121 /* 3122 * We can't return an error code, because the CEC 3123 * framework will emit WARN_ON messages at unbind 3124 * otherwise. 3125 */ 3126 return 0; 3127 3128 mutex_lock(&vc4_hdmi->mutex); 3129 3130 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 3131 3132 if (!vc4_hdmi->variant->external_irq_controller) 3133 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC); 3134 3135 HDMI_WRITE(HDMI_CEC_CNTRL_5, HDMI_READ(HDMI_CEC_CNTRL_5) | 3136 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 3137 3138 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 3139 3140 mutex_unlock(&vc4_hdmi->mutex); 3141 3142 pm_runtime_put(&vc4_hdmi->pdev->dev); 3143 3144 drm_dev_exit(idx); 3145 3146 return 0; 3147 } 3148 3149 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable) 3150 { 3151 if (enable) 3152 return vc4_hdmi_cec_enable(adap); 3153 else 3154 return vc4_hdmi_cec_disable(adap); 3155 } 3156 3157 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr) 3158 { 3159 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 3160 struct drm_device *drm = vc4_hdmi->connector.dev; 3161 unsigned long flags; 3162 int idx; 3163 3164 if (!drm_dev_enter(drm, &idx)) 3165 /* 3166 * We can't return an error code, because the CEC 3167 * framework will emit WARN_ON messages at unbind 3168 * otherwise. 3169 */ 3170 return 0; 3171 3172 mutex_lock(&vc4_hdmi->mutex); 3173 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 3174 HDMI_WRITE(HDMI_CEC_CNTRL_1, 3175 (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) | 3176 (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT); 3177 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 3178 mutex_unlock(&vc4_hdmi->mutex); 3179 3180 drm_dev_exit(idx); 3181 3182 return 0; 3183 } 3184 3185 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts, 3186 u32 signal_free_time, struct cec_msg *msg) 3187 { 3188 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 3189 struct drm_device *dev = vc4_hdmi->connector.dev; 3190 unsigned long flags; 3191 u32 val; 3192 unsigned int i; 3193 int idx; 3194 3195 if (!drm_dev_enter(dev, &idx)) 3196 return -ENODEV; 3197 3198 if (msg->len > 16) { 3199 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len); 3200 drm_dev_exit(idx); 3201 return -ENOMEM; 3202 } 3203 3204 mutex_lock(&vc4_hdmi->mutex); 3205 3206 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 3207 3208 for (i = 0; i < msg->len; i += 4) 3209 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2), 3210 (msg->msg[i]) | 3211 (msg->msg[i + 1] << 8) | 3212 (msg->msg[i + 2] << 16) | 3213 (msg->msg[i + 3] << 24)); 3214 3215 val = HDMI_READ(HDMI_CEC_CNTRL_1); 3216 val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 3217 HDMI_WRITE(HDMI_CEC_CNTRL_1, val); 3218 val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK; 3219 val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT; 3220 val |= VC4_HDMI_CEC_START_XMIT_BEGIN; 3221 3222 HDMI_WRITE(HDMI_CEC_CNTRL_1, val); 3223 3224 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 3225 mutex_unlock(&vc4_hdmi->mutex); 3226 drm_dev_exit(idx); 3227 3228 return 0; 3229 } 3230 3231 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = { 3232 .adap_enable = vc4_hdmi_cec_adap_enable, 3233 .adap_log_addr = vc4_hdmi_cec_adap_log_addr, 3234 .adap_transmit = vc4_hdmi_cec_adap_transmit, 3235 }; 3236 3237 static void vc4_hdmi_cec_release(void *ptr) 3238 { 3239 struct vc4_hdmi *vc4_hdmi = ptr; 3240 3241 cec_unregister_adapter(vc4_hdmi->cec_adap); 3242 vc4_hdmi->cec_adap = NULL; 3243 } 3244 3245 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi) 3246 { 3247 struct cec_connector_info conn_info; 3248 struct platform_device *pdev = vc4_hdmi->pdev; 3249 struct device *dev = &pdev->dev; 3250 int ret; 3251 3252 if (!of_property_present(dev->of_node, "interrupts")) { 3253 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n"); 3254 return 0; 3255 } 3256 3257 vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops, 3258 vc4_hdmi, 3259 vc4_hdmi->variant->card_name, 3260 CEC_CAP_DEFAULTS | 3261 CEC_CAP_CONNECTOR_INFO, 1); 3262 ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap); 3263 if (ret < 0) 3264 return ret; 3265 3266 cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector); 3267 cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info); 3268 3269 if (vc4_hdmi->variant->external_irq_controller) { 3270 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-rx"), 3271 vc4_cec_irq_handler_rx_bare, 3272 vc4_cec_irq_handler_rx_thread, 0, 3273 "vc4 hdmi cec rx", vc4_hdmi); 3274 if (ret) 3275 goto err_delete_cec_adap; 3276 3277 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-tx"), 3278 vc4_cec_irq_handler_tx_bare, 3279 vc4_cec_irq_handler_tx_thread, 0, 3280 "vc4 hdmi cec tx", vc4_hdmi); 3281 if (ret) 3282 goto err_delete_cec_adap; 3283 } else { 3284 ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0), 3285 vc4_cec_irq_handler, 3286 vc4_cec_irq_handler_thread, 0, 3287 "vc4 hdmi cec", vc4_hdmi); 3288 if (ret) 3289 goto err_delete_cec_adap; 3290 } 3291 3292 ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev); 3293 if (ret < 0) 3294 goto err_delete_cec_adap; 3295 3296 /* 3297 * NOTE: Strictly speaking, we should probably use a DRM-managed 3298 * registration there to avoid removing the CEC adapter by the 3299 * time the DRM driver doesn't have any user anymore. 3300 * 3301 * However, the CEC framework already cleans up the CEC adapter 3302 * only when the last user has closed its file descriptor, so we 3303 * don't need to handle it in DRM. 3304 * 3305 * By the time the device-managed hook is executed, we will give 3306 * up our reference to the CEC adapter and therefore don't 3307 * really care when it's actually freed. 3308 * 3309 * There's still a problematic sequence: if we unregister our 3310 * CEC adapter, but the userspace keeps a handle on the CEC 3311 * adapter but not the DRM device for some reason. In such a 3312 * case, our vc4_hdmi structure will be freed, but the 3313 * cec_adapter structure will have a dangling pointer to what 3314 * used to be our HDMI controller. If we get a CEC call at that 3315 * moment, we could end up with a use-after-free. Fortunately, 3316 * the CEC framework already handles this too, by calling 3317 * cec_is_registered() in cec_ioctl() and cec_poll(). 3318 */ 3319 ret = devm_add_action_or_reset(dev, vc4_hdmi_cec_release, vc4_hdmi); 3320 if (ret) 3321 return ret; 3322 3323 return 0; 3324 3325 err_delete_cec_adap: 3326 cec_delete_adapter(vc4_hdmi->cec_adap); 3327 3328 return ret; 3329 } 3330 #else 3331 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi) 3332 { 3333 return 0; 3334 } 3335 #endif 3336 3337 static void vc4_hdmi_free_regset(struct drm_device *drm, void *ptr) 3338 { 3339 struct debugfs_reg32 *regs = ptr; 3340 3341 kfree(regs); 3342 } 3343 3344 static int vc4_hdmi_build_regset(struct drm_device *drm, 3345 struct vc4_hdmi *vc4_hdmi, 3346 struct debugfs_regset32 *regset, 3347 enum vc4_hdmi_regs reg) 3348 { 3349 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant; 3350 struct debugfs_reg32 *regs, *new_regs; 3351 unsigned int count = 0; 3352 unsigned int i; 3353 int ret; 3354 3355 regs = kcalloc(variant->num_registers, sizeof(*regs), 3356 GFP_KERNEL); 3357 if (!regs) 3358 return -ENOMEM; 3359 3360 for (i = 0; i < variant->num_registers; i++) { 3361 const struct vc4_hdmi_register *field = &variant->registers[i]; 3362 3363 if (field->reg != reg) 3364 continue; 3365 3366 regs[count].name = field->name; 3367 regs[count].offset = field->offset; 3368 count++; 3369 } 3370 3371 new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL); 3372 if (!new_regs) 3373 return -ENOMEM; 3374 3375 regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg); 3376 regset->regs = new_regs; 3377 regset->nregs = count; 3378 3379 ret = drmm_add_action_or_reset(drm, vc4_hdmi_free_regset, new_regs); 3380 if (ret) 3381 return ret; 3382 3383 return 0; 3384 } 3385 3386 static int vc4_hdmi_init_resources(struct drm_device *drm, 3387 struct vc4_hdmi *vc4_hdmi) 3388 { 3389 struct platform_device *pdev = vc4_hdmi->pdev; 3390 struct device *dev = &pdev->dev; 3391 int ret; 3392 3393 vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0); 3394 if (IS_ERR(vc4_hdmi->hdmicore_regs)) 3395 return PTR_ERR(vc4_hdmi->hdmicore_regs); 3396 3397 vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1); 3398 if (IS_ERR(vc4_hdmi->hd_regs)) 3399 return PTR_ERR(vc4_hdmi->hd_regs); 3400 3401 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD); 3402 if (ret) 3403 return ret; 3404 3405 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI); 3406 if (ret) 3407 return ret; 3408 3409 vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel"); 3410 if (IS_ERR(vc4_hdmi->pixel_clock)) { 3411 ret = PTR_ERR(vc4_hdmi->pixel_clock); 3412 if (ret != -EPROBE_DEFER) 3413 DRM_ERROR("Failed to get pixel clock\n"); 3414 return ret; 3415 } 3416 3417 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); 3418 if (IS_ERR(vc4_hdmi->hsm_clock)) { 3419 DRM_ERROR("Failed to get HDMI state machine clock\n"); 3420 return PTR_ERR(vc4_hdmi->hsm_clock); 3421 } 3422 vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock; 3423 vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock; 3424 3425 return 0; 3426 } 3427 3428 static int vc5_hdmi_init_resources(struct drm_device *drm, 3429 struct vc4_hdmi *vc4_hdmi) 3430 { 3431 struct platform_device *pdev = vc4_hdmi->pdev; 3432 struct device *dev = &pdev->dev; 3433 struct resource *res; 3434 int ret; 3435 3436 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi"); 3437 if (!res) 3438 return -ENODEV; 3439 3440 vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start, 3441 resource_size(res)); 3442 if (!vc4_hdmi->hdmicore_regs) 3443 return -ENOMEM; 3444 3445 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd"); 3446 if (!res) 3447 return -ENODEV; 3448 3449 vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res)); 3450 if (!vc4_hdmi->hd_regs) 3451 return -ENOMEM; 3452 3453 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec"); 3454 if (!res) 3455 return -ENODEV; 3456 3457 vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res)); 3458 if (!vc4_hdmi->cec_regs) 3459 return -ENOMEM; 3460 3461 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc"); 3462 if (!res) 3463 return -ENODEV; 3464 3465 vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res)); 3466 if (!vc4_hdmi->csc_regs) 3467 return -ENOMEM; 3468 3469 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp"); 3470 if (!res) 3471 return -ENODEV; 3472 3473 vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res)); 3474 if (!vc4_hdmi->dvp_regs) 3475 return -ENOMEM; 3476 3477 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy"); 3478 if (!res) 3479 return -ENODEV; 3480 3481 vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res)); 3482 if (!vc4_hdmi->phy_regs) 3483 return -ENOMEM; 3484 3485 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet"); 3486 if (!res) 3487 return -ENODEV; 3488 3489 vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res)); 3490 if (!vc4_hdmi->ram_regs) 3491 return -ENOMEM; 3492 3493 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm"); 3494 if (!res) 3495 return -ENODEV; 3496 3497 vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res)); 3498 if (!vc4_hdmi->rm_regs) 3499 return -ENOMEM; 3500 3501 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); 3502 if (IS_ERR(vc4_hdmi->hsm_clock)) { 3503 DRM_ERROR("Failed to get HDMI state machine clock\n"); 3504 return PTR_ERR(vc4_hdmi->hsm_clock); 3505 } 3506 3507 vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb"); 3508 if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) { 3509 DRM_ERROR("Failed to get pixel bvb clock\n"); 3510 return PTR_ERR(vc4_hdmi->pixel_bvb_clock); 3511 } 3512 3513 vc4_hdmi->audio_clock = devm_clk_get(dev, "audio"); 3514 if (IS_ERR(vc4_hdmi->audio_clock)) { 3515 DRM_ERROR("Failed to get audio clock\n"); 3516 return PTR_ERR(vc4_hdmi->audio_clock); 3517 } 3518 3519 vc4_hdmi->cec_clock = devm_clk_get(dev, "cec"); 3520 if (IS_ERR(vc4_hdmi->cec_clock)) { 3521 DRM_ERROR("Failed to get CEC clock\n"); 3522 return PTR_ERR(vc4_hdmi->cec_clock); 3523 } 3524 3525 vc4_hdmi->reset = devm_reset_control_get(dev, NULL); 3526 if (IS_ERR(vc4_hdmi->reset)) { 3527 DRM_ERROR("Failed to get HDMI reset line\n"); 3528 return PTR_ERR(vc4_hdmi->reset); 3529 } 3530 3531 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI); 3532 if (ret) 3533 return ret; 3534 3535 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD); 3536 if (ret) 3537 return ret; 3538 3539 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->cec_regset, VC5_CEC); 3540 if (ret) 3541 return ret; 3542 3543 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->csc_regset, VC5_CSC); 3544 if (ret) 3545 return ret; 3546 3547 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->dvp_regset, VC5_DVP); 3548 if (ret) 3549 return ret; 3550 3551 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->phy_regset, VC5_PHY); 3552 if (ret) 3553 return ret; 3554 3555 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->ram_regset, VC5_RAM); 3556 if (ret) 3557 return ret; 3558 3559 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->rm_regset, VC5_RM); 3560 if (ret) 3561 return ret; 3562 3563 return 0; 3564 } 3565 3566 static int vc4_hdmi_runtime_suspend(struct device *dev) 3567 { 3568 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 3569 3570 clk_disable_unprepare(vc4_hdmi->hsm_clock); 3571 3572 return 0; 3573 } 3574 3575 static int vc4_hdmi_runtime_resume(struct device *dev) 3576 { 3577 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 3578 unsigned long __maybe_unused flags; 3579 u32 __maybe_unused value; 3580 unsigned long rate; 3581 int ret; 3582 3583 ret = clk_prepare_enable(vc4_hdmi->hsm_clock); 3584 if (ret) 3585 return ret; 3586 3587 /* 3588 * Whenever the RaspberryPi boots without an HDMI monitor 3589 * plugged in, the firmware won't have initialized the HSM clock 3590 * rate and it will be reported as 0. 3591 * 3592 * If we try to access a register of the controller in such a 3593 * case, it will lead to a silent CPU stall. Let's make sure we 3594 * prevent such a case. 3595 */ 3596 rate = clk_get_rate(vc4_hdmi->hsm_clock); 3597 if (!rate) { 3598 ret = -EINVAL; 3599 goto err_disable_clk; 3600 } 3601 3602 if (vc4_hdmi->variant->reset) 3603 vc4_hdmi->variant->reset(vc4_hdmi); 3604 3605 #ifdef CONFIG_DRM_VC4_HDMI_CEC 3606 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 3607 value = HDMI_READ(HDMI_CEC_CNTRL_1); 3608 /* Set the logical address to Unregistered */ 3609 value |= VC4_HDMI_CEC_ADDR_MASK; 3610 HDMI_WRITE(HDMI_CEC_CNTRL_1, value); 3611 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 3612 3613 vc4_hdmi_cec_update_clk_div(vc4_hdmi); 3614 3615 if (!vc4_hdmi->variant->external_irq_controller) { 3616 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 3617 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff); 3618 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 3619 } 3620 #endif 3621 3622 return 0; 3623 3624 err_disable_clk: 3625 clk_disable_unprepare(vc4_hdmi->hsm_clock); 3626 return ret; 3627 } 3628 3629 static void vc4_hdmi_put_ddc_device(void *ptr) 3630 { 3631 struct vc4_hdmi *vc4_hdmi = ptr; 3632 3633 put_device(&vc4_hdmi->ddc->dev); 3634 } 3635 3636 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data) 3637 { 3638 const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev); 3639 struct platform_device *pdev = to_platform_device(dev); 3640 struct drm_device *drm = dev_get_drvdata(master); 3641 struct vc4_hdmi *vc4_hdmi; 3642 struct drm_encoder *encoder; 3643 struct device_node *ddc_node; 3644 int ret; 3645 3646 vc4_hdmi = drmm_kzalloc(drm, sizeof(*vc4_hdmi), GFP_KERNEL); 3647 if (!vc4_hdmi) 3648 return -ENOMEM; 3649 3650 ret = drmm_mutex_init(drm, &vc4_hdmi->mutex); 3651 if (ret) 3652 return ret; 3653 3654 spin_lock_init(&vc4_hdmi->hw_lock); 3655 INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq); 3656 3657 dev_set_drvdata(dev, vc4_hdmi); 3658 encoder = &vc4_hdmi->encoder.base; 3659 vc4_hdmi->encoder.type = variant->encoder_type; 3660 vc4_hdmi->encoder.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure; 3661 vc4_hdmi->encoder.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable; 3662 vc4_hdmi->encoder.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable; 3663 vc4_hdmi->encoder.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable; 3664 vc4_hdmi->encoder.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown; 3665 vc4_hdmi->pdev = pdev; 3666 vc4_hdmi->variant = variant; 3667 3668 /* 3669 * Since we don't know the state of the controller and its 3670 * display (if any), let's assume it's always enabled. 3671 * vc4_hdmi_disable_scrambling() will thus run at boot, make 3672 * sure it's disabled, and avoid any inconsistency. 3673 */ 3674 if (variant->max_pixel_clock > HDMI_14_MAX_TMDS_CLK) 3675 vc4_hdmi->scdc_enabled = true; 3676 3677 ret = variant->init_resources(drm, vc4_hdmi); 3678 if (ret) 3679 return ret; 3680 3681 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0); 3682 if (!ddc_node) { 3683 DRM_ERROR("Failed to find ddc node in device tree\n"); 3684 return -ENODEV; 3685 } 3686 3687 vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node); 3688 of_node_put(ddc_node); 3689 if (!vc4_hdmi->ddc) { 3690 DRM_DEBUG("Failed to get ddc i2c adapter by node\n"); 3691 return -EPROBE_DEFER; 3692 } 3693 3694 ret = devm_add_action_or_reset(dev, vc4_hdmi_put_ddc_device, vc4_hdmi); 3695 if (ret) 3696 return ret; 3697 3698 /* Only use the GPIO HPD pin if present in the DT, otherwise 3699 * we'll use the HDMI core's register. 3700 */ 3701 vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN); 3702 if (IS_ERR(vc4_hdmi->hpd_gpio)) { 3703 return PTR_ERR(vc4_hdmi->hpd_gpio); 3704 } 3705 3706 vc4_hdmi->disable_wifi_frequencies = 3707 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence"); 3708 3709 ret = devm_pm_runtime_enable(dev); 3710 if (ret) 3711 return ret; 3712 3713 /* 3714 * We need to have the device powered up at this point to call 3715 * our reset hook and for the CEC init. 3716 */ 3717 ret = pm_runtime_resume_and_get(dev); 3718 if (ret) 3719 return ret; 3720 3721 if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") || 3722 of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1")) && 3723 HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) { 3724 clk_prepare_enable(vc4_hdmi->pixel_clock); 3725 clk_prepare_enable(vc4_hdmi->hsm_clock); 3726 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock); 3727 } 3728 3729 ret = drmm_encoder_init(drm, encoder, 3730 &vc4_hdmi_encoder_funcs, 3731 DRM_MODE_ENCODER_TMDS, 3732 NULL); 3733 if (ret) 3734 goto err_put_runtime_pm; 3735 3736 drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs); 3737 3738 ret = vc4_hdmi_connector_init(drm, vc4_hdmi); 3739 if (ret) 3740 goto err_put_runtime_pm; 3741 3742 ret = vc4_hdmi_hotplug_init(vc4_hdmi); 3743 if (ret) 3744 goto err_put_runtime_pm; 3745 3746 ret = vc4_hdmi_cec_init(vc4_hdmi); 3747 if (ret) 3748 goto err_put_runtime_pm; 3749 3750 ret = vc4_hdmi_audio_init(vc4_hdmi); 3751 if (ret) 3752 goto err_put_runtime_pm; 3753 3754 pm_runtime_put_sync(dev); 3755 3756 return 0; 3757 3758 err_put_runtime_pm: 3759 pm_runtime_put_sync(dev); 3760 3761 return ret; 3762 } 3763 3764 static const struct component_ops vc4_hdmi_ops = { 3765 .bind = vc4_hdmi_bind, 3766 }; 3767 3768 static int vc4_hdmi_dev_probe(struct platform_device *pdev) 3769 { 3770 return component_add(&pdev->dev, &vc4_hdmi_ops); 3771 } 3772 3773 static int vc4_hdmi_dev_remove(struct platform_device *pdev) 3774 { 3775 component_del(&pdev->dev, &vc4_hdmi_ops); 3776 return 0; 3777 } 3778 3779 static const struct vc4_hdmi_variant bcm2835_variant = { 3780 .encoder_type = VC4_ENCODER_TYPE_HDMI0, 3781 .debugfs_name = "hdmi_regs", 3782 .card_name = "vc4-hdmi", 3783 .max_pixel_clock = 162000000, 3784 .registers = vc4_hdmi_fields, 3785 .num_registers = ARRAY_SIZE(vc4_hdmi_fields), 3786 3787 .init_resources = vc4_hdmi_init_resources, 3788 .csc_setup = vc4_hdmi_csc_setup, 3789 .reset = vc4_hdmi_reset, 3790 .set_timings = vc4_hdmi_set_timings, 3791 .phy_init = vc4_hdmi_phy_init, 3792 .phy_disable = vc4_hdmi_phy_disable, 3793 .phy_rng_enable = vc4_hdmi_phy_rng_enable, 3794 .phy_rng_disable = vc4_hdmi_phy_rng_disable, 3795 .channel_map = vc4_hdmi_channel_map, 3796 .supports_hdr = false, 3797 }; 3798 3799 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = { 3800 .encoder_type = VC4_ENCODER_TYPE_HDMI0, 3801 .debugfs_name = "hdmi0_regs", 3802 .card_name = "vc4-hdmi-0", 3803 .max_pixel_clock = 600000000, 3804 .registers = vc5_hdmi_hdmi0_fields, 3805 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi0_fields), 3806 .phy_lane_mapping = { 3807 PHY_LANE_0, 3808 PHY_LANE_1, 3809 PHY_LANE_2, 3810 PHY_LANE_CK, 3811 }, 3812 .unsupported_odd_h_timings = true, 3813 .external_irq_controller = true, 3814 3815 .init_resources = vc5_hdmi_init_resources, 3816 .csc_setup = vc5_hdmi_csc_setup, 3817 .reset = vc5_hdmi_reset, 3818 .set_timings = vc5_hdmi_set_timings, 3819 .phy_init = vc5_hdmi_phy_init, 3820 .phy_disable = vc5_hdmi_phy_disable, 3821 .phy_rng_enable = vc5_hdmi_phy_rng_enable, 3822 .phy_rng_disable = vc5_hdmi_phy_rng_disable, 3823 .channel_map = vc5_hdmi_channel_map, 3824 .supports_hdr = true, 3825 .hp_detect = vc5_hdmi_hp_detect, 3826 }; 3827 3828 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = { 3829 .encoder_type = VC4_ENCODER_TYPE_HDMI1, 3830 .debugfs_name = "hdmi1_regs", 3831 .card_name = "vc4-hdmi-1", 3832 .max_pixel_clock = HDMI_14_MAX_TMDS_CLK, 3833 .registers = vc5_hdmi_hdmi1_fields, 3834 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi1_fields), 3835 .phy_lane_mapping = { 3836 PHY_LANE_1, 3837 PHY_LANE_0, 3838 PHY_LANE_CK, 3839 PHY_LANE_2, 3840 }, 3841 .unsupported_odd_h_timings = true, 3842 .external_irq_controller = true, 3843 3844 .init_resources = vc5_hdmi_init_resources, 3845 .csc_setup = vc5_hdmi_csc_setup, 3846 .reset = vc5_hdmi_reset, 3847 .set_timings = vc5_hdmi_set_timings, 3848 .phy_init = vc5_hdmi_phy_init, 3849 .phy_disable = vc5_hdmi_phy_disable, 3850 .phy_rng_enable = vc5_hdmi_phy_rng_enable, 3851 .phy_rng_disable = vc5_hdmi_phy_rng_disable, 3852 .channel_map = vc5_hdmi_channel_map, 3853 .supports_hdr = true, 3854 .hp_detect = vc5_hdmi_hp_detect, 3855 }; 3856 3857 static const struct of_device_id vc4_hdmi_dt_match[] = { 3858 { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant }, 3859 { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant }, 3860 { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant }, 3861 {} 3862 }; 3863 3864 static const struct dev_pm_ops vc4_hdmi_pm_ops = { 3865 SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend, 3866 vc4_hdmi_runtime_resume, 3867 NULL) 3868 }; 3869 3870 struct platform_driver vc4_hdmi_driver = { 3871 .probe = vc4_hdmi_dev_probe, 3872 .remove = vc4_hdmi_dev_remove, 3873 .driver = { 3874 .name = "vc4_hdmi", 3875 .of_match_table = vc4_hdmi_dt_match, 3876 .pm = &vc4_hdmi_pm_ops, 3877 }, 3878 }; 3879