1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 Broadcom 4 * Copyright (c) 2014 The Linux Foundation. All rights reserved. 5 * Copyright (C) 2013 Red Hat 6 * Author: Rob Clark <robdclark@gmail.com> 7 */ 8 9 /** 10 * DOC: VC4 Falcon HDMI module 11 * 12 * The HDMI core has a state machine and a PHY. On BCM2835, most of 13 * the unit operates off of the HSM clock from CPRMAN. It also 14 * internally uses the PLLH_PIX clock for the PHY. 15 * 16 * HDMI infoframes are kept within a small packet ram, where each 17 * packet can be individually enabled for including in a frame. 18 * 19 * HDMI audio is implemented entirely within the HDMI IP block. A 20 * register in the HDMI encoder takes SPDIF frames from the DMA engine 21 * and transfers them over an internal MAI (multi-channel audio 22 * interconnect) bus to the encoder side for insertion into the video 23 * blank regions. 24 * 25 * The driver's HDMI encoder does not yet support power management. 26 * The HDMI encoder's power domain and the HSM/pixel clocks are kept 27 * continuously running, and only the HDMI logic and packet ram are 28 * powered off/on at disable/enable time. 29 * 30 * The driver does not yet support CEC control, though the HDMI 31 * encoder block has CEC support. 32 */ 33 34 #include <drm/drm_atomic_helper.h> 35 #include <drm/drm_edid.h> 36 #include <drm/drm_probe_helper.h> 37 #include <drm/drm_simple_kms_helper.h> 38 #include <drm/drm_scdc_helper.h> 39 #include <linux/clk.h> 40 #include <linux/component.h> 41 #include <linux/i2c.h> 42 #include <linux/of_address.h> 43 #include <linux/of_gpio.h> 44 #include <linux/of_platform.h> 45 #include <linux/pm_runtime.h> 46 #include <linux/rational.h> 47 #include <linux/reset.h> 48 #include <sound/dmaengine_pcm.h> 49 #include <sound/hdmi-codec.h> 50 #include <sound/pcm_drm_eld.h> 51 #include <sound/pcm_params.h> 52 #include <sound/soc.h> 53 #include "media/cec.h" 54 #include "vc4_drv.h" 55 #include "vc4_hdmi.h" 56 #include "vc4_hdmi_regs.h" 57 #include "vc4_regs.h" 58 59 #define VC5_HDMI_HORZA_HFP_SHIFT 16 60 #define VC5_HDMI_HORZA_HFP_MASK VC4_MASK(28, 16) 61 #define VC5_HDMI_HORZA_VPOS BIT(15) 62 #define VC5_HDMI_HORZA_HPOS BIT(14) 63 #define VC5_HDMI_HORZA_HAP_SHIFT 0 64 #define VC5_HDMI_HORZA_HAP_MASK VC4_MASK(13, 0) 65 66 #define VC5_HDMI_HORZB_HBP_SHIFT 16 67 #define VC5_HDMI_HORZB_HBP_MASK VC4_MASK(26, 16) 68 #define VC5_HDMI_HORZB_HSP_SHIFT 0 69 #define VC5_HDMI_HORZB_HSP_MASK VC4_MASK(10, 0) 70 71 #define VC5_HDMI_VERTA_VSP_SHIFT 24 72 #define VC5_HDMI_VERTA_VSP_MASK VC4_MASK(28, 24) 73 #define VC5_HDMI_VERTA_VFP_SHIFT 16 74 #define VC5_HDMI_VERTA_VFP_MASK VC4_MASK(22, 16) 75 #define VC5_HDMI_VERTA_VAL_SHIFT 0 76 #define VC5_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0) 77 78 #define VC5_HDMI_VERTB_VSPO_SHIFT 16 79 #define VC5_HDMI_VERTB_VSPO_MASK VC4_MASK(29, 16) 80 81 #define VC5_HDMI_SCRAMBLER_CTL_ENABLE BIT(0) 82 83 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT 8 84 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK VC4_MASK(10, 8) 85 86 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT 0 87 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK VC4_MASK(3, 0) 88 89 #define VC5_HDMI_GCP_CONFIG_GCP_ENABLE BIT(31) 90 91 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT 8 92 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK VC4_MASK(15, 8) 93 94 # define VC4_HD_M_SW_RST BIT(2) 95 # define VC4_HD_M_ENABLE BIT(0) 96 97 #define HSM_MIN_CLOCK_FREQ 120000000 98 #define CEC_CLOCK_FREQ 40000 99 100 #define HDMI_14_MAX_TMDS_CLK (340 * 1000 * 1000) 101 102 static const char * const output_format_str[] = { 103 [VC4_HDMI_OUTPUT_RGB] = "RGB", 104 [VC4_HDMI_OUTPUT_YUV420] = "YUV 4:2:0", 105 [VC4_HDMI_OUTPUT_YUV422] = "YUV 4:2:2", 106 [VC4_HDMI_OUTPUT_YUV444] = "YUV 4:4:4", 107 }; 108 109 static const char *vc4_hdmi_output_fmt_str(enum vc4_hdmi_output_format fmt) 110 { 111 if (fmt >= ARRAY_SIZE(output_format_str)) 112 return "invalid"; 113 114 return output_format_str[fmt]; 115 } 116 117 static unsigned long long 118 vc4_hdmi_encoder_compute_mode_clock(const struct drm_display_mode *mode, 119 unsigned int bpc, enum vc4_hdmi_output_format fmt); 120 121 static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode, 122 unsigned int bpc, 123 enum vc4_hdmi_output_format fmt) 124 { 125 unsigned long long clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc, fmt); 126 127 return clock > HDMI_14_MAX_TMDS_CLK; 128 } 129 130 static bool vc4_hdmi_is_full_range_rgb(struct vc4_hdmi *vc4_hdmi, 131 const struct drm_display_mode *mode) 132 { 133 struct vc4_hdmi_encoder *vc4_encoder = &vc4_hdmi->encoder; 134 135 return !vc4_encoder->hdmi_monitor || 136 drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_FULL; 137 } 138 139 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused) 140 { 141 struct drm_info_node *node = (struct drm_info_node *)m->private; 142 struct vc4_hdmi *vc4_hdmi = node->info_ent->data; 143 struct drm_printer p = drm_seq_file_printer(m); 144 145 drm_print_regset32(&p, &vc4_hdmi->hdmi_regset); 146 drm_print_regset32(&p, &vc4_hdmi->hd_regset); 147 148 return 0; 149 } 150 151 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi) 152 { 153 unsigned long flags; 154 155 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 156 157 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST); 158 udelay(1); 159 HDMI_WRITE(HDMI_M_CTL, 0); 160 161 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE); 162 163 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 164 VC4_HDMI_SW_RESET_HDMI | 165 VC4_HDMI_SW_RESET_FORMAT_DETECT); 166 167 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0); 168 169 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 170 } 171 172 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi) 173 { 174 unsigned long flags; 175 176 reset_control_reset(vc4_hdmi->reset); 177 178 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 179 180 HDMI_WRITE(HDMI_DVP_CTL, 0); 181 182 HDMI_WRITE(HDMI_CLOCK_STOP, 183 HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL); 184 185 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 186 } 187 188 #ifdef CONFIG_DRM_VC4_HDMI_CEC 189 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) 190 { 191 unsigned long cec_rate = clk_get_rate(vc4_hdmi->cec_clock); 192 unsigned long flags; 193 u16 clk_cnt; 194 u32 value; 195 196 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 197 198 value = HDMI_READ(HDMI_CEC_CNTRL_1); 199 value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK; 200 201 /* 202 * Set the clock divider: the hsm_clock rate and this divider 203 * setting will give a 40 kHz CEC clock. 204 */ 205 clk_cnt = cec_rate / CEC_CLOCK_FREQ; 206 value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT; 207 HDMI_WRITE(HDMI_CEC_CNTRL_1, value); 208 209 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 210 } 211 #else 212 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {} 213 #endif 214 215 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder); 216 217 static enum drm_connector_status 218 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force) 219 { 220 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 221 bool connected = false; 222 223 mutex_lock(&vc4_hdmi->mutex); 224 225 WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev)); 226 227 if (vc4_hdmi->hpd_gpio) { 228 if (gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio)) 229 connected = true; 230 } else { 231 unsigned long flags; 232 u32 hotplug; 233 234 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 235 hotplug = HDMI_READ(HDMI_HOTPLUG); 236 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 237 238 if (hotplug & VC4_HDMI_HOTPLUG_CONNECTED) 239 connected = true; 240 } 241 242 if (connected) { 243 if (connector->status != connector_status_connected) { 244 struct edid *edid = drm_get_edid(connector, vc4_hdmi->ddc); 245 246 if (edid) { 247 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid); 248 vc4_hdmi->encoder.hdmi_monitor = drm_detect_hdmi_monitor(edid); 249 kfree(edid); 250 } 251 } 252 253 vc4_hdmi_enable_scrambling(&vc4_hdmi->encoder.base.base); 254 pm_runtime_put(&vc4_hdmi->pdev->dev); 255 mutex_unlock(&vc4_hdmi->mutex); 256 return connector_status_connected; 257 } 258 259 cec_phys_addr_invalidate(vc4_hdmi->cec_adap); 260 pm_runtime_put(&vc4_hdmi->pdev->dev); 261 mutex_unlock(&vc4_hdmi->mutex); 262 return connector_status_disconnected; 263 } 264 265 static void vc4_hdmi_connector_destroy(struct drm_connector *connector) 266 { 267 drm_connector_unregister(connector); 268 drm_connector_cleanup(connector); 269 } 270 271 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector) 272 { 273 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 274 struct vc4_hdmi_encoder *vc4_encoder = &vc4_hdmi->encoder; 275 int ret = 0; 276 struct edid *edid; 277 278 mutex_lock(&vc4_hdmi->mutex); 279 280 edid = drm_get_edid(connector, vc4_hdmi->ddc); 281 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid); 282 if (!edid) { 283 ret = -ENODEV; 284 goto out; 285 } 286 287 vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid); 288 289 drm_connector_update_edid_property(connector, edid); 290 ret = drm_add_edid_modes(connector, edid); 291 kfree(edid); 292 293 if (vc4_hdmi->disable_4kp60) { 294 struct drm_device *drm = connector->dev; 295 struct drm_display_mode *mode; 296 297 list_for_each_entry(mode, &connector->probed_modes, head) { 298 if (vc4_hdmi_mode_needs_scrambling(mode, 8, VC4_HDMI_OUTPUT_RGB)) { 299 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz."); 300 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60."); 301 } 302 } 303 } 304 305 out: 306 mutex_unlock(&vc4_hdmi->mutex); 307 308 return ret; 309 } 310 311 static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector, 312 struct drm_atomic_state *state) 313 { 314 struct drm_connector_state *old_state = 315 drm_atomic_get_old_connector_state(state, connector); 316 struct drm_connector_state *new_state = 317 drm_atomic_get_new_connector_state(state, connector); 318 struct drm_crtc *crtc = new_state->crtc; 319 320 if (!crtc) 321 return 0; 322 323 if (old_state->colorspace != new_state->colorspace || 324 !drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) { 325 struct drm_crtc_state *crtc_state; 326 327 crtc_state = drm_atomic_get_crtc_state(state, crtc); 328 if (IS_ERR(crtc_state)) 329 return PTR_ERR(crtc_state); 330 331 crtc_state->mode_changed = true; 332 } 333 334 return 0; 335 } 336 337 static void vc4_hdmi_connector_reset(struct drm_connector *connector) 338 { 339 struct vc4_hdmi_connector_state *old_state = 340 conn_state_to_vc4_hdmi_conn_state(connector->state); 341 struct vc4_hdmi_connector_state *new_state = 342 kzalloc(sizeof(*new_state), GFP_KERNEL); 343 344 if (connector->state) 345 __drm_atomic_helper_connector_destroy_state(connector->state); 346 347 kfree(old_state); 348 __drm_atomic_helper_connector_reset(connector, &new_state->base); 349 350 if (!new_state) 351 return; 352 353 new_state->base.max_bpc = 8; 354 new_state->base.max_requested_bpc = 8; 355 new_state->output_format = VC4_HDMI_OUTPUT_RGB; 356 drm_atomic_helper_connector_tv_reset(connector); 357 } 358 359 static struct drm_connector_state * 360 vc4_hdmi_connector_duplicate_state(struct drm_connector *connector) 361 { 362 struct drm_connector_state *conn_state = connector->state; 363 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state); 364 struct vc4_hdmi_connector_state *new_state; 365 366 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL); 367 if (!new_state) 368 return NULL; 369 370 new_state->tmds_char_rate = vc4_state->tmds_char_rate; 371 new_state->output_bpc = vc4_state->output_bpc; 372 new_state->output_format = vc4_state->output_format; 373 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base); 374 375 return &new_state->base; 376 } 377 378 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = { 379 .detect = vc4_hdmi_connector_detect, 380 .fill_modes = drm_helper_probe_single_connector_modes, 381 .destroy = vc4_hdmi_connector_destroy, 382 .reset = vc4_hdmi_connector_reset, 383 .atomic_duplicate_state = vc4_hdmi_connector_duplicate_state, 384 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 385 }; 386 387 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = { 388 .get_modes = vc4_hdmi_connector_get_modes, 389 .atomic_check = vc4_hdmi_connector_atomic_check, 390 }; 391 392 static int vc4_hdmi_connector_init(struct drm_device *dev, 393 struct vc4_hdmi *vc4_hdmi) 394 { 395 struct drm_connector *connector = &vc4_hdmi->connector; 396 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base; 397 int ret; 398 399 drm_connector_init_with_ddc(dev, connector, 400 &vc4_hdmi_connector_funcs, 401 DRM_MODE_CONNECTOR_HDMIA, 402 vc4_hdmi->ddc); 403 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs); 404 405 /* 406 * Some of the properties below require access to state, like bpc. 407 * Allocate some default initial connector state with our reset helper. 408 */ 409 if (connector->funcs->reset) 410 connector->funcs->reset(connector); 411 412 /* Create and attach TV margin props to this connector. */ 413 ret = drm_mode_create_tv_margin_properties(dev); 414 if (ret) 415 return ret; 416 417 ret = drm_mode_create_hdmi_colorspace_property(connector); 418 if (ret) 419 return ret; 420 421 drm_connector_attach_colorspace_property(connector); 422 drm_connector_attach_tv_margin_properties(connector); 423 drm_connector_attach_max_bpc_property(connector, 8, 12); 424 425 connector->polled = (DRM_CONNECTOR_POLL_CONNECT | 426 DRM_CONNECTOR_POLL_DISCONNECT); 427 428 connector->interlace_allowed = 1; 429 connector->doublescan_allowed = 0; 430 431 if (vc4_hdmi->variant->supports_hdr) 432 drm_connector_attach_hdr_output_metadata_property(connector); 433 434 drm_connector_attach_encoder(connector, encoder); 435 436 return 0; 437 } 438 439 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder, 440 enum hdmi_infoframe_type type, 441 bool poll) 442 { 443 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 444 u32 packet_id = type - 0x80; 445 unsigned long flags; 446 447 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 448 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 449 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id)); 450 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 451 452 if (!poll) 453 return 0; 454 455 return wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) & 456 BIT(packet_id)), 100); 457 } 458 459 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder, 460 union hdmi_infoframe *frame) 461 { 462 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 463 u32 packet_id = frame->any.type - 0x80; 464 const struct vc4_hdmi_register *ram_packet_start = 465 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START]; 466 u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id; 467 void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi, 468 ram_packet_start->reg); 469 uint8_t buffer[VC4_HDMI_PACKET_STRIDE]; 470 unsigned long flags; 471 ssize_t len, i; 472 int ret; 473 474 WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) & 475 VC4_HDMI_RAM_PACKET_ENABLE), 476 "Packet RAM has to be on to store the packet."); 477 478 len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer)); 479 if (len < 0) 480 return; 481 482 ret = vc4_hdmi_stop_packet(encoder, frame->any.type, true); 483 if (ret) { 484 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret); 485 return; 486 } 487 488 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 489 490 for (i = 0; i < len; i += 7) { 491 writel(buffer[i + 0] << 0 | 492 buffer[i + 1] << 8 | 493 buffer[i + 2] << 16, 494 base + packet_reg); 495 packet_reg += 4; 496 497 writel(buffer[i + 3] << 0 | 498 buffer[i + 4] << 8 | 499 buffer[i + 5] << 16 | 500 buffer[i + 6] << 24, 501 base + packet_reg); 502 packet_reg += 4; 503 } 504 505 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 506 HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id)); 507 508 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 509 510 ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) & 511 BIT(packet_id)), 100); 512 if (ret) 513 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret); 514 } 515 516 static void vc4_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame, 517 enum vc4_hdmi_output_format fmt) 518 { 519 switch (fmt) { 520 case VC4_HDMI_OUTPUT_RGB: 521 frame->colorspace = HDMI_COLORSPACE_RGB; 522 break; 523 524 case VC4_HDMI_OUTPUT_YUV420: 525 frame->colorspace = HDMI_COLORSPACE_YUV420; 526 break; 527 528 case VC4_HDMI_OUTPUT_YUV422: 529 frame->colorspace = HDMI_COLORSPACE_YUV422; 530 break; 531 532 case VC4_HDMI_OUTPUT_YUV444: 533 frame->colorspace = HDMI_COLORSPACE_YUV444; 534 break; 535 536 default: 537 break; 538 } 539 } 540 541 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder) 542 { 543 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 544 struct drm_connector *connector = &vc4_hdmi->connector; 545 struct drm_connector_state *cstate = connector->state; 546 struct vc4_hdmi_connector_state *vc4_state = 547 conn_state_to_vc4_hdmi_conn_state(cstate); 548 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 549 union hdmi_infoframe frame; 550 int ret; 551 552 lockdep_assert_held(&vc4_hdmi->mutex); 553 554 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, 555 connector, mode); 556 if (ret < 0) { 557 DRM_ERROR("couldn't fill AVI infoframe\n"); 558 return; 559 } 560 561 drm_hdmi_avi_infoframe_quant_range(&frame.avi, 562 connector, mode, 563 vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode) ? 564 HDMI_QUANTIZATION_RANGE_FULL : 565 HDMI_QUANTIZATION_RANGE_LIMITED); 566 drm_hdmi_avi_infoframe_colorimetry(&frame.avi, cstate); 567 vc4_hdmi_avi_infoframe_colorspace(&frame.avi, vc4_state->output_format); 568 drm_hdmi_avi_infoframe_bars(&frame.avi, cstate); 569 570 vc4_hdmi_write_infoframe(encoder, &frame); 571 } 572 573 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder) 574 { 575 union hdmi_infoframe frame; 576 int ret; 577 578 ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore"); 579 if (ret < 0) { 580 DRM_ERROR("couldn't fill SPD infoframe\n"); 581 return; 582 } 583 584 frame.spd.sdi = HDMI_SPD_SDI_PC; 585 586 vc4_hdmi_write_infoframe(encoder, &frame); 587 } 588 589 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder) 590 { 591 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 592 struct hdmi_audio_infoframe *audio = &vc4_hdmi->audio.infoframe; 593 union hdmi_infoframe frame; 594 595 memcpy(&frame.audio, audio, sizeof(*audio)); 596 vc4_hdmi_write_infoframe(encoder, &frame); 597 } 598 599 static void vc4_hdmi_set_hdr_infoframe(struct drm_encoder *encoder) 600 { 601 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 602 struct drm_connector *connector = &vc4_hdmi->connector; 603 struct drm_connector_state *conn_state = connector->state; 604 union hdmi_infoframe frame; 605 606 lockdep_assert_held(&vc4_hdmi->mutex); 607 608 if (!vc4_hdmi->variant->supports_hdr) 609 return; 610 611 if (!conn_state->hdr_output_metadata) 612 return; 613 614 if (drm_hdmi_infoframe_set_hdr_metadata(&frame.drm, conn_state)) 615 return; 616 617 vc4_hdmi_write_infoframe(encoder, &frame); 618 } 619 620 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder) 621 { 622 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 623 624 lockdep_assert_held(&vc4_hdmi->mutex); 625 626 vc4_hdmi_set_avi_infoframe(encoder); 627 vc4_hdmi_set_spd_infoframe(encoder); 628 /* 629 * If audio was streaming, then we need to reenabled the audio 630 * infoframe here during encoder_enable. 631 */ 632 if (vc4_hdmi->audio.streaming) 633 vc4_hdmi_set_audio_infoframe(encoder); 634 635 vc4_hdmi_set_hdr_infoframe(encoder); 636 } 637 638 static bool vc4_hdmi_supports_scrambling(struct drm_encoder *encoder, 639 struct drm_display_mode *mode) 640 { 641 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 642 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 643 struct drm_display_info *display = &vc4_hdmi->connector.display_info; 644 645 lockdep_assert_held(&vc4_hdmi->mutex); 646 647 if (!vc4_encoder->hdmi_monitor) 648 return false; 649 650 if (!display->hdmi.scdc.supported || 651 !display->hdmi.scdc.scrambling.supported) 652 return false; 653 654 return true; 655 } 656 657 #define SCRAMBLING_POLLING_DELAY_MS 1000 658 659 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder) 660 { 661 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 662 struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 663 unsigned long flags; 664 665 lockdep_assert_held(&vc4_hdmi->mutex); 666 667 if (!vc4_hdmi_supports_scrambling(encoder, mode)) 668 return; 669 670 if (!vc4_hdmi_mode_needs_scrambling(mode, 671 vc4_hdmi->output_bpc, 672 vc4_hdmi->output_format)) 673 return; 674 675 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true); 676 drm_scdc_set_scrambling(vc4_hdmi->ddc, true); 677 678 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 679 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) | 680 VC5_HDMI_SCRAMBLER_CTL_ENABLE); 681 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 682 683 vc4_hdmi->scdc_enabled = true; 684 685 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work, 686 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS)); 687 } 688 689 static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder) 690 { 691 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 692 unsigned long flags; 693 694 lockdep_assert_held(&vc4_hdmi->mutex); 695 696 if (!vc4_hdmi->scdc_enabled) 697 return; 698 699 vc4_hdmi->scdc_enabled = false; 700 701 if (delayed_work_pending(&vc4_hdmi->scrambling_work)) 702 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work); 703 704 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 705 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) & 706 ~VC5_HDMI_SCRAMBLER_CTL_ENABLE); 707 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 708 709 drm_scdc_set_scrambling(vc4_hdmi->ddc, false); 710 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, false); 711 } 712 713 static void vc4_hdmi_scrambling_wq(struct work_struct *work) 714 { 715 struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work), 716 struct vc4_hdmi, 717 scrambling_work); 718 719 if (drm_scdc_get_scrambling_status(vc4_hdmi->ddc)) 720 return; 721 722 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true); 723 drm_scdc_set_scrambling(vc4_hdmi->ddc, true); 724 725 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work, 726 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS)); 727 } 728 729 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder, 730 struct drm_atomic_state *state) 731 { 732 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 733 unsigned long flags; 734 735 mutex_lock(&vc4_hdmi->mutex); 736 737 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 738 739 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0); 740 741 HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB); 742 743 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 744 745 mdelay(1); 746 747 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 748 HDMI_WRITE(HDMI_VID_CTL, 749 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE); 750 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 751 752 vc4_hdmi_disable_scrambling(encoder); 753 754 mutex_unlock(&vc4_hdmi->mutex); 755 } 756 757 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder, 758 struct drm_atomic_state *state) 759 { 760 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 761 unsigned long flags; 762 int ret; 763 764 mutex_lock(&vc4_hdmi->mutex); 765 766 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 767 HDMI_WRITE(HDMI_VID_CTL, 768 HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX); 769 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 770 771 if (vc4_hdmi->variant->phy_disable) 772 vc4_hdmi->variant->phy_disable(vc4_hdmi); 773 774 clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock); 775 clk_disable_unprepare(vc4_hdmi->pixel_clock); 776 777 ret = pm_runtime_put(&vc4_hdmi->pdev->dev); 778 if (ret < 0) 779 DRM_ERROR("Failed to release power domain: %d\n", ret); 780 781 mutex_unlock(&vc4_hdmi->mutex); 782 } 783 784 static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder) 785 { 786 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 787 788 mutex_lock(&vc4_hdmi->mutex); 789 vc4_hdmi->output_enabled = false; 790 mutex_unlock(&vc4_hdmi->mutex); 791 } 792 793 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, 794 struct drm_connector_state *state, 795 const struct drm_display_mode *mode) 796 { 797 unsigned long flags; 798 u32 csc_ctl; 799 800 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 801 802 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR, 803 VC4_HD_CSC_CTL_ORDER); 804 805 if (!vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode)) { 806 /* CEA VICs other than #1 requre limited range RGB 807 * output unless overridden by an AVI infoframe. 808 * Apply a colorspace conversion to squash 0-255 down 809 * to 16-235. The matrix here is: 810 * 811 * [ 0 0 0.8594 16] 812 * [ 0 0.8594 0 16] 813 * [ 0.8594 0 0 16] 814 * [ 0 0 0 1] 815 */ 816 csc_ctl |= VC4_HD_CSC_CTL_ENABLE; 817 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC; 818 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM, 819 VC4_HD_CSC_CTL_MODE); 820 821 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000); 822 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0); 823 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000); 824 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000); 825 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0); 826 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000); 827 } 828 829 /* The RGB order applies even when CSC is disabled. */ 830 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl); 831 832 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 833 } 834 835 /* 836 * If we need to output Full Range RGB, then use the unity matrix 837 * 838 * [ 1 0 0 0] 839 * [ 0 1 0 0] 840 * [ 0 0 1 0] 841 * 842 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets 843 */ 844 static const u16 vc5_hdmi_csc_full_rgb_unity[3][4] = { 845 { 0x2000, 0x0000, 0x0000, 0x0000 }, 846 { 0x0000, 0x2000, 0x0000, 0x0000 }, 847 { 0x0000, 0x0000, 0x2000, 0x0000 }, 848 }; 849 850 /* 851 * CEA VICs other than #1 require limited range RGB output unless 852 * overridden by an AVI infoframe. Apply a colorspace conversion to 853 * squash 0-255 down to 16-235. The matrix here is: 854 * 855 * [ 0.8594 0 0 16] 856 * [ 0 0.8594 0 16] 857 * [ 0 0 0.8594 16] 858 * 859 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets 860 */ 861 static const u16 vc5_hdmi_csc_full_rgb_to_limited_rgb[3][4] = { 862 { 0x1b80, 0x0000, 0x0000, 0x0400 }, 863 { 0x0000, 0x1b80, 0x0000, 0x0400 }, 864 { 0x0000, 0x0000, 0x1b80, 0x0400 }, 865 }; 866 867 /* 868 * Conversion between Full Range RGB and Full Range YUV422 using the 869 * BT.709 Colorspace 870 * 871 * 872 * [ 0.181906 0.611804 0.061758 16 ] 873 * [ -0.100268 -0.337232 0.437500 128 ] 874 * [ 0.437500 -0.397386 -0.040114 128 ] 875 * 876 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets 877 */ 878 static const u16 vc5_hdmi_csc_full_rgb_to_limited_yuv422_bt709[3][4] = { 879 { 0x05d2, 0x1394, 0x01fa, 0x0400 }, 880 { 0xfccc, 0xf536, 0x0e00, 0x2000 }, 881 { 0x0e00, 0xf34a, 0xfeb8, 0x2000 }, 882 }; 883 884 /* 885 * Conversion between Full Range RGB and Full Range YUV444 using the 886 * BT.709 Colorspace 887 * 888 * [ -0.100268 -0.337232 0.437500 128 ] 889 * [ 0.437500 -0.397386 -0.040114 128 ] 890 * [ 0.181906 0.611804 0.061758 16 ] 891 * 892 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets 893 */ 894 static const u16 vc5_hdmi_csc_full_rgb_to_limited_yuv444_bt709[3][4] = { 895 { 0xfccc, 0xf536, 0x0e00, 0x2000 }, 896 { 0x0e00, 0xf34a, 0xfeb8, 0x2000 }, 897 { 0x05d2, 0x1394, 0x01fa, 0x0400 }, 898 }; 899 900 static void vc5_hdmi_set_csc_coeffs(struct vc4_hdmi *vc4_hdmi, 901 const u16 coeffs[3][4]) 902 { 903 lockdep_assert_held(&vc4_hdmi->hw_lock); 904 905 HDMI_WRITE(HDMI_CSC_12_11, (coeffs[0][1] << 16) | coeffs[0][0]); 906 HDMI_WRITE(HDMI_CSC_14_13, (coeffs[0][3] << 16) | coeffs[0][2]); 907 HDMI_WRITE(HDMI_CSC_22_21, (coeffs[1][1] << 16) | coeffs[1][0]); 908 HDMI_WRITE(HDMI_CSC_24_23, (coeffs[1][3] << 16) | coeffs[1][2]); 909 HDMI_WRITE(HDMI_CSC_32_31, (coeffs[2][1] << 16) | coeffs[2][0]); 910 HDMI_WRITE(HDMI_CSC_34_33, (coeffs[2][3] << 16) | coeffs[2][2]); 911 } 912 913 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, 914 struct drm_connector_state *state, 915 const struct drm_display_mode *mode) 916 { 917 struct vc4_hdmi_connector_state *vc4_state = 918 conn_state_to_vc4_hdmi_conn_state(state); 919 unsigned long flags; 920 u32 if_cfg = 0; 921 u32 if_xbar = 0x543210; 922 u32 csc_chan_ctl = 0; 923 u32 csc_ctl = VC5_MT_CP_CSC_CTL_ENABLE | VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM, 924 VC5_MT_CP_CSC_CTL_MODE); 925 926 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 927 928 switch (vc4_state->output_format) { 929 case VC4_HDMI_OUTPUT_YUV444: 930 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_limited_yuv444_bt709); 931 break; 932 933 case VC4_HDMI_OUTPUT_YUV422: 934 csc_ctl |= VC4_SET_FIELD(VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422_STANDARD, 935 VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422) | 936 VC5_MT_CP_CSC_CTL_USE_444_TO_422 | 937 VC5_MT_CP_CSC_CTL_USE_RNG_SUPPRESSION; 938 939 csc_chan_ctl |= VC4_SET_FIELD(VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP_LEGACY_STYLE, 940 VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP); 941 942 if_cfg |= VC4_SET_FIELD(VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422_FORMAT_422_LEGACY, 943 VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422); 944 945 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_limited_yuv422_bt709); 946 break; 947 948 case VC4_HDMI_OUTPUT_RGB: 949 if_xbar = 0x354021; 950 951 if (!vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode)) 952 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_limited_rgb); 953 else 954 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_unity); 955 break; 956 957 default: 958 break; 959 } 960 961 HDMI_WRITE(HDMI_VEC_INTERFACE_CFG, if_cfg); 962 HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, if_xbar); 963 HDMI_WRITE(HDMI_CSC_CHANNEL_CTL, csc_chan_ctl); 964 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl); 965 966 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 967 } 968 969 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi, 970 struct drm_connector_state *state, 971 struct drm_display_mode *mode) 972 { 973 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 974 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 975 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 976 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 977 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 978 VC4_HDMI_VERTA_VSP) | 979 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 980 VC4_HDMI_VERTA_VFP) | 981 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL)); 982 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 983 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end, 984 VC4_HDMI_VERTB_VBP)); 985 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 986 VC4_SET_FIELD(mode->crtc_vtotal - 987 mode->crtc_vsync_end - 988 interlaced, 989 VC4_HDMI_VERTB_VBP)); 990 unsigned long flags; 991 992 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 993 994 HDMI_WRITE(HDMI_HORZA, 995 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) | 996 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) | 997 VC4_SET_FIELD(mode->hdisplay * pixel_rep, 998 VC4_HDMI_HORZA_HAP)); 999 1000 HDMI_WRITE(HDMI_HORZB, 1001 VC4_SET_FIELD((mode->htotal - 1002 mode->hsync_end) * pixel_rep, 1003 VC4_HDMI_HORZB_HBP) | 1004 VC4_SET_FIELD((mode->hsync_end - 1005 mode->hsync_start) * pixel_rep, 1006 VC4_HDMI_HORZB_HSP) | 1007 VC4_SET_FIELD((mode->hsync_start - 1008 mode->hdisplay) * pixel_rep, 1009 VC4_HDMI_HORZB_HFP)); 1010 1011 HDMI_WRITE(HDMI_VERTA0, verta); 1012 HDMI_WRITE(HDMI_VERTA1, verta); 1013 1014 HDMI_WRITE(HDMI_VERTB0, vertb_even); 1015 HDMI_WRITE(HDMI_VERTB1, vertb); 1016 1017 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1018 } 1019 1020 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi, 1021 struct drm_connector_state *state, 1022 struct drm_display_mode *mode) 1023 { 1024 const struct vc4_hdmi_connector_state *vc4_state = 1025 conn_state_to_vc4_hdmi_conn_state(state); 1026 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 1027 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 1028 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 1029 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 1030 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 1031 VC5_HDMI_VERTA_VSP) | 1032 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 1033 VC5_HDMI_VERTA_VFP) | 1034 VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL)); 1035 u32 vertb = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) | 1036 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end, 1037 VC4_HDMI_VERTB_VBP)); 1038 u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) | 1039 VC4_SET_FIELD(mode->crtc_vtotal - 1040 mode->crtc_vsync_end - 1041 interlaced, 1042 VC4_HDMI_VERTB_VBP)); 1043 unsigned long flags; 1044 unsigned char gcp; 1045 bool gcp_en; 1046 u32 reg; 1047 1048 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1049 1050 HDMI_WRITE(HDMI_HORZA, 1051 (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) | 1052 (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) | 1053 VC4_SET_FIELD(mode->hdisplay * pixel_rep, 1054 VC5_HDMI_HORZA_HAP) | 1055 VC4_SET_FIELD((mode->hsync_start - 1056 mode->hdisplay) * pixel_rep, 1057 VC5_HDMI_HORZA_HFP)); 1058 1059 HDMI_WRITE(HDMI_HORZB, 1060 VC4_SET_FIELD((mode->htotal - 1061 mode->hsync_end) * pixel_rep, 1062 VC5_HDMI_HORZB_HBP) | 1063 VC4_SET_FIELD((mode->hsync_end - 1064 mode->hsync_start) * pixel_rep, 1065 VC5_HDMI_HORZB_HSP)); 1066 1067 HDMI_WRITE(HDMI_VERTA0, verta); 1068 HDMI_WRITE(HDMI_VERTA1, verta); 1069 1070 HDMI_WRITE(HDMI_VERTB0, vertb_even); 1071 HDMI_WRITE(HDMI_VERTB1, vertb); 1072 1073 switch (vc4_state->output_bpc) { 1074 case 12: 1075 gcp = 6; 1076 gcp_en = true; 1077 break; 1078 case 10: 1079 gcp = 5; 1080 gcp_en = true; 1081 break; 1082 case 8: 1083 default: 1084 gcp = 4; 1085 gcp_en = false; 1086 break; 1087 } 1088 1089 /* 1090 * YCC422 is always 36-bit and not considered deep colour so 1091 * doesn't signal in GCP. 1092 */ 1093 if (vc4_state->output_format == VC4_HDMI_OUTPUT_YUV422) { 1094 gcp = 4; 1095 gcp_en = false; 1096 } 1097 1098 reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1); 1099 reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK | 1100 VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK); 1101 reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) | 1102 VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH); 1103 HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg); 1104 1105 reg = HDMI_READ(HDMI_GCP_WORD_1); 1106 reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK; 1107 reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1); 1108 HDMI_WRITE(HDMI_GCP_WORD_1, reg); 1109 1110 reg = HDMI_READ(HDMI_GCP_CONFIG); 1111 reg &= ~VC5_HDMI_GCP_CONFIG_GCP_ENABLE; 1112 reg |= gcp_en ? VC5_HDMI_GCP_CONFIG_GCP_ENABLE : 0; 1113 HDMI_WRITE(HDMI_GCP_CONFIG, reg); 1114 1115 HDMI_WRITE(HDMI_CLOCK_STOP, 0); 1116 1117 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1118 } 1119 1120 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi) 1121 { 1122 unsigned long flags; 1123 u32 drift; 1124 int ret; 1125 1126 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1127 1128 drift = HDMI_READ(HDMI_FIFO_CTL); 1129 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK; 1130 1131 HDMI_WRITE(HDMI_FIFO_CTL, 1132 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 1133 HDMI_WRITE(HDMI_FIFO_CTL, 1134 drift | VC4_HDMI_FIFO_CTL_RECENTER); 1135 1136 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1137 1138 usleep_range(1000, 1100); 1139 1140 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1141 1142 HDMI_WRITE(HDMI_FIFO_CTL, 1143 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 1144 HDMI_WRITE(HDMI_FIFO_CTL, 1145 drift | VC4_HDMI_FIFO_CTL_RECENTER); 1146 1147 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1148 1149 ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) & 1150 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1); 1151 WARN_ONCE(ret, "Timeout waiting for " 1152 "VC4_HDMI_FIFO_CTL_RECENTER_DONE"); 1153 } 1154 1155 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder, 1156 struct drm_atomic_state *state) 1157 { 1158 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1159 struct drm_connector *connector = &vc4_hdmi->connector; 1160 struct drm_connector_state *conn_state = 1161 drm_atomic_get_new_connector_state(state, connector); 1162 struct vc4_hdmi_connector_state *vc4_conn_state = 1163 conn_state_to_vc4_hdmi_conn_state(conn_state); 1164 struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1165 unsigned long tmds_char_rate = vc4_conn_state->tmds_char_rate; 1166 unsigned long bvb_rate, hsm_rate; 1167 unsigned long flags; 1168 int ret; 1169 1170 mutex_lock(&vc4_hdmi->mutex); 1171 1172 /* 1173 * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must 1174 * be faster than pixel clock, infinitesimally faster, tested in 1175 * simulation. Otherwise, exact value is unimportant for HDMI 1176 * operation." This conflicts with bcm2835's vc4 documentation, which 1177 * states HSM's clock has to be at least 108% of the pixel clock. 1178 * 1179 * Real life tests reveal that vc4's firmware statement holds up, and 1180 * users are able to use pixel clocks closer to HSM's, namely for 1181 * 1920x1200@60Hz. So it was decided to have leave a 1% margin between 1182 * both clocks. Which, for RPi0-3 implies a maximum pixel clock of 1183 * 162MHz. 1184 * 1185 * Additionally, the AXI clock needs to be at least 25% of 1186 * pixel clock, but HSM ends up being the limiting factor. 1187 */ 1188 hsm_rate = max_t(unsigned long, 120000000, (tmds_char_rate / 100) * 101); 1189 ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate); 1190 if (ret) { 1191 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret); 1192 goto out; 1193 } 1194 1195 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev); 1196 if (ret < 0) { 1197 DRM_ERROR("Failed to retain power domain: %d\n", ret); 1198 goto out; 1199 } 1200 1201 ret = clk_set_rate(vc4_hdmi->pixel_clock, tmds_char_rate); 1202 if (ret) { 1203 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret); 1204 goto err_put_runtime_pm; 1205 } 1206 1207 ret = clk_prepare_enable(vc4_hdmi->pixel_clock); 1208 if (ret) { 1209 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret); 1210 goto err_put_runtime_pm; 1211 } 1212 1213 1214 vc4_hdmi_cec_update_clk_div(vc4_hdmi); 1215 1216 if (tmds_char_rate > 297000000) 1217 bvb_rate = 300000000; 1218 else if (tmds_char_rate > 148500000) 1219 bvb_rate = 150000000; 1220 else 1221 bvb_rate = 75000000; 1222 1223 ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate); 1224 if (ret) { 1225 DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret); 1226 goto err_disable_pixel_clock; 1227 } 1228 1229 ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock); 1230 if (ret) { 1231 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret); 1232 goto err_disable_pixel_clock; 1233 } 1234 1235 if (vc4_hdmi->variant->phy_init) 1236 vc4_hdmi->variant->phy_init(vc4_hdmi, vc4_conn_state); 1237 1238 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1239 1240 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1241 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 1242 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT | 1243 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS); 1244 1245 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1246 1247 if (vc4_hdmi->variant->set_timings) 1248 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode); 1249 1250 mutex_unlock(&vc4_hdmi->mutex); 1251 1252 return; 1253 1254 err_disable_pixel_clock: 1255 clk_disable_unprepare(vc4_hdmi->pixel_clock); 1256 err_put_runtime_pm: 1257 pm_runtime_put(&vc4_hdmi->pdev->dev); 1258 out: 1259 mutex_unlock(&vc4_hdmi->mutex); 1260 return; 1261 } 1262 1263 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder, 1264 struct drm_atomic_state *state) 1265 { 1266 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1267 struct drm_connector *connector = &vc4_hdmi->connector; 1268 struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1269 struct drm_connector_state *conn_state = 1270 drm_atomic_get_new_connector_state(state, connector); 1271 unsigned long flags; 1272 1273 mutex_lock(&vc4_hdmi->mutex); 1274 1275 if (vc4_hdmi->variant->csc_setup) 1276 vc4_hdmi->variant->csc_setup(vc4_hdmi, conn_state, mode); 1277 1278 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1279 HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N); 1280 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1281 1282 mutex_unlock(&vc4_hdmi->mutex); 1283 } 1284 1285 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder, 1286 struct drm_atomic_state *state) 1287 { 1288 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1289 struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1290 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 1291 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 1292 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 1293 unsigned long flags; 1294 int ret; 1295 1296 mutex_lock(&vc4_hdmi->mutex); 1297 1298 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1299 1300 HDMI_WRITE(HDMI_VID_CTL, 1301 VC4_HD_VID_CTL_ENABLE | 1302 VC4_HD_VID_CTL_CLRRGB | 1303 VC4_HD_VID_CTL_UNDERFLOW_ENABLE | 1304 VC4_HD_VID_CTL_FRAME_COUNTER_RESET | 1305 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) | 1306 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW)); 1307 1308 HDMI_WRITE(HDMI_VID_CTL, 1309 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX); 1310 1311 if (vc4_encoder->hdmi_monitor) { 1312 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1313 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 1314 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 1315 1316 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1317 1318 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1319 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000); 1320 WARN_ONCE(ret, "Timeout waiting for " 1321 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 1322 } else { 1323 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 1324 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & 1325 ~(VC4_HDMI_RAM_PACKET_ENABLE)); 1326 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1327 HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1328 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 1329 1330 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1331 1332 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1333 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000); 1334 WARN_ONCE(ret, "Timeout waiting for " 1335 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 1336 } 1337 1338 if (vc4_encoder->hdmi_monitor) { 1339 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1340 1341 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1342 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE)); 1343 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1344 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 1345 VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT); 1346 1347 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 1348 VC4_HDMI_RAM_PACKET_ENABLE); 1349 1350 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1351 1352 vc4_hdmi_set_infoframes(encoder); 1353 } 1354 1355 vc4_hdmi_recenter_fifo(vc4_hdmi); 1356 vc4_hdmi_enable_scrambling(encoder); 1357 1358 mutex_unlock(&vc4_hdmi->mutex); 1359 } 1360 1361 static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder) 1362 { 1363 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1364 1365 mutex_lock(&vc4_hdmi->mutex); 1366 vc4_hdmi->output_enabled = true; 1367 mutex_unlock(&vc4_hdmi->mutex); 1368 } 1369 1370 static void vc4_hdmi_encoder_atomic_mode_set(struct drm_encoder *encoder, 1371 struct drm_crtc_state *crtc_state, 1372 struct drm_connector_state *conn_state) 1373 { 1374 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1375 struct vc4_hdmi_connector_state *vc4_state = 1376 conn_state_to_vc4_hdmi_conn_state(conn_state); 1377 1378 mutex_lock(&vc4_hdmi->mutex); 1379 drm_mode_copy(&vc4_hdmi->saved_adjusted_mode, 1380 &crtc_state->adjusted_mode); 1381 vc4_hdmi->output_bpc = vc4_state->output_bpc; 1382 vc4_hdmi->output_format = vc4_state->output_format; 1383 mutex_unlock(&vc4_hdmi->mutex); 1384 } 1385 1386 static bool 1387 vc4_hdmi_sink_supports_format_bpc(const struct vc4_hdmi *vc4_hdmi, 1388 const struct drm_display_info *info, 1389 const struct drm_display_mode *mode, 1390 unsigned int format, unsigned int bpc) 1391 { 1392 struct drm_device *dev = vc4_hdmi->connector.dev; 1393 u8 vic = drm_match_cea_mode(mode); 1394 1395 if (vic == 1 && bpc != 8) { 1396 drm_dbg(dev, "VIC1 requires a bpc of 8, got %u\n", bpc); 1397 return false; 1398 } 1399 1400 if (!info->is_hdmi && 1401 (format != VC4_HDMI_OUTPUT_RGB || bpc != 8)) { 1402 drm_dbg(dev, "DVI Monitors require an RGB output at 8 bpc\n"); 1403 return false; 1404 } 1405 1406 switch (format) { 1407 case VC4_HDMI_OUTPUT_RGB: 1408 drm_dbg(dev, "RGB Format, checking the constraints.\n"); 1409 1410 if (!(info->color_formats & DRM_COLOR_FORMAT_RGB444)) 1411 return false; 1412 1413 if (bpc == 10 && !(info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30)) { 1414 drm_dbg(dev, "10 BPC but sink doesn't support Deep Color 30.\n"); 1415 return false; 1416 } 1417 1418 if (bpc == 12 && !(info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36)) { 1419 drm_dbg(dev, "12 BPC but sink doesn't support Deep Color 36.\n"); 1420 return false; 1421 } 1422 1423 drm_dbg(dev, "RGB format supported in that configuration.\n"); 1424 1425 return true; 1426 1427 case VC4_HDMI_OUTPUT_YUV422: 1428 drm_dbg(dev, "YUV422 format, checking the constraints.\n"); 1429 1430 if (!(info->color_formats & DRM_COLOR_FORMAT_YCBCR422)) { 1431 drm_dbg(dev, "Sink doesn't support YUV422.\n"); 1432 return false; 1433 } 1434 1435 if (bpc != 12) { 1436 drm_dbg(dev, "YUV422 only supports 12 bpc.\n"); 1437 return false; 1438 } 1439 1440 drm_dbg(dev, "YUV422 format supported in that configuration.\n"); 1441 1442 return true; 1443 1444 case VC4_HDMI_OUTPUT_YUV444: 1445 drm_dbg(dev, "YUV444 format, checking the constraints.\n"); 1446 1447 if (!(info->color_formats & DRM_COLOR_FORMAT_YCBCR444)) { 1448 drm_dbg(dev, "Sink doesn't support YUV444.\n"); 1449 return false; 1450 } 1451 1452 if (bpc == 10 && !(info->edid_hdmi_ycbcr444_dc_modes & DRM_EDID_HDMI_DC_30)) { 1453 drm_dbg(dev, "10 BPC but sink doesn't support Deep Color 30.\n"); 1454 return false; 1455 } 1456 1457 if (bpc == 12 && !(info->edid_hdmi_ycbcr444_dc_modes & DRM_EDID_HDMI_DC_36)) { 1458 drm_dbg(dev, "12 BPC but sink doesn't support Deep Color 36.\n"); 1459 return false; 1460 } 1461 1462 drm_dbg(dev, "YUV444 format supported in that configuration.\n"); 1463 1464 return true; 1465 } 1466 1467 return false; 1468 } 1469 1470 static enum drm_mode_status 1471 vc4_hdmi_encoder_clock_valid(const struct vc4_hdmi *vc4_hdmi, 1472 unsigned long long clock) 1473 { 1474 const struct drm_connector *connector = &vc4_hdmi->connector; 1475 const struct drm_display_info *info = &connector->display_info; 1476 1477 if (clock > vc4_hdmi->variant->max_pixel_clock) 1478 return MODE_CLOCK_HIGH; 1479 1480 if (vc4_hdmi->disable_4kp60 && clock > HDMI_14_MAX_TMDS_CLK) 1481 return MODE_CLOCK_HIGH; 1482 1483 if (info->max_tmds_clock && clock > (info->max_tmds_clock * 1000)) 1484 return MODE_CLOCK_HIGH; 1485 1486 return MODE_OK; 1487 } 1488 1489 static unsigned long long 1490 vc4_hdmi_encoder_compute_mode_clock(const struct drm_display_mode *mode, 1491 unsigned int bpc, 1492 enum vc4_hdmi_output_format fmt) 1493 { 1494 unsigned long long clock = mode->clock * 1000; 1495 1496 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 1497 clock = clock * 2; 1498 1499 if (fmt == VC4_HDMI_OUTPUT_YUV422) 1500 bpc = 8; 1501 1502 clock = clock * bpc; 1503 do_div(clock, 8); 1504 1505 return clock; 1506 } 1507 1508 static int 1509 vc4_hdmi_encoder_compute_clock(const struct vc4_hdmi *vc4_hdmi, 1510 struct vc4_hdmi_connector_state *vc4_state, 1511 const struct drm_display_mode *mode, 1512 unsigned int bpc, unsigned int fmt) 1513 { 1514 unsigned long long clock; 1515 1516 clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc, fmt); 1517 if (vc4_hdmi_encoder_clock_valid(vc4_hdmi, clock) != MODE_OK) 1518 return -EINVAL; 1519 1520 vc4_state->tmds_char_rate = clock; 1521 1522 return 0; 1523 } 1524 1525 static int 1526 vc4_hdmi_encoder_compute_format(const struct vc4_hdmi *vc4_hdmi, 1527 struct vc4_hdmi_connector_state *vc4_state, 1528 const struct drm_display_mode *mode, 1529 unsigned int bpc) 1530 { 1531 struct drm_device *dev = vc4_hdmi->connector.dev; 1532 const struct drm_connector *connector = &vc4_hdmi->connector; 1533 const struct drm_display_info *info = &connector->display_info; 1534 unsigned int format; 1535 1536 drm_dbg(dev, "Trying with an RGB output\n"); 1537 1538 format = VC4_HDMI_OUTPUT_RGB; 1539 if (vc4_hdmi_sink_supports_format_bpc(vc4_hdmi, info, mode, format, bpc)) { 1540 int ret; 1541 1542 ret = vc4_hdmi_encoder_compute_clock(vc4_hdmi, vc4_state, 1543 mode, bpc, format); 1544 if (!ret) { 1545 vc4_state->output_format = format; 1546 return 0; 1547 } 1548 } 1549 1550 drm_dbg(dev, "Failed, Trying with an YUV422 output\n"); 1551 1552 format = VC4_HDMI_OUTPUT_YUV422; 1553 if (vc4_hdmi_sink_supports_format_bpc(vc4_hdmi, info, mode, format, bpc)) { 1554 int ret; 1555 1556 ret = vc4_hdmi_encoder_compute_clock(vc4_hdmi, vc4_state, 1557 mode, bpc, format); 1558 if (!ret) { 1559 vc4_state->output_format = format; 1560 return 0; 1561 } 1562 } 1563 1564 drm_dbg(dev, "Failed. No Format Supported for that bpc count.\n"); 1565 1566 return -EINVAL; 1567 } 1568 1569 static int 1570 vc4_hdmi_encoder_compute_config(const struct vc4_hdmi *vc4_hdmi, 1571 struct vc4_hdmi_connector_state *vc4_state, 1572 const struct drm_display_mode *mode) 1573 { 1574 struct drm_device *dev = vc4_hdmi->connector.dev; 1575 struct drm_connector_state *conn_state = &vc4_state->base; 1576 unsigned int max_bpc = clamp_t(unsigned int, conn_state->max_bpc, 8, 12); 1577 unsigned int bpc; 1578 int ret; 1579 1580 for (bpc = max_bpc; bpc >= 8; bpc -= 2) { 1581 drm_dbg(dev, "Trying with a %d bpc output\n", bpc); 1582 1583 ret = vc4_hdmi_encoder_compute_format(vc4_hdmi, vc4_state, 1584 mode, bpc); 1585 if (ret) 1586 continue; 1587 1588 vc4_state->output_bpc = bpc; 1589 1590 drm_dbg(dev, 1591 "Mode %ux%u @ %uHz: Found configuration: bpc: %u, fmt: %s, clock: %llu\n", 1592 mode->hdisplay, mode->vdisplay, drm_mode_vrefresh(mode), 1593 vc4_state->output_bpc, 1594 vc4_hdmi_output_fmt_str(vc4_state->output_format), 1595 vc4_state->tmds_char_rate); 1596 1597 break; 1598 } 1599 1600 return ret; 1601 } 1602 1603 #define WIFI_2_4GHz_CH1_MIN_FREQ 2400000000ULL 1604 #define WIFI_2_4GHz_CH1_MAX_FREQ 2422000000ULL 1605 1606 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder, 1607 struct drm_crtc_state *crtc_state, 1608 struct drm_connector_state *conn_state) 1609 { 1610 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state); 1611 struct drm_display_mode *mode = &crtc_state->adjusted_mode; 1612 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1613 unsigned long long tmds_char_rate = mode->clock * 1000; 1614 unsigned long long tmds_bit_rate; 1615 int ret; 1616 1617 if (vc4_hdmi->variant->unsupported_odd_h_timings && 1618 ((mode->hdisplay % 2) || (mode->hsync_start % 2) || 1619 (mode->hsync_end % 2) || (mode->htotal % 2))) 1620 return -EINVAL; 1621 1622 /* 1623 * The 1440p@60 pixel rate is in the same range than the first 1624 * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz 1625 * bandwidth). Slightly lower the frequency to bring it out of 1626 * the WiFi range. 1627 */ 1628 tmds_bit_rate = tmds_char_rate * 10; 1629 if (vc4_hdmi->disable_wifi_frequencies && 1630 (tmds_bit_rate >= WIFI_2_4GHz_CH1_MIN_FREQ && 1631 tmds_bit_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) { 1632 mode->clock = 238560; 1633 tmds_char_rate = mode->clock * 1000; 1634 } 1635 1636 ret = vc4_hdmi_encoder_compute_config(vc4_hdmi, vc4_state, mode); 1637 if (ret) 1638 return ret; 1639 1640 return 0; 1641 } 1642 1643 static enum drm_mode_status 1644 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder, 1645 const struct drm_display_mode *mode) 1646 { 1647 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1648 1649 if (vc4_hdmi->variant->unsupported_odd_h_timings && 1650 ((mode->hdisplay % 2) || (mode->hsync_start % 2) || 1651 (mode->hsync_end % 2) || (mode->htotal % 2))) 1652 return MODE_H_ILLEGAL; 1653 1654 return vc4_hdmi_encoder_clock_valid(vc4_hdmi, mode->clock * 1000); 1655 } 1656 1657 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = { 1658 .atomic_check = vc4_hdmi_encoder_atomic_check, 1659 .atomic_mode_set = vc4_hdmi_encoder_atomic_mode_set, 1660 .mode_valid = vc4_hdmi_encoder_mode_valid, 1661 .disable = vc4_hdmi_encoder_disable, 1662 .enable = vc4_hdmi_encoder_enable, 1663 }; 1664 1665 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask) 1666 { 1667 int i; 1668 u32 channel_map = 0; 1669 1670 for (i = 0; i < 8; i++) { 1671 if (channel_mask & BIT(i)) 1672 channel_map |= i << (3 * i); 1673 } 1674 return channel_map; 1675 } 1676 1677 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask) 1678 { 1679 int i; 1680 u32 channel_map = 0; 1681 1682 for (i = 0; i < 8; i++) { 1683 if (channel_mask & BIT(i)) 1684 channel_map |= i << (4 * i); 1685 } 1686 return channel_map; 1687 } 1688 1689 /* HDMI audio codec callbacks */ 1690 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi, 1691 unsigned int samplerate) 1692 { 1693 u32 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock); 1694 unsigned long flags; 1695 unsigned long n, m; 1696 1697 rational_best_approximation(hsm_clock, samplerate, 1698 VC4_HD_MAI_SMP_N_MASK >> 1699 VC4_HD_MAI_SMP_N_SHIFT, 1700 (VC4_HD_MAI_SMP_M_MASK >> 1701 VC4_HD_MAI_SMP_M_SHIFT) + 1, 1702 &n, &m); 1703 1704 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1705 HDMI_WRITE(HDMI_MAI_SMP, 1706 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) | 1707 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M)); 1708 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1709 } 1710 1711 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi, unsigned int samplerate) 1712 { 1713 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1714 u32 n, cts; 1715 u64 tmp; 1716 1717 lockdep_assert_held(&vc4_hdmi->mutex); 1718 lockdep_assert_held(&vc4_hdmi->hw_lock); 1719 1720 n = 128 * samplerate / 1000; 1721 tmp = (u64)(mode->clock * 1000) * n; 1722 do_div(tmp, 128 * samplerate); 1723 cts = tmp; 1724 1725 HDMI_WRITE(HDMI_CRP_CFG, 1726 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN | 1727 VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N)); 1728 1729 /* 1730 * We could get slightly more accurate clocks in some cases by 1731 * providing a CTS_1 value. The two CTS values are alternated 1732 * between based on the period fields 1733 */ 1734 HDMI_WRITE(HDMI_CTS_0, cts); 1735 HDMI_WRITE(HDMI_CTS_1, cts); 1736 } 1737 1738 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai) 1739 { 1740 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai); 1741 1742 return snd_soc_card_get_drvdata(card); 1743 } 1744 1745 static bool vc4_hdmi_audio_can_stream(struct vc4_hdmi *vc4_hdmi) 1746 { 1747 lockdep_assert_held(&vc4_hdmi->mutex); 1748 1749 /* 1750 * If the controller is disabled, prevent any ALSA output. 1751 */ 1752 if (!vc4_hdmi->output_enabled) 1753 return false; 1754 1755 /* 1756 * If the encoder is currently in DVI mode, treat the codec DAI 1757 * as missing. 1758 */ 1759 if (!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) & VC4_HDMI_RAM_PACKET_ENABLE)) 1760 return false; 1761 1762 return true; 1763 } 1764 1765 static int vc4_hdmi_audio_startup(struct device *dev, void *data) 1766 { 1767 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 1768 unsigned long flags; 1769 1770 mutex_lock(&vc4_hdmi->mutex); 1771 1772 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) { 1773 mutex_unlock(&vc4_hdmi->mutex); 1774 return -ENODEV; 1775 } 1776 1777 vc4_hdmi->audio.streaming = true; 1778 1779 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1780 HDMI_WRITE(HDMI_MAI_CTL, 1781 VC4_HD_MAI_CTL_RESET | 1782 VC4_HD_MAI_CTL_FLUSH | 1783 VC4_HD_MAI_CTL_DLATE | 1784 VC4_HD_MAI_CTL_ERRORE | 1785 VC4_HD_MAI_CTL_ERRORF); 1786 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1787 1788 if (vc4_hdmi->variant->phy_rng_enable) 1789 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi); 1790 1791 mutex_unlock(&vc4_hdmi->mutex); 1792 1793 return 0; 1794 } 1795 1796 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi) 1797 { 1798 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base; 1799 struct device *dev = &vc4_hdmi->pdev->dev; 1800 unsigned long flags; 1801 int ret; 1802 1803 lockdep_assert_held(&vc4_hdmi->mutex); 1804 1805 vc4_hdmi->audio.streaming = false; 1806 ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO, false); 1807 if (ret) 1808 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret); 1809 1810 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1811 1812 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET); 1813 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF); 1814 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH); 1815 1816 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1817 } 1818 1819 static void vc4_hdmi_audio_shutdown(struct device *dev, void *data) 1820 { 1821 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 1822 unsigned long flags; 1823 1824 mutex_lock(&vc4_hdmi->mutex); 1825 1826 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1827 1828 HDMI_WRITE(HDMI_MAI_CTL, 1829 VC4_HD_MAI_CTL_DLATE | 1830 VC4_HD_MAI_CTL_ERRORE | 1831 VC4_HD_MAI_CTL_ERRORF); 1832 1833 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1834 1835 if (vc4_hdmi->variant->phy_rng_disable) 1836 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi); 1837 1838 vc4_hdmi->audio.streaming = false; 1839 vc4_hdmi_audio_reset(vc4_hdmi); 1840 1841 mutex_unlock(&vc4_hdmi->mutex); 1842 } 1843 1844 static int sample_rate_to_mai_fmt(int samplerate) 1845 { 1846 switch (samplerate) { 1847 case 8000: 1848 return VC4_HDMI_MAI_SAMPLE_RATE_8000; 1849 case 11025: 1850 return VC4_HDMI_MAI_SAMPLE_RATE_11025; 1851 case 12000: 1852 return VC4_HDMI_MAI_SAMPLE_RATE_12000; 1853 case 16000: 1854 return VC4_HDMI_MAI_SAMPLE_RATE_16000; 1855 case 22050: 1856 return VC4_HDMI_MAI_SAMPLE_RATE_22050; 1857 case 24000: 1858 return VC4_HDMI_MAI_SAMPLE_RATE_24000; 1859 case 32000: 1860 return VC4_HDMI_MAI_SAMPLE_RATE_32000; 1861 case 44100: 1862 return VC4_HDMI_MAI_SAMPLE_RATE_44100; 1863 case 48000: 1864 return VC4_HDMI_MAI_SAMPLE_RATE_48000; 1865 case 64000: 1866 return VC4_HDMI_MAI_SAMPLE_RATE_64000; 1867 case 88200: 1868 return VC4_HDMI_MAI_SAMPLE_RATE_88200; 1869 case 96000: 1870 return VC4_HDMI_MAI_SAMPLE_RATE_96000; 1871 case 128000: 1872 return VC4_HDMI_MAI_SAMPLE_RATE_128000; 1873 case 176400: 1874 return VC4_HDMI_MAI_SAMPLE_RATE_176400; 1875 case 192000: 1876 return VC4_HDMI_MAI_SAMPLE_RATE_192000; 1877 default: 1878 return VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED; 1879 } 1880 } 1881 1882 /* HDMI audio codec callbacks */ 1883 static int vc4_hdmi_audio_prepare(struct device *dev, void *data, 1884 struct hdmi_codec_daifmt *daifmt, 1885 struct hdmi_codec_params *params) 1886 { 1887 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 1888 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base; 1889 unsigned int sample_rate = params->sample_rate; 1890 unsigned int channels = params->channels; 1891 unsigned long flags; 1892 u32 audio_packet_config, channel_mask; 1893 u32 channel_map; 1894 u32 mai_audio_format; 1895 u32 mai_sample_rate; 1896 1897 dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__, 1898 sample_rate, params->sample_width, channels); 1899 1900 mutex_lock(&vc4_hdmi->mutex); 1901 1902 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) { 1903 mutex_unlock(&vc4_hdmi->mutex); 1904 return -EINVAL; 1905 } 1906 1907 vc4_hdmi_audio_set_mai_clock(vc4_hdmi, sample_rate); 1908 1909 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1910 HDMI_WRITE(HDMI_MAI_CTL, 1911 VC4_SET_FIELD(channels, VC4_HD_MAI_CTL_CHNUM) | 1912 VC4_HD_MAI_CTL_WHOLSMP | 1913 VC4_HD_MAI_CTL_CHALIGN | 1914 VC4_HD_MAI_CTL_ENABLE); 1915 1916 mai_sample_rate = sample_rate_to_mai_fmt(sample_rate); 1917 if (params->iec.status[0] & IEC958_AES0_NONAUDIO && 1918 params->channels == 8) 1919 mai_audio_format = VC4_HDMI_MAI_FORMAT_HBR; 1920 else 1921 mai_audio_format = VC4_HDMI_MAI_FORMAT_PCM; 1922 HDMI_WRITE(HDMI_MAI_FMT, 1923 VC4_SET_FIELD(mai_sample_rate, 1924 VC4_HDMI_MAI_FORMAT_SAMPLE_RATE) | 1925 VC4_SET_FIELD(mai_audio_format, 1926 VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT)); 1927 1928 /* The B frame identifier should match the value used by alsa-lib (8) */ 1929 audio_packet_config = 1930 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT | 1931 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS | 1932 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER); 1933 1934 channel_mask = GENMASK(channels - 1, 0); 1935 audio_packet_config |= VC4_SET_FIELD(channel_mask, 1936 VC4_HDMI_AUDIO_PACKET_CEA_MASK); 1937 1938 /* Set the MAI threshold */ 1939 HDMI_WRITE(HDMI_MAI_THR, 1940 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) | 1941 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) | 1942 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQHIGH) | 1943 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQLOW)); 1944 1945 HDMI_WRITE(HDMI_MAI_CONFIG, 1946 VC4_HDMI_MAI_CONFIG_BIT_REVERSE | 1947 VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE | 1948 VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK)); 1949 1950 channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask); 1951 HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map); 1952 HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config); 1953 1954 vc4_hdmi_set_n_cts(vc4_hdmi, sample_rate); 1955 1956 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1957 1958 memcpy(&vc4_hdmi->audio.infoframe, ¶ms->cea, sizeof(params->cea)); 1959 vc4_hdmi_set_audio_infoframe(encoder); 1960 1961 mutex_unlock(&vc4_hdmi->mutex); 1962 1963 return 0; 1964 } 1965 1966 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = { 1967 .name = "vc4-hdmi-cpu-dai-component", 1968 }; 1969 1970 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai) 1971 { 1972 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai); 1973 1974 snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL); 1975 1976 return 0; 1977 } 1978 1979 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = { 1980 .name = "vc4-hdmi-cpu-dai", 1981 .probe = vc4_hdmi_audio_cpu_dai_probe, 1982 .playback = { 1983 .stream_name = "Playback", 1984 .channels_min = 1, 1985 .channels_max = 8, 1986 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 1987 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 1988 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 1989 SNDRV_PCM_RATE_192000, 1990 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 1991 }, 1992 }; 1993 1994 static const struct snd_dmaengine_pcm_config pcm_conf = { 1995 .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx", 1996 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 1997 }; 1998 1999 static int vc4_hdmi_audio_get_eld(struct device *dev, void *data, 2000 uint8_t *buf, size_t len) 2001 { 2002 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 2003 struct drm_connector *connector = &vc4_hdmi->connector; 2004 2005 mutex_lock(&vc4_hdmi->mutex); 2006 memcpy(buf, connector->eld, min(sizeof(connector->eld), len)); 2007 mutex_unlock(&vc4_hdmi->mutex); 2008 2009 return 0; 2010 } 2011 2012 static const struct hdmi_codec_ops vc4_hdmi_codec_ops = { 2013 .get_eld = vc4_hdmi_audio_get_eld, 2014 .prepare = vc4_hdmi_audio_prepare, 2015 .audio_shutdown = vc4_hdmi_audio_shutdown, 2016 .audio_startup = vc4_hdmi_audio_startup, 2017 }; 2018 2019 static struct hdmi_codec_pdata vc4_hdmi_codec_pdata = { 2020 .ops = &vc4_hdmi_codec_ops, 2021 .max_i2s_channels = 8, 2022 .i2s = 1, 2023 }; 2024 2025 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi) 2026 { 2027 const struct vc4_hdmi_register *mai_data = 2028 &vc4_hdmi->variant->registers[HDMI_MAI_DATA]; 2029 struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link; 2030 struct snd_soc_card *card = &vc4_hdmi->audio.card; 2031 struct device *dev = &vc4_hdmi->pdev->dev; 2032 struct platform_device *codec_pdev; 2033 const __be32 *addr; 2034 int index; 2035 int ret; 2036 2037 if (!of_find_property(dev->of_node, "dmas", NULL)) { 2038 dev_warn(dev, 2039 "'dmas' DT property is missing, no HDMI audio\n"); 2040 return 0; 2041 } 2042 2043 if (mai_data->reg != VC4_HD) { 2044 WARN_ONCE(true, "MAI isn't in the HD block\n"); 2045 return -EINVAL; 2046 } 2047 2048 /* 2049 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve 2050 * the bus address specified in the DT, because the physical address 2051 * (the one returned by platform_get_resource()) is not appropriate 2052 * for DMA transfers. 2053 * This VC/MMU should probably be exposed to avoid this kind of hacks. 2054 */ 2055 index = of_property_match_string(dev->of_node, "reg-names", "hd"); 2056 /* Before BCM2711, we don't have a named register range */ 2057 if (index < 0) 2058 index = 1; 2059 2060 addr = of_get_address(dev->of_node, index, NULL, NULL); 2061 2062 vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset; 2063 vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 2064 vc4_hdmi->audio.dma_data.maxburst = 2; 2065 2066 ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0); 2067 if (ret) { 2068 dev_err(dev, "Could not register PCM component: %d\n", ret); 2069 return ret; 2070 } 2071 2072 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp, 2073 &vc4_hdmi_audio_cpu_dai_drv, 1); 2074 if (ret) { 2075 dev_err(dev, "Could not register CPU DAI: %d\n", ret); 2076 return ret; 2077 } 2078 2079 codec_pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME, 2080 PLATFORM_DEVID_AUTO, 2081 &vc4_hdmi_codec_pdata, 2082 sizeof(vc4_hdmi_codec_pdata)); 2083 if (IS_ERR(codec_pdev)) { 2084 dev_err(dev, "Couldn't register the HDMI codec: %ld\n", PTR_ERR(codec_pdev)); 2085 return PTR_ERR(codec_pdev); 2086 } 2087 2088 dai_link->cpus = &vc4_hdmi->audio.cpu; 2089 dai_link->codecs = &vc4_hdmi->audio.codec; 2090 dai_link->platforms = &vc4_hdmi->audio.platform; 2091 2092 dai_link->num_cpus = 1; 2093 dai_link->num_codecs = 1; 2094 dai_link->num_platforms = 1; 2095 2096 dai_link->name = "MAI"; 2097 dai_link->stream_name = "MAI PCM"; 2098 dai_link->codecs->dai_name = "i2s-hifi"; 2099 dai_link->cpus->dai_name = dev_name(dev); 2100 dai_link->codecs->name = dev_name(&codec_pdev->dev); 2101 dai_link->platforms->name = dev_name(dev); 2102 2103 card->dai_link = dai_link; 2104 card->num_links = 1; 2105 card->name = vc4_hdmi->variant->card_name; 2106 card->driver_name = "vc4-hdmi"; 2107 card->dev = dev; 2108 card->owner = THIS_MODULE; 2109 2110 /* 2111 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and 2112 * stores a pointer to the snd card object in dev->driver_data. This 2113 * means we cannot use it for something else. The hdmi back-pointer is 2114 * now stored in card->drvdata and should be retrieved with 2115 * snd_soc_card_get_drvdata() if needed. 2116 */ 2117 snd_soc_card_set_drvdata(card, vc4_hdmi); 2118 ret = devm_snd_soc_register_card(dev, card); 2119 if (ret) 2120 dev_err_probe(dev, ret, "Could not register sound card\n"); 2121 2122 return ret; 2123 2124 } 2125 2126 static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv) 2127 { 2128 struct vc4_hdmi *vc4_hdmi = priv; 2129 struct drm_connector *connector = &vc4_hdmi->connector; 2130 struct drm_device *dev = connector->dev; 2131 2132 if (dev && dev->registered) 2133 drm_connector_helper_hpd_irq_event(connector); 2134 2135 return IRQ_HANDLED; 2136 } 2137 2138 static int vc4_hdmi_hotplug_init(struct vc4_hdmi *vc4_hdmi) 2139 { 2140 struct drm_connector *connector = &vc4_hdmi->connector; 2141 struct platform_device *pdev = vc4_hdmi->pdev; 2142 int ret; 2143 2144 if (vc4_hdmi->variant->external_irq_controller) { 2145 unsigned int hpd_con = platform_get_irq_byname(pdev, "hpd-connected"); 2146 unsigned int hpd_rm = platform_get_irq_byname(pdev, "hpd-removed"); 2147 2148 ret = request_threaded_irq(hpd_con, 2149 NULL, 2150 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT, 2151 "vc4 hdmi hpd connected", vc4_hdmi); 2152 if (ret) 2153 return ret; 2154 2155 ret = request_threaded_irq(hpd_rm, 2156 NULL, 2157 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT, 2158 "vc4 hdmi hpd disconnected", vc4_hdmi); 2159 if (ret) { 2160 free_irq(hpd_con, vc4_hdmi); 2161 return ret; 2162 } 2163 2164 connector->polled = DRM_CONNECTOR_POLL_HPD; 2165 } 2166 2167 return 0; 2168 } 2169 2170 static void vc4_hdmi_hotplug_exit(struct vc4_hdmi *vc4_hdmi) 2171 { 2172 struct platform_device *pdev = vc4_hdmi->pdev; 2173 2174 if (vc4_hdmi->variant->external_irq_controller) { 2175 free_irq(platform_get_irq_byname(pdev, "hpd-connected"), vc4_hdmi); 2176 free_irq(platform_get_irq_byname(pdev, "hpd-removed"), vc4_hdmi); 2177 } 2178 } 2179 2180 #ifdef CONFIG_DRM_VC4_HDMI_CEC 2181 static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv) 2182 { 2183 struct vc4_hdmi *vc4_hdmi = priv; 2184 2185 if (vc4_hdmi->cec_rx_msg.len) 2186 cec_received_msg(vc4_hdmi->cec_adap, 2187 &vc4_hdmi->cec_rx_msg); 2188 2189 return IRQ_HANDLED; 2190 } 2191 2192 static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv) 2193 { 2194 struct vc4_hdmi *vc4_hdmi = priv; 2195 2196 if (vc4_hdmi->cec_tx_ok) { 2197 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK, 2198 0, 0, 0, 0); 2199 } else { 2200 /* 2201 * This CEC implementation makes 1 retry, so if we 2202 * get a NACK, then that means it made 2 attempts. 2203 */ 2204 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK, 2205 0, 2, 0, 0); 2206 } 2207 return IRQ_HANDLED; 2208 } 2209 2210 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv) 2211 { 2212 struct vc4_hdmi *vc4_hdmi = priv; 2213 irqreturn_t ret; 2214 2215 if (vc4_hdmi->cec_irq_was_rx) 2216 ret = vc4_cec_irq_handler_rx_thread(irq, priv); 2217 else 2218 ret = vc4_cec_irq_handler_tx_thread(irq, priv); 2219 2220 return ret; 2221 } 2222 2223 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1) 2224 { 2225 struct drm_device *dev = vc4_hdmi->connector.dev; 2226 struct cec_msg *msg = &vc4_hdmi->cec_rx_msg; 2227 unsigned int i; 2228 2229 lockdep_assert_held(&vc4_hdmi->hw_lock); 2230 2231 msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >> 2232 VC4_HDMI_CEC_REC_WRD_CNT_SHIFT); 2233 2234 if (msg->len > 16) { 2235 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len); 2236 return; 2237 } 2238 2239 for (i = 0; i < msg->len; i += 4) { 2240 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2)); 2241 2242 msg->msg[i] = val & 0xff; 2243 msg->msg[i + 1] = (val >> 8) & 0xff; 2244 msg->msg[i + 2] = (val >> 16) & 0xff; 2245 msg->msg[i + 3] = (val >> 24) & 0xff; 2246 } 2247 } 2248 2249 static irqreturn_t vc4_cec_irq_handler_tx_bare_locked(struct vc4_hdmi *vc4_hdmi) 2250 { 2251 u32 cntrl1; 2252 2253 lockdep_assert_held(&vc4_hdmi->hw_lock); 2254 2255 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1); 2256 vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD; 2257 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 2258 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 2259 2260 return IRQ_WAKE_THREAD; 2261 } 2262 2263 static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv) 2264 { 2265 struct vc4_hdmi *vc4_hdmi = priv; 2266 irqreturn_t ret; 2267 2268 spin_lock(&vc4_hdmi->hw_lock); 2269 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi); 2270 spin_unlock(&vc4_hdmi->hw_lock); 2271 2272 return ret; 2273 } 2274 2275 static irqreturn_t vc4_cec_irq_handler_rx_bare_locked(struct vc4_hdmi *vc4_hdmi) 2276 { 2277 u32 cntrl1; 2278 2279 lockdep_assert_held(&vc4_hdmi->hw_lock); 2280 2281 vc4_hdmi->cec_rx_msg.len = 0; 2282 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1); 2283 vc4_cec_read_msg(vc4_hdmi, cntrl1); 2284 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 2285 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 2286 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 2287 2288 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 2289 2290 return IRQ_WAKE_THREAD; 2291 } 2292 2293 static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv) 2294 { 2295 struct vc4_hdmi *vc4_hdmi = priv; 2296 irqreturn_t ret; 2297 2298 spin_lock(&vc4_hdmi->hw_lock); 2299 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi); 2300 spin_unlock(&vc4_hdmi->hw_lock); 2301 2302 return ret; 2303 } 2304 2305 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv) 2306 { 2307 struct vc4_hdmi *vc4_hdmi = priv; 2308 u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS); 2309 irqreturn_t ret; 2310 u32 cntrl5; 2311 2312 if (!(stat & VC4_HDMI_CPU_CEC)) 2313 return IRQ_NONE; 2314 2315 spin_lock(&vc4_hdmi->hw_lock); 2316 cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5); 2317 vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT; 2318 if (vc4_hdmi->cec_irq_was_rx) 2319 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi); 2320 else 2321 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi); 2322 2323 HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC); 2324 spin_unlock(&vc4_hdmi->hw_lock); 2325 2326 return ret; 2327 } 2328 2329 static int vc4_hdmi_cec_enable(struct cec_adapter *adap) 2330 { 2331 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 2332 /* clock period in microseconds */ 2333 const u32 usecs = 1000000 / CEC_CLOCK_FREQ; 2334 unsigned long flags; 2335 u32 val; 2336 int ret; 2337 2338 /* 2339 * NOTE: This function should really take vc4_hdmi->mutex, but doing so 2340 * results in a reentrancy since cec_s_phys_addr_from_edid() called in 2341 * .detect or .get_modes might call .adap_enable, which leads to this 2342 * function being called with that mutex held. 2343 * 2344 * Concurrency is not an issue for the moment since we don't share any 2345 * state with KMS, so we can ignore the lock for now, but we need to 2346 * keep it in mind if we were to change that assumption. 2347 */ 2348 2349 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev); 2350 if (ret) 2351 return ret; 2352 2353 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2354 2355 val = HDMI_READ(HDMI_CEC_CNTRL_5); 2356 val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET | 2357 VC4_HDMI_CEC_CNT_TO_4700_US_MASK | 2358 VC4_HDMI_CEC_CNT_TO_4500_US_MASK); 2359 val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) | 2360 ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT); 2361 2362 HDMI_WRITE(HDMI_CEC_CNTRL_5, val | 2363 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 2364 HDMI_WRITE(HDMI_CEC_CNTRL_5, val); 2365 HDMI_WRITE(HDMI_CEC_CNTRL_2, 2366 ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) | 2367 ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) | 2368 ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) | 2369 ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) | 2370 ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT)); 2371 HDMI_WRITE(HDMI_CEC_CNTRL_3, 2372 ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) | 2373 ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) | 2374 ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) | 2375 ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT)); 2376 HDMI_WRITE(HDMI_CEC_CNTRL_4, 2377 ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) | 2378 ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) | 2379 ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) | 2380 ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT)); 2381 2382 if (!vc4_hdmi->variant->external_irq_controller) 2383 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC); 2384 2385 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2386 2387 return 0; 2388 } 2389 2390 static int vc4_hdmi_cec_disable(struct cec_adapter *adap) 2391 { 2392 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 2393 unsigned long flags; 2394 2395 /* 2396 * NOTE: This function should really take vc4_hdmi->mutex, but doing so 2397 * results in a reentrancy since cec_s_phys_addr_from_edid() called in 2398 * .detect or .get_modes might call .adap_enable, which leads to this 2399 * function being called with that mutex held. 2400 * 2401 * Concurrency is not an issue for the moment since we don't share any 2402 * state with KMS, so we can ignore the lock for now, but we need to 2403 * keep it in mind if we were to change that assumption. 2404 */ 2405 2406 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2407 2408 if (!vc4_hdmi->variant->external_irq_controller) 2409 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC); 2410 2411 HDMI_WRITE(HDMI_CEC_CNTRL_5, HDMI_READ(HDMI_CEC_CNTRL_5) | 2412 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 2413 2414 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2415 2416 pm_runtime_put(&vc4_hdmi->pdev->dev); 2417 2418 return 0; 2419 } 2420 2421 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable) 2422 { 2423 if (enable) 2424 return vc4_hdmi_cec_enable(adap); 2425 else 2426 return vc4_hdmi_cec_disable(adap); 2427 } 2428 2429 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr) 2430 { 2431 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 2432 unsigned long flags; 2433 2434 /* 2435 * NOTE: This function should really take vc4_hdmi->mutex, but doing so 2436 * results in a reentrancy since cec_s_phys_addr_from_edid() called in 2437 * .detect or .get_modes might call .adap_enable, which leads to this 2438 * function being called with that mutex held. 2439 * 2440 * Concurrency is not an issue for the moment since we don't share any 2441 * state with KMS, so we can ignore the lock for now, but we need to 2442 * keep it in mind if we were to change that assumption. 2443 */ 2444 2445 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2446 HDMI_WRITE(HDMI_CEC_CNTRL_1, 2447 (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) | 2448 (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT); 2449 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2450 2451 return 0; 2452 } 2453 2454 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts, 2455 u32 signal_free_time, struct cec_msg *msg) 2456 { 2457 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 2458 struct drm_device *dev = vc4_hdmi->connector.dev; 2459 unsigned long flags; 2460 u32 val; 2461 unsigned int i; 2462 2463 /* 2464 * NOTE: This function should really take vc4_hdmi->mutex, but doing so 2465 * results in a reentrancy since cec_s_phys_addr_from_edid() called in 2466 * .detect or .get_modes might call .adap_enable, which leads to this 2467 * function being called with that mutex held. 2468 * 2469 * Concurrency is not an issue for the moment since we don't share any 2470 * state with KMS, so we can ignore the lock for now, but we need to 2471 * keep it in mind if we were to change that assumption. 2472 */ 2473 2474 if (msg->len > 16) { 2475 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len); 2476 return -ENOMEM; 2477 } 2478 2479 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2480 2481 for (i = 0; i < msg->len; i += 4) 2482 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2), 2483 (msg->msg[i]) | 2484 (msg->msg[i + 1] << 8) | 2485 (msg->msg[i + 2] << 16) | 2486 (msg->msg[i + 3] << 24)); 2487 2488 val = HDMI_READ(HDMI_CEC_CNTRL_1); 2489 val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 2490 HDMI_WRITE(HDMI_CEC_CNTRL_1, val); 2491 val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK; 2492 val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT; 2493 val |= VC4_HDMI_CEC_START_XMIT_BEGIN; 2494 2495 HDMI_WRITE(HDMI_CEC_CNTRL_1, val); 2496 2497 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2498 2499 return 0; 2500 } 2501 2502 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = { 2503 .adap_enable = vc4_hdmi_cec_adap_enable, 2504 .adap_log_addr = vc4_hdmi_cec_adap_log_addr, 2505 .adap_transmit = vc4_hdmi_cec_adap_transmit, 2506 }; 2507 2508 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi) 2509 { 2510 struct cec_connector_info conn_info; 2511 struct platform_device *pdev = vc4_hdmi->pdev; 2512 struct device *dev = &pdev->dev; 2513 unsigned long flags; 2514 u32 value; 2515 int ret; 2516 2517 if (!of_find_property(dev->of_node, "interrupts", NULL)) { 2518 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n"); 2519 return 0; 2520 } 2521 2522 vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops, 2523 vc4_hdmi, "vc4", 2524 CEC_CAP_DEFAULTS | 2525 CEC_CAP_CONNECTOR_INFO, 1); 2526 ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap); 2527 if (ret < 0) 2528 return ret; 2529 2530 cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector); 2531 cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info); 2532 2533 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2534 value = HDMI_READ(HDMI_CEC_CNTRL_1); 2535 /* Set the logical address to Unregistered */ 2536 value |= VC4_HDMI_CEC_ADDR_MASK; 2537 HDMI_WRITE(HDMI_CEC_CNTRL_1, value); 2538 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2539 2540 vc4_hdmi_cec_update_clk_div(vc4_hdmi); 2541 2542 if (vc4_hdmi->variant->external_irq_controller) { 2543 ret = request_threaded_irq(platform_get_irq_byname(pdev, "cec-rx"), 2544 vc4_cec_irq_handler_rx_bare, 2545 vc4_cec_irq_handler_rx_thread, 0, 2546 "vc4 hdmi cec rx", vc4_hdmi); 2547 if (ret) 2548 goto err_delete_cec_adap; 2549 2550 ret = request_threaded_irq(platform_get_irq_byname(pdev, "cec-tx"), 2551 vc4_cec_irq_handler_tx_bare, 2552 vc4_cec_irq_handler_tx_thread, 0, 2553 "vc4 hdmi cec tx", vc4_hdmi); 2554 if (ret) 2555 goto err_remove_cec_rx_handler; 2556 } else { 2557 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2558 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff); 2559 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2560 2561 ret = request_threaded_irq(platform_get_irq(pdev, 0), 2562 vc4_cec_irq_handler, 2563 vc4_cec_irq_handler_thread, 0, 2564 "vc4 hdmi cec", vc4_hdmi); 2565 if (ret) 2566 goto err_delete_cec_adap; 2567 } 2568 2569 ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev); 2570 if (ret < 0) 2571 goto err_remove_handlers; 2572 2573 return 0; 2574 2575 err_remove_handlers: 2576 if (vc4_hdmi->variant->external_irq_controller) 2577 free_irq(platform_get_irq_byname(pdev, "cec-tx"), vc4_hdmi); 2578 else 2579 free_irq(platform_get_irq(pdev, 0), vc4_hdmi); 2580 2581 err_remove_cec_rx_handler: 2582 if (vc4_hdmi->variant->external_irq_controller) 2583 free_irq(platform_get_irq_byname(pdev, "cec-rx"), vc4_hdmi); 2584 2585 err_delete_cec_adap: 2586 cec_delete_adapter(vc4_hdmi->cec_adap); 2587 2588 return ret; 2589 } 2590 2591 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi) 2592 { 2593 struct platform_device *pdev = vc4_hdmi->pdev; 2594 2595 if (vc4_hdmi->variant->external_irq_controller) { 2596 free_irq(platform_get_irq_byname(pdev, "cec-rx"), vc4_hdmi); 2597 free_irq(platform_get_irq_byname(pdev, "cec-tx"), vc4_hdmi); 2598 } else { 2599 free_irq(platform_get_irq(pdev, 0), vc4_hdmi); 2600 } 2601 2602 cec_unregister_adapter(vc4_hdmi->cec_adap); 2603 } 2604 #else 2605 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi) 2606 { 2607 return 0; 2608 } 2609 2610 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi) {}; 2611 2612 #endif 2613 2614 static int vc4_hdmi_build_regset(struct vc4_hdmi *vc4_hdmi, 2615 struct debugfs_regset32 *regset, 2616 enum vc4_hdmi_regs reg) 2617 { 2618 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant; 2619 struct debugfs_reg32 *regs, *new_regs; 2620 unsigned int count = 0; 2621 unsigned int i; 2622 2623 regs = kcalloc(variant->num_registers, sizeof(*regs), 2624 GFP_KERNEL); 2625 if (!regs) 2626 return -ENOMEM; 2627 2628 for (i = 0; i < variant->num_registers; i++) { 2629 const struct vc4_hdmi_register *field = &variant->registers[i]; 2630 2631 if (field->reg != reg) 2632 continue; 2633 2634 regs[count].name = field->name; 2635 regs[count].offset = field->offset; 2636 count++; 2637 } 2638 2639 new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL); 2640 if (!new_regs) 2641 return -ENOMEM; 2642 2643 regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg); 2644 regset->regs = new_regs; 2645 regset->nregs = count; 2646 2647 return 0; 2648 } 2649 2650 static int vc4_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi) 2651 { 2652 struct platform_device *pdev = vc4_hdmi->pdev; 2653 struct device *dev = &pdev->dev; 2654 int ret; 2655 2656 vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0); 2657 if (IS_ERR(vc4_hdmi->hdmicore_regs)) 2658 return PTR_ERR(vc4_hdmi->hdmicore_regs); 2659 2660 vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1); 2661 if (IS_ERR(vc4_hdmi->hd_regs)) 2662 return PTR_ERR(vc4_hdmi->hd_regs); 2663 2664 ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD); 2665 if (ret) 2666 return ret; 2667 2668 ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI); 2669 if (ret) 2670 return ret; 2671 2672 vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel"); 2673 if (IS_ERR(vc4_hdmi->pixel_clock)) { 2674 ret = PTR_ERR(vc4_hdmi->pixel_clock); 2675 if (ret != -EPROBE_DEFER) 2676 DRM_ERROR("Failed to get pixel clock\n"); 2677 return ret; 2678 } 2679 2680 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); 2681 if (IS_ERR(vc4_hdmi->hsm_clock)) { 2682 DRM_ERROR("Failed to get HDMI state machine clock\n"); 2683 return PTR_ERR(vc4_hdmi->hsm_clock); 2684 } 2685 vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock; 2686 vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock; 2687 2688 return 0; 2689 } 2690 2691 static int vc5_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi) 2692 { 2693 struct platform_device *pdev = vc4_hdmi->pdev; 2694 struct device *dev = &pdev->dev; 2695 struct resource *res; 2696 2697 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi"); 2698 if (!res) 2699 return -ENODEV; 2700 2701 vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start, 2702 resource_size(res)); 2703 if (!vc4_hdmi->hdmicore_regs) 2704 return -ENOMEM; 2705 2706 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd"); 2707 if (!res) 2708 return -ENODEV; 2709 2710 vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res)); 2711 if (!vc4_hdmi->hd_regs) 2712 return -ENOMEM; 2713 2714 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec"); 2715 if (!res) 2716 return -ENODEV; 2717 2718 vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res)); 2719 if (!vc4_hdmi->cec_regs) 2720 return -ENOMEM; 2721 2722 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc"); 2723 if (!res) 2724 return -ENODEV; 2725 2726 vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res)); 2727 if (!vc4_hdmi->csc_regs) 2728 return -ENOMEM; 2729 2730 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp"); 2731 if (!res) 2732 return -ENODEV; 2733 2734 vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res)); 2735 if (!vc4_hdmi->dvp_regs) 2736 return -ENOMEM; 2737 2738 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy"); 2739 if (!res) 2740 return -ENODEV; 2741 2742 vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res)); 2743 if (!vc4_hdmi->phy_regs) 2744 return -ENOMEM; 2745 2746 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet"); 2747 if (!res) 2748 return -ENODEV; 2749 2750 vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res)); 2751 if (!vc4_hdmi->ram_regs) 2752 return -ENOMEM; 2753 2754 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm"); 2755 if (!res) 2756 return -ENODEV; 2757 2758 vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res)); 2759 if (!vc4_hdmi->rm_regs) 2760 return -ENOMEM; 2761 2762 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); 2763 if (IS_ERR(vc4_hdmi->hsm_clock)) { 2764 DRM_ERROR("Failed to get HDMI state machine clock\n"); 2765 return PTR_ERR(vc4_hdmi->hsm_clock); 2766 } 2767 2768 vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb"); 2769 if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) { 2770 DRM_ERROR("Failed to get pixel bvb clock\n"); 2771 return PTR_ERR(vc4_hdmi->pixel_bvb_clock); 2772 } 2773 2774 vc4_hdmi->audio_clock = devm_clk_get(dev, "audio"); 2775 if (IS_ERR(vc4_hdmi->audio_clock)) { 2776 DRM_ERROR("Failed to get audio clock\n"); 2777 return PTR_ERR(vc4_hdmi->audio_clock); 2778 } 2779 2780 vc4_hdmi->cec_clock = devm_clk_get(dev, "cec"); 2781 if (IS_ERR(vc4_hdmi->cec_clock)) { 2782 DRM_ERROR("Failed to get CEC clock\n"); 2783 return PTR_ERR(vc4_hdmi->cec_clock); 2784 } 2785 2786 vc4_hdmi->reset = devm_reset_control_get(dev, NULL); 2787 if (IS_ERR(vc4_hdmi->reset)) { 2788 DRM_ERROR("Failed to get HDMI reset line\n"); 2789 return PTR_ERR(vc4_hdmi->reset); 2790 } 2791 2792 return 0; 2793 } 2794 2795 static int __maybe_unused vc4_hdmi_runtime_suspend(struct device *dev) 2796 { 2797 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 2798 2799 clk_disable_unprepare(vc4_hdmi->hsm_clock); 2800 2801 return 0; 2802 } 2803 2804 static int vc4_hdmi_runtime_resume(struct device *dev) 2805 { 2806 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 2807 int ret; 2808 2809 ret = clk_prepare_enable(vc4_hdmi->hsm_clock); 2810 if (ret) 2811 return ret; 2812 2813 return 0; 2814 } 2815 2816 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data) 2817 { 2818 const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev); 2819 struct platform_device *pdev = to_platform_device(dev); 2820 struct drm_device *drm = dev_get_drvdata(master); 2821 struct vc4_hdmi *vc4_hdmi; 2822 struct drm_encoder *encoder; 2823 struct device_node *ddc_node; 2824 int ret; 2825 2826 vc4_hdmi = devm_kzalloc(dev, sizeof(*vc4_hdmi), GFP_KERNEL); 2827 if (!vc4_hdmi) 2828 return -ENOMEM; 2829 mutex_init(&vc4_hdmi->mutex); 2830 spin_lock_init(&vc4_hdmi->hw_lock); 2831 INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq); 2832 2833 dev_set_drvdata(dev, vc4_hdmi); 2834 encoder = &vc4_hdmi->encoder.base.base; 2835 vc4_hdmi->encoder.base.type = variant->encoder_type; 2836 vc4_hdmi->encoder.base.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure; 2837 vc4_hdmi->encoder.base.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable; 2838 vc4_hdmi->encoder.base.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable; 2839 vc4_hdmi->encoder.base.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable; 2840 vc4_hdmi->encoder.base.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown; 2841 vc4_hdmi->pdev = pdev; 2842 vc4_hdmi->variant = variant; 2843 2844 /* 2845 * Since we don't know the state of the controller and its 2846 * display (if any), let's assume it's always enabled. 2847 * vc4_hdmi_disable_scrambling() will thus run at boot, make 2848 * sure it's disabled, and avoid any inconsistency. 2849 */ 2850 vc4_hdmi->scdc_enabled = true; 2851 2852 ret = variant->init_resources(vc4_hdmi); 2853 if (ret) 2854 return ret; 2855 2856 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0); 2857 if (!ddc_node) { 2858 DRM_ERROR("Failed to find ddc node in device tree\n"); 2859 return -ENODEV; 2860 } 2861 2862 vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node); 2863 of_node_put(ddc_node); 2864 if (!vc4_hdmi->ddc) { 2865 DRM_DEBUG("Failed to get ddc i2c adapter by node\n"); 2866 return -EPROBE_DEFER; 2867 } 2868 2869 /* Only use the GPIO HPD pin if present in the DT, otherwise 2870 * we'll use the HDMI core's register. 2871 */ 2872 vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN); 2873 if (IS_ERR(vc4_hdmi->hpd_gpio)) { 2874 ret = PTR_ERR(vc4_hdmi->hpd_gpio); 2875 goto err_put_ddc; 2876 } 2877 2878 vc4_hdmi->disable_wifi_frequencies = 2879 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence"); 2880 2881 if (variant->max_pixel_clock == 600000000) { 2882 struct vc4_dev *vc4 = to_vc4_dev(drm); 2883 long max_rate = clk_round_rate(vc4->hvs->core_clk, 550000000); 2884 2885 if (max_rate < 550000000) 2886 vc4_hdmi->disable_4kp60 = true; 2887 } 2888 2889 /* 2890 * If we boot without any cable connected to the HDMI connector, 2891 * the firmware will skip the HSM initialization and leave it 2892 * with a rate of 0, resulting in a bus lockup when we're 2893 * accessing the registers even if it's enabled. 2894 * 2895 * Let's put a sensible default at runtime_resume so that we 2896 * don't end up in this situation. 2897 */ 2898 ret = clk_set_min_rate(vc4_hdmi->hsm_clock, HSM_MIN_CLOCK_FREQ); 2899 if (ret) 2900 goto err_put_ddc; 2901 2902 /* 2903 * We need to have the device powered up at this point to call 2904 * our reset hook and for the CEC init. 2905 */ 2906 ret = vc4_hdmi_runtime_resume(dev); 2907 if (ret) 2908 goto err_put_ddc; 2909 2910 pm_runtime_get_noresume(dev); 2911 pm_runtime_set_active(dev); 2912 pm_runtime_enable(dev); 2913 2914 if (vc4_hdmi->variant->reset) 2915 vc4_hdmi->variant->reset(vc4_hdmi); 2916 2917 if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") || 2918 of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1")) && 2919 HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) { 2920 clk_prepare_enable(vc4_hdmi->pixel_clock); 2921 clk_prepare_enable(vc4_hdmi->hsm_clock); 2922 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock); 2923 } 2924 2925 drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS); 2926 drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs); 2927 2928 ret = vc4_hdmi_connector_init(drm, vc4_hdmi); 2929 if (ret) 2930 goto err_destroy_encoder; 2931 2932 ret = vc4_hdmi_hotplug_init(vc4_hdmi); 2933 if (ret) 2934 goto err_destroy_conn; 2935 2936 ret = vc4_hdmi_cec_init(vc4_hdmi); 2937 if (ret) 2938 goto err_free_hotplug; 2939 2940 ret = vc4_hdmi_audio_init(vc4_hdmi); 2941 if (ret) 2942 goto err_free_cec; 2943 2944 vc4_debugfs_add_file(drm, variant->debugfs_name, 2945 vc4_hdmi_debugfs_regs, 2946 vc4_hdmi); 2947 2948 pm_runtime_put_sync(dev); 2949 2950 return 0; 2951 2952 err_free_cec: 2953 vc4_hdmi_cec_exit(vc4_hdmi); 2954 err_free_hotplug: 2955 vc4_hdmi_hotplug_exit(vc4_hdmi); 2956 err_destroy_conn: 2957 vc4_hdmi_connector_destroy(&vc4_hdmi->connector); 2958 err_destroy_encoder: 2959 drm_encoder_cleanup(encoder); 2960 pm_runtime_put_sync(dev); 2961 pm_runtime_disable(dev); 2962 err_put_ddc: 2963 put_device(&vc4_hdmi->ddc->dev); 2964 2965 return ret; 2966 } 2967 2968 static void vc4_hdmi_unbind(struct device *dev, struct device *master, 2969 void *data) 2970 { 2971 struct vc4_hdmi *vc4_hdmi; 2972 2973 /* 2974 * ASoC makes it a bit hard to retrieve a pointer to the 2975 * vc4_hdmi structure. Registering the card will overwrite our 2976 * device drvdata with a pointer to the snd_soc_card structure, 2977 * which can then be used to retrieve whatever drvdata we want 2978 * to associate. 2979 * 2980 * However, that doesn't fly in the case where we wouldn't 2981 * register an ASoC card (because of an old DT that is missing 2982 * the dmas properties for example), then the card isn't 2983 * registered and the device drvdata wouldn't be set. 2984 * 2985 * We can deal with both cases by making sure a snd_soc_card 2986 * pointer and a vc4_hdmi structure are pointing to the same 2987 * memory address, so we can treat them indistinctly without any 2988 * issue. 2989 */ 2990 BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0); 2991 BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0); 2992 vc4_hdmi = dev_get_drvdata(dev); 2993 2994 kfree(vc4_hdmi->hdmi_regset.regs); 2995 kfree(vc4_hdmi->hd_regset.regs); 2996 2997 vc4_hdmi_cec_exit(vc4_hdmi); 2998 vc4_hdmi_hotplug_exit(vc4_hdmi); 2999 vc4_hdmi_connector_destroy(&vc4_hdmi->connector); 3000 drm_encoder_cleanup(&vc4_hdmi->encoder.base.base); 3001 3002 pm_runtime_disable(dev); 3003 3004 put_device(&vc4_hdmi->ddc->dev); 3005 } 3006 3007 static const struct component_ops vc4_hdmi_ops = { 3008 .bind = vc4_hdmi_bind, 3009 .unbind = vc4_hdmi_unbind, 3010 }; 3011 3012 static int vc4_hdmi_dev_probe(struct platform_device *pdev) 3013 { 3014 return component_add(&pdev->dev, &vc4_hdmi_ops); 3015 } 3016 3017 static int vc4_hdmi_dev_remove(struct platform_device *pdev) 3018 { 3019 component_del(&pdev->dev, &vc4_hdmi_ops); 3020 return 0; 3021 } 3022 3023 static const struct vc4_hdmi_variant bcm2835_variant = { 3024 .encoder_type = VC4_ENCODER_TYPE_HDMI0, 3025 .debugfs_name = "hdmi_regs", 3026 .card_name = "vc4-hdmi", 3027 .max_pixel_clock = 162000000, 3028 .registers = vc4_hdmi_fields, 3029 .num_registers = ARRAY_SIZE(vc4_hdmi_fields), 3030 3031 .init_resources = vc4_hdmi_init_resources, 3032 .csc_setup = vc4_hdmi_csc_setup, 3033 .reset = vc4_hdmi_reset, 3034 .set_timings = vc4_hdmi_set_timings, 3035 .phy_init = vc4_hdmi_phy_init, 3036 .phy_disable = vc4_hdmi_phy_disable, 3037 .phy_rng_enable = vc4_hdmi_phy_rng_enable, 3038 .phy_rng_disable = vc4_hdmi_phy_rng_disable, 3039 .channel_map = vc4_hdmi_channel_map, 3040 .supports_hdr = false, 3041 }; 3042 3043 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = { 3044 .encoder_type = VC4_ENCODER_TYPE_HDMI0, 3045 .debugfs_name = "hdmi0_regs", 3046 .card_name = "vc4-hdmi-0", 3047 .max_pixel_clock = 600000000, 3048 .registers = vc5_hdmi_hdmi0_fields, 3049 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi0_fields), 3050 .phy_lane_mapping = { 3051 PHY_LANE_0, 3052 PHY_LANE_1, 3053 PHY_LANE_2, 3054 PHY_LANE_CK, 3055 }, 3056 .unsupported_odd_h_timings = true, 3057 .external_irq_controller = true, 3058 3059 .init_resources = vc5_hdmi_init_resources, 3060 .csc_setup = vc5_hdmi_csc_setup, 3061 .reset = vc5_hdmi_reset, 3062 .set_timings = vc5_hdmi_set_timings, 3063 .phy_init = vc5_hdmi_phy_init, 3064 .phy_disable = vc5_hdmi_phy_disable, 3065 .phy_rng_enable = vc5_hdmi_phy_rng_enable, 3066 .phy_rng_disable = vc5_hdmi_phy_rng_disable, 3067 .channel_map = vc5_hdmi_channel_map, 3068 .supports_hdr = true, 3069 }; 3070 3071 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = { 3072 .encoder_type = VC4_ENCODER_TYPE_HDMI1, 3073 .debugfs_name = "hdmi1_regs", 3074 .card_name = "vc4-hdmi-1", 3075 .max_pixel_clock = HDMI_14_MAX_TMDS_CLK, 3076 .registers = vc5_hdmi_hdmi1_fields, 3077 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi1_fields), 3078 .phy_lane_mapping = { 3079 PHY_LANE_1, 3080 PHY_LANE_0, 3081 PHY_LANE_CK, 3082 PHY_LANE_2, 3083 }, 3084 .unsupported_odd_h_timings = true, 3085 .external_irq_controller = true, 3086 3087 .init_resources = vc5_hdmi_init_resources, 3088 .csc_setup = vc5_hdmi_csc_setup, 3089 .reset = vc5_hdmi_reset, 3090 .set_timings = vc5_hdmi_set_timings, 3091 .phy_init = vc5_hdmi_phy_init, 3092 .phy_disable = vc5_hdmi_phy_disable, 3093 .phy_rng_enable = vc5_hdmi_phy_rng_enable, 3094 .phy_rng_disable = vc5_hdmi_phy_rng_disable, 3095 .channel_map = vc5_hdmi_channel_map, 3096 .supports_hdr = true, 3097 }; 3098 3099 static const struct of_device_id vc4_hdmi_dt_match[] = { 3100 { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant }, 3101 { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant }, 3102 { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant }, 3103 {} 3104 }; 3105 3106 static const struct dev_pm_ops vc4_hdmi_pm_ops = { 3107 SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend, 3108 vc4_hdmi_runtime_resume, 3109 NULL) 3110 }; 3111 3112 struct platform_driver vc4_hdmi_driver = { 3113 .probe = vc4_hdmi_dev_probe, 3114 .remove = vc4_hdmi_dev_remove, 3115 .driver = { 3116 .name = "vc4_hdmi", 3117 .of_match_table = vc4_hdmi_dt_match, 3118 .pm = &vc4_hdmi_pm_ops, 3119 }, 3120 }; 3121