1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 Broadcom 4 * Copyright (c) 2014 The Linux Foundation. All rights reserved. 5 * Copyright (C) 2013 Red Hat 6 * Author: Rob Clark <robdclark@gmail.com> 7 */ 8 9 /** 10 * DOC: VC4 Falcon HDMI module 11 * 12 * The HDMI core has a state machine and a PHY. On BCM2835, most of 13 * the unit operates off of the HSM clock from CPRMAN. It also 14 * internally uses the PLLH_PIX clock for the PHY. 15 * 16 * HDMI infoframes are kept within a small packet ram, where each 17 * packet can be individually enabled for including in a frame. 18 * 19 * HDMI audio is implemented entirely within the HDMI IP block. A 20 * register in the HDMI encoder takes SPDIF frames from the DMA engine 21 * and transfers them over an internal MAI (multi-channel audio 22 * interconnect) bus to the encoder side for insertion into the video 23 * blank regions. 24 * 25 * The driver's HDMI encoder does not yet support power management. 26 * The HDMI encoder's power domain and the HSM/pixel clocks are kept 27 * continuously running, and only the HDMI logic and packet ram are 28 * powered off/on at disable/enable time. 29 * 30 * The driver does not yet support CEC control, though the HDMI 31 * encoder block has CEC support. 32 */ 33 34 #include <drm/drm_atomic_helper.h> 35 #include <drm/drm_edid.h> 36 #include <drm/drm_probe_helper.h> 37 #include <drm/drm_simple_kms_helper.h> 38 #include <drm/drm_scdc_helper.h> 39 #include <linux/clk.h> 40 #include <linux/component.h> 41 #include <linux/i2c.h> 42 #include <linux/of_address.h> 43 #include <linux/of_gpio.h> 44 #include <linux/of_platform.h> 45 #include <linux/pm_runtime.h> 46 #include <linux/rational.h> 47 #include <linux/reset.h> 48 #include <sound/dmaengine_pcm.h> 49 #include <sound/hdmi-codec.h> 50 #include <sound/pcm_drm_eld.h> 51 #include <sound/pcm_params.h> 52 #include <sound/soc.h> 53 #include "media/cec.h" 54 #include "vc4_drv.h" 55 #include "vc4_hdmi.h" 56 #include "vc4_hdmi_regs.h" 57 #include "vc4_regs.h" 58 59 #define VC5_HDMI_HORZA_HFP_SHIFT 16 60 #define VC5_HDMI_HORZA_HFP_MASK VC4_MASK(28, 16) 61 #define VC5_HDMI_HORZA_VPOS BIT(15) 62 #define VC5_HDMI_HORZA_HPOS BIT(14) 63 #define VC5_HDMI_HORZA_HAP_SHIFT 0 64 #define VC5_HDMI_HORZA_HAP_MASK VC4_MASK(13, 0) 65 66 #define VC5_HDMI_HORZB_HBP_SHIFT 16 67 #define VC5_HDMI_HORZB_HBP_MASK VC4_MASK(26, 16) 68 #define VC5_HDMI_HORZB_HSP_SHIFT 0 69 #define VC5_HDMI_HORZB_HSP_MASK VC4_MASK(10, 0) 70 71 #define VC5_HDMI_VERTA_VSP_SHIFT 24 72 #define VC5_HDMI_VERTA_VSP_MASK VC4_MASK(28, 24) 73 #define VC5_HDMI_VERTA_VFP_SHIFT 16 74 #define VC5_HDMI_VERTA_VFP_MASK VC4_MASK(22, 16) 75 #define VC5_HDMI_VERTA_VAL_SHIFT 0 76 #define VC5_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0) 77 78 #define VC5_HDMI_VERTB_VSPO_SHIFT 16 79 #define VC5_HDMI_VERTB_VSPO_MASK VC4_MASK(29, 16) 80 81 #define VC5_HDMI_SCRAMBLER_CTL_ENABLE BIT(0) 82 83 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT 8 84 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK VC4_MASK(10, 8) 85 86 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT 0 87 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK VC4_MASK(3, 0) 88 89 #define VC5_HDMI_GCP_CONFIG_GCP_ENABLE BIT(31) 90 91 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT 8 92 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK VC4_MASK(15, 8) 93 94 # define VC4_HD_M_SW_RST BIT(2) 95 # define VC4_HD_M_ENABLE BIT(0) 96 97 #define HSM_MIN_CLOCK_FREQ 120000000 98 #define CEC_CLOCK_FREQ 40000 99 100 #define HDMI_14_MAX_TMDS_CLK (340 * 1000 * 1000) 101 102 static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode) 103 { 104 return (mode->clock * 1000) > HDMI_14_MAX_TMDS_CLK; 105 } 106 107 static bool vc4_hdmi_is_full_range_rgb(struct vc4_hdmi *vc4_hdmi, 108 const struct drm_display_mode *mode) 109 { 110 struct vc4_hdmi_encoder *vc4_encoder = &vc4_hdmi->encoder; 111 112 return !vc4_encoder->hdmi_monitor || 113 drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_FULL; 114 } 115 116 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused) 117 { 118 struct drm_info_node *node = (struct drm_info_node *)m->private; 119 struct vc4_hdmi *vc4_hdmi = node->info_ent->data; 120 struct drm_printer p = drm_seq_file_printer(m); 121 122 drm_print_regset32(&p, &vc4_hdmi->hdmi_regset); 123 drm_print_regset32(&p, &vc4_hdmi->hd_regset); 124 125 return 0; 126 } 127 128 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi) 129 { 130 unsigned long flags; 131 132 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 133 134 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST); 135 udelay(1); 136 HDMI_WRITE(HDMI_M_CTL, 0); 137 138 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE); 139 140 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 141 VC4_HDMI_SW_RESET_HDMI | 142 VC4_HDMI_SW_RESET_FORMAT_DETECT); 143 144 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0); 145 146 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 147 } 148 149 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi) 150 { 151 unsigned long flags; 152 153 reset_control_reset(vc4_hdmi->reset); 154 155 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 156 157 HDMI_WRITE(HDMI_DVP_CTL, 0); 158 159 HDMI_WRITE(HDMI_CLOCK_STOP, 160 HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL); 161 162 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 163 } 164 165 #ifdef CONFIG_DRM_VC4_HDMI_CEC 166 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) 167 { 168 unsigned long cec_rate = clk_get_rate(vc4_hdmi->cec_clock); 169 unsigned long flags; 170 u16 clk_cnt; 171 u32 value; 172 173 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 174 175 value = HDMI_READ(HDMI_CEC_CNTRL_1); 176 value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK; 177 178 /* 179 * Set the clock divider: the hsm_clock rate and this divider 180 * setting will give a 40 kHz CEC clock. 181 */ 182 clk_cnt = cec_rate / CEC_CLOCK_FREQ; 183 value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT; 184 HDMI_WRITE(HDMI_CEC_CNTRL_1, value); 185 186 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 187 } 188 #else 189 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {} 190 #endif 191 192 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder); 193 194 static enum drm_connector_status 195 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force) 196 { 197 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 198 bool connected = false; 199 200 mutex_lock(&vc4_hdmi->mutex); 201 202 WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev)); 203 204 if (vc4_hdmi->hpd_gpio) { 205 if (gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio)) 206 connected = true; 207 } else { 208 unsigned long flags; 209 u32 hotplug; 210 211 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 212 hotplug = HDMI_READ(HDMI_HOTPLUG); 213 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 214 215 if (hotplug & VC4_HDMI_HOTPLUG_CONNECTED) 216 connected = true; 217 } 218 219 if (connected) { 220 if (connector->status != connector_status_connected) { 221 struct edid *edid = drm_get_edid(connector, vc4_hdmi->ddc); 222 223 if (edid) { 224 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid); 225 vc4_hdmi->encoder.hdmi_monitor = drm_detect_hdmi_monitor(edid); 226 kfree(edid); 227 } 228 } 229 230 vc4_hdmi_enable_scrambling(&vc4_hdmi->encoder.base.base); 231 pm_runtime_put(&vc4_hdmi->pdev->dev); 232 mutex_unlock(&vc4_hdmi->mutex); 233 return connector_status_connected; 234 } 235 236 cec_phys_addr_invalidate(vc4_hdmi->cec_adap); 237 pm_runtime_put(&vc4_hdmi->pdev->dev); 238 mutex_unlock(&vc4_hdmi->mutex); 239 return connector_status_disconnected; 240 } 241 242 static void vc4_hdmi_connector_destroy(struct drm_connector *connector) 243 { 244 drm_connector_unregister(connector); 245 drm_connector_cleanup(connector); 246 } 247 248 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector) 249 { 250 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 251 struct vc4_hdmi_encoder *vc4_encoder = &vc4_hdmi->encoder; 252 int ret = 0; 253 struct edid *edid; 254 255 mutex_lock(&vc4_hdmi->mutex); 256 257 edid = drm_get_edid(connector, vc4_hdmi->ddc); 258 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid); 259 if (!edid) { 260 ret = -ENODEV; 261 goto out; 262 } 263 264 vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid); 265 266 drm_connector_update_edid_property(connector, edid); 267 ret = drm_add_edid_modes(connector, edid); 268 kfree(edid); 269 270 if (vc4_hdmi->disable_4kp60) { 271 struct drm_device *drm = connector->dev; 272 struct drm_display_mode *mode; 273 274 list_for_each_entry(mode, &connector->probed_modes, head) { 275 if (vc4_hdmi_mode_needs_scrambling(mode)) { 276 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz."); 277 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60."); 278 } 279 } 280 } 281 282 out: 283 mutex_unlock(&vc4_hdmi->mutex); 284 285 return ret; 286 } 287 288 static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector, 289 struct drm_atomic_state *state) 290 { 291 struct drm_connector_state *old_state = 292 drm_atomic_get_old_connector_state(state, connector); 293 struct drm_connector_state *new_state = 294 drm_atomic_get_new_connector_state(state, connector); 295 struct drm_crtc *crtc = new_state->crtc; 296 297 if (!crtc) 298 return 0; 299 300 if (old_state->colorspace != new_state->colorspace || 301 !drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) { 302 struct drm_crtc_state *crtc_state; 303 304 crtc_state = drm_atomic_get_crtc_state(state, crtc); 305 if (IS_ERR(crtc_state)) 306 return PTR_ERR(crtc_state); 307 308 crtc_state->mode_changed = true; 309 } 310 311 return 0; 312 } 313 314 static void vc4_hdmi_connector_reset(struct drm_connector *connector) 315 { 316 struct vc4_hdmi_connector_state *old_state = 317 conn_state_to_vc4_hdmi_conn_state(connector->state); 318 struct vc4_hdmi_connector_state *new_state = 319 kzalloc(sizeof(*new_state), GFP_KERNEL); 320 321 if (connector->state) 322 __drm_atomic_helper_connector_destroy_state(connector->state); 323 324 kfree(old_state); 325 __drm_atomic_helper_connector_reset(connector, &new_state->base); 326 327 if (!new_state) 328 return; 329 330 new_state->base.max_bpc = 8; 331 new_state->base.max_requested_bpc = 8; 332 drm_atomic_helper_connector_tv_reset(connector); 333 } 334 335 static struct drm_connector_state * 336 vc4_hdmi_connector_duplicate_state(struct drm_connector *connector) 337 { 338 struct drm_connector_state *conn_state = connector->state; 339 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state); 340 struct vc4_hdmi_connector_state *new_state; 341 342 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL); 343 if (!new_state) 344 return NULL; 345 346 new_state->pixel_rate = vc4_state->pixel_rate; 347 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base); 348 349 return &new_state->base; 350 } 351 352 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = { 353 .detect = vc4_hdmi_connector_detect, 354 .fill_modes = drm_helper_probe_single_connector_modes, 355 .destroy = vc4_hdmi_connector_destroy, 356 .reset = vc4_hdmi_connector_reset, 357 .atomic_duplicate_state = vc4_hdmi_connector_duplicate_state, 358 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 359 }; 360 361 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = { 362 .get_modes = vc4_hdmi_connector_get_modes, 363 .atomic_check = vc4_hdmi_connector_atomic_check, 364 }; 365 366 static int vc4_hdmi_connector_init(struct drm_device *dev, 367 struct vc4_hdmi *vc4_hdmi) 368 { 369 struct drm_connector *connector = &vc4_hdmi->connector; 370 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base; 371 int ret; 372 373 drm_connector_init_with_ddc(dev, connector, 374 &vc4_hdmi_connector_funcs, 375 DRM_MODE_CONNECTOR_HDMIA, 376 vc4_hdmi->ddc); 377 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs); 378 379 /* 380 * Some of the properties below require access to state, like bpc. 381 * Allocate some default initial connector state with our reset helper. 382 */ 383 if (connector->funcs->reset) 384 connector->funcs->reset(connector); 385 386 /* Create and attach TV margin props to this connector. */ 387 ret = drm_mode_create_tv_margin_properties(dev); 388 if (ret) 389 return ret; 390 391 ret = drm_mode_create_hdmi_colorspace_property(connector); 392 if (ret) 393 return ret; 394 395 drm_connector_attach_colorspace_property(connector); 396 drm_connector_attach_tv_margin_properties(connector); 397 drm_connector_attach_max_bpc_property(connector, 8, 12); 398 399 connector->polled = (DRM_CONNECTOR_POLL_CONNECT | 400 DRM_CONNECTOR_POLL_DISCONNECT); 401 402 connector->interlace_allowed = 1; 403 connector->doublescan_allowed = 0; 404 405 if (vc4_hdmi->variant->supports_hdr) 406 drm_connector_attach_hdr_output_metadata_property(connector); 407 408 drm_connector_attach_encoder(connector, encoder); 409 410 return 0; 411 } 412 413 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder, 414 enum hdmi_infoframe_type type, 415 bool poll) 416 { 417 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 418 u32 packet_id = type - 0x80; 419 unsigned long flags; 420 421 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 422 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 423 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id)); 424 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 425 426 if (!poll) 427 return 0; 428 429 return wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) & 430 BIT(packet_id)), 100); 431 } 432 433 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder, 434 union hdmi_infoframe *frame) 435 { 436 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 437 u32 packet_id = frame->any.type - 0x80; 438 const struct vc4_hdmi_register *ram_packet_start = 439 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START]; 440 u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id; 441 void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi, 442 ram_packet_start->reg); 443 uint8_t buffer[VC4_HDMI_PACKET_STRIDE]; 444 unsigned long flags; 445 ssize_t len, i; 446 int ret; 447 448 WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) & 449 VC4_HDMI_RAM_PACKET_ENABLE), 450 "Packet RAM has to be on to store the packet."); 451 452 len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer)); 453 if (len < 0) 454 return; 455 456 ret = vc4_hdmi_stop_packet(encoder, frame->any.type, true); 457 if (ret) { 458 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret); 459 return; 460 } 461 462 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 463 464 for (i = 0; i < len; i += 7) { 465 writel(buffer[i + 0] << 0 | 466 buffer[i + 1] << 8 | 467 buffer[i + 2] << 16, 468 base + packet_reg); 469 packet_reg += 4; 470 471 writel(buffer[i + 3] << 0 | 472 buffer[i + 4] << 8 | 473 buffer[i + 5] << 16 | 474 buffer[i + 6] << 24, 475 base + packet_reg); 476 packet_reg += 4; 477 } 478 479 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 480 HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id)); 481 482 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 483 484 ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) & 485 BIT(packet_id)), 100); 486 if (ret) 487 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret); 488 } 489 490 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder) 491 { 492 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 493 struct drm_connector *connector = &vc4_hdmi->connector; 494 struct drm_connector_state *cstate = connector->state; 495 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 496 union hdmi_infoframe frame; 497 int ret; 498 499 lockdep_assert_held(&vc4_hdmi->mutex); 500 501 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, 502 connector, mode); 503 if (ret < 0) { 504 DRM_ERROR("couldn't fill AVI infoframe\n"); 505 return; 506 } 507 508 drm_hdmi_avi_infoframe_quant_range(&frame.avi, 509 connector, mode, 510 vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode) ? 511 HDMI_QUANTIZATION_RANGE_FULL : 512 HDMI_QUANTIZATION_RANGE_LIMITED); 513 drm_hdmi_avi_infoframe_colorimetry(&frame.avi, cstate); 514 drm_hdmi_avi_infoframe_bars(&frame.avi, cstate); 515 516 vc4_hdmi_write_infoframe(encoder, &frame); 517 } 518 519 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder) 520 { 521 union hdmi_infoframe frame; 522 int ret; 523 524 ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore"); 525 if (ret < 0) { 526 DRM_ERROR("couldn't fill SPD infoframe\n"); 527 return; 528 } 529 530 frame.spd.sdi = HDMI_SPD_SDI_PC; 531 532 vc4_hdmi_write_infoframe(encoder, &frame); 533 } 534 535 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder) 536 { 537 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 538 struct hdmi_audio_infoframe *audio = &vc4_hdmi->audio.infoframe; 539 union hdmi_infoframe frame; 540 541 memcpy(&frame.audio, audio, sizeof(*audio)); 542 vc4_hdmi_write_infoframe(encoder, &frame); 543 } 544 545 static void vc4_hdmi_set_hdr_infoframe(struct drm_encoder *encoder) 546 { 547 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 548 struct drm_connector *connector = &vc4_hdmi->connector; 549 struct drm_connector_state *conn_state = connector->state; 550 union hdmi_infoframe frame; 551 552 lockdep_assert_held(&vc4_hdmi->mutex); 553 554 if (!vc4_hdmi->variant->supports_hdr) 555 return; 556 557 if (!conn_state->hdr_output_metadata) 558 return; 559 560 if (drm_hdmi_infoframe_set_hdr_metadata(&frame.drm, conn_state)) 561 return; 562 563 vc4_hdmi_write_infoframe(encoder, &frame); 564 } 565 566 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder) 567 { 568 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 569 570 lockdep_assert_held(&vc4_hdmi->mutex); 571 572 vc4_hdmi_set_avi_infoframe(encoder); 573 vc4_hdmi_set_spd_infoframe(encoder); 574 /* 575 * If audio was streaming, then we need to reenabled the audio 576 * infoframe here during encoder_enable. 577 */ 578 if (vc4_hdmi->audio.streaming) 579 vc4_hdmi_set_audio_infoframe(encoder); 580 581 vc4_hdmi_set_hdr_infoframe(encoder); 582 } 583 584 static bool vc4_hdmi_supports_scrambling(struct drm_encoder *encoder, 585 struct drm_display_mode *mode) 586 { 587 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 588 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 589 struct drm_display_info *display = &vc4_hdmi->connector.display_info; 590 591 lockdep_assert_held(&vc4_hdmi->mutex); 592 593 if (!vc4_encoder->hdmi_monitor) 594 return false; 595 596 if (!display->hdmi.scdc.supported || 597 !display->hdmi.scdc.scrambling.supported) 598 return false; 599 600 return true; 601 } 602 603 #define SCRAMBLING_POLLING_DELAY_MS 1000 604 605 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder) 606 { 607 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 608 struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 609 unsigned long flags; 610 611 lockdep_assert_held(&vc4_hdmi->mutex); 612 613 if (!vc4_hdmi_supports_scrambling(encoder, mode)) 614 return; 615 616 if (!vc4_hdmi_mode_needs_scrambling(mode)) 617 return; 618 619 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true); 620 drm_scdc_set_scrambling(vc4_hdmi->ddc, true); 621 622 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 623 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) | 624 VC5_HDMI_SCRAMBLER_CTL_ENABLE); 625 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 626 627 vc4_hdmi->scdc_enabled = true; 628 629 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work, 630 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS)); 631 } 632 633 static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder) 634 { 635 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 636 unsigned long flags; 637 638 lockdep_assert_held(&vc4_hdmi->mutex); 639 640 if (!vc4_hdmi->scdc_enabled) 641 return; 642 643 vc4_hdmi->scdc_enabled = false; 644 645 if (delayed_work_pending(&vc4_hdmi->scrambling_work)) 646 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work); 647 648 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 649 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) & 650 ~VC5_HDMI_SCRAMBLER_CTL_ENABLE); 651 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 652 653 drm_scdc_set_scrambling(vc4_hdmi->ddc, false); 654 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, false); 655 } 656 657 static void vc4_hdmi_scrambling_wq(struct work_struct *work) 658 { 659 struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work), 660 struct vc4_hdmi, 661 scrambling_work); 662 663 if (drm_scdc_get_scrambling_status(vc4_hdmi->ddc)) 664 return; 665 666 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true); 667 drm_scdc_set_scrambling(vc4_hdmi->ddc, true); 668 669 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work, 670 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS)); 671 } 672 673 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder, 674 struct drm_atomic_state *state) 675 { 676 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 677 unsigned long flags; 678 679 mutex_lock(&vc4_hdmi->mutex); 680 681 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 682 683 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0); 684 685 HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB); 686 687 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 688 689 mdelay(1); 690 691 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 692 HDMI_WRITE(HDMI_VID_CTL, 693 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE); 694 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 695 696 vc4_hdmi_disable_scrambling(encoder); 697 698 mutex_unlock(&vc4_hdmi->mutex); 699 } 700 701 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder, 702 struct drm_atomic_state *state) 703 { 704 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 705 unsigned long flags; 706 int ret; 707 708 mutex_lock(&vc4_hdmi->mutex); 709 710 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 711 HDMI_WRITE(HDMI_VID_CTL, 712 HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX); 713 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 714 715 if (vc4_hdmi->variant->phy_disable) 716 vc4_hdmi->variant->phy_disable(vc4_hdmi); 717 718 clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock); 719 clk_disable_unprepare(vc4_hdmi->pixel_clock); 720 721 ret = pm_runtime_put(&vc4_hdmi->pdev->dev); 722 if (ret < 0) 723 DRM_ERROR("Failed to release power domain: %d\n", ret); 724 725 mutex_unlock(&vc4_hdmi->mutex); 726 } 727 728 static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder) 729 { 730 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 731 732 mutex_lock(&vc4_hdmi->mutex); 733 vc4_hdmi->output_enabled = false; 734 mutex_unlock(&vc4_hdmi->mutex); 735 } 736 737 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, 738 struct drm_connector_state *state, 739 const struct drm_display_mode *mode) 740 { 741 unsigned long flags; 742 u32 csc_ctl; 743 744 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 745 746 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR, 747 VC4_HD_CSC_CTL_ORDER); 748 749 if (!vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode)) { 750 /* CEA VICs other than #1 requre limited range RGB 751 * output unless overridden by an AVI infoframe. 752 * Apply a colorspace conversion to squash 0-255 down 753 * to 16-235. The matrix here is: 754 * 755 * [ 0 0 0.8594 16] 756 * [ 0 0.8594 0 16] 757 * [ 0.8594 0 0 16] 758 * [ 0 0 0 1] 759 */ 760 csc_ctl |= VC4_HD_CSC_CTL_ENABLE; 761 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC; 762 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM, 763 VC4_HD_CSC_CTL_MODE); 764 765 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000); 766 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0); 767 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000); 768 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000); 769 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0); 770 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000); 771 } 772 773 /* The RGB order applies even when CSC is disabled. */ 774 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl); 775 776 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 777 } 778 779 /* 780 * If we need to output Full Range RGB, then use the unity matrix 781 * 782 * [ 1 0 0 0] 783 * [ 0 1 0 0] 784 * [ 0 0 1 0] 785 * 786 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets 787 */ 788 static const u16 vc5_hdmi_csc_full_rgb_unity[3][4] = { 789 { 0x2000, 0x0000, 0x0000, 0x0000 }, 790 { 0x0000, 0x2000, 0x0000, 0x0000 }, 791 { 0x0000, 0x0000, 0x2000, 0x0000 }, 792 }; 793 794 /* 795 * CEA VICs other than #1 require limited range RGB output unless 796 * overridden by an AVI infoframe. Apply a colorspace conversion to 797 * squash 0-255 down to 16-235. The matrix here is: 798 * 799 * [ 0.8594 0 0 16] 800 * [ 0 0.8594 0 16] 801 * [ 0 0 0.8594 16] 802 * 803 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets 804 */ 805 static const u16 vc5_hdmi_csc_full_rgb_to_limited_rgb[3][4] = { 806 { 0x1b80, 0x0000, 0x0000, 0x0400 }, 807 { 0x0000, 0x1b80, 0x0000, 0x0400 }, 808 { 0x0000, 0x0000, 0x1b80, 0x0400 }, 809 }; 810 811 static void vc5_hdmi_set_csc_coeffs(struct vc4_hdmi *vc4_hdmi, 812 const u16 coeffs[3][4]) 813 { 814 lockdep_assert_held(&vc4_hdmi->hw_lock); 815 816 HDMI_WRITE(HDMI_CSC_12_11, (coeffs[0][1] << 16) | coeffs[0][0]); 817 HDMI_WRITE(HDMI_CSC_14_13, (coeffs[0][3] << 16) | coeffs[0][2]); 818 HDMI_WRITE(HDMI_CSC_22_21, (coeffs[1][1] << 16) | coeffs[1][0]); 819 HDMI_WRITE(HDMI_CSC_24_23, (coeffs[1][3] << 16) | coeffs[1][2]); 820 HDMI_WRITE(HDMI_CSC_32_31, (coeffs[2][1] << 16) | coeffs[2][0]); 821 HDMI_WRITE(HDMI_CSC_34_33, (coeffs[2][3] << 16) | coeffs[2][2]); 822 } 823 824 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, 825 struct drm_connector_state *state, 826 const struct drm_display_mode *mode) 827 { 828 unsigned long flags; 829 u32 csc_ctl = VC5_MT_CP_CSC_CTL_ENABLE | VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM, 830 VC5_MT_CP_CSC_CTL_MODE); 831 832 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 833 834 HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, 0x354021); 835 836 if (!vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode)) 837 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_limited_rgb); 838 else 839 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_unity); 840 841 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl); 842 843 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 844 } 845 846 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi, 847 struct drm_connector_state *state, 848 struct drm_display_mode *mode) 849 { 850 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 851 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 852 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 853 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 854 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 855 VC4_HDMI_VERTA_VSP) | 856 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 857 VC4_HDMI_VERTA_VFP) | 858 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL)); 859 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 860 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end, 861 VC4_HDMI_VERTB_VBP)); 862 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 863 VC4_SET_FIELD(mode->crtc_vtotal - 864 mode->crtc_vsync_end - 865 interlaced, 866 VC4_HDMI_VERTB_VBP)); 867 unsigned long flags; 868 869 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 870 871 HDMI_WRITE(HDMI_HORZA, 872 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) | 873 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) | 874 VC4_SET_FIELD(mode->hdisplay * pixel_rep, 875 VC4_HDMI_HORZA_HAP)); 876 877 HDMI_WRITE(HDMI_HORZB, 878 VC4_SET_FIELD((mode->htotal - 879 mode->hsync_end) * pixel_rep, 880 VC4_HDMI_HORZB_HBP) | 881 VC4_SET_FIELD((mode->hsync_end - 882 mode->hsync_start) * pixel_rep, 883 VC4_HDMI_HORZB_HSP) | 884 VC4_SET_FIELD((mode->hsync_start - 885 mode->hdisplay) * pixel_rep, 886 VC4_HDMI_HORZB_HFP)); 887 888 HDMI_WRITE(HDMI_VERTA0, verta); 889 HDMI_WRITE(HDMI_VERTA1, verta); 890 891 HDMI_WRITE(HDMI_VERTB0, vertb_even); 892 HDMI_WRITE(HDMI_VERTB1, vertb); 893 894 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 895 } 896 897 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi, 898 struct drm_connector_state *state, 899 struct drm_display_mode *mode) 900 { 901 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 902 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 903 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 904 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 905 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 906 VC5_HDMI_VERTA_VSP) | 907 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 908 VC5_HDMI_VERTA_VFP) | 909 VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL)); 910 u32 vertb = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) | 911 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end, 912 VC4_HDMI_VERTB_VBP)); 913 u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) | 914 VC4_SET_FIELD(mode->crtc_vtotal - 915 mode->crtc_vsync_end - 916 interlaced, 917 VC4_HDMI_VERTB_VBP)); 918 unsigned long flags; 919 unsigned char gcp; 920 bool gcp_en; 921 u32 reg; 922 923 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 924 925 HDMI_WRITE(HDMI_HORZA, 926 (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) | 927 (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) | 928 VC4_SET_FIELD(mode->hdisplay * pixel_rep, 929 VC5_HDMI_HORZA_HAP) | 930 VC4_SET_FIELD((mode->hsync_start - 931 mode->hdisplay) * pixel_rep, 932 VC5_HDMI_HORZA_HFP)); 933 934 HDMI_WRITE(HDMI_HORZB, 935 VC4_SET_FIELD((mode->htotal - 936 mode->hsync_end) * pixel_rep, 937 VC5_HDMI_HORZB_HBP) | 938 VC4_SET_FIELD((mode->hsync_end - 939 mode->hsync_start) * pixel_rep, 940 VC5_HDMI_HORZB_HSP)); 941 942 HDMI_WRITE(HDMI_VERTA0, verta); 943 HDMI_WRITE(HDMI_VERTA1, verta); 944 945 HDMI_WRITE(HDMI_VERTB0, vertb_even); 946 HDMI_WRITE(HDMI_VERTB1, vertb); 947 948 switch (state->max_bpc) { 949 case 12: 950 gcp = 6; 951 gcp_en = true; 952 break; 953 case 10: 954 gcp = 5; 955 gcp_en = true; 956 break; 957 case 8: 958 default: 959 gcp = 4; 960 gcp_en = false; 961 break; 962 } 963 964 reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1); 965 reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK | 966 VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK); 967 reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) | 968 VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH); 969 HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg); 970 971 reg = HDMI_READ(HDMI_GCP_WORD_1); 972 reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK; 973 reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1); 974 HDMI_WRITE(HDMI_GCP_WORD_1, reg); 975 976 reg = HDMI_READ(HDMI_GCP_CONFIG); 977 reg &= ~VC5_HDMI_GCP_CONFIG_GCP_ENABLE; 978 reg |= gcp_en ? VC5_HDMI_GCP_CONFIG_GCP_ENABLE : 0; 979 HDMI_WRITE(HDMI_GCP_CONFIG, reg); 980 981 HDMI_WRITE(HDMI_CLOCK_STOP, 0); 982 983 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 984 } 985 986 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi) 987 { 988 unsigned long flags; 989 u32 drift; 990 int ret; 991 992 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 993 994 drift = HDMI_READ(HDMI_FIFO_CTL); 995 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK; 996 997 HDMI_WRITE(HDMI_FIFO_CTL, 998 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 999 HDMI_WRITE(HDMI_FIFO_CTL, 1000 drift | VC4_HDMI_FIFO_CTL_RECENTER); 1001 1002 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1003 1004 usleep_range(1000, 1100); 1005 1006 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1007 1008 HDMI_WRITE(HDMI_FIFO_CTL, 1009 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 1010 HDMI_WRITE(HDMI_FIFO_CTL, 1011 drift | VC4_HDMI_FIFO_CTL_RECENTER); 1012 1013 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1014 1015 ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) & 1016 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1); 1017 WARN_ONCE(ret, "Timeout waiting for " 1018 "VC4_HDMI_FIFO_CTL_RECENTER_DONE"); 1019 } 1020 1021 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder, 1022 struct drm_atomic_state *state) 1023 { 1024 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1025 struct drm_connector *connector = &vc4_hdmi->connector; 1026 struct drm_connector_state *conn_state = 1027 drm_atomic_get_new_connector_state(state, connector); 1028 struct vc4_hdmi_connector_state *vc4_conn_state = 1029 conn_state_to_vc4_hdmi_conn_state(conn_state); 1030 struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1031 unsigned long pixel_rate = vc4_conn_state->pixel_rate; 1032 unsigned long bvb_rate, hsm_rate; 1033 unsigned long flags; 1034 int ret; 1035 1036 mutex_lock(&vc4_hdmi->mutex); 1037 1038 /* 1039 * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must 1040 * be faster than pixel clock, infinitesimally faster, tested in 1041 * simulation. Otherwise, exact value is unimportant for HDMI 1042 * operation." This conflicts with bcm2835's vc4 documentation, which 1043 * states HSM's clock has to be at least 108% of the pixel clock. 1044 * 1045 * Real life tests reveal that vc4's firmware statement holds up, and 1046 * users are able to use pixel clocks closer to HSM's, namely for 1047 * 1920x1200@60Hz. So it was decided to have leave a 1% margin between 1048 * both clocks. Which, for RPi0-3 implies a maximum pixel clock of 1049 * 162MHz. 1050 * 1051 * Additionally, the AXI clock needs to be at least 25% of 1052 * pixel clock, but HSM ends up being the limiting factor. 1053 */ 1054 hsm_rate = max_t(unsigned long, 120000000, (pixel_rate / 100) * 101); 1055 ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate); 1056 if (ret) { 1057 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret); 1058 goto out; 1059 } 1060 1061 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev); 1062 if (ret < 0) { 1063 DRM_ERROR("Failed to retain power domain: %d\n", ret); 1064 goto out; 1065 } 1066 1067 ret = clk_set_rate(vc4_hdmi->pixel_clock, pixel_rate); 1068 if (ret) { 1069 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret); 1070 goto err_put_runtime_pm; 1071 } 1072 1073 ret = clk_prepare_enable(vc4_hdmi->pixel_clock); 1074 if (ret) { 1075 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret); 1076 goto err_put_runtime_pm; 1077 } 1078 1079 1080 vc4_hdmi_cec_update_clk_div(vc4_hdmi); 1081 1082 if (pixel_rate > 297000000) 1083 bvb_rate = 300000000; 1084 else if (pixel_rate > 148500000) 1085 bvb_rate = 150000000; 1086 else 1087 bvb_rate = 75000000; 1088 1089 ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate); 1090 if (ret) { 1091 DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret); 1092 goto err_disable_pixel_clock; 1093 } 1094 1095 ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock); 1096 if (ret) { 1097 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret); 1098 goto err_disable_pixel_clock; 1099 } 1100 1101 if (vc4_hdmi->variant->phy_init) 1102 vc4_hdmi->variant->phy_init(vc4_hdmi, vc4_conn_state); 1103 1104 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1105 1106 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1107 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 1108 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT | 1109 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS); 1110 1111 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1112 1113 if (vc4_hdmi->variant->set_timings) 1114 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode); 1115 1116 mutex_unlock(&vc4_hdmi->mutex); 1117 1118 return; 1119 1120 err_disable_pixel_clock: 1121 clk_disable_unprepare(vc4_hdmi->pixel_clock); 1122 err_put_runtime_pm: 1123 pm_runtime_put(&vc4_hdmi->pdev->dev); 1124 out: 1125 mutex_unlock(&vc4_hdmi->mutex); 1126 return; 1127 } 1128 1129 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder, 1130 struct drm_atomic_state *state) 1131 { 1132 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1133 struct drm_connector *connector = &vc4_hdmi->connector; 1134 struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1135 struct drm_connector_state *conn_state = 1136 drm_atomic_get_new_connector_state(state, connector); 1137 unsigned long flags; 1138 1139 mutex_lock(&vc4_hdmi->mutex); 1140 1141 if (vc4_hdmi->variant->csc_setup) 1142 vc4_hdmi->variant->csc_setup(vc4_hdmi, conn_state, mode); 1143 1144 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1145 HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N); 1146 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1147 1148 mutex_unlock(&vc4_hdmi->mutex); 1149 } 1150 1151 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder, 1152 struct drm_atomic_state *state) 1153 { 1154 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1155 struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1156 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 1157 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 1158 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 1159 unsigned long flags; 1160 int ret; 1161 1162 mutex_lock(&vc4_hdmi->mutex); 1163 1164 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1165 1166 HDMI_WRITE(HDMI_VID_CTL, 1167 VC4_HD_VID_CTL_ENABLE | 1168 VC4_HD_VID_CTL_CLRRGB | 1169 VC4_HD_VID_CTL_UNDERFLOW_ENABLE | 1170 VC4_HD_VID_CTL_FRAME_COUNTER_RESET | 1171 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) | 1172 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW)); 1173 1174 HDMI_WRITE(HDMI_VID_CTL, 1175 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX); 1176 1177 if (vc4_encoder->hdmi_monitor) { 1178 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1179 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 1180 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 1181 1182 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1183 1184 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1185 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000); 1186 WARN_ONCE(ret, "Timeout waiting for " 1187 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 1188 } else { 1189 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 1190 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & 1191 ~(VC4_HDMI_RAM_PACKET_ENABLE)); 1192 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1193 HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1194 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 1195 1196 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1197 1198 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1199 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000); 1200 WARN_ONCE(ret, "Timeout waiting for " 1201 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 1202 } 1203 1204 if (vc4_encoder->hdmi_monitor) { 1205 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1206 1207 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1208 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE)); 1209 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1210 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 1211 VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT); 1212 1213 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 1214 VC4_HDMI_RAM_PACKET_ENABLE); 1215 1216 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1217 1218 vc4_hdmi_set_infoframes(encoder); 1219 } 1220 1221 vc4_hdmi_recenter_fifo(vc4_hdmi); 1222 vc4_hdmi_enable_scrambling(encoder); 1223 1224 mutex_unlock(&vc4_hdmi->mutex); 1225 } 1226 1227 static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder) 1228 { 1229 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1230 1231 mutex_lock(&vc4_hdmi->mutex); 1232 vc4_hdmi->output_enabled = true; 1233 mutex_unlock(&vc4_hdmi->mutex); 1234 } 1235 1236 static void vc4_hdmi_encoder_atomic_mode_set(struct drm_encoder *encoder, 1237 struct drm_crtc_state *crtc_state, 1238 struct drm_connector_state *conn_state) 1239 { 1240 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1241 1242 mutex_lock(&vc4_hdmi->mutex); 1243 drm_mode_copy(&vc4_hdmi->saved_adjusted_mode, 1244 &crtc_state->adjusted_mode); 1245 mutex_unlock(&vc4_hdmi->mutex); 1246 } 1247 1248 #define WIFI_2_4GHz_CH1_MIN_FREQ 2400000000ULL 1249 #define WIFI_2_4GHz_CH1_MAX_FREQ 2422000000ULL 1250 1251 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder, 1252 struct drm_crtc_state *crtc_state, 1253 struct drm_connector_state *conn_state) 1254 { 1255 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state); 1256 struct drm_display_mode *mode = &crtc_state->adjusted_mode; 1257 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1258 unsigned long long pixel_rate = mode->clock * 1000; 1259 unsigned long long tmds_rate; 1260 1261 if (vc4_hdmi->variant->unsupported_odd_h_timings && 1262 ((mode->hdisplay % 2) || (mode->hsync_start % 2) || 1263 (mode->hsync_end % 2) || (mode->htotal % 2))) 1264 return -EINVAL; 1265 1266 /* 1267 * The 1440p@60 pixel rate is in the same range than the first 1268 * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz 1269 * bandwidth). Slightly lower the frequency to bring it out of 1270 * the WiFi range. 1271 */ 1272 tmds_rate = pixel_rate * 10; 1273 if (vc4_hdmi->disable_wifi_frequencies && 1274 (tmds_rate >= WIFI_2_4GHz_CH1_MIN_FREQ && 1275 tmds_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) { 1276 mode->clock = 238560; 1277 pixel_rate = mode->clock * 1000; 1278 } 1279 1280 if (conn_state->max_bpc == 12) { 1281 pixel_rate = pixel_rate * 150; 1282 do_div(pixel_rate, 100); 1283 } else if (conn_state->max_bpc == 10) { 1284 pixel_rate = pixel_rate * 125; 1285 do_div(pixel_rate, 100); 1286 } 1287 1288 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 1289 pixel_rate = pixel_rate * 2; 1290 1291 if (pixel_rate > vc4_hdmi->variant->max_pixel_clock) 1292 return -EINVAL; 1293 1294 if (vc4_hdmi->disable_4kp60 && (pixel_rate > HDMI_14_MAX_TMDS_CLK)) 1295 return -EINVAL; 1296 1297 vc4_state->pixel_rate = pixel_rate; 1298 1299 return 0; 1300 } 1301 1302 static enum drm_mode_status 1303 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder, 1304 const struct drm_display_mode *mode) 1305 { 1306 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1307 1308 if (vc4_hdmi->variant->unsupported_odd_h_timings && 1309 ((mode->hdisplay % 2) || (mode->hsync_start % 2) || 1310 (mode->hsync_end % 2) || (mode->htotal % 2))) 1311 return MODE_H_ILLEGAL; 1312 1313 if ((mode->clock * 1000) > vc4_hdmi->variant->max_pixel_clock) 1314 return MODE_CLOCK_HIGH; 1315 1316 if (vc4_hdmi->disable_4kp60 && vc4_hdmi_mode_needs_scrambling(mode)) 1317 return MODE_CLOCK_HIGH; 1318 1319 return MODE_OK; 1320 } 1321 1322 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = { 1323 .atomic_check = vc4_hdmi_encoder_atomic_check, 1324 .atomic_mode_set = vc4_hdmi_encoder_atomic_mode_set, 1325 .mode_valid = vc4_hdmi_encoder_mode_valid, 1326 .disable = vc4_hdmi_encoder_disable, 1327 .enable = vc4_hdmi_encoder_enable, 1328 }; 1329 1330 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask) 1331 { 1332 int i; 1333 u32 channel_map = 0; 1334 1335 for (i = 0; i < 8; i++) { 1336 if (channel_mask & BIT(i)) 1337 channel_map |= i << (3 * i); 1338 } 1339 return channel_map; 1340 } 1341 1342 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask) 1343 { 1344 int i; 1345 u32 channel_map = 0; 1346 1347 for (i = 0; i < 8; i++) { 1348 if (channel_mask & BIT(i)) 1349 channel_map |= i << (4 * i); 1350 } 1351 return channel_map; 1352 } 1353 1354 /* HDMI audio codec callbacks */ 1355 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi, 1356 unsigned int samplerate) 1357 { 1358 u32 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock); 1359 unsigned long flags; 1360 unsigned long n, m; 1361 1362 rational_best_approximation(hsm_clock, samplerate, 1363 VC4_HD_MAI_SMP_N_MASK >> 1364 VC4_HD_MAI_SMP_N_SHIFT, 1365 (VC4_HD_MAI_SMP_M_MASK >> 1366 VC4_HD_MAI_SMP_M_SHIFT) + 1, 1367 &n, &m); 1368 1369 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1370 HDMI_WRITE(HDMI_MAI_SMP, 1371 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) | 1372 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M)); 1373 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1374 } 1375 1376 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi, unsigned int samplerate) 1377 { 1378 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1379 u32 n, cts; 1380 u64 tmp; 1381 1382 lockdep_assert_held(&vc4_hdmi->mutex); 1383 lockdep_assert_held(&vc4_hdmi->hw_lock); 1384 1385 n = 128 * samplerate / 1000; 1386 tmp = (u64)(mode->clock * 1000) * n; 1387 do_div(tmp, 128 * samplerate); 1388 cts = tmp; 1389 1390 HDMI_WRITE(HDMI_CRP_CFG, 1391 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN | 1392 VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N)); 1393 1394 /* 1395 * We could get slightly more accurate clocks in some cases by 1396 * providing a CTS_1 value. The two CTS values are alternated 1397 * between based on the period fields 1398 */ 1399 HDMI_WRITE(HDMI_CTS_0, cts); 1400 HDMI_WRITE(HDMI_CTS_1, cts); 1401 } 1402 1403 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai) 1404 { 1405 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai); 1406 1407 return snd_soc_card_get_drvdata(card); 1408 } 1409 1410 static bool vc4_hdmi_audio_can_stream(struct vc4_hdmi *vc4_hdmi) 1411 { 1412 lockdep_assert_held(&vc4_hdmi->mutex); 1413 1414 /* 1415 * If the controller is disabled, prevent any ALSA output. 1416 */ 1417 if (!vc4_hdmi->output_enabled) 1418 return false; 1419 1420 /* 1421 * If the encoder is currently in DVI mode, treat the codec DAI 1422 * as missing. 1423 */ 1424 if (!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) & VC4_HDMI_RAM_PACKET_ENABLE)) 1425 return false; 1426 1427 return true; 1428 } 1429 1430 static int vc4_hdmi_audio_startup(struct device *dev, void *data) 1431 { 1432 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 1433 unsigned long flags; 1434 1435 mutex_lock(&vc4_hdmi->mutex); 1436 1437 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) { 1438 mutex_unlock(&vc4_hdmi->mutex); 1439 return -ENODEV; 1440 } 1441 1442 vc4_hdmi->audio.streaming = true; 1443 1444 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1445 HDMI_WRITE(HDMI_MAI_CTL, 1446 VC4_HD_MAI_CTL_RESET | 1447 VC4_HD_MAI_CTL_FLUSH | 1448 VC4_HD_MAI_CTL_DLATE | 1449 VC4_HD_MAI_CTL_ERRORE | 1450 VC4_HD_MAI_CTL_ERRORF); 1451 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1452 1453 if (vc4_hdmi->variant->phy_rng_enable) 1454 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi); 1455 1456 mutex_unlock(&vc4_hdmi->mutex); 1457 1458 return 0; 1459 } 1460 1461 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi) 1462 { 1463 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base; 1464 struct device *dev = &vc4_hdmi->pdev->dev; 1465 unsigned long flags; 1466 int ret; 1467 1468 lockdep_assert_held(&vc4_hdmi->mutex); 1469 1470 vc4_hdmi->audio.streaming = false; 1471 ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO, false); 1472 if (ret) 1473 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret); 1474 1475 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1476 1477 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET); 1478 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF); 1479 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH); 1480 1481 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1482 } 1483 1484 static void vc4_hdmi_audio_shutdown(struct device *dev, void *data) 1485 { 1486 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 1487 unsigned long flags; 1488 1489 mutex_lock(&vc4_hdmi->mutex); 1490 1491 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1492 1493 HDMI_WRITE(HDMI_MAI_CTL, 1494 VC4_HD_MAI_CTL_DLATE | 1495 VC4_HD_MAI_CTL_ERRORE | 1496 VC4_HD_MAI_CTL_ERRORF); 1497 1498 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1499 1500 if (vc4_hdmi->variant->phy_rng_disable) 1501 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi); 1502 1503 vc4_hdmi->audio.streaming = false; 1504 vc4_hdmi_audio_reset(vc4_hdmi); 1505 1506 mutex_unlock(&vc4_hdmi->mutex); 1507 } 1508 1509 static int sample_rate_to_mai_fmt(int samplerate) 1510 { 1511 switch (samplerate) { 1512 case 8000: 1513 return VC4_HDMI_MAI_SAMPLE_RATE_8000; 1514 case 11025: 1515 return VC4_HDMI_MAI_SAMPLE_RATE_11025; 1516 case 12000: 1517 return VC4_HDMI_MAI_SAMPLE_RATE_12000; 1518 case 16000: 1519 return VC4_HDMI_MAI_SAMPLE_RATE_16000; 1520 case 22050: 1521 return VC4_HDMI_MAI_SAMPLE_RATE_22050; 1522 case 24000: 1523 return VC4_HDMI_MAI_SAMPLE_RATE_24000; 1524 case 32000: 1525 return VC4_HDMI_MAI_SAMPLE_RATE_32000; 1526 case 44100: 1527 return VC4_HDMI_MAI_SAMPLE_RATE_44100; 1528 case 48000: 1529 return VC4_HDMI_MAI_SAMPLE_RATE_48000; 1530 case 64000: 1531 return VC4_HDMI_MAI_SAMPLE_RATE_64000; 1532 case 88200: 1533 return VC4_HDMI_MAI_SAMPLE_RATE_88200; 1534 case 96000: 1535 return VC4_HDMI_MAI_SAMPLE_RATE_96000; 1536 case 128000: 1537 return VC4_HDMI_MAI_SAMPLE_RATE_128000; 1538 case 176400: 1539 return VC4_HDMI_MAI_SAMPLE_RATE_176400; 1540 case 192000: 1541 return VC4_HDMI_MAI_SAMPLE_RATE_192000; 1542 default: 1543 return VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED; 1544 } 1545 } 1546 1547 /* HDMI audio codec callbacks */ 1548 static int vc4_hdmi_audio_prepare(struct device *dev, void *data, 1549 struct hdmi_codec_daifmt *daifmt, 1550 struct hdmi_codec_params *params) 1551 { 1552 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 1553 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base; 1554 unsigned int sample_rate = params->sample_rate; 1555 unsigned int channels = params->channels; 1556 unsigned long flags; 1557 u32 audio_packet_config, channel_mask; 1558 u32 channel_map; 1559 u32 mai_audio_format; 1560 u32 mai_sample_rate; 1561 1562 dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__, 1563 sample_rate, params->sample_width, channels); 1564 1565 mutex_lock(&vc4_hdmi->mutex); 1566 1567 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) { 1568 mutex_unlock(&vc4_hdmi->mutex); 1569 return -EINVAL; 1570 } 1571 1572 vc4_hdmi_audio_set_mai_clock(vc4_hdmi, sample_rate); 1573 1574 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1575 HDMI_WRITE(HDMI_MAI_CTL, 1576 VC4_SET_FIELD(channels, VC4_HD_MAI_CTL_CHNUM) | 1577 VC4_HD_MAI_CTL_WHOLSMP | 1578 VC4_HD_MAI_CTL_CHALIGN | 1579 VC4_HD_MAI_CTL_ENABLE); 1580 1581 mai_sample_rate = sample_rate_to_mai_fmt(sample_rate); 1582 if (params->iec.status[0] & IEC958_AES0_NONAUDIO && 1583 params->channels == 8) 1584 mai_audio_format = VC4_HDMI_MAI_FORMAT_HBR; 1585 else 1586 mai_audio_format = VC4_HDMI_MAI_FORMAT_PCM; 1587 HDMI_WRITE(HDMI_MAI_FMT, 1588 VC4_SET_FIELD(mai_sample_rate, 1589 VC4_HDMI_MAI_FORMAT_SAMPLE_RATE) | 1590 VC4_SET_FIELD(mai_audio_format, 1591 VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT)); 1592 1593 /* The B frame identifier should match the value used by alsa-lib (8) */ 1594 audio_packet_config = 1595 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT | 1596 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS | 1597 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER); 1598 1599 channel_mask = GENMASK(channels - 1, 0); 1600 audio_packet_config |= VC4_SET_FIELD(channel_mask, 1601 VC4_HDMI_AUDIO_PACKET_CEA_MASK); 1602 1603 /* Set the MAI threshold */ 1604 HDMI_WRITE(HDMI_MAI_THR, 1605 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) | 1606 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) | 1607 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQHIGH) | 1608 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQLOW)); 1609 1610 HDMI_WRITE(HDMI_MAI_CONFIG, 1611 VC4_HDMI_MAI_CONFIG_BIT_REVERSE | 1612 VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE | 1613 VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK)); 1614 1615 channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask); 1616 HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map); 1617 HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config); 1618 1619 vc4_hdmi_set_n_cts(vc4_hdmi, sample_rate); 1620 1621 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1622 1623 memcpy(&vc4_hdmi->audio.infoframe, ¶ms->cea, sizeof(params->cea)); 1624 vc4_hdmi_set_audio_infoframe(encoder); 1625 1626 mutex_unlock(&vc4_hdmi->mutex); 1627 1628 return 0; 1629 } 1630 1631 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = { 1632 .name = "vc4-hdmi-cpu-dai-component", 1633 }; 1634 1635 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai) 1636 { 1637 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai); 1638 1639 snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL); 1640 1641 return 0; 1642 } 1643 1644 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = { 1645 .name = "vc4-hdmi-cpu-dai", 1646 .probe = vc4_hdmi_audio_cpu_dai_probe, 1647 .playback = { 1648 .stream_name = "Playback", 1649 .channels_min = 1, 1650 .channels_max = 8, 1651 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 1652 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 1653 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 1654 SNDRV_PCM_RATE_192000, 1655 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 1656 }, 1657 }; 1658 1659 static const struct snd_dmaengine_pcm_config pcm_conf = { 1660 .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx", 1661 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 1662 }; 1663 1664 static int vc4_hdmi_audio_get_eld(struct device *dev, void *data, 1665 uint8_t *buf, size_t len) 1666 { 1667 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 1668 struct drm_connector *connector = &vc4_hdmi->connector; 1669 1670 mutex_lock(&vc4_hdmi->mutex); 1671 memcpy(buf, connector->eld, min(sizeof(connector->eld), len)); 1672 mutex_unlock(&vc4_hdmi->mutex); 1673 1674 return 0; 1675 } 1676 1677 static const struct hdmi_codec_ops vc4_hdmi_codec_ops = { 1678 .get_eld = vc4_hdmi_audio_get_eld, 1679 .prepare = vc4_hdmi_audio_prepare, 1680 .audio_shutdown = vc4_hdmi_audio_shutdown, 1681 .audio_startup = vc4_hdmi_audio_startup, 1682 }; 1683 1684 static struct hdmi_codec_pdata vc4_hdmi_codec_pdata = { 1685 .ops = &vc4_hdmi_codec_ops, 1686 .max_i2s_channels = 8, 1687 .i2s = 1, 1688 }; 1689 1690 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi) 1691 { 1692 const struct vc4_hdmi_register *mai_data = 1693 &vc4_hdmi->variant->registers[HDMI_MAI_DATA]; 1694 struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link; 1695 struct snd_soc_card *card = &vc4_hdmi->audio.card; 1696 struct device *dev = &vc4_hdmi->pdev->dev; 1697 struct platform_device *codec_pdev; 1698 const __be32 *addr; 1699 int index; 1700 int ret; 1701 1702 if (!of_find_property(dev->of_node, "dmas", NULL)) { 1703 dev_warn(dev, 1704 "'dmas' DT property is missing, no HDMI audio\n"); 1705 return 0; 1706 } 1707 1708 if (mai_data->reg != VC4_HD) { 1709 WARN_ONCE(true, "MAI isn't in the HD block\n"); 1710 return -EINVAL; 1711 } 1712 1713 /* 1714 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve 1715 * the bus address specified in the DT, because the physical address 1716 * (the one returned by platform_get_resource()) is not appropriate 1717 * for DMA transfers. 1718 * This VC/MMU should probably be exposed to avoid this kind of hacks. 1719 */ 1720 index = of_property_match_string(dev->of_node, "reg-names", "hd"); 1721 /* Before BCM2711, we don't have a named register range */ 1722 if (index < 0) 1723 index = 1; 1724 1725 addr = of_get_address(dev->of_node, index, NULL, NULL); 1726 1727 vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset; 1728 vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1729 vc4_hdmi->audio.dma_data.maxburst = 2; 1730 1731 ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0); 1732 if (ret) { 1733 dev_err(dev, "Could not register PCM component: %d\n", ret); 1734 return ret; 1735 } 1736 1737 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp, 1738 &vc4_hdmi_audio_cpu_dai_drv, 1); 1739 if (ret) { 1740 dev_err(dev, "Could not register CPU DAI: %d\n", ret); 1741 return ret; 1742 } 1743 1744 codec_pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME, 1745 PLATFORM_DEVID_AUTO, 1746 &vc4_hdmi_codec_pdata, 1747 sizeof(vc4_hdmi_codec_pdata)); 1748 if (IS_ERR(codec_pdev)) { 1749 dev_err(dev, "Couldn't register the HDMI codec: %ld\n", PTR_ERR(codec_pdev)); 1750 return PTR_ERR(codec_pdev); 1751 } 1752 1753 dai_link->cpus = &vc4_hdmi->audio.cpu; 1754 dai_link->codecs = &vc4_hdmi->audio.codec; 1755 dai_link->platforms = &vc4_hdmi->audio.platform; 1756 1757 dai_link->num_cpus = 1; 1758 dai_link->num_codecs = 1; 1759 dai_link->num_platforms = 1; 1760 1761 dai_link->name = "MAI"; 1762 dai_link->stream_name = "MAI PCM"; 1763 dai_link->codecs->dai_name = "i2s-hifi"; 1764 dai_link->cpus->dai_name = dev_name(dev); 1765 dai_link->codecs->name = dev_name(&codec_pdev->dev); 1766 dai_link->platforms->name = dev_name(dev); 1767 1768 card->dai_link = dai_link; 1769 card->num_links = 1; 1770 card->name = vc4_hdmi->variant->card_name; 1771 card->driver_name = "vc4-hdmi"; 1772 card->dev = dev; 1773 card->owner = THIS_MODULE; 1774 1775 /* 1776 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and 1777 * stores a pointer to the snd card object in dev->driver_data. This 1778 * means we cannot use it for something else. The hdmi back-pointer is 1779 * now stored in card->drvdata and should be retrieved with 1780 * snd_soc_card_get_drvdata() if needed. 1781 */ 1782 snd_soc_card_set_drvdata(card, vc4_hdmi); 1783 ret = devm_snd_soc_register_card(dev, card); 1784 if (ret) 1785 dev_err_probe(dev, ret, "Could not register sound card\n"); 1786 1787 return ret; 1788 1789 } 1790 1791 static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv) 1792 { 1793 struct vc4_hdmi *vc4_hdmi = priv; 1794 struct drm_connector *connector = &vc4_hdmi->connector; 1795 struct drm_device *dev = connector->dev; 1796 1797 if (dev && dev->registered) 1798 drm_connector_helper_hpd_irq_event(connector); 1799 1800 return IRQ_HANDLED; 1801 } 1802 1803 static int vc4_hdmi_hotplug_init(struct vc4_hdmi *vc4_hdmi) 1804 { 1805 struct drm_connector *connector = &vc4_hdmi->connector; 1806 struct platform_device *pdev = vc4_hdmi->pdev; 1807 int ret; 1808 1809 if (vc4_hdmi->variant->external_irq_controller) { 1810 unsigned int hpd_con = platform_get_irq_byname(pdev, "hpd-connected"); 1811 unsigned int hpd_rm = platform_get_irq_byname(pdev, "hpd-removed"); 1812 1813 ret = request_threaded_irq(hpd_con, 1814 NULL, 1815 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT, 1816 "vc4 hdmi hpd connected", vc4_hdmi); 1817 if (ret) 1818 return ret; 1819 1820 ret = request_threaded_irq(hpd_rm, 1821 NULL, 1822 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT, 1823 "vc4 hdmi hpd disconnected", vc4_hdmi); 1824 if (ret) { 1825 free_irq(hpd_con, vc4_hdmi); 1826 return ret; 1827 } 1828 1829 connector->polled = DRM_CONNECTOR_POLL_HPD; 1830 } 1831 1832 return 0; 1833 } 1834 1835 static void vc4_hdmi_hotplug_exit(struct vc4_hdmi *vc4_hdmi) 1836 { 1837 struct platform_device *pdev = vc4_hdmi->pdev; 1838 1839 if (vc4_hdmi->variant->external_irq_controller) { 1840 free_irq(platform_get_irq_byname(pdev, "hpd-connected"), vc4_hdmi); 1841 free_irq(platform_get_irq_byname(pdev, "hpd-removed"), vc4_hdmi); 1842 } 1843 } 1844 1845 #ifdef CONFIG_DRM_VC4_HDMI_CEC 1846 static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv) 1847 { 1848 struct vc4_hdmi *vc4_hdmi = priv; 1849 1850 if (vc4_hdmi->cec_rx_msg.len) 1851 cec_received_msg(vc4_hdmi->cec_adap, 1852 &vc4_hdmi->cec_rx_msg); 1853 1854 return IRQ_HANDLED; 1855 } 1856 1857 static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv) 1858 { 1859 struct vc4_hdmi *vc4_hdmi = priv; 1860 1861 if (vc4_hdmi->cec_tx_ok) { 1862 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK, 1863 0, 0, 0, 0); 1864 } else { 1865 /* 1866 * This CEC implementation makes 1 retry, so if we 1867 * get a NACK, then that means it made 2 attempts. 1868 */ 1869 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK, 1870 0, 2, 0, 0); 1871 } 1872 return IRQ_HANDLED; 1873 } 1874 1875 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv) 1876 { 1877 struct vc4_hdmi *vc4_hdmi = priv; 1878 irqreturn_t ret; 1879 1880 if (vc4_hdmi->cec_irq_was_rx) 1881 ret = vc4_cec_irq_handler_rx_thread(irq, priv); 1882 else 1883 ret = vc4_cec_irq_handler_tx_thread(irq, priv); 1884 1885 return ret; 1886 } 1887 1888 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1) 1889 { 1890 struct drm_device *dev = vc4_hdmi->connector.dev; 1891 struct cec_msg *msg = &vc4_hdmi->cec_rx_msg; 1892 unsigned int i; 1893 1894 lockdep_assert_held(&vc4_hdmi->hw_lock); 1895 1896 msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >> 1897 VC4_HDMI_CEC_REC_WRD_CNT_SHIFT); 1898 1899 if (msg->len > 16) { 1900 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len); 1901 return; 1902 } 1903 1904 for (i = 0; i < msg->len; i += 4) { 1905 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2)); 1906 1907 msg->msg[i] = val & 0xff; 1908 msg->msg[i + 1] = (val >> 8) & 0xff; 1909 msg->msg[i + 2] = (val >> 16) & 0xff; 1910 msg->msg[i + 3] = (val >> 24) & 0xff; 1911 } 1912 } 1913 1914 static irqreturn_t vc4_cec_irq_handler_tx_bare_locked(struct vc4_hdmi *vc4_hdmi) 1915 { 1916 u32 cntrl1; 1917 1918 lockdep_assert_held(&vc4_hdmi->hw_lock); 1919 1920 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1); 1921 vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD; 1922 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 1923 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 1924 1925 return IRQ_WAKE_THREAD; 1926 } 1927 1928 static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv) 1929 { 1930 struct vc4_hdmi *vc4_hdmi = priv; 1931 irqreturn_t ret; 1932 1933 spin_lock(&vc4_hdmi->hw_lock); 1934 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi); 1935 spin_unlock(&vc4_hdmi->hw_lock); 1936 1937 return ret; 1938 } 1939 1940 static irqreturn_t vc4_cec_irq_handler_rx_bare_locked(struct vc4_hdmi *vc4_hdmi) 1941 { 1942 u32 cntrl1; 1943 1944 lockdep_assert_held(&vc4_hdmi->hw_lock); 1945 1946 vc4_hdmi->cec_rx_msg.len = 0; 1947 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1); 1948 vc4_cec_read_msg(vc4_hdmi, cntrl1); 1949 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 1950 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 1951 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 1952 1953 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 1954 1955 return IRQ_WAKE_THREAD; 1956 } 1957 1958 static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv) 1959 { 1960 struct vc4_hdmi *vc4_hdmi = priv; 1961 irqreturn_t ret; 1962 1963 spin_lock(&vc4_hdmi->hw_lock); 1964 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi); 1965 spin_unlock(&vc4_hdmi->hw_lock); 1966 1967 return ret; 1968 } 1969 1970 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv) 1971 { 1972 struct vc4_hdmi *vc4_hdmi = priv; 1973 u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS); 1974 irqreturn_t ret; 1975 u32 cntrl5; 1976 1977 if (!(stat & VC4_HDMI_CPU_CEC)) 1978 return IRQ_NONE; 1979 1980 spin_lock(&vc4_hdmi->hw_lock); 1981 cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5); 1982 vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT; 1983 if (vc4_hdmi->cec_irq_was_rx) 1984 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi); 1985 else 1986 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi); 1987 1988 HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC); 1989 spin_unlock(&vc4_hdmi->hw_lock); 1990 1991 return ret; 1992 } 1993 1994 static int vc4_hdmi_cec_enable(struct cec_adapter *adap) 1995 { 1996 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 1997 /* clock period in microseconds */ 1998 const u32 usecs = 1000000 / CEC_CLOCK_FREQ; 1999 unsigned long flags; 2000 u32 val; 2001 int ret; 2002 2003 /* 2004 * NOTE: This function should really take vc4_hdmi->mutex, but doing so 2005 * results in a reentrancy since cec_s_phys_addr_from_edid() called in 2006 * .detect or .get_modes might call .adap_enable, which leads to this 2007 * function being called with that mutex held. 2008 * 2009 * Concurrency is not an issue for the moment since we don't share any 2010 * state with KMS, so we can ignore the lock for now, but we need to 2011 * keep it in mind if we were to change that assumption. 2012 */ 2013 2014 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev); 2015 if (ret) 2016 return ret; 2017 2018 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2019 2020 val = HDMI_READ(HDMI_CEC_CNTRL_5); 2021 val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET | 2022 VC4_HDMI_CEC_CNT_TO_4700_US_MASK | 2023 VC4_HDMI_CEC_CNT_TO_4500_US_MASK); 2024 val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) | 2025 ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT); 2026 2027 HDMI_WRITE(HDMI_CEC_CNTRL_5, val | 2028 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 2029 HDMI_WRITE(HDMI_CEC_CNTRL_5, val); 2030 HDMI_WRITE(HDMI_CEC_CNTRL_2, 2031 ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) | 2032 ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) | 2033 ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) | 2034 ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) | 2035 ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT)); 2036 HDMI_WRITE(HDMI_CEC_CNTRL_3, 2037 ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) | 2038 ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) | 2039 ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) | 2040 ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT)); 2041 HDMI_WRITE(HDMI_CEC_CNTRL_4, 2042 ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) | 2043 ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) | 2044 ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) | 2045 ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT)); 2046 2047 if (!vc4_hdmi->variant->external_irq_controller) 2048 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC); 2049 2050 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2051 2052 return 0; 2053 } 2054 2055 static int vc4_hdmi_cec_disable(struct cec_adapter *adap) 2056 { 2057 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 2058 unsigned long flags; 2059 2060 /* 2061 * NOTE: This function should really take vc4_hdmi->mutex, but doing so 2062 * results in a reentrancy since cec_s_phys_addr_from_edid() called in 2063 * .detect or .get_modes might call .adap_enable, which leads to this 2064 * function being called with that mutex held. 2065 * 2066 * Concurrency is not an issue for the moment since we don't share any 2067 * state with KMS, so we can ignore the lock for now, but we need to 2068 * keep it in mind if we were to change that assumption. 2069 */ 2070 2071 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2072 2073 if (!vc4_hdmi->variant->external_irq_controller) 2074 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC); 2075 2076 HDMI_WRITE(HDMI_CEC_CNTRL_5, HDMI_READ(HDMI_CEC_CNTRL_5) | 2077 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 2078 2079 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2080 2081 pm_runtime_put(&vc4_hdmi->pdev->dev); 2082 2083 return 0; 2084 } 2085 2086 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable) 2087 { 2088 if (enable) 2089 return vc4_hdmi_cec_enable(adap); 2090 else 2091 return vc4_hdmi_cec_disable(adap); 2092 } 2093 2094 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr) 2095 { 2096 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 2097 unsigned long flags; 2098 2099 /* 2100 * NOTE: This function should really take vc4_hdmi->mutex, but doing so 2101 * results in a reentrancy since cec_s_phys_addr_from_edid() called in 2102 * .detect or .get_modes might call .adap_enable, which leads to this 2103 * function being called with that mutex held. 2104 * 2105 * Concurrency is not an issue for the moment since we don't share any 2106 * state with KMS, so we can ignore the lock for now, but we need to 2107 * keep it in mind if we were to change that assumption. 2108 */ 2109 2110 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2111 HDMI_WRITE(HDMI_CEC_CNTRL_1, 2112 (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) | 2113 (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT); 2114 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2115 2116 return 0; 2117 } 2118 2119 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts, 2120 u32 signal_free_time, struct cec_msg *msg) 2121 { 2122 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 2123 struct drm_device *dev = vc4_hdmi->connector.dev; 2124 unsigned long flags; 2125 u32 val; 2126 unsigned int i; 2127 2128 /* 2129 * NOTE: This function should really take vc4_hdmi->mutex, but doing so 2130 * results in a reentrancy since cec_s_phys_addr_from_edid() called in 2131 * .detect or .get_modes might call .adap_enable, which leads to this 2132 * function being called with that mutex held. 2133 * 2134 * Concurrency is not an issue for the moment since we don't share any 2135 * state with KMS, so we can ignore the lock for now, but we need to 2136 * keep it in mind if we were to change that assumption. 2137 */ 2138 2139 if (msg->len > 16) { 2140 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len); 2141 return -ENOMEM; 2142 } 2143 2144 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2145 2146 for (i = 0; i < msg->len; i += 4) 2147 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2), 2148 (msg->msg[i]) | 2149 (msg->msg[i + 1] << 8) | 2150 (msg->msg[i + 2] << 16) | 2151 (msg->msg[i + 3] << 24)); 2152 2153 val = HDMI_READ(HDMI_CEC_CNTRL_1); 2154 val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 2155 HDMI_WRITE(HDMI_CEC_CNTRL_1, val); 2156 val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK; 2157 val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT; 2158 val |= VC4_HDMI_CEC_START_XMIT_BEGIN; 2159 2160 HDMI_WRITE(HDMI_CEC_CNTRL_1, val); 2161 2162 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2163 2164 return 0; 2165 } 2166 2167 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = { 2168 .adap_enable = vc4_hdmi_cec_adap_enable, 2169 .adap_log_addr = vc4_hdmi_cec_adap_log_addr, 2170 .adap_transmit = vc4_hdmi_cec_adap_transmit, 2171 }; 2172 2173 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi) 2174 { 2175 struct cec_connector_info conn_info; 2176 struct platform_device *pdev = vc4_hdmi->pdev; 2177 struct device *dev = &pdev->dev; 2178 unsigned long flags; 2179 u32 value; 2180 int ret; 2181 2182 if (!of_find_property(dev->of_node, "interrupts", NULL)) { 2183 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n"); 2184 return 0; 2185 } 2186 2187 vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops, 2188 vc4_hdmi, "vc4", 2189 CEC_CAP_DEFAULTS | 2190 CEC_CAP_CONNECTOR_INFO, 1); 2191 ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap); 2192 if (ret < 0) 2193 return ret; 2194 2195 cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector); 2196 cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info); 2197 2198 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2199 value = HDMI_READ(HDMI_CEC_CNTRL_1); 2200 /* Set the logical address to Unregistered */ 2201 value |= VC4_HDMI_CEC_ADDR_MASK; 2202 HDMI_WRITE(HDMI_CEC_CNTRL_1, value); 2203 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2204 2205 vc4_hdmi_cec_update_clk_div(vc4_hdmi); 2206 2207 if (vc4_hdmi->variant->external_irq_controller) { 2208 ret = request_threaded_irq(platform_get_irq_byname(pdev, "cec-rx"), 2209 vc4_cec_irq_handler_rx_bare, 2210 vc4_cec_irq_handler_rx_thread, 0, 2211 "vc4 hdmi cec rx", vc4_hdmi); 2212 if (ret) 2213 goto err_delete_cec_adap; 2214 2215 ret = request_threaded_irq(platform_get_irq_byname(pdev, "cec-tx"), 2216 vc4_cec_irq_handler_tx_bare, 2217 vc4_cec_irq_handler_tx_thread, 0, 2218 "vc4 hdmi cec tx", vc4_hdmi); 2219 if (ret) 2220 goto err_remove_cec_rx_handler; 2221 } else { 2222 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2223 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff); 2224 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2225 2226 ret = request_threaded_irq(platform_get_irq(pdev, 0), 2227 vc4_cec_irq_handler, 2228 vc4_cec_irq_handler_thread, 0, 2229 "vc4 hdmi cec", vc4_hdmi); 2230 if (ret) 2231 goto err_delete_cec_adap; 2232 } 2233 2234 ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev); 2235 if (ret < 0) 2236 goto err_remove_handlers; 2237 2238 return 0; 2239 2240 err_remove_handlers: 2241 if (vc4_hdmi->variant->external_irq_controller) 2242 free_irq(platform_get_irq_byname(pdev, "cec-tx"), vc4_hdmi); 2243 else 2244 free_irq(platform_get_irq(pdev, 0), vc4_hdmi); 2245 2246 err_remove_cec_rx_handler: 2247 if (vc4_hdmi->variant->external_irq_controller) 2248 free_irq(platform_get_irq_byname(pdev, "cec-rx"), vc4_hdmi); 2249 2250 err_delete_cec_adap: 2251 cec_delete_adapter(vc4_hdmi->cec_adap); 2252 2253 return ret; 2254 } 2255 2256 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi) 2257 { 2258 struct platform_device *pdev = vc4_hdmi->pdev; 2259 2260 if (vc4_hdmi->variant->external_irq_controller) { 2261 free_irq(platform_get_irq_byname(pdev, "cec-rx"), vc4_hdmi); 2262 free_irq(platform_get_irq_byname(pdev, "cec-tx"), vc4_hdmi); 2263 } else { 2264 free_irq(platform_get_irq(pdev, 0), vc4_hdmi); 2265 } 2266 2267 cec_unregister_adapter(vc4_hdmi->cec_adap); 2268 } 2269 #else 2270 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi) 2271 { 2272 return 0; 2273 } 2274 2275 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi) {}; 2276 2277 #endif 2278 2279 static int vc4_hdmi_build_regset(struct vc4_hdmi *vc4_hdmi, 2280 struct debugfs_regset32 *regset, 2281 enum vc4_hdmi_regs reg) 2282 { 2283 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant; 2284 struct debugfs_reg32 *regs, *new_regs; 2285 unsigned int count = 0; 2286 unsigned int i; 2287 2288 regs = kcalloc(variant->num_registers, sizeof(*regs), 2289 GFP_KERNEL); 2290 if (!regs) 2291 return -ENOMEM; 2292 2293 for (i = 0; i < variant->num_registers; i++) { 2294 const struct vc4_hdmi_register *field = &variant->registers[i]; 2295 2296 if (field->reg != reg) 2297 continue; 2298 2299 regs[count].name = field->name; 2300 regs[count].offset = field->offset; 2301 count++; 2302 } 2303 2304 new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL); 2305 if (!new_regs) 2306 return -ENOMEM; 2307 2308 regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg); 2309 regset->regs = new_regs; 2310 regset->nregs = count; 2311 2312 return 0; 2313 } 2314 2315 static int vc4_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi) 2316 { 2317 struct platform_device *pdev = vc4_hdmi->pdev; 2318 struct device *dev = &pdev->dev; 2319 int ret; 2320 2321 vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0); 2322 if (IS_ERR(vc4_hdmi->hdmicore_regs)) 2323 return PTR_ERR(vc4_hdmi->hdmicore_regs); 2324 2325 vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1); 2326 if (IS_ERR(vc4_hdmi->hd_regs)) 2327 return PTR_ERR(vc4_hdmi->hd_regs); 2328 2329 ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD); 2330 if (ret) 2331 return ret; 2332 2333 ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI); 2334 if (ret) 2335 return ret; 2336 2337 vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel"); 2338 if (IS_ERR(vc4_hdmi->pixel_clock)) { 2339 ret = PTR_ERR(vc4_hdmi->pixel_clock); 2340 if (ret != -EPROBE_DEFER) 2341 DRM_ERROR("Failed to get pixel clock\n"); 2342 return ret; 2343 } 2344 2345 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); 2346 if (IS_ERR(vc4_hdmi->hsm_clock)) { 2347 DRM_ERROR("Failed to get HDMI state machine clock\n"); 2348 return PTR_ERR(vc4_hdmi->hsm_clock); 2349 } 2350 vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock; 2351 vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock; 2352 2353 return 0; 2354 } 2355 2356 static int vc5_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi) 2357 { 2358 struct platform_device *pdev = vc4_hdmi->pdev; 2359 struct device *dev = &pdev->dev; 2360 struct resource *res; 2361 2362 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi"); 2363 if (!res) 2364 return -ENODEV; 2365 2366 vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start, 2367 resource_size(res)); 2368 if (!vc4_hdmi->hdmicore_regs) 2369 return -ENOMEM; 2370 2371 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd"); 2372 if (!res) 2373 return -ENODEV; 2374 2375 vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res)); 2376 if (!vc4_hdmi->hd_regs) 2377 return -ENOMEM; 2378 2379 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec"); 2380 if (!res) 2381 return -ENODEV; 2382 2383 vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res)); 2384 if (!vc4_hdmi->cec_regs) 2385 return -ENOMEM; 2386 2387 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc"); 2388 if (!res) 2389 return -ENODEV; 2390 2391 vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res)); 2392 if (!vc4_hdmi->csc_regs) 2393 return -ENOMEM; 2394 2395 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp"); 2396 if (!res) 2397 return -ENODEV; 2398 2399 vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res)); 2400 if (!vc4_hdmi->dvp_regs) 2401 return -ENOMEM; 2402 2403 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy"); 2404 if (!res) 2405 return -ENODEV; 2406 2407 vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res)); 2408 if (!vc4_hdmi->phy_regs) 2409 return -ENOMEM; 2410 2411 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet"); 2412 if (!res) 2413 return -ENODEV; 2414 2415 vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res)); 2416 if (!vc4_hdmi->ram_regs) 2417 return -ENOMEM; 2418 2419 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm"); 2420 if (!res) 2421 return -ENODEV; 2422 2423 vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res)); 2424 if (!vc4_hdmi->rm_regs) 2425 return -ENOMEM; 2426 2427 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); 2428 if (IS_ERR(vc4_hdmi->hsm_clock)) { 2429 DRM_ERROR("Failed to get HDMI state machine clock\n"); 2430 return PTR_ERR(vc4_hdmi->hsm_clock); 2431 } 2432 2433 vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb"); 2434 if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) { 2435 DRM_ERROR("Failed to get pixel bvb clock\n"); 2436 return PTR_ERR(vc4_hdmi->pixel_bvb_clock); 2437 } 2438 2439 vc4_hdmi->audio_clock = devm_clk_get(dev, "audio"); 2440 if (IS_ERR(vc4_hdmi->audio_clock)) { 2441 DRM_ERROR("Failed to get audio clock\n"); 2442 return PTR_ERR(vc4_hdmi->audio_clock); 2443 } 2444 2445 vc4_hdmi->cec_clock = devm_clk_get(dev, "cec"); 2446 if (IS_ERR(vc4_hdmi->cec_clock)) { 2447 DRM_ERROR("Failed to get CEC clock\n"); 2448 return PTR_ERR(vc4_hdmi->cec_clock); 2449 } 2450 2451 vc4_hdmi->reset = devm_reset_control_get(dev, NULL); 2452 if (IS_ERR(vc4_hdmi->reset)) { 2453 DRM_ERROR("Failed to get HDMI reset line\n"); 2454 return PTR_ERR(vc4_hdmi->reset); 2455 } 2456 2457 return 0; 2458 } 2459 2460 static int __maybe_unused vc4_hdmi_runtime_suspend(struct device *dev) 2461 { 2462 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 2463 2464 clk_disable_unprepare(vc4_hdmi->hsm_clock); 2465 2466 return 0; 2467 } 2468 2469 static int vc4_hdmi_runtime_resume(struct device *dev) 2470 { 2471 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 2472 int ret; 2473 2474 ret = clk_prepare_enable(vc4_hdmi->hsm_clock); 2475 if (ret) 2476 return ret; 2477 2478 return 0; 2479 } 2480 2481 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data) 2482 { 2483 const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev); 2484 struct platform_device *pdev = to_platform_device(dev); 2485 struct drm_device *drm = dev_get_drvdata(master); 2486 struct vc4_hdmi *vc4_hdmi; 2487 struct drm_encoder *encoder; 2488 struct device_node *ddc_node; 2489 int ret; 2490 2491 vc4_hdmi = devm_kzalloc(dev, sizeof(*vc4_hdmi), GFP_KERNEL); 2492 if (!vc4_hdmi) 2493 return -ENOMEM; 2494 mutex_init(&vc4_hdmi->mutex); 2495 spin_lock_init(&vc4_hdmi->hw_lock); 2496 INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq); 2497 2498 dev_set_drvdata(dev, vc4_hdmi); 2499 encoder = &vc4_hdmi->encoder.base.base; 2500 vc4_hdmi->encoder.base.type = variant->encoder_type; 2501 vc4_hdmi->encoder.base.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure; 2502 vc4_hdmi->encoder.base.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable; 2503 vc4_hdmi->encoder.base.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable; 2504 vc4_hdmi->encoder.base.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable; 2505 vc4_hdmi->encoder.base.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown; 2506 vc4_hdmi->pdev = pdev; 2507 vc4_hdmi->variant = variant; 2508 2509 /* 2510 * Since we don't know the state of the controller and its 2511 * display (if any), let's assume it's always enabled. 2512 * vc4_hdmi_disable_scrambling() will thus run at boot, make 2513 * sure it's disabled, and avoid any inconsistency. 2514 */ 2515 vc4_hdmi->scdc_enabled = true; 2516 2517 ret = variant->init_resources(vc4_hdmi); 2518 if (ret) 2519 return ret; 2520 2521 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0); 2522 if (!ddc_node) { 2523 DRM_ERROR("Failed to find ddc node in device tree\n"); 2524 return -ENODEV; 2525 } 2526 2527 vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node); 2528 of_node_put(ddc_node); 2529 if (!vc4_hdmi->ddc) { 2530 DRM_DEBUG("Failed to get ddc i2c adapter by node\n"); 2531 return -EPROBE_DEFER; 2532 } 2533 2534 /* Only use the GPIO HPD pin if present in the DT, otherwise 2535 * we'll use the HDMI core's register. 2536 */ 2537 vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN); 2538 if (IS_ERR(vc4_hdmi->hpd_gpio)) { 2539 ret = PTR_ERR(vc4_hdmi->hpd_gpio); 2540 goto err_put_ddc; 2541 } 2542 2543 vc4_hdmi->disable_wifi_frequencies = 2544 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence"); 2545 2546 if (variant->max_pixel_clock == 600000000) { 2547 struct vc4_dev *vc4 = to_vc4_dev(drm); 2548 long max_rate = clk_round_rate(vc4->hvs->core_clk, 550000000); 2549 2550 if (max_rate < 550000000) 2551 vc4_hdmi->disable_4kp60 = true; 2552 } 2553 2554 /* 2555 * If we boot without any cable connected to the HDMI connector, 2556 * the firmware will skip the HSM initialization and leave it 2557 * with a rate of 0, resulting in a bus lockup when we're 2558 * accessing the registers even if it's enabled. 2559 * 2560 * Let's put a sensible default at runtime_resume so that we 2561 * don't end up in this situation. 2562 */ 2563 ret = clk_set_min_rate(vc4_hdmi->hsm_clock, HSM_MIN_CLOCK_FREQ); 2564 if (ret) 2565 goto err_put_ddc; 2566 2567 /* 2568 * We need to have the device powered up at this point to call 2569 * our reset hook and for the CEC init. 2570 */ 2571 ret = vc4_hdmi_runtime_resume(dev); 2572 if (ret) 2573 goto err_put_ddc; 2574 2575 pm_runtime_get_noresume(dev); 2576 pm_runtime_set_active(dev); 2577 pm_runtime_enable(dev); 2578 2579 if (vc4_hdmi->variant->reset) 2580 vc4_hdmi->variant->reset(vc4_hdmi); 2581 2582 if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") || 2583 of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1")) && 2584 HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) { 2585 clk_prepare_enable(vc4_hdmi->pixel_clock); 2586 clk_prepare_enable(vc4_hdmi->hsm_clock); 2587 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock); 2588 } 2589 2590 drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS); 2591 drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs); 2592 2593 ret = vc4_hdmi_connector_init(drm, vc4_hdmi); 2594 if (ret) 2595 goto err_destroy_encoder; 2596 2597 ret = vc4_hdmi_hotplug_init(vc4_hdmi); 2598 if (ret) 2599 goto err_destroy_conn; 2600 2601 ret = vc4_hdmi_cec_init(vc4_hdmi); 2602 if (ret) 2603 goto err_free_hotplug; 2604 2605 ret = vc4_hdmi_audio_init(vc4_hdmi); 2606 if (ret) 2607 goto err_free_cec; 2608 2609 vc4_debugfs_add_file(drm, variant->debugfs_name, 2610 vc4_hdmi_debugfs_regs, 2611 vc4_hdmi); 2612 2613 pm_runtime_put_sync(dev); 2614 2615 return 0; 2616 2617 err_free_cec: 2618 vc4_hdmi_cec_exit(vc4_hdmi); 2619 err_free_hotplug: 2620 vc4_hdmi_hotplug_exit(vc4_hdmi); 2621 err_destroy_conn: 2622 vc4_hdmi_connector_destroy(&vc4_hdmi->connector); 2623 err_destroy_encoder: 2624 drm_encoder_cleanup(encoder); 2625 pm_runtime_put_sync(dev); 2626 pm_runtime_disable(dev); 2627 err_put_ddc: 2628 put_device(&vc4_hdmi->ddc->dev); 2629 2630 return ret; 2631 } 2632 2633 static void vc4_hdmi_unbind(struct device *dev, struct device *master, 2634 void *data) 2635 { 2636 struct vc4_hdmi *vc4_hdmi; 2637 2638 /* 2639 * ASoC makes it a bit hard to retrieve a pointer to the 2640 * vc4_hdmi structure. Registering the card will overwrite our 2641 * device drvdata with a pointer to the snd_soc_card structure, 2642 * which can then be used to retrieve whatever drvdata we want 2643 * to associate. 2644 * 2645 * However, that doesn't fly in the case where we wouldn't 2646 * register an ASoC card (because of an old DT that is missing 2647 * the dmas properties for example), then the card isn't 2648 * registered and the device drvdata wouldn't be set. 2649 * 2650 * We can deal with both cases by making sure a snd_soc_card 2651 * pointer and a vc4_hdmi structure are pointing to the same 2652 * memory address, so we can treat them indistinctly without any 2653 * issue. 2654 */ 2655 BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0); 2656 BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0); 2657 vc4_hdmi = dev_get_drvdata(dev); 2658 2659 kfree(vc4_hdmi->hdmi_regset.regs); 2660 kfree(vc4_hdmi->hd_regset.regs); 2661 2662 vc4_hdmi_cec_exit(vc4_hdmi); 2663 vc4_hdmi_hotplug_exit(vc4_hdmi); 2664 vc4_hdmi_connector_destroy(&vc4_hdmi->connector); 2665 drm_encoder_cleanup(&vc4_hdmi->encoder.base.base); 2666 2667 pm_runtime_disable(dev); 2668 2669 put_device(&vc4_hdmi->ddc->dev); 2670 } 2671 2672 static const struct component_ops vc4_hdmi_ops = { 2673 .bind = vc4_hdmi_bind, 2674 .unbind = vc4_hdmi_unbind, 2675 }; 2676 2677 static int vc4_hdmi_dev_probe(struct platform_device *pdev) 2678 { 2679 return component_add(&pdev->dev, &vc4_hdmi_ops); 2680 } 2681 2682 static int vc4_hdmi_dev_remove(struct platform_device *pdev) 2683 { 2684 component_del(&pdev->dev, &vc4_hdmi_ops); 2685 return 0; 2686 } 2687 2688 static const struct vc4_hdmi_variant bcm2835_variant = { 2689 .encoder_type = VC4_ENCODER_TYPE_HDMI0, 2690 .debugfs_name = "hdmi_regs", 2691 .card_name = "vc4-hdmi", 2692 .max_pixel_clock = 162000000, 2693 .registers = vc4_hdmi_fields, 2694 .num_registers = ARRAY_SIZE(vc4_hdmi_fields), 2695 2696 .init_resources = vc4_hdmi_init_resources, 2697 .csc_setup = vc4_hdmi_csc_setup, 2698 .reset = vc4_hdmi_reset, 2699 .set_timings = vc4_hdmi_set_timings, 2700 .phy_init = vc4_hdmi_phy_init, 2701 .phy_disable = vc4_hdmi_phy_disable, 2702 .phy_rng_enable = vc4_hdmi_phy_rng_enable, 2703 .phy_rng_disable = vc4_hdmi_phy_rng_disable, 2704 .channel_map = vc4_hdmi_channel_map, 2705 .supports_hdr = false, 2706 }; 2707 2708 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = { 2709 .encoder_type = VC4_ENCODER_TYPE_HDMI0, 2710 .debugfs_name = "hdmi0_regs", 2711 .card_name = "vc4-hdmi-0", 2712 .max_pixel_clock = 600000000, 2713 .registers = vc5_hdmi_hdmi0_fields, 2714 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi0_fields), 2715 .phy_lane_mapping = { 2716 PHY_LANE_0, 2717 PHY_LANE_1, 2718 PHY_LANE_2, 2719 PHY_LANE_CK, 2720 }, 2721 .unsupported_odd_h_timings = true, 2722 .external_irq_controller = true, 2723 2724 .init_resources = vc5_hdmi_init_resources, 2725 .csc_setup = vc5_hdmi_csc_setup, 2726 .reset = vc5_hdmi_reset, 2727 .set_timings = vc5_hdmi_set_timings, 2728 .phy_init = vc5_hdmi_phy_init, 2729 .phy_disable = vc5_hdmi_phy_disable, 2730 .phy_rng_enable = vc5_hdmi_phy_rng_enable, 2731 .phy_rng_disable = vc5_hdmi_phy_rng_disable, 2732 .channel_map = vc5_hdmi_channel_map, 2733 .supports_hdr = true, 2734 }; 2735 2736 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = { 2737 .encoder_type = VC4_ENCODER_TYPE_HDMI1, 2738 .debugfs_name = "hdmi1_regs", 2739 .card_name = "vc4-hdmi-1", 2740 .max_pixel_clock = HDMI_14_MAX_TMDS_CLK, 2741 .registers = vc5_hdmi_hdmi1_fields, 2742 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi1_fields), 2743 .phy_lane_mapping = { 2744 PHY_LANE_1, 2745 PHY_LANE_0, 2746 PHY_LANE_CK, 2747 PHY_LANE_2, 2748 }, 2749 .unsupported_odd_h_timings = true, 2750 .external_irq_controller = true, 2751 2752 .init_resources = vc5_hdmi_init_resources, 2753 .csc_setup = vc5_hdmi_csc_setup, 2754 .reset = vc5_hdmi_reset, 2755 .set_timings = vc5_hdmi_set_timings, 2756 .phy_init = vc5_hdmi_phy_init, 2757 .phy_disable = vc5_hdmi_phy_disable, 2758 .phy_rng_enable = vc5_hdmi_phy_rng_enable, 2759 .phy_rng_disable = vc5_hdmi_phy_rng_disable, 2760 .channel_map = vc5_hdmi_channel_map, 2761 .supports_hdr = true, 2762 }; 2763 2764 static const struct of_device_id vc4_hdmi_dt_match[] = { 2765 { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant }, 2766 { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant }, 2767 { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant }, 2768 {} 2769 }; 2770 2771 static const struct dev_pm_ops vc4_hdmi_pm_ops = { 2772 SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend, 2773 vc4_hdmi_runtime_resume, 2774 NULL) 2775 }; 2776 2777 struct platform_driver vc4_hdmi_driver = { 2778 .probe = vc4_hdmi_dev_probe, 2779 .remove = vc4_hdmi_dev_remove, 2780 .driver = { 2781 .name = "vc4_hdmi", 2782 .of_match_table = vc4_hdmi_dt_match, 2783 .pm = &vc4_hdmi_pm_ops, 2784 }, 2785 }; 2786