1 /* 2 * Copyright (C) 2015 Broadcom 3 * Copyright (c) 2014 The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License version 2 as published by 9 * the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 /** 21 * DOC: VC4 Falcon HDMI module 22 * 23 * The HDMI core has a state machine and a PHY. On BCM2835, most of 24 * the unit operates off of the HSM clock from CPRMAN. It also 25 * internally uses the PLLH_PIX clock for the PHY. 26 * 27 * HDMI infoframes are kept within a small packet ram, where each 28 * packet can be individually enabled for including in a frame. 29 * 30 * HDMI audio is implemented entirely within the HDMI IP block. A 31 * register in the HDMI encoder takes SPDIF frames from the DMA engine 32 * and transfers them over an internal MAI (multi-channel audio 33 * interconnect) bus to the encoder side for insertion into the video 34 * blank regions. 35 * 36 * The driver's HDMI encoder does not yet support power management. 37 * The HDMI encoder's power domain and the HSM/pixel clocks are kept 38 * continuously running, and only the HDMI logic and packet ram are 39 * powered off/on at disable/enable time. 40 * 41 * The driver does not yet support CEC control, though the HDMI 42 * encoder block has CEC support. 43 */ 44 45 #include <drm/drm_atomic_helper.h> 46 #include <drm/drm_crtc_helper.h> 47 #include <drm/drm_edid.h> 48 #include <linux/clk.h> 49 #include <linux/component.h> 50 #include <linux/i2c.h> 51 #include <linux/of_address.h> 52 #include <linux/of_gpio.h> 53 #include <linux/of_platform.h> 54 #include <linux/pm_runtime.h> 55 #include <linux/rational.h> 56 #include <sound/dmaengine_pcm.h> 57 #include <sound/pcm_drm_eld.h> 58 #include <sound/pcm_params.h> 59 #include <sound/soc.h> 60 #include "vc4_drv.h" 61 #include "vc4_regs.h" 62 63 /* HDMI audio information */ 64 struct vc4_hdmi_audio { 65 struct snd_soc_card card; 66 struct snd_soc_dai_link link; 67 int samplerate; 68 int channels; 69 struct snd_dmaengine_dai_dma_data dma_data; 70 struct snd_pcm_substream *substream; 71 }; 72 73 /* General HDMI hardware state. */ 74 struct vc4_hdmi { 75 struct platform_device *pdev; 76 77 struct drm_encoder *encoder; 78 struct drm_connector *connector; 79 80 struct vc4_hdmi_audio audio; 81 82 struct i2c_adapter *ddc; 83 void __iomem *hdmicore_regs; 84 void __iomem *hd_regs; 85 int hpd_gpio; 86 bool hpd_active_low; 87 88 struct clk *pixel_clock; 89 struct clk *hsm_clock; 90 }; 91 92 #define HDMI_READ(offset) readl(vc4->hdmi->hdmicore_regs + offset) 93 #define HDMI_WRITE(offset, val) writel(val, vc4->hdmi->hdmicore_regs + offset) 94 #define HD_READ(offset) readl(vc4->hdmi->hd_regs + offset) 95 #define HD_WRITE(offset, val) writel(val, vc4->hdmi->hd_regs + offset) 96 97 /* VC4 HDMI encoder KMS struct */ 98 struct vc4_hdmi_encoder { 99 struct vc4_encoder base; 100 bool hdmi_monitor; 101 bool limited_rgb_range; 102 bool rgb_range_selectable; 103 }; 104 105 static inline struct vc4_hdmi_encoder * 106 to_vc4_hdmi_encoder(struct drm_encoder *encoder) 107 { 108 return container_of(encoder, struct vc4_hdmi_encoder, base.base); 109 } 110 111 /* VC4 HDMI connector KMS struct */ 112 struct vc4_hdmi_connector { 113 struct drm_connector base; 114 115 /* Since the connector is attached to just the one encoder, 116 * this is the reference to it so we can do the best_encoder() 117 * hook. 118 */ 119 struct drm_encoder *encoder; 120 }; 121 122 static inline struct vc4_hdmi_connector * 123 to_vc4_hdmi_connector(struct drm_connector *connector) 124 { 125 return container_of(connector, struct vc4_hdmi_connector, base); 126 } 127 128 #define HDMI_REG(reg) { reg, #reg } 129 static const struct { 130 u32 reg; 131 const char *name; 132 } hdmi_regs[] = { 133 HDMI_REG(VC4_HDMI_CORE_REV), 134 HDMI_REG(VC4_HDMI_SW_RESET_CONTROL), 135 HDMI_REG(VC4_HDMI_HOTPLUG_INT), 136 HDMI_REG(VC4_HDMI_HOTPLUG), 137 HDMI_REG(VC4_HDMI_MAI_CHANNEL_MAP), 138 HDMI_REG(VC4_HDMI_MAI_CONFIG), 139 HDMI_REG(VC4_HDMI_MAI_FORMAT), 140 HDMI_REG(VC4_HDMI_AUDIO_PACKET_CONFIG), 141 HDMI_REG(VC4_HDMI_RAM_PACKET_CONFIG), 142 HDMI_REG(VC4_HDMI_HORZA), 143 HDMI_REG(VC4_HDMI_HORZB), 144 HDMI_REG(VC4_HDMI_FIFO_CTL), 145 HDMI_REG(VC4_HDMI_SCHEDULER_CONTROL), 146 HDMI_REG(VC4_HDMI_VERTA0), 147 HDMI_REG(VC4_HDMI_VERTA1), 148 HDMI_REG(VC4_HDMI_VERTB0), 149 HDMI_REG(VC4_HDMI_VERTB1), 150 HDMI_REG(VC4_HDMI_TX_PHY_RESET_CTL), 151 HDMI_REG(VC4_HDMI_TX_PHY_CTL0), 152 }; 153 154 static const struct { 155 u32 reg; 156 const char *name; 157 } hd_regs[] = { 158 HDMI_REG(VC4_HD_M_CTL), 159 HDMI_REG(VC4_HD_MAI_CTL), 160 HDMI_REG(VC4_HD_MAI_THR), 161 HDMI_REG(VC4_HD_MAI_FMT), 162 HDMI_REG(VC4_HD_MAI_SMP), 163 HDMI_REG(VC4_HD_VID_CTL), 164 HDMI_REG(VC4_HD_CSC_CTL), 165 HDMI_REG(VC4_HD_FRAME_COUNT), 166 }; 167 168 #ifdef CONFIG_DEBUG_FS 169 int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused) 170 { 171 struct drm_info_node *node = (struct drm_info_node *)m->private; 172 struct drm_device *dev = node->minor->dev; 173 struct vc4_dev *vc4 = to_vc4_dev(dev); 174 int i; 175 176 for (i = 0; i < ARRAY_SIZE(hdmi_regs); i++) { 177 seq_printf(m, "%s (0x%04x): 0x%08x\n", 178 hdmi_regs[i].name, hdmi_regs[i].reg, 179 HDMI_READ(hdmi_regs[i].reg)); 180 } 181 182 for (i = 0; i < ARRAY_SIZE(hd_regs); i++) { 183 seq_printf(m, "%s (0x%04x): 0x%08x\n", 184 hd_regs[i].name, hd_regs[i].reg, 185 HD_READ(hd_regs[i].reg)); 186 } 187 188 return 0; 189 } 190 #endif /* CONFIG_DEBUG_FS */ 191 192 static void vc4_hdmi_dump_regs(struct drm_device *dev) 193 { 194 struct vc4_dev *vc4 = to_vc4_dev(dev); 195 int i; 196 197 for (i = 0; i < ARRAY_SIZE(hdmi_regs); i++) { 198 DRM_INFO("0x%04x (%s): 0x%08x\n", 199 hdmi_regs[i].reg, hdmi_regs[i].name, 200 HDMI_READ(hdmi_regs[i].reg)); 201 } 202 for (i = 0; i < ARRAY_SIZE(hd_regs); i++) { 203 DRM_INFO("0x%04x (%s): 0x%08x\n", 204 hd_regs[i].reg, hd_regs[i].name, 205 HD_READ(hd_regs[i].reg)); 206 } 207 } 208 209 static enum drm_connector_status 210 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force) 211 { 212 struct drm_device *dev = connector->dev; 213 struct vc4_dev *vc4 = to_vc4_dev(dev); 214 215 if (vc4->hdmi->hpd_gpio) { 216 if (gpio_get_value_cansleep(vc4->hdmi->hpd_gpio) ^ 217 vc4->hdmi->hpd_active_low) 218 return connector_status_connected; 219 else 220 return connector_status_disconnected; 221 } 222 223 if (drm_probe_ddc(vc4->hdmi->ddc)) 224 return connector_status_connected; 225 226 if (HDMI_READ(VC4_HDMI_HOTPLUG) & VC4_HDMI_HOTPLUG_CONNECTED) 227 return connector_status_connected; 228 else 229 return connector_status_disconnected; 230 } 231 232 static void vc4_hdmi_connector_destroy(struct drm_connector *connector) 233 { 234 drm_connector_unregister(connector); 235 drm_connector_cleanup(connector); 236 } 237 238 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector) 239 { 240 struct vc4_hdmi_connector *vc4_connector = 241 to_vc4_hdmi_connector(connector); 242 struct drm_encoder *encoder = vc4_connector->encoder; 243 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 244 struct drm_device *dev = connector->dev; 245 struct vc4_dev *vc4 = to_vc4_dev(dev); 246 int ret = 0; 247 struct edid *edid; 248 249 edid = drm_get_edid(connector, vc4->hdmi->ddc); 250 if (!edid) 251 return -ENODEV; 252 253 vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid); 254 255 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) { 256 vc4_encoder->rgb_range_selectable = 257 drm_rgb_quant_range_selectable(edid); 258 } 259 260 drm_mode_connector_update_edid_property(connector, edid); 261 ret = drm_add_edid_modes(connector, edid); 262 drm_edid_to_eld(connector, edid); 263 264 return ret; 265 } 266 267 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = { 268 .dpms = drm_atomic_helper_connector_dpms, 269 .detect = vc4_hdmi_connector_detect, 270 .fill_modes = drm_helper_probe_single_connector_modes, 271 .destroy = vc4_hdmi_connector_destroy, 272 .reset = drm_atomic_helper_connector_reset, 273 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 274 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 275 }; 276 277 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = { 278 .get_modes = vc4_hdmi_connector_get_modes, 279 }; 280 281 static struct drm_connector *vc4_hdmi_connector_init(struct drm_device *dev, 282 struct drm_encoder *encoder) 283 { 284 struct drm_connector *connector = NULL; 285 struct vc4_hdmi_connector *hdmi_connector; 286 int ret = 0; 287 288 hdmi_connector = devm_kzalloc(dev->dev, sizeof(*hdmi_connector), 289 GFP_KERNEL); 290 if (!hdmi_connector) { 291 ret = -ENOMEM; 292 goto fail; 293 } 294 connector = &hdmi_connector->base; 295 296 hdmi_connector->encoder = encoder; 297 298 drm_connector_init(dev, connector, &vc4_hdmi_connector_funcs, 299 DRM_MODE_CONNECTOR_HDMIA); 300 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs); 301 302 connector->polled = (DRM_CONNECTOR_POLL_CONNECT | 303 DRM_CONNECTOR_POLL_DISCONNECT); 304 305 connector->interlace_allowed = 1; 306 connector->doublescan_allowed = 0; 307 308 drm_mode_connector_attach_encoder(connector, encoder); 309 310 return connector; 311 312 fail: 313 if (connector) 314 vc4_hdmi_connector_destroy(connector); 315 316 return ERR_PTR(ret); 317 } 318 319 static void vc4_hdmi_encoder_destroy(struct drm_encoder *encoder) 320 { 321 drm_encoder_cleanup(encoder); 322 } 323 324 static const struct drm_encoder_funcs vc4_hdmi_encoder_funcs = { 325 .destroy = vc4_hdmi_encoder_destroy, 326 }; 327 328 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder, 329 enum hdmi_infoframe_type type) 330 { 331 struct drm_device *dev = encoder->dev; 332 struct vc4_dev *vc4 = to_vc4_dev(dev); 333 u32 packet_id = type - 0x80; 334 335 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, 336 HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id)); 337 338 return wait_for(!(HDMI_READ(VC4_HDMI_RAM_PACKET_STATUS) & 339 BIT(packet_id)), 100); 340 } 341 342 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder, 343 union hdmi_infoframe *frame) 344 { 345 struct drm_device *dev = encoder->dev; 346 struct vc4_dev *vc4 = to_vc4_dev(dev); 347 u32 packet_id = frame->any.type - 0x80; 348 u32 packet_reg = VC4_HDMI_RAM_PACKET(packet_id); 349 uint8_t buffer[VC4_HDMI_PACKET_STRIDE]; 350 ssize_t len, i; 351 int ret; 352 353 WARN_ONCE(!(HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) & 354 VC4_HDMI_RAM_PACKET_ENABLE), 355 "Packet RAM has to be on to store the packet."); 356 357 len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer)); 358 if (len < 0) 359 return; 360 361 ret = vc4_hdmi_stop_packet(encoder, frame->any.type); 362 if (ret) { 363 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret); 364 return; 365 } 366 367 for (i = 0; i < len; i += 7) { 368 HDMI_WRITE(packet_reg, 369 buffer[i + 0] << 0 | 370 buffer[i + 1] << 8 | 371 buffer[i + 2] << 16); 372 packet_reg += 4; 373 374 HDMI_WRITE(packet_reg, 375 buffer[i + 3] << 0 | 376 buffer[i + 4] << 8 | 377 buffer[i + 5] << 16 | 378 buffer[i + 6] << 24); 379 packet_reg += 4; 380 } 381 382 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, 383 HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) | BIT(packet_id)); 384 ret = wait_for((HDMI_READ(VC4_HDMI_RAM_PACKET_STATUS) & 385 BIT(packet_id)), 100); 386 if (ret) 387 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret); 388 } 389 390 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder) 391 { 392 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 393 struct drm_crtc *crtc = encoder->crtc; 394 const struct drm_display_mode *mode = &crtc->state->adjusted_mode; 395 union hdmi_infoframe frame; 396 int ret; 397 398 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, mode); 399 if (ret < 0) { 400 DRM_ERROR("couldn't fill AVI infoframe\n"); 401 return; 402 } 403 404 drm_hdmi_avi_infoframe_quant_range(&frame.avi, mode, 405 vc4_encoder->limited_rgb_range ? 406 HDMI_QUANTIZATION_RANGE_LIMITED : 407 HDMI_QUANTIZATION_RANGE_FULL, 408 vc4_encoder->rgb_range_selectable); 409 410 vc4_hdmi_write_infoframe(encoder, &frame); 411 } 412 413 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder) 414 { 415 union hdmi_infoframe frame; 416 int ret; 417 418 ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore"); 419 if (ret < 0) { 420 DRM_ERROR("couldn't fill SPD infoframe\n"); 421 return; 422 } 423 424 frame.spd.sdi = HDMI_SPD_SDI_PC; 425 426 vc4_hdmi_write_infoframe(encoder, &frame); 427 } 428 429 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder) 430 { 431 struct drm_device *drm = encoder->dev; 432 struct vc4_dev *vc4 = drm->dev_private; 433 struct vc4_hdmi *hdmi = vc4->hdmi; 434 union hdmi_infoframe frame; 435 int ret; 436 437 ret = hdmi_audio_infoframe_init(&frame.audio); 438 439 frame.audio.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM; 440 frame.audio.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM; 441 frame.audio.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM; 442 frame.audio.channels = hdmi->audio.channels; 443 444 vc4_hdmi_write_infoframe(encoder, &frame); 445 } 446 447 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder) 448 { 449 vc4_hdmi_set_avi_infoframe(encoder); 450 vc4_hdmi_set_spd_infoframe(encoder); 451 } 452 453 static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder) 454 { 455 struct drm_device *dev = encoder->dev; 456 struct vc4_dev *vc4 = to_vc4_dev(dev); 457 struct vc4_hdmi *hdmi = vc4->hdmi; 458 int ret; 459 460 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, 0); 461 462 HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16); 463 HD_WRITE(VC4_HD_VID_CTL, 464 HD_READ(VC4_HD_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE); 465 466 HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_SW_RST); 467 udelay(1); 468 HD_WRITE(VC4_HD_M_CTL, 0); 469 470 clk_disable_unprepare(hdmi->hsm_clock); 471 clk_disable_unprepare(hdmi->pixel_clock); 472 473 ret = pm_runtime_put(&hdmi->pdev->dev); 474 if (ret < 0) 475 DRM_ERROR("Failed to release power domain: %d\n", ret); 476 } 477 478 static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder) 479 { 480 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; 481 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 482 struct drm_device *dev = encoder->dev; 483 struct vc4_dev *vc4 = to_vc4_dev(dev); 484 struct vc4_hdmi *hdmi = vc4->hdmi; 485 bool debug_dump_regs = false; 486 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 487 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 488 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 489 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 490 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 491 VC4_HDMI_VERTA_VSP) | 492 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 493 VC4_HDMI_VERTA_VFP) | 494 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL)); 495 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 496 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end, 497 VC4_HDMI_VERTB_VBP)); 498 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 499 VC4_SET_FIELD(mode->crtc_vtotal - 500 mode->crtc_vsync_end - 501 interlaced, 502 VC4_HDMI_VERTB_VBP)); 503 u32 csc_ctl; 504 int ret; 505 506 ret = pm_runtime_get_sync(&hdmi->pdev->dev); 507 if (ret < 0) { 508 DRM_ERROR("Failed to retain power domain: %d\n", ret); 509 return; 510 } 511 512 /* This is the rate that is set by the firmware. The number 513 * needs to be a bit higher than the pixel clock rate 514 * (generally 148.5Mhz). 515 */ 516 ret = clk_set_rate(hdmi->hsm_clock, 163682864); 517 if (ret) { 518 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret); 519 return; 520 } 521 522 ret = clk_set_rate(hdmi->pixel_clock, 523 mode->clock * 1000 * 524 ((mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1)); 525 if (ret) { 526 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret); 527 return; 528 } 529 530 ret = clk_prepare_enable(hdmi->pixel_clock); 531 if (ret) { 532 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret); 533 return; 534 } 535 536 ret = clk_prepare_enable(hdmi->hsm_clock); 537 if (ret) { 538 DRM_ERROR("Failed to turn on HDMI state machine clock: %d\n", 539 ret); 540 clk_disable_unprepare(hdmi->pixel_clock); 541 return; 542 } 543 544 HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_SW_RST); 545 udelay(1); 546 HD_WRITE(VC4_HD_M_CTL, 0); 547 548 HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_ENABLE); 549 550 HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL, 551 VC4_HDMI_SW_RESET_HDMI | 552 VC4_HDMI_SW_RESET_FORMAT_DETECT); 553 554 HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL, 0); 555 556 /* PHY should be in reset, like 557 * vc4_hdmi_encoder_disable() does. 558 */ 559 HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16); 560 561 HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0); 562 563 if (debug_dump_regs) { 564 DRM_INFO("HDMI regs before:\n"); 565 vc4_hdmi_dump_regs(dev); 566 } 567 568 HD_WRITE(VC4_HD_VID_CTL, 0); 569 570 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL, 571 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) | 572 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT | 573 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS); 574 575 HDMI_WRITE(VC4_HDMI_HORZA, 576 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) | 577 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) | 578 VC4_SET_FIELD(mode->hdisplay * pixel_rep, 579 VC4_HDMI_HORZA_HAP)); 580 581 HDMI_WRITE(VC4_HDMI_HORZB, 582 VC4_SET_FIELD((mode->htotal - 583 mode->hsync_end) * pixel_rep, 584 VC4_HDMI_HORZB_HBP) | 585 VC4_SET_FIELD((mode->hsync_end - 586 mode->hsync_start) * pixel_rep, 587 VC4_HDMI_HORZB_HSP) | 588 VC4_SET_FIELD((mode->hsync_start - 589 mode->hdisplay) * pixel_rep, 590 VC4_HDMI_HORZB_HFP)); 591 592 HDMI_WRITE(VC4_HDMI_VERTA0, verta); 593 HDMI_WRITE(VC4_HDMI_VERTA1, verta); 594 595 HDMI_WRITE(VC4_HDMI_VERTB0, vertb_even); 596 HDMI_WRITE(VC4_HDMI_VERTB1, vertb); 597 598 HD_WRITE(VC4_HD_VID_CTL, 599 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) | 600 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW)); 601 602 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR, 603 VC4_HD_CSC_CTL_ORDER); 604 605 if (vc4_encoder->hdmi_monitor && 606 drm_default_rgb_quant_range(mode) == 607 HDMI_QUANTIZATION_RANGE_LIMITED) { 608 /* CEA VICs other than #1 requre limited range RGB 609 * output unless overridden by an AVI infoframe. 610 * Apply a colorspace conversion to squash 0-255 down 611 * to 16-235. The matrix here is: 612 * 613 * [ 0 0 0.8594 16] 614 * [ 0 0.8594 0 16] 615 * [ 0.8594 0 0 16] 616 * [ 0 0 0 1] 617 */ 618 csc_ctl |= VC4_HD_CSC_CTL_ENABLE; 619 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC; 620 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM, 621 VC4_HD_CSC_CTL_MODE); 622 623 HD_WRITE(VC4_HD_CSC_12_11, (0x000 << 16) | 0x000); 624 HD_WRITE(VC4_HD_CSC_14_13, (0x100 << 16) | 0x6e0); 625 HD_WRITE(VC4_HD_CSC_22_21, (0x6e0 << 16) | 0x000); 626 HD_WRITE(VC4_HD_CSC_24_23, (0x100 << 16) | 0x000); 627 HD_WRITE(VC4_HD_CSC_32_31, (0x000 << 16) | 0x6e0); 628 HD_WRITE(VC4_HD_CSC_34_33, (0x100 << 16) | 0x000); 629 vc4_encoder->limited_rgb_range = true; 630 } else { 631 vc4_encoder->limited_rgb_range = false; 632 } 633 634 /* The RGB order applies even when CSC is disabled. */ 635 HD_WRITE(VC4_HD_CSC_CTL, csc_ctl); 636 637 HDMI_WRITE(VC4_HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N); 638 639 if (debug_dump_regs) { 640 DRM_INFO("HDMI regs after:\n"); 641 vc4_hdmi_dump_regs(dev); 642 } 643 644 HD_WRITE(VC4_HD_VID_CTL, 645 HD_READ(VC4_HD_VID_CTL) | 646 VC4_HD_VID_CTL_ENABLE | 647 VC4_HD_VID_CTL_UNDERFLOW_ENABLE | 648 VC4_HD_VID_CTL_FRAME_COUNTER_RESET); 649 650 if (vc4_encoder->hdmi_monitor) { 651 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL, 652 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) | 653 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 654 655 ret = wait_for(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) & 656 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000); 657 WARN_ONCE(ret, "Timeout waiting for " 658 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 659 } else { 660 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, 661 HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) & 662 ~(VC4_HDMI_RAM_PACKET_ENABLE)); 663 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL, 664 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) & 665 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 666 667 ret = wait_for(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) & 668 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000); 669 WARN_ONCE(ret, "Timeout waiting for " 670 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 671 } 672 673 if (vc4_encoder->hdmi_monitor) { 674 u32 drift; 675 676 WARN_ON(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) & 677 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE)); 678 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL, 679 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) | 680 VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT); 681 682 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, 683 VC4_HDMI_RAM_PACKET_ENABLE); 684 685 vc4_hdmi_set_infoframes(encoder); 686 687 drift = HDMI_READ(VC4_HDMI_FIFO_CTL); 688 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK; 689 690 HDMI_WRITE(VC4_HDMI_FIFO_CTL, 691 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 692 HDMI_WRITE(VC4_HDMI_FIFO_CTL, 693 drift | VC4_HDMI_FIFO_CTL_RECENTER); 694 udelay(1000); 695 HDMI_WRITE(VC4_HDMI_FIFO_CTL, 696 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 697 HDMI_WRITE(VC4_HDMI_FIFO_CTL, 698 drift | VC4_HDMI_FIFO_CTL_RECENTER); 699 700 ret = wait_for(HDMI_READ(VC4_HDMI_FIFO_CTL) & 701 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1); 702 WARN_ONCE(ret, "Timeout waiting for " 703 "VC4_HDMI_FIFO_CTL_RECENTER_DONE"); 704 } 705 } 706 707 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = { 708 .disable = vc4_hdmi_encoder_disable, 709 .enable = vc4_hdmi_encoder_enable, 710 }; 711 712 /* HDMI audio codec callbacks */ 713 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *hdmi) 714 { 715 struct drm_device *drm = hdmi->encoder->dev; 716 struct vc4_dev *vc4 = to_vc4_dev(drm); 717 u32 hsm_clock = clk_get_rate(hdmi->hsm_clock); 718 unsigned long n, m; 719 720 rational_best_approximation(hsm_clock, hdmi->audio.samplerate, 721 VC4_HD_MAI_SMP_N_MASK >> 722 VC4_HD_MAI_SMP_N_SHIFT, 723 (VC4_HD_MAI_SMP_M_MASK >> 724 VC4_HD_MAI_SMP_M_SHIFT) + 1, 725 &n, &m); 726 727 HD_WRITE(VC4_HD_MAI_SMP, 728 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) | 729 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M)); 730 } 731 732 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *hdmi) 733 { 734 struct drm_encoder *encoder = hdmi->encoder; 735 struct drm_crtc *crtc = encoder->crtc; 736 struct drm_device *drm = encoder->dev; 737 struct vc4_dev *vc4 = to_vc4_dev(drm); 738 const struct drm_display_mode *mode = &crtc->state->adjusted_mode; 739 u32 samplerate = hdmi->audio.samplerate; 740 u32 n, cts; 741 u64 tmp; 742 743 n = 128 * samplerate / 1000; 744 tmp = (u64)(mode->clock * 1000) * n; 745 do_div(tmp, 128 * samplerate); 746 cts = tmp; 747 748 HDMI_WRITE(VC4_HDMI_CRP_CFG, 749 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN | 750 VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N)); 751 752 /* 753 * We could get slightly more accurate clocks in some cases by 754 * providing a CTS_1 value. The two CTS values are alternated 755 * between based on the period fields 756 */ 757 HDMI_WRITE(VC4_HDMI_CTS_0, cts); 758 HDMI_WRITE(VC4_HDMI_CTS_1, cts); 759 } 760 761 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai) 762 { 763 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai); 764 765 return snd_soc_card_get_drvdata(card); 766 } 767 768 static int vc4_hdmi_audio_startup(struct snd_pcm_substream *substream, 769 struct snd_soc_dai *dai) 770 { 771 struct vc4_hdmi *hdmi = dai_to_hdmi(dai); 772 struct drm_encoder *encoder = hdmi->encoder; 773 struct vc4_dev *vc4 = to_vc4_dev(encoder->dev); 774 int ret; 775 776 if (hdmi->audio.substream && hdmi->audio.substream != substream) 777 return -EINVAL; 778 779 hdmi->audio.substream = substream; 780 781 /* 782 * If the HDMI encoder hasn't probed, or the encoder is 783 * currently in DVI mode, treat the codec dai as missing. 784 */ 785 if (!encoder->crtc || !(HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) & 786 VC4_HDMI_RAM_PACKET_ENABLE)) 787 return -ENODEV; 788 789 ret = snd_pcm_hw_constraint_eld(substream->runtime, 790 hdmi->connector->eld); 791 if (ret) 792 return ret; 793 794 return 0; 795 } 796 797 static int vc4_hdmi_audio_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 798 { 799 return 0; 800 } 801 802 static void vc4_hdmi_audio_reset(struct vc4_hdmi *hdmi) 803 { 804 struct drm_encoder *encoder = hdmi->encoder; 805 struct drm_device *drm = encoder->dev; 806 struct device *dev = &hdmi->pdev->dev; 807 struct vc4_dev *vc4 = to_vc4_dev(drm); 808 int ret; 809 810 ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO); 811 if (ret) 812 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret); 813 814 HD_WRITE(VC4_HD_MAI_CTL, VC4_HD_MAI_CTL_RESET); 815 HD_WRITE(VC4_HD_MAI_CTL, VC4_HD_MAI_CTL_ERRORF); 816 HD_WRITE(VC4_HD_MAI_CTL, VC4_HD_MAI_CTL_FLUSH); 817 } 818 819 static void vc4_hdmi_audio_shutdown(struct snd_pcm_substream *substream, 820 struct snd_soc_dai *dai) 821 { 822 struct vc4_hdmi *hdmi = dai_to_hdmi(dai); 823 824 if (substream != hdmi->audio.substream) 825 return; 826 827 vc4_hdmi_audio_reset(hdmi); 828 829 hdmi->audio.substream = NULL; 830 } 831 832 /* HDMI audio codec callbacks */ 833 static int vc4_hdmi_audio_hw_params(struct snd_pcm_substream *substream, 834 struct snd_pcm_hw_params *params, 835 struct snd_soc_dai *dai) 836 { 837 struct vc4_hdmi *hdmi = dai_to_hdmi(dai); 838 struct drm_encoder *encoder = hdmi->encoder; 839 struct drm_device *drm = encoder->dev; 840 struct device *dev = &hdmi->pdev->dev; 841 struct vc4_dev *vc4 = to_vc4_dev(drm); 842 u32 audio_packet_config, channel_mask; 843 u32 channel_map, i; 844 845 if (substream != hdmi->audio.substream) 846 return -EINVAL; 847 848 dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__, 849 params_rate(params), params_width(params), 850 params_channels(params)); 851 852 hdmi->audio.channels = params_channels(params); 853 hdmi->audio.samplerate = params_rate(params); 854 855 HD_WRITE(VC4_HD_MAI_CTL, 856 VC4_HD_MAI_CTL_RESET | 857 VC4_HD_MAI_CTL_FLUSH | 858 VC4_HD_MAI_CTL_DLATE | 859 VC4_HD_MAI_CTL_ERRORE | 860 VC4_HD_MAI_CTL_ERRORF); 861 862 vc4_hdmi_audio_set_mai_clock(hdmi); 863 864 audio_packet_config = 865 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT | 866 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS | 867 VC4_SET_FIELD(0xf, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER); 868 869 channel_mask = GENMASK(hdmi->audio.channels - 1, 0); 870 audio_packet_config |= VC4_SET_FIELD(channel_mask, 871 VC4_HDMI_AUDIO_PACKET_CEA_MASK); 872 873 /* Set the MAI threshold. This logic mimics the firmware's. */ 874 if (hdmi->audio.samplerate > 96000) { 875 HD_WRITE(VC4_HD_MAI_THR, 876 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQHIGH) | 877 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW)); 878 } else if (hdmi->audio.samplerate > 48000) { 879 HD_WRITE(VC4_HD_MAI_THR, 880 VC4_SET_FIELD(0x14, VC4_HD_MAI_THR_DREQHIGH) | 881 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW)); 882 } else { 883 HD_WRITE(VC4_HD_MAI_THR, 884 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) | 885 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) | 886 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQHIGH) | 887 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQLOW)); 888 } 889 890 HDMI_WRITE(VC4_HDMI_MAI_CONFIG, 891 VC4_HDMI_MAI_CONFIG_BIT_REVERSE | 892 VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK)); 893 894 channel_map = 0; 895 for (i = 0; i < 8; i++) { 896 if (channel_mask & BIT(i)) 897 channel_map |= i << (3 * i); 898 } 899 900 HDMI_WRITE(VC4_HDMI_MAI_CHANNEL_MAP, channel_map); 901 HDMI_WRITE(VC4_HDMI_AUDIO_PACKET_CONFIG, audio_packet_config); 902 vc4_hdmi_set_n_cts(hdmi); 903 904 return 0; 905 } 906 907 static int vc4_hdmi_audio_trigger(struct snd_pcm_substream *substream, int cmd, 908 struct snd_soc_dai *dai) 909 { 910 struct vc4_hdmi *hdmi = dai_to_hdmi(dai); 911 struct drm_encoder *encoder = hdmi->encoder; 912 struct drm_device *drm = encoder->dev; 913 struct vc4_dev *vc4 = to_vc4_dev(drm); 914 915 switch (cmd) { 916 case SNDRV_PCM_TRIGGER_START: 917 vc4_hdmi_set_audio_infoframe(encoder); 918 HDMI_WRITE(VC4_HDMI_TX_PHY_CTL0, 919 HDMI_READ(VC4_HDMI_TX_PHY_CTL0) & 920 ~VC4_HDMI_TX_PHY_RNG_PWRDN); 921 HD_WRITE(VC4_HD_MAI_CTL, 922 VC4_SET_FIELD(hdmi->audio.channels, 923 VC4_HD_MAI_CTL_CHNUM) | 924 VC4_HD_MAI_CTL_ENABLE); 925 break; 926 case SNDRV_PCM_TRIGGER_STOP: 927 HD_WRITE(VC4_HD_MAI_CTL, 928 VC4_HD_MAI_CTL_DLATE | 929 VC4_HD_MAI_CTL_ERRORE | 930 VC4_HD_MAI_CTL_ERRORF); 931 HDMI_WRITE(VC4_HDMI_TX_PHY_CTL0, 932 HDMI_READ(VC4_HDMI_TX_PHY_CTL0) | 933 VC4_HDMI_TX_PHY_RNG_PWRDN); 934 break; 935 default: 936 break; 937 } 938 939 return 0; 940 } 941 942 static inline struct vc4_hdmi * 943 snd_component_to_hdmi(struct snd_soc_component *component) 944 { 945 struct snd_soc_card *card = snd_soc_component_get_drvdata(component); 946 947 return snd_soc_card_get_drvdata(card); 948 } 949 950 static int vc4_hdmi_audio_eld_ctl_info(struct snd_kcontrol *kcontrol, 951 struct snd_ctl_elem_info *uinfo) 952 { 953 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 954 struct vc4_hdmi *hdmi = snd_component_to_hdmi(component); 955 956 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 957 uinfo->count = sizeof(hdmi->connector->eld); 958 959 return 0; 960 } 961 962 static int vc4_hdmi_audio_eld_ctl_get(struct snd_kcontrol *kcontrol, 963 struct snd_ctl_elem_value *ucontrol) 964 { 965 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 966 struct vc4_hdmi *hdmi = snd_component_to_hdmi(component); 967 968 memcpy(ucontrol->value.bytes.data, hdmi->connector->eld, 969 sizeof(hdmi->connector->eld)); 970 971 return 0; 972 } 973 974 static const struct snd_kcontrol_new vc4_hdmi_audio_controls[] = { 975 { 976 .access = SNDRV_CTL_ELEM_ACCESS_READ | 977 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 978 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 979 .name = "ELD", 980 .info = vc4_hdmi_audio_eld_ctl_info, 981 .get = vc4_hdmi_audio_eld_ctl_get, 982 }, 983 }; 984 985 static const struct snd_soc_dapm_widget vc4_hdmi_audio_widgets[] = { 986 SND_SOC_DAPM_OUTPUT("TX"), 987 }; 988 989 static const struct snd_soc_dapm_route vc4_hdmi_audio_routes[] = { 990 { "TX", NULL, "Playback" }, 991 }; 992 993 static const struct snd_soc_codec_driver vc4_hdmi_audio_codec_drv = { 994 .component_driver = { 995 .controls = vc4_hdmi_audio_controls, 996 .num_controls = ARRAY_SIZE(vc4_hdmi_audio_controls), 997 .dapm_widgets = vc4_hdmi_audio_widgets, 998 .num_dapm_widgets = ARRAY_SIZE(vc4_hdmi_audio_widgets), 999 .dapm_routes = vc4_hdmi_audio_routes, 1000 .num_dapm_routes = ARRAY_SIZE(vc4_hdmi_audio_routes), 1001 }, 1002 }; 1003 1004 static const struct snd_soc_dai_ops vc4_hdmi_audio_dai_ops = { 1005 .startup = vc4_hdmi_audio_startup, 1006 .shutdown = vc4_hdmi_audio_shutdown, 1007 .hw_params = vc4_hdmi_audio_hw_params, 1008 .set_fmt = vc4_hdmi_audio_set_fmt, 1009 .trigger = vc4_hdmi_audio_trigger, 1010 }; 1011 1012 static struct snd_soc_dai_driver vc4_hdmi_audio_codec_dai_drv = { 1013 .name = "vc4-hdmi-hifi", 1014 .playback = { 1015 .stream_name = "Playback", 1016 .channels_min = 2, 1017 .channels_max = 8, 1018 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 1019 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 1020 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 1021 SNDRV_PCM_RATE_192000, 1022 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 1023 }, 1024 }; 1025 1026 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = { 1027 .name = "vc4-hdmi-cpu-dai-component", 1028 }; 1029 1030 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai) 1031 { 1032 struct vc4_hdmi *hdmi = dai_to_hdmi(dai); 1033 1034 snd_soc_dai_init_dma_data(dai, &hdmi->audio.dma_data, NULL); 1035 1036 return 0; 1037 } 1038 1039 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = { 1040 .name = "vc4-hdmi-cpu-dai", 1041 .probe = vc4_hdmi_audio_cpu_dai_probe, 1042 .playback = { 1043 .stream_name = "Playback", 1044 .channels_min = 1, 1045 .channels_max = 8, 1046 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 1047 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 1048 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 1049 SNDRV_PCM_RATE_192000, 1050 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 1051 }, 1052 .ops = &vc4_hdmi_audio_dai_ops, 1053 }; 1054 1055 static const struct snd_dmaengine_pcm_config pcm_conf = { 1056 .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx", 1057 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 1058 }; 1059 1060 static int vc4_hdmi_audio_init(struct vc4_hdmi *hdmi) 1061 { 1062 struct snd_soc_dai_link *dai_link = &hdmi->audio.link; 1063 struct snd_soc_card *card = &hdmi->audio.card; 1064 struct device *dev = &hdmi->pdev->dev; 1065 const __be32 *addr; 1066 int ret; 1067 1068 if (!of_find_property(dev->of_node, "dmas", NULL)) { 1069 dev_warn(dev, 1070 "'dmas' DT property is missing, no HDMI audio\n"); 1071 return 0; 1072 } 1073 1074 /* 1075 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve 1076 * the bus address specified in the DT, because the physical address 1077 * (the one returned by platform_get_resource()) is not appropriate 1078 * for DMA transfers. 1079 * This VC/MMU should probably be exposed to avoid this kind of hacks. 1080 */ 1081 addr = of_get_address(dev->of_node, 1, NULL, NULL); 1082 hdmi->audio.dma_data.addr = be32_to_cpup(addr) + VC4_HD_MAI_DATA; 1083 hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1084 hdmi->audio.dma_data.maxburst = 2; 1085 1086 ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0); 1087 if (ret) { 1088 dev_err(dev, "Could not register PCM component: %d\n", ret); 1089 return ret; 1090 } 1091 1092 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp, 1093 &vc4_hdmi_audio_cpu_dai_drv, 1); 1094 if (ret) { 1095 dev_err(dev, "Could not register CPU DAI: %d\n", ret); 1096 return ret; 1097 } 1098 1099 /* register codec and codec dai */ 1100 ret = snd_soc_register_codec(dev, &vc4_hdmi_audio_codec_drv, 1101 &vc4_hdmi_audio_codec_dai_drv, 1); 1102 if (ret) { 1103 dev_err(dev, "Could not register codec: %d\n", ret); 1104 return ret; 1105 } 1106 1107 dai_link->name = "MAI"; 1108 dai_link->stream_name = "MAI PCM"; 1109 dai_link->codec_dai_name = vc4_hdmi_audio_codec_dai_drv.name; 1110 dai_link->cpu_dai_name = dev_name(dev); 1111 dai_link->codec_name = dev_name(dev); 1112 dai_link->platform_name = dev_name(dev); 1113 1114 card->dai_link = dai_link; 1115 card->num_links = 1; 1116 card->name = "vc4-hdmi"; 1117 card->dev = dev; 1118 1119 /* 1120 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and 1121 * stores a pointer to the snd card object in dev->driver_data. This 1122 * means we cannot use it for something else. The hdmi back-pointer is 1123 * now stored in card->drvdata and should be retrieved with 1124 * snd_soc_card_get_drvdata() if needed. 1125 */ 1126 snd_soc_card_set_drvdata(card, hdmi); 1127 ret = devm_snd_soc_register_card(dev, card); 1128 if (ret) { 1129 dev_err(dev, "Could not register sound card: %d\n", ret); 1130 goto unregister_codec; 1131 } 1132 1133 return 0; 1134 1135 unregister_codec: 1136 snd_soc_unregister_codec(dev); 1137 1138 return ret; 1139 } 1140 1141 static void vc4_hdmi_audio_cleanup(struct vc4_hdmi *hdmi) 1142 { 1143 struct device *dev = &hdmi->pdev->dev; 1144 1145 /* 1146 * If drvdata is not set this means the audio card was not 1147 * registered, just skip codec unregistration in this case. 1148 */ 1149 if (dev_get_drvdata(dev)) 1150 snd_soc_unregister_codec(dev); 1151 } 1152 1153 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data) 1154 { 1155 struct platform_device *pdev = to_platform_device(dev); 1156 struct drm_device *drm = dev_get_drvdata(master); 1157 struct vc4_dev *vc4 = drm->dev_private; 1158 struct vc4_hdmi *hdmi; 1159 struct vc4_hdmi_encoder *vc4_hdmi_encoder; 1160 struct device_node *ddc_node; 1161 u32 value; 1162 int ret; 1163 1164 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); 1165 if (!hdmi) 1166 return -ENOMEM; 1167 1168 vc4_hdmi_encoder = devm_kzalloc(dev, sizeof(*vc4_hdmi_encoder), 1169 GFP_KERNEL); 1170 if (!vc4_hdmi_encoder) 1171 return -ENOMEM; 1172 vc4_hdmi_encoder->base.type = VC4_ENCODER_TYPE_HDMI; 1173 hdmi->encoder = &vc4_hdmi_encoder->base.base; 1174 1175 hdmi->pdev = pdev; 1176 hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0); 1177 if (IS_ERR(hdmi->hdmicore_regs)) 1178 return PTR_ERR(hdmi->hdmicore_regs); 1179 1180 hdmi->hd_regs = vc4_ioremap_regs(pdev, 1); 1181 if (IS_ERR(hdmi->hd_regs)) 1182 return PTR_ERR(hdmi->hd_regs); 1183 1184 hdmi->pixel_clock = devm_clk_get(dev, "pixel"); 1185 if (IS_ERR(hdmi->pixel_clock)) { 1186 DRM_ERROR("Failed to get pixel clock\n"); 1187 return PTR_ERR(hdmi->pixel_clock); 1188 } 1189 hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); 1190 if (IS_ERR(hdmi->hsm_clock)) { 1191 DRM_ERROR("Failed to get HDMI state machine clock\n"); 1192 return PTR_ERR(hdmi->hsm_clock); 1193 } 1194 1195 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0); 1196 if (!ddc_node) { 1197 DRM_ERROR("Failed to find ddc node in device tree\n"); 1198 return -ENODEV; 1199 } 1200 1201 hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node); 1202 of_node_put(ddc_node); 1203 if (!hdmi->ddc) { 1204 DRM_DEBUG("Failed to get ddc i2c adapter by node\n"); 1205 return -EPROBE_DEFER; 1206 } 1207 1208 /* Only use the GPIO HPD pin if present in the DT, otherwise 1209 * we'll use the HDMI core's register. 1210 */ 1211 if (of_find_property(dev->of_node, "hpd-gpios", &value)) { 1212 enum of_gpio_flags hpd_gpio_flags; 1213 1214 hdmi->hpd_gpio = of_get_named_gpio_flags(dev->of_node, 1215 "hpd-gpios", 0, 1216 &hpd_gpio_flags); 1217 if (hdmi->hpd_gpio < 0) { 1218 ret = hdmi->hpd_gpio; 1219 goto err_put_i2c; 1220 } 1221 1222 hdmi->hpd_active_low = hpd_gpio_flags & OF_GPIO_ACTIVE_LOW; 1223 } 1224 1225 vc4->hdmi = hdmi; 1226 1227 pm_runtime_enable(dev); 1228 1229 drm_encoder_init(drm, hdmi->encoder, &vc4_hdmi_encoder_funcs, 1230 DRM_MODE_ENCODER_TMDS, NULL); 1231 drm_encoder_helper_add(hdmi->encoder, &vc4_hdmi_encoder_helper_funcs); 1232 1233 hdmi->connector = vc4_hdmi_connector_init(drm, hdmi->encoder); 1234 if (IS_ERR(hdmi->connector)) { 1235 ret = PTR_ERR(hdmi->connector); 1236 goto err_destroy_encoder; 1237 } 1238 1239 ret = vc4_hdmi_audio_init(hdmi); 1240 if (ret) 1241 goto err_destroy_encoder; 1242 1243 return 0; 1244 1245 err_destroy_encoder: 1246 vc4_hdmi_encoder_destroy(hdmi->encoder); 1247 pm_runtime_disable(dev); 1248 err_put_i2c: 1249 put_device(&hdmi->ddc->dev); 1250 1251 return ret; 1252 } 1253 1254 static void vc4_hdmi_unbind(struct device *dev, struct device *master, 1255 void *data) 1256 { 1257 struct drm_device *drm = dev_get_drvdata(master); 1258 struct vc4_dev *vc4 = drm->dev_private; 1259 struct vc4_hdmi *hdmi = vc4->hdmi; 1260 1261 vc4_hdmi_audio_cleanup(hdmi); 1262 1263 vc4_hdmi_connector_destroy(hdmi->connector); 1264 vc4_hdmi_encoder_destroy(hdmi->encoder); 1265 1266 pm_runtime_disable(dev); 1267 1268 put_device(&hdmi->ddc->dev); 1269 1270 vc4->hdmi = NULL; 1271 } 1272 1273 static const struct component_ops vc4_hdmi_ops = { 1274 .bind = vc4_hdmi_bind, 1275 .unbind = vc4_hdmi_unbind, 1276 }; 1277 1278 static int vc4_hdmi_dev_probe(struct platform_device *pdev) 1279 { 1280 return component_add(&pdev->dev, &vc4_hdmi_ops); 1281 } 1282 1283 static int vc4_hdmi_dev_remove(struct platform_device *pdev) 1284 { 1285 component_del(&pdev->dev, &vc4_hdmi_ops); 1286 return 0; 1287 } 1288 1289 static const struct of_device_id vc4_hdmi_dt_match[] = { 1290 { .compatible = "brcm,bcm2835-hdmi" }, 1291 {} 1292 }; 1293 1294 struct platform_driver vc4_hdmi_driver = { 1295 .probe = vc4_hdmi_dev_probe, 1296 .remove = vc4_hdmi_dev_remove, 1297 .driver = { 1298 .name = "vc4_hdmi", 1299 .of_match_table = vc4_hdmi_dt_match, 1300 }, 1301 }; 1302