1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 Broadcom 4 * Copyright (c) 2014 The Linux Foundation. All rights reserved. 5 * Copyright (C) 2013 Red Hat 6 * Author: Rob Clark <robdclark@gmail.com> 7 */ 8 9 /** 10 * DOC: VC4 Falcon HDMI module 11 * 12 * The HDMI core has a state machine and a PHY. On BCM2835, most of 13 * the unit operates off of the HSM clock from CPRMAN. It also 14 * internally uses the PLLH_PIX clock for the PHY. 15 * 16 * HDMI infoframes are kept within a small packet ram, where each 17 * packet can be individually enabled for including in a frame. 18 * 19 * HDMI audio is implemented entirely within the HDMI IP block. A 20 * register in the HDMI encoder takes SPDIF frames from the DMA engine 21 * and transfers them over an internal MAI (multi-channel audio 22 * interconnect) bus to the encoder side for insertion into the video 23 * blank regions. 24 * 25 * The driver's HDMI encoder does not yet support power management. 26 * The HDMI encoder's power domain and the HSM/pixel clocks are kept 27 * continuously running, and only the HDMI logic and packet ram are 28 * powered off/on at disable/enable time. 29 * 30 * The driver does not yet support CEC control, though the HDMI 31 * encoder block has CEC support. 32 */ 33 34 #include <drm/display/drm_hdmi_helper.h> 35 #include <drm/display/drm_scdc_helper.h> 36 #include <drm/drm_atomic_helper.h> 37 #include <drm/drm_drv.h> 38 #include <drm/drm_probe_helper.h> 39 #include <drm/drm_simple_kms_helper.h> 40 #include <linux/clk.h> 41 #include <linux/component.h> 42 #include <linux/gpio/consumer.h> 43 #include <linux/i2c.h> 44 #include <linux/of_address.h> 45 #include <linux/of_platform.h> 46 #include <linux/pm_runtime.h> 47 #include <linux/rational.h> 48 #include <linux/reset.h> 49 #include <sound/dmaengine_pcm.h> 50 #include <sound/hdmi-codec.h> 51 #include <sound/pcm_drm_eld.h> 52 #include <sound/pcm_params.h> 53 #include <sound/soc.h> 54 #include "media/cec.h" 55 #include "vc4_drv.h" 56 #include "vc4_hdmi.h" 57 #include "vc4_hdmi_regs.h" 58 #include "vc4_regs.h" 59 60 #define VC5_HDMI_HORZA_HFP_SHIFT 16 61 #define VC5_HDMI_HORZA_HFP_MASK VC4_MASK(28, 16) 62 #define VC5_HDMI_HORZA_VPOS BIT(15) 63 #define VC5_HDMI_HORZA_HPOS BIT(14) 64 #define VC5_HDMI_HORZA_HAP_SHIFT 0 65 #define VC5_HDMI_HORZA_HAP_MASK VC4_MASK(13, 0) 66 67 #define VC5_HDMI_HORZB_HBP_SHIFT 16 68 #define VC5_HDMI_HORZB_HBP_MASK VC4_MASK(26, 16) 69 #define VC5_HDMI_HORZB_HSP_SHIFT 0 70 #define VC5_HDMI_HORZB_HSP_MASK VC4_MASK(10, 0) 71 72 #define VC5_HDMI_VERTA_VSP_SHIFT 24 73 #define VC5_HDMI_VERTA_VSP_MASK VC4_MASK(28, 24) 74 #define VC5_HDMI_VERTA_VFP_SHIFT 16 75 #define VC5_HDMI_VERTA_VFP_MASK VC4_MASK(22, 16) 76 #define VC5_HDMI_VERTA_VAL_SHIFT 0 77 #define VC5_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0) 78 79 #define VC5_HDMI_VERTB_VSPO_SHIFT 16 80 #define VC5_HDMI_VERTB_VSPO_MASK VC4_MASK(29, 16) 81 82 #define VC4_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT 0 83 #define VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK VC4_MASK(3, 0) 84 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT 0 85 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK VC4_MASK(3, 0) 86 87 #define VC5_HDMI_SCRAMBLER_CTL_ENABLE BIT(0) 88 89 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT 8 90 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK VC4_MASK(10, 8) 91 92 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT 0 93 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK VC4_MASK(3, 0) 94 95 #define VC5_HDMI_GCP_CONFIG_GCP_ENABLE BIT(31) 96 97 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT 8 98 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK VC4_MASK(15, 8) 99 100 # define VC4_HD_M_SW_RST BIT(2) 101 # define VC4_HD_M_ENABLE BIT(0) 102 103 #define HSM_MIN_CLOCK_FREQ 120000000 104 #define CEC_CLOCK_FREQ 40000 105 106 #define HDMI_14_MAX_TMDS_CLK (340 * 1000 * 1000) 107 108 static const char * const output_format_str[] = { 109 [VC4_HDMI_OUTPUT_RGB] = "RGB", 110 [VC4_HDMI_OUTPUT_YUV420] = "YUV 4:2:0", 111 [VC4_HDMI_OUTPUT_YUV422] = "YUV 4:2:2", 112 [VC4_HDMI_OUTPUT_YUV444] = "YUV 4:4:4", 113 }; 114 115 static const char *vc4_hdmi_output_fmt_str(enum vc4_hdmi_output_format fmt) 116 { 117 if (fmt >= ARRAY_SIZE(output_format_str)) 118 return "invalid"; 119 120 return output_format_str[fmt]; 121 } 122 123 static unsigned long long 124 vc4_hdmi_encoder_compute_mode_clock(const struct drm_display_mode *mode, 125 unsigned int bpc, enum vc4_hdmi_output_format fmt); 126 127 static bool vc4_hdmi_supports_scrambling(struct drm_encoder *encoder) 128 { 129 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 130 struct drm_display_info *display = &vc4_hdmi->connector.display_info; 131 132 lockdep_assert_held(&vc4_hdmi->mutex); 133 134 if (!display->is_hdmi) 135 return false; 136 137 if (!display->hdmi.scdc.supported || 138 !display->hdmi.scdc.scrambling.supported) 139 return false; 140 141 return true; 142 } 143 144 static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode, 145 unsigned int bpc, 146 enum vc4_hdmi_output_format fmt) 147 { 148 unsigned long long clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc, fmt); 149 150 return clock > HDMI_14_MAX_TMDS_CLK; 151 } 152 153 static bool vc4_hdmi_is_full_range_rgb(struct vc4_hdmi *vc4_hdmi, 154 const struct drm_display_mode *mode) 155 { 156 struct drm_display_info *display = &vc4_hdmi->connector.display_info; 157 158 return !display->is_hdmi || 159 drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_FULL; 160 } 161 162 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused) 163 { 164 struct drm_info_node *node = (struct drm_info_node *)m->private; 165 struct vc4_hdmi *vc4_hdmi = node->info_ent->data; 166 struct drm_device *drm = vc4_hdmi->connector.dev; 167 struct drm_printer p = drm_seq_file_printer(m); 168 int idx; 169 170 if (!drm_dev_enter(drm, &idx)) 171 return -ENODEV; 172 173 drm_print_regset32(&p, &vc4_hdmi->hdmi_regset); 174 drm_print_regset32(&p, &vc4_hdmi->hd_regset); 175 drm_print_regset32(&p, &vc4_hdmi->cec_regset); 176 drm_print_regset32(&p, &vc4_hdmi->csc_regset); 177 drm_print_regset32(&p, &vc4_hdmi->dvp_regset); 178 drm_print_regset32(&p, &vc4_hdmi->phy_regset); 179 drm_print_regset32(&p, &vc4_hdmi->ram_regset); 180 drm_print_regset32(&p, &vc4_hdmi->rm_regset); 181 182 drm_dev_exit(idx); 183 184 return 0; 185 } 186 187 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi) 188 { 189 struct drm_device *drm = vc4_hdmi->connector.dev; 190 unsigned long flags; 191 int idx; 192 193 /* 194 * We can be called by our bind callback, when the 195 * connector->dev pointer might not be initialised yet. 196 */ 197 if (drm && !drm_dev_enter(drm, &idx)) 198 return; 199 200 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 201 202 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST); 203 udelay(1); 204 HDMI_WRITE(HDMI_M_CTL, 0); 205 206 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE); 207 208 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 209 VC4_HDMI_SW_RESET_HDMI | 210 VC4_HDMI_SW_RESET_FORMAT_DETECT); 211 212 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0); 213 214 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 215 216 if (drm) 217 drm_dev_exit(idx); 218 } 219 220 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi) 221 { 222 struct drm_device *drm = vc4_hdmi->connector.dev; 223 unsigned long flags; 224 int idx; 225 226 /* 227 * We can be called by our bind callback, when the 228 * connector->dev pointer might not be initialised yet. 229 */ 230 if (drm && !drm_dev_enter(drm, &idx)) 231 return; 232 233 reset_control_reset(vc4_hdmi->reset); 234 235 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 236 237 HDMI_WRITE(HDMI_DVP_CTL, 0); 238 239 HDMI_WRITE(HDMI_CLOCK_STOP, 240 HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL); 241 242 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 243 244 if (drm) 245 drm_dev_exit(idx); 246 } 247 248 #ifdef CONFIG_DRM_VC4_HDMI_CEC 249 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) 250 { 251 struct drm_device *drm = vc4_hdmi->connector.dev; 252 unsigned long cec_rate; 253 unsigned long flags; 254 u16 clk_cnt; 255 u32 value; 256 int idx; 257 258 /* 259 * This function is called by our runtime_resume implementation 260 * and thus at bind time, when we haven't registered our 261 * connector yet and thus don't have a pointer to the DRM 262 * device. 263 */ 264 if (drm && !drm_dev_enter(drm, &idx)) 265 return; 266 267 cec_rate = clk_get_rate(vc4_hdmi->cec_clock); 268 269 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 270 271 value = HDMI_READ(HDMI_CEC_CNTRL_1); 272 value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK; 273 274 /* 275 * Set the clock divider: the hsm_clock rate and this divider 276 * setting will give a 40 kHz CEC clock. 277 */ 278 clk_cnt = cec_rate / CEC_CLOCK_FREQ; 279 value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT; 280 HDMI_WRITE(HDMI_CEC_CNTRL_1, value); 281 282 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 283 284 if (drm) 285 drm_dev_exit(idx); 286 } 287 #else 288 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {} 289 #endif 290 291 static int reset_pipe(struct drm_crtc *crtc, 292 struct drm_modeset_acquire_ctx *ctx) 293 { 294 struct drm_atomic_state *state; 295 struct drm_crtc_state *crtc_state; 296 int ret; 297 298 state = drm_atomic_state_alloc(crtc->dev); 299 if (!state) 300 return -ENOMEM; 301 302 state->acquire_ctx = ctx; 303 304 crtc_state = drm_atomic_get_crtc_state(state, crtc); 305 if (IS_ERR(crtc_state)) { 306 ret = PTR_ERR(crtc_state); 307 goto out; 308 } 309 310 crtc_state->connectors_changed = true; 311 312 ret = drm_atomic_commit(state); 313 out: 314 drm_atomic_state_put(state); 315 316 return ret; 317 } 318 319 static int vc4_hdmi_reset_link(struct drm_connector *connector, 320 struct drm_modeset_acquire_ctx *ctx) 321 { 322 struct drm_device *drm = connector->dev; 323 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 324 struct drm_encoder *encoder = &vc4_hdmi->encoder.base; 325 struct drm_connector_state *conn_state; 326 struct drm_crtc_state *crtc_state; 327 struct drm_crtc *crtc; 328 bool scrambling_needed; 329 u8 config; 330 int ret; 331 332 if (!connector) 333 return 0; 334 335 ret = drm_modeset_lock(&drm->mode_config.connection_mutex, ctx); 336 if (ret) 337 return ret; 338 339 conn_state = connector->state; 340 crtc = conn_state->crtc; 341 if (!crtc) 342 return 0; 343 344 ret = drm_modeset_lock(&crtc->mutex, ctx); 345 if (ret) 346 return ret; 347 348 crtc_state = crtc->state; 349 if (!crtc_state->active) 350 return 0; 351 352 if (!vc4_hdmi_supports_scrambling(encoder)) 353 return 0; 354 355 scrambling_needed = vc4_hdmi_mode_needs_scrambling(&vc4_hdmi->saved_adjusted_mode, 356 vc4_hdmi->output_bpc, 357 vc4_hdmi->output_format); 358 if (!scrambling_needed) 359 return 0; 360 361 if (conn_state->commit && 362 !try_wait_for_completion(&conn_state->commit->hw_done)) 363 return 0; 364 365 ret = drm_scdc_readb(connector->ddc, SCDC_TMDS_CONFIG, &config); 366 if (ret < 0) { 367 drm_err(drm, "Failed to read TMDS config: %d\n", ret); 368 return 0; 369 } 370 371 if (!!(config & SCDC_SCRAMBLING_ENABLE) == scrambling_needed) 372 return 0; 373 374 /* 375 * HDMI 2.0 says that one should not send scrambled data 376 * prior to configuring the sink scrambling, and that 377 * TMDS clock/data transmission should be suspended when 378 * changing the TMDS clock rate in the sink. So let's 379 * just do a full modeset here, even though some sinks 380 * would be perfectly happy if were to just reconfigure 381 * the SCDC settings on the fly. 382 */ 383 return reset_pipe(crtc, ctx); 384 } 385 386 static void vc4_hdmi_handle_hotplug(struct vc4_hdmi *vc4_hdmi, 387 struct drm_modeset_acquire_ctx *ctx, 388 enum drm_connector_status status) 389 { 390 struct drm_connector *connector = &vc4_hdmi->connector; 391 struct edid *edid; 392 393 /* 394 * NOTE: This function should really be called with 395 * vc4_hdmi->mutex held, but doing so results in reentrancy 396 * issues since cec_s_phys_addr_from_edid might call 397 * .adap_enable, which leads to that funtion being called with 398 * our mutex held. 399 * 400 * A similar situation occurs with 401 * drm_atomic_helper_connector_hdmi_reset_link() that will call 402 * into our KMS hooks if the scrambling was enabled. 403 * 404 * Concurrency isn't an issue at the moment since we don't share 405 * any state with any of the other frameworks so we can ignore 406 * the lock for now. 407 */ 408 409 if (status == connector_status_disconnected) { 410 cec_phys_addr_invalidate(vc4_hdmi->cec_adap); 411 return; 412 } 413 414 edid = drm_get_edid(connector, vc4_hdmi->ddc); 415 if (!edid) 416 return; 417 418 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid); 419 kfree(edid); 420 421 vc4_hdmi_reset_link(connector, ctx); 422 } 423 424 static int vc4_hdmi_connector_detect_ctx(struct drm_connector *connector, 425 struct drm_modeset_acquire_ctx *ctx, 426 bool force) 427 { 428 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 429 enum drm_connector_status status = connector_status_disconnected; 430 431 /* 432 * NOTE: This function should really take vc4_hdmi->mutex, but 433 * doing so results in reentrancy issues since 434 * vc4_hdmi_handle_hotplug() can call into other functions that 435 * would take the mutex while it's held here. 436 * 437 * Concurrency isn't an issue at the moment since we don't share 438 * any state with any of the other frameworks so we can ignore 439 * the lock for now. 440 */ 441 442 WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev)); 443 444 if (vc4_hdmi->hpd_gpio) { 445 if (gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio)) 446 status = connector_status_connected; 447 } else { 448 if (vc4_hdmi->variant->hp_detect && 449 vc4_hdmi->variant->hp_detect(vc4_hdmi)) 450 status = connector_status_connected; 451 } 452 453 vc4_hdmi_handle_hotplug(vc4_hdmi, ctx, status); 454 pm_runtime_put(&vc4_hdmi->pdev->dev); 455 456 return status; 457 } 458 459 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector) 460 { 461 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 462 struct vc4_dev *vc4 = to_vc4_dev(connector->dev); 463 int ret = 0; 464 struct edid *edid; 465 466 /* 467 * NOTE: This function should really take vc4_hdmi->mutex, but 468 * doing so results in reentrancy issues since 469 * cec_s_phys_addr_from_edid might call .adap_enable, which 470 * leads to that funtion being called with our mutex held. 471 * 472 * Concurrency isn't an issue at the moment since we don't share 473 * any state with any of the other frameworks so we can ignore 474 * the lock for now. 475 */ 476 477 edid = drm_get_edid(connector, vc4_hdmi->ddc); 478 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid); 479 if (!edid) 480 return -ENODEV; 481 482 drm_connector_update_edid_property(connector, edid); 483 ret = drm_add_edid_modes(connector, edid); 484 kfree(edid); 485 486 if (!vc4->hvs->vc5_hdmi_enable_hdmi_20) { 487 struct drm_device *drm = connector->dev; 488 const struct drm_display_mode *mode; 489 490 list_for_each_entry(mode, &connector->probed_modes, head) { 491 if (vc4_hdmi_mode_needs_scrambling(mode, 8, VC4_HDMI_OUTPUT_RGB)) { 492 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz."); 493 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60."); 494 } 495 } 496 } 497 498 return ret; 499 } 500 501 static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector, 502 struct drm_atomic_state *state) 503 { 504 struct drm_connector_state *old_state = 505 drm_atomic_get_old_connector_state(state, connector); 506 struct drm_connector_state *new_state = 507 drm_atomic_get_new_connector_state(state, connector); 508 struct drm_crtc *crtc = new_state->crtc; 509 510 if (!crtc) 511 return 0; 512 513 if (old_state->colorspace != new_state->colorspace || 514 !drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) { 515 struct drm_crtc_state *crtc_state; 516 517 crtc_state = drm_atomic_get_crtc_state(state, crtc); 518 if (IS_ERR(crtc_state)) 519 return PTR_ERR(crtc_state); 520 521 crtc_state->mode_changed = true; 522 } 523 524 return 0; 525 } 526 527 static void vc4_hdmi_connector_reset(struct drm_connector *connector) 528 { 529 struct vc4_hdmi_connector_state *old_state = 530 conn_state_to_vc4_hdmi_conn_state(connector->state); 531 struct vc4_hdmi_connector_state *new_state = 532 kzalloc(sizeof(*new_state), GFP_KERNEL); 533 534 if (connector->state) 535 __drm_atomic_helper_connector_destroy_state(connector->state); 536 537 kfree(old_state); 538 __drm_atomic_helper_connector_reset(connector, &new_state->base); 539 540 if (!new_state) 541 return; 542 543 new_state->base.max_bpc = 8; 544 new_state->base.max_requested_bpc = 8; 545 new_state->output_format = VC4_HDMI_OUTPUT_RGB; 546 drm_atomic_helper_connector_tv_margins_reset(connector); 547 } 548 549 static struct drm_connector_state * 550 vc4_hdmi_connector_duplicate_state(struct drm_connector *connector) 551 { 552 struct drm_connector_state *conn_state = connector->state; 553 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state); 554 struct vc4_hdmi_connector_state *new_state; 555 556 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL); 557 if (!new_state) 558 return NULL; 559 560 new_state->tmds_char_rate = vc4_state->tmds_char_rate; 561 new_state->output_bpc = vc4_state->output_bpc; 562 new_state->output_format = vc4_state->output_format; 563 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base); 564 565 return &new_state->base; 566 } 567 568 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = { 569 .fill_modes = drm_helper_probe_single_connector_modes, 570 .reset = vc4_hdmi_connector_reset, 571 .atomic_duplicate_state = vc4_hdmi_connector_duplicate_state, 572 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 573 }; 574 575 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = { 576 .detect_ctx = vc4_hdmi_connector_detect_ctx, 577 .get_modes = vc4_hdmi_connector_get_modes, 578 .atomic_check = vc4_hdmi_connector_atomic_check, 579 }; 580 581 static int vc4_hdmi_connector_init(struct drm_device *dev, 582 struct vc4_hdmi *vc4_hdmi) 583 { 584 struct drm_connector *connector = &vc4_hdmi->connector; 585 struct drm_encoder *encoder = &vc4_hdmi->encoder.base; 586 int ret; 587 588 ret = drmm_connector_init(dev, connector, 589 &vc4_hdmi_connector_funcs, 590 DRM_MODE_CONNECTOR_HDMIA, 591 vc4_hdmi->ddc); 592 if (ret) 593 return ret; 594 595 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs); 596 597 /* 598 * Some of the properties below require access to state, like bpc. 599 * Allocate some default initial connector state with our reset helper. 600 */ 601 if (connector->funcs->reset) 602 connector->funcs->reset(connector); 603 604 /* Create and attach TV margin props to this connector. */ 605 ret = drm_mode_create_tv_margin_properties(dev); 606 if (ret) 607 return ret; 608 609 ret = drm_mode_create_hdmi_colorspace_property(connector); 610 if (ret) 611 return ret; 612 613 drm_connector_attach_colorspace_property(connector); 614 drm_connector_attach_tv_margin_properties(connector); 615 drm_connector_attach_max_bpc_property(connector, 8, 12); 616 617 connector->polled = (DRM_CONNECTOR_POLL_CONNECT | 618 DRM_CONNECTOR_POLL_DISCONNECT); 619 620 connector->interlace_allowed = 1; 621 connector->doublescan_allowed = 0; 622 connector->stereo_allowed = 1; 623 624 if (vc4_hdmi->variant->supports_hdr) 625 drm_connector_attach_hdr_output_metadata_property(connector); 626 627 drm_connector_attach_encoder(connector, encoder); 628 629 return 0; 630 } 631 632 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder, 633 enum hdmi_infoframe_type type, 634 bool poll) 635 { 636 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 637 struct drm_device *drm = vc4_hdmi->connector.dev; 638 u32 packet_id = type - 0x80; 639 unsigned long flags; 640 int ret = 0; 641 int idx; 642 643 if (!drm_dev_enter(drm, &idx)) 644 return -ENODEV; 645 646 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 647 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 648 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id)); 649 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 650 651 if (poll) { 652 ret = wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) & 653 BIT(packet_id)), 100); 654 } 655 656 drm_dev_exit(idx); 657 return ret; 658 } 659 660 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder, 661 union hdmi_infoframe *frame) 662 { 663 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 664 struct drm_device *drm = vc4_hdmi->connector.dev; 665 u32 packet_id = frame->any.type - 0x80; 666 const struct vc4_hdmi_register *ram_packet_start = 667 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START]; 668 u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id; 669 u32 packet_reg_next = ram_packet_start->offset + 670 VC4_HDMI_PACKET_STRIDE * (packet_id + 1); 671 void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi, 672 ram_packet_start->reg); 673 uint8_t buffer[VC4_HDMI_PACKET_STRIDE] = {}; 674 unsigned long flags; 675 ssize_t len, i; 676 int ret; 677 int idx; 678 679 if (!drm_dev_enter(drm, &idx)) 680 return; 681 682 WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) & 683 VC4_HDMI_RAM_PACKET_ENABLE), 684 "Packet RAM has to be on to store the packet."); 685 686 len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer)); 687 if (len < 0) 688 goto out; 689 690 ret = vc4_hdmi_stop_packet(encoder, frame->any.type, true); 691 if (ret) { 692 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret); 693 goto out; 694 } 695 696 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 697 698 for (i = 0; i < len; i += 7) { 699 writel(buffer[i + 0] << 0 | 700 buffer[i + 1] << 8 | 701 buffer[i + 2] << 16, 702 base + packet_reg); 703 packet_reg += 4; 704 705 writel(buffer[i + 3] << 0 | 706 buffer[i + 4] << 8 | 707 buffer[i + 5] << 16 | 708 buffer[i + 6] << 24, 709 base + packet_reg); 710 packet_reg += 4; 711 } 712 713 /* 714 * clear remainder of packet ram as it's included in the 715 * infoframe and triggers a checksum error on hdmi analyser 716 */ 717 for (; packet_reg < packet_reg_next; packet_reg += 4) 718 writel(0, base + packet_reg); 719 720 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 721 HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id)); 722 723 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 724 725 ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) & 726 BIT(packet_id)), 100); 727 if (ret) 728 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret); 729 730 out: 731 drm_dev_exit(idx); 732 } 733 734 static void vc4_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame, 735 enum vc4_hdmi_output_format fmt) 736 { 737 switch (fmt) { 738 case VC4_HDMI_OUTPUT_RGB: 739 frame->colorspace = HDMI_COLORSPACE_RGB; 740 break; 741 742 case VC4_HDMI_OUTPUT_YUV420: 743 frame->colorspace = HDMI_COLORSPACE_YUV420; 744 break; 745 746 case VC4_HDMI_OUTPUT_YUV422: 747 frame->colorspace = HDMI_COLORSPACE_YUV422; 748 break; 749 750 case VC4_HDMI_OUTPUT_YUV444: 751 frame->colorspace = HDMI_COLORSPACE_YUV444; 752 break; 753 754 default: 755 break; 756 } 757 } 758 759 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder) 760 { 761 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 762 struct drm_connector *connector = &vc4_hdmi->connector; 763 struct drm_connector_state *cstate = connector->state; 764 struct vc4_hdmi_connector_state *vc4_state = 765 conn_state_to_vc4_hdmi_conn_state(cstate); 766 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 767 union hdmi_infoframe frame; 768 int ret; 769 770 lockdep_assert_held(&vc4_hdmi->mutex); 771 772 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, 773 connector, mode); 774 if (ret < 0) { 775 DRM_ERROR("couldn't fill AVI infoframe\n"); 776 return; 777 } 778 779 drm_hdmi_avi_infoframe_quant_range(&frame.avi, 780 connector, mode, 781 vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode) ? 782 HDMI_QUANTIZATION_RANGE_FULL : 783 HDMI_QUANTIZATION_RANGE_LIMITED); 784 drm_hdmi_avi_infoframe_colorimetry(&frame.avi, cstate); 785 vc4_hdmi_avi_infoframe_colorspace(&frame.avi, vc4_state->output_format); 786 drm_hdmi_avi_infoframe_bars(&frame.avi, cstate); 787 788 vc4_hdmi_write_infoframe(encoder, &frame); 789 } 790 791 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder) 792 { 793 union hdmi_infoframe frame; 794 int ret; 795 796 ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore"); 797 if (ret < 0) { 798 DRM_ERROR("couldn't fill SPD infoframe\n"); 799 return; 800 } 801 802 frame.spd.sdi = HDMI_SPD_SDI_PC; 803 804 vc4_hdmi_write_infoframe(encoder, &frame); 805 } 806 807 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder) 808 { 809 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 810 struct hdmi_audio_infoframe *audio = &vc4_hdmi->audio.infoframe; 811 union hdmi_infoframe frame; 812 813 memcpy(&frame.audio, audio, sizeof(*audio)); 814 815 if (vc4_hdmi->packet_ram_enabled) 816 vc4_hdmi_write_infoframe(encoder, &frame); 817 } 818 819 static void vc4_hdmi_set_hdr_infoframe(struct drm_encoder *encoder) 820 { 821 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 822 struct drm_connector *connector = &vc4_hdmi->connector; 823 struct drm_connector_state *conn_state = connector->state; 824 union hdmi_infoframe frame; 825 826 lockdep_assert_held(&vc4_hdmi->mutex); 827 828 if (!vc4_hdmi->variant->supports_hdr) 829 return; 830 831 if (!conn_state->hdr_output_metadata) 832 return; 833 834 if (drm_hdmi_infoframe_set_hdr_metadata(&frame.drm, conn_state)) 835 return; 836 837 vc4_hdmi_write_infoframe(encoder, &frame); 838 } 839 840 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder) 841 { 842 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 843 844 lockdep_assert_held(&vc4_hdmi->mutex); 845 846 vc4_hdmi_set_avi_infoframe(encoder); 847 vc4_hdmi_set_spd_infoframe(encoder); 848 /* 849 * If audio was streaming, then we need to reenabled the audio 850 * infoframe here during encoder_enable. 851 */ 852 if (vc4_hdmi->audio.streaming) 853 vc4_hdmi_set_audio_infoframe(encoder); 854 855 vc4_hdmi_set_hdr_infoframe(encoder); 856 } 857 858 #define SCRAMBLING_POLLING_DELAY_MS 1000 859 860 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder) 861 { 862 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 863 struct drm_device *drm = vc4_hdmi->connector.dev; 864 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 865 unsigned long flags; 866 int idx; 867 868 lockdep_assert_held(&vc4_hdmi->mutex); 869 870 if (!vc4_hdmi_supports_scrambling(encoder)) 871 return; 872 873 if (!vc4_hdmi_mode_needs_scrambling(mode, 874 vc4_hdmi->output_bpc, 875 vc4_hdmi->output_format)) 876 return; 877 878 if (!drm_dev_enter(drm, &idx)) 879 return; 880 881 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true); 882 drm_scdc_set_scrambling(vc4_hdmi->ddc, true); 883 884 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 885 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) | 886 VC5_HDMI_SCRAMBLER_CTL_ENABLE); 887 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 888 889 drm_dev_exit(idx); 890 891 vc4_hdmi->scdc_enabled = true; 892 893 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work, 894 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS)); 895 } 896 897 static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder) 898 { 899 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 900 struct drm_device *drm = vc4_hdmi->connector.dev; 901 unsigned long flags; 902 int idx; 903 904 lockdep_assert_held(&vc4_hdmi->mutex); 905 906 if (!vc4_hdmi->scdc_enabled) 907 return; 908 909 vc4_hdmi->scdc_enabled = false; 910 911 if (delayed_work_pending(&vc4_hdmi->scrambling_work)) 912 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work); 913 914 if (!drm_dev_enter(drm, &idx)) 915 return; 916 917 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 918 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) & 919 ~VC5_HDMI_SCRAMBLER_CTL_ENABLE); 920 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 921 922 drm_scdc_set_scrambling(vc4_hdmi->ddc, false); 923 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, false); 924 925 drm_dev_exit(idx); 926 } 927 928 static void vc4_hdmi_scrambling_wq(struct work_struct *work) 929 { 930 struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work), 931 struct vc4_hdmi, 932 scrambling_work); 933 934 if (drm_scdc_get_scrambling_status(vc4_hdmi->ddc)) 935 return; 936 937 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true); 938 drm_scdc_set_scrambling(vc4_hdmi->ddc, true); 939 940 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work, 941 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS)); 942 } 943 944 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder, 945 struct drm_atomic_state *state) 946 { 947 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 948 struct drm_device *drm = vc4_hdmi->connector.dev; 949 unsigned long flags; 950 int idx; 951 952 mutex_lock(&vc4_hdmi->mutex); 953 954 vc4_hdmi->packet_ram_enabled = false; 955 956 if (!drm_dev_enter(drm, &idx)) 957 goto out; 958 959 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 960 961 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0); 962 963 HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB); 964 965 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 966 967 mdelay(1); 968 969 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 970 HDMI_WRITE(HDMI_VID_CTL, 971 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE); 972 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 973 974 vc4_hdmi_disable_scrambling(encoder); 975 976 drm_dev_exit(idx); 977 978 out: 979 mutex_unlock(&vc4_hdmi->mutex); 980 } 981 982 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder, 983 struct drm_atomic_state *state) 984 { 985 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 986 struct drm_device *drm = vc4_hdmi->connector.dev; 987 unsigned long flags; 988 int ret; 989 int idx; 990 991 mutex_lock(&vc4_hdmi->mutex); 992 993 if (!drm_dev_enter(drm, &idx)) 994 goto out; 995 996 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 997 HDMI_WRITE(HDMI_VID_CTL, 998 HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX); 999 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1000 1001 if (vc4_hdmi->variant->phy_disable) 1002 vc4_hdmi->variant->phy_disable(vc4_hdmi); 1003 1004 clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock); 1005 clk_disable_unprepare(vc4_hdmi->pixel_clock); 1006 1007 ret = pm_runtime_put(&vc4_hdmi->pdev->dev); 1008 if (ret < 0) 1009 DRM_ERROR("Failed to release power domain: %d\n", ret); 1010 1011 drm_dev_exit(idx); 1012 1013 out: 1014 mutex_unlock(&vc4_hdmi->mutex); 1015 } 1016 1017 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, 1018 struct drm_connector_state *state, 1019 const struct drm_display_mode *mode) 1020 { 1021 struct drm_device *drm = vc4_hdmi->connector.dev; 1022 unsigned long flags; 1023 u32 csc_ctl; 1024 int idx; 1025 1026 if (!drm_dev_enter(drm, &idx)) 1027 return; 1028 1029 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1030 1031 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR, 1032 VC4_HD_CSC_CTL_ORDER); 1033 1034 if (!vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode)) { 1035 /* CEA VICs other than #1 requre limited range RGB 1036 * output unless overridden by an AVI infoframe. 1037 * Apply a colorspace conversion to squash 0-255 down 1038 * to 16-235. The matrix here is: 1039 * 1040 * [ 0 0 0.8594 16] 1041 * [ 0 0.8594 0 16] 1042 * [ 0.8594 0 0 16] 1043 * [ 0 0 0 1] 1044 */ 1045 csc_ctl |= VC4_HD_CSC_CTL_ENABLE; 1046 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC; 1047 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM, 1048 VC4_HD_CSC_CTL_MODE); 1049 1050 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000); 1051 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0); 1052 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000); 1053 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000); 1054 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0); 1055 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000); 1056 } 1057 1058 /* The RGB order applies even when CSC is disabled. */ 1059 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl); 1060 1061 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1062 1063 drm_dev_exit(idx); 1064 } 1065 1066 /* 1067 * If we need to output Full Range RGB, then use the unity matrix 1068 * 1069 * [ 1 0 0 0] 1070 * [ 0 1 0 0] 1071 * [ 0 0 1 0] 1072 * 1073 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets 1074 */ 1075 static const u16 vc5_hdmi_csc_full_rgb_unity[3][4] = { 1076 { 0x2000, 0x0000, 0x0000, 0x0000 }, 1077 { 0x0000, 0x2000, 0x0000, 0x0000 }, 1078 { 0x0000, 0x0000, 0x2000, 0x0000 }, 1079 }; 1080 1081 /* 1082 * CEA VICs other than #1 require limited range RGB output unless 1083 * overridden by an AVI infoframe. Apply a colorspace conversion to 1084 * squash 0-255 down to 16-235. The matrix here is: 1085 * 1086 * [ 0.8594 0 0 16] 1087 * [ 0 0.8594 0 16] 1088 * [ 0 0 0.8594 16] 1089 * 1090 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets 1091 */ 1092 static const u16 vc5_hdmi_csc_full_rgb_to_limited_rgb[3][4] = { 1093 { 0x1b80, 0x0000, 0x0000, 0x0400 }, 1094 { 0x0000, 0x1b80, 0x0000, 0x0400 }, 1095 { 0x0000, 0x0000, 0x1b80, 0x0400 }, 1096 }; 1097 1098 /* 1099 * Conversion between Full Range RGB and Full Range YUV422 using the 1100 * BT.709 Colorspace 1101 * 1102 * 1103 * [ 0.181906 0.611804 0.061758 16 ] 1104 * [ -0.100268 -0.337232 0.437500 128 ] 1105 * [ 0.437500 -0.397386 -0.040114 128 ] 1106 * 1107 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets 1108 */ 1109 static const u16 vc5_hdmi_csc_full_rgb_to_limited_yuv422_bt709[3][4] = { 1110 { 0x05d2, 0x1394, 0x01fa, 0x0400 }, 1111 { 0xfccc, 0xf536, 0x0e00, 0x2000 }, 1112 { 0x0e00, 0xf34a, 0xfeb8, 0x2000 }, 1113 }; 1114 1115 /* 1116 * Conversion between Full Range RGB and Full Range YUV444 using the 1117 * BT.709 Colorspace 1118 * 1119 * [ -0.100268 -0.337232 0.437500 128 ] 1120 * [ 0.437500 -0.397386 -0.040114 128 ] 1121 * [ 0.181906 0.611804 0.061758 16 ] 1122 * 1123 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets 1124 */ 1125 static const u16 vc5_hdmi_csc_full_rgb_to_limited_yuv444_bt709[3][4] = { 1126 { 0xfccc, 0xf536, 0x0e00, 0x2000 }, 1127 { 0x0e00, 0xf34a, 0xfeb8, 0x2000 }, 1128 { 0x05d2, 0x1394, 0x01fa, 0x0400 }, 1129 }; 1130 1131 static void vc5_hdmi_set_csc_coeffs(struct vc4_hdmi *vc4_hdmi, 1132 const u16 coeffs[3][4]) 1133 { 1134 lockdep_assert_held(&vc4_hdmi->hw_lock); 1135 1136 HDMI_WRITE(HDMI_CSC_12_11, (coeffs[0][1] << 16) | coeffs[0][0]); 1137 HDMI_WRITE(HDMI_CSC_14_13, (coeffs[0][3] << 16) | coeffs[0][2]); 1138 HDMI_WRITE(HDMI_CSC_22_21, (coeffs[1][1] << 16) | coeffs[1][0]); 1139 HDMI_WRITE(HDMI_CSC_24_23, (coeffs[1][3] << 16) | coeffs[1][2]); 1140 HDMI_WRITE(HDMI_CSC_32_31, (coeffs[2][1] << 16) | coeffs[2][0]); 1141 HDMI_WRITE(HDMI_CSC_34_33, (coeffs[2][3] << 16) | coeffs[2][2]); 1142 } 1143 1144 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, 1145 struct drm_connector_state *state, 1146 const struct drm_display_mode *mode) 1147 { 1148 struct drm_device *drm = vc4_hdmi->connector.dev; 1149 struct vc4_hdmi_connector_state *vc4_state = 1150 conn_state_to_vc4_hdmi_conn_state(state); 1151 unsigned long flags; 1152 u32 if_cfg = 0; 1153 u32 if_xbar = 0x543210; 1154 u32 csc_chan_ctl = 0; 1155 u32 csc_ctl = VC5_MT_CP_CSC_CTL_ENABLE | VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM, 1156 VC5_MT_CP_CSC_CTL_MODE); 1157 int idx; 1158 1159 if (!drm_dev_enter(drm, &idx)) 1160 return; 1161 1162 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1163 1164 switch (vc4_state->output_format) { 1165 case VC4_HDMI_OUTPUT_YUV444: 1166 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_limited_yuv444_bt709); 1167 break; 1168 1169 case VC4_HDMI_OUTPUT_YUV422: 1170 csc_ctl |= VC4_SET_FIELD(VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422_STANDARD, 1171 VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422) | 1172 VC5_MT_CP_CSC_CTL_USE_444_TO_422 | 1173 VC5_MT_CP_CSC_CTL_USE_RNG_SUPPRESSION; 1174 1175 csc_chan_ctl |= VC4_SET_FIELD(VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP_LEGACY_STYLE, 1176 VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP); 1177 1178 if_cfg |= VC4_SET_FIELD(VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422_FORMAT_422_LEGACY, 1179 VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422); 1180 1181 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_limited_yuv422_bt709); 1182 break; 1183 1184 case VC4_HDMI_OUTPUT_RGB: 1185 if_xbar = 0x354021; 1186 1187 if (!vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode)) 1188 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_limited_rgb); 1189 else 1190 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_unity); 1191 break; 1192 1193 default: 1194 break; 1195 } 1196 1197 HDMI_WRITE(HDMI_VEC_INTERFACE_CFG, if_cfg); 1198 HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, if_xbar); 1199 HDMI_WRITE(HDMI_CSC_CHANNEL_CTL, csc_chan_ctl); 1200 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl); 1201 1202 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1203 1204 drm_dev_exit(idx); 1205 } 1206 1207 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi, 1208 struct drm_connector_state *state, 1209 const struct drm_display_mode *mode) 1210 { 1211 struct drm_device *drm = vc4_hdmi->connector.dev; 1212 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 1213 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 1214 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 1215 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 1216 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 1217 VC4_HDMI_VERTA_VSP) | 1218 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 1219 VC4_HDMI_VERTA_VFP) | 1220 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL)); 1221 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 1222 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end + 1223 interlaced, 1224 VC4_HDMI_VERTB_VBP)); 1225 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 1226 VC4_SET_FIELD(mode->crtc_vtotal - 1227 mode->crtc_vsync_end, 1228 VC4_HDMI_VERTB_VBP)); 1229 unsigned long flags; 1230 u32 reg; 1231 int idx; 1232 1233 if (!drm_dev_enter(drm, &idx)) 1234 return; 1235 1236 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1237 1238 HDMI_WRITE(HDMI_HORZA, 1239 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) | 1240 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) | 1241 VC4_SET_FIELD(mode->hdisplay * pixel_rep, 1242 VC4_HDMI_HORZA_HAP)); 1243 1244 HDMI_WRITE(HDMI_HORZB, 1245 VC4_SET_FIELD((mode->htotal - 1246 mode->hsync_end) * pixel_rep, 1247 VC4_HDMI_HORZB_HBP) | 1248 VC4_SET_FIELD((mode->hsync_end - 1249 mode->hsync_start) * pixel_rep, 1250 VC4_HDMI_HORZB_HSP) | 1251 VC4_SET_FIELD((mode->hsync_start - 1252 mode->hdisplay) * pixel_rep, 1253 VC4_HDMI_HORZB_HFP)); 1254 1255 HDMI_WRITE(HDMI_VERTA0, verta); 1256 HDMI_WRITE(HDMI_VERTA1, verta); 1257 1258 HDMI_WRITE(HDMI_VERTB0, vertb_even); 1259 HDMI_WRITE(HDMI_VERTB1, vertb); 1260 1261 reg = HDMI_READ(HDMI_MISC_CONTROL); 1262 reg &= ~VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK; 1263 reg |= VC4_SET_FIELD(pixel_rep - 1, VC4_HDMI_MISC_CONTROL_PIXEL_REP); 1264 HDMI_WRITE(HDMI_MISC_CONTROL, reg); 1265 1266 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1267 1268 drm_dev_exit(idx); 1269 } 1270 1271 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi, 1272 struct drm_connector_state *state, 1273 const struct drm_display_mode *mode) 1274 { 1275 struct drm_device *drm = vc4_hdmi->connector.dev; 1276 const struct vc4_hdmi_connector_state *vc4_state = 1277 conn_state_to_vc4_hdmi_conn_state(state); 1278 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 1279 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 1280 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 1281 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 1282 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 1283 VC5_HDMI_VERTA_VSP) | 1284 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 1285 VC5_HDMI_VERTA_VFP) | 1286 VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL)); 1287 u32 vertb = (VC4_SET_FIELD(mode->htotal >> (2 - pixel_rep), 1288 VC5_HDMI_VERTB_VSPO) | 1289 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end, 1290 VC4_HDMI_VERTB_VBP)); 1291 u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) | 1292 VC4_SET_FIELD(mode->crtc_vtotal - 1293 mode->crtc_vsync_end - interlaced, 1294 VC4_HDMI_VERTB_VBP)); 1295 unsigned long flags; 1296 unsigned char gcp; 1297 bool gcp_en; 1298 u32 reg; 1299 int idx; 1300 1301 if (!drm_dev_enter(drm, &idx)) 1302 return; 1303 1304 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1305 1306 HDMI_WRITE(HDMI_HORZA, 1307 (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) | 1308 (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) | 1309 VC4_SET_FIELD(mode->hdisplay * pixel_rep, 1310 VC5_HDMI_HORZA_HAP) | 1311 VC4_SET_FIELD((mode->hsync_start - 1312 mode->hdisplay) * pixel_rep, 1313 VC5_HDMI_HORZA_HFP)); 1314 1315 HDMI_WRITE(HDMI_HORZB, 1316 VC4_SET_FIELD((mode->htotal - 1317 mode->hsync_end) * pixel_rep, 1318 VC5_HDMI_HORZB_HBP) | 1319 VC4_SET_FIELD((mode->hsync_end - 1320 mode->hsync_start) * pixel_rep, 1321 VC5_HDMI_HORZB_HSP)); 1322 1323 HDMI_WRITE(HDMI_VERTA0, verta); 1324 HDMI_WRITE(HDMI_VERTA1, verta); 1325 1326 HDMI_WRITE(HDMI_VERTB0, vertb_even); 1327 HDMI_WRITE(HDMI_VERTB1, vertb); 1328 1329 switch (vc4_state->output_bpc) { 1330 case 12: 1331 gcp = 6; 1332 gcp_en = true; 1333 break; 1334 case 10: 1335 gcp = 5; 1336 gcp_en = true; 1337 break; 1338 case 8: 1339 default: 1340 gcp = 4; 1341 gcp_en = false; 1342 break; 1343 } 1344 1345 /* 1346 * YCC422 is always 36-bit and not considered deep colour so 1347 * doesn't signal in GCP. 1348 */ 1349 if (vc4_state->output_format == VC4_HDMI_OUTPUT_YUV422) { 1350 gcp = 4; 1351 gcp_en = false; 1352 } 1353 1354 reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1); 1355 reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK | 1356 VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK); 1357 reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) | 1358 VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH); 1359 HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg); 1360 1361 reg = HDMI_READ(HDMI_GCP_WORD_1); 1362 reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK; 1363 reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1); 1364 HDMI_WRITE(HDMI_GCP_WORD_1, reg); 1365 1366 reg = HDMI_READ(HDMI_GCP_CONFIG); 1367 reg &= ~VC5_HDMI_GCP_CONFIG_GCP_ENABLE; 1368 reg |= gcp_en ? VC5_HDMI_GCP_CONFIG_GCP_ENABLE : 0; 1369 HDMI_WRITE(HDMI_GCP_CONFIG, reg); 1370 1371 reg = HDMI_READ(HDMI_MISC_CONTROL); 1372 reg &= ~VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK; 1373 reg |= VC4_SET_FIELD(pixel_rep - 1, VC5_HDMI_MISC_CONTROL_PIXEL_REP); 1374 HDMI_WRITE(HDMI_MISC_CONTROL, reg); 1375 1376 HDMI_WRITE(HDMI_CLOCK_STOP, 0); 1377 1378 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1379 1380 drm_dev_exit(idx); 1381 } 1382 1383 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi) 1384 { 1385 struct drm_device *drm = vc4_hdmi->connector.dev; 1386 unsigned long flags; 1387 u32 drift; 1388 int ret; 1389 int idx; 1390 1391 if (!drm_dev_enter(drm, &idx)) 1392 return; 1393 1394 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1395 1396 drift = HDMI_READ(HDMI_FIFO_CTL); 1397 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK; 1398 1399 HDMI_WRITE(HDMI_FIFO_CTL, 1400 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 1401 HDMI_WRITE(HDMI_FIFO_CTL, 1402 drift | VC4_HDMI_FIFO_CTL_RECENTER); 1403 1404 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1405 1406 usleep_range(1000, 1100); 1407 1408 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1409 1410 HDMI_WRITE(HDMI_FIFO_CTL, 1411 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 1412 HDMI_WRITE(HDMI_FIFO_CTL, 1413 drift | VC4_HDMI_FIFO_CTL_RECENTER); 1414 1415 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1416 1417 ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) & 1418 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1); 1419 WARN_ONCE(ret, "Timeout waiting for " 1420 "VC4_HDMI_FIFO_CTL_RECENTER_DONE"); 1421 1422 drm_dev_exit(idx); 1423 } 1424 1425 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder, 1426 struct drm_atomic_state *state) 1427 { 1428 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1429 struct drm_device *drm = vc4_hdmi->connector.dev; 1430 struct drm_connector *connector = &vc4_hdmi->connector; 1431 struct drm_connector_state *conn_state = 1432 drm_atomic_get_new_connector_state(state, connector); 1433 struct vc4_hdmi_connector_state *vc4_conn_state = 1434 conn_state_to_vc4_hdmi_conn_state(conn_state); 1435 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1436 unsigned long tmds_char_rate = vc4_conn_state->tmds_char_rate; 1437 unsigned long bvb_rate, hsm_rate; 1438 unsigned long flags; 1439 int ret; 1440 int idx; 1441 1442 mutex_lock(&vc4_hdmi->mutex); 1443 1444 if (!drm_dev_enter(drm, &idx)) 1445 goto out; 1446 1447 /* 1448 * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must 1449 * be faster than pixel clock, infinitesimally faster, tested in 1450 * simulation. Otherwise, exact value is unimportant for HDMI 1451 * operation." This conflicts with bcm2835's vc4 documentation, which 1452 * states HSM's clock has to be at least 108% of the pixel clock. 1453 * 1454 * Real life tests reveal that vc4's firmware statement holds up, and 1455 * users are able to use pixel clocks closer to HSM's, namely for 1456 * 1920x1200@60Hz. So it was decided to have leave a 1% margin between 1457 * both clocks. Which, for RPi0-3 implies a maximum pixel clock of 1458 * 162MHz. 1459 * 1460 * Additionally, the AXI clock needs to be at least 25% of 1461 * pixel clock, but HSM ends up being the limiting factor. 1462 */ 1463 hsm_rate = max_t(unsigned long, 120000000, (tmds_char_rate / 100) * 101); 1464 ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate); 1465 if (ret) { 1466 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret); 1467 goto err_dev_exit; 1468 } 1469 1470 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev); 1471 if (ret < 0) { 1472 DRM_ERROR("Failed to retain power domain: %d\n", ret); 1473 goto err_dev_exit; 1474 } 1475 1476 ret = clk_set_rate(vc4_hdmi->pixel_clock, tmds_char_rate); 1477 if (ret) { 1478 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret); 1479 goto err_put_runtime_pm; 1480 } 1481 1482 ret = clk_prepare_enable(vc4_hdmi->pixel_clock); 1483 if (ret) { 1484 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret); 1485 goto err_put_runtime_pm; 1486 } 1487 1488 1489 vc4_hdmi_cec_update_clk_div(vc4_hdmi); 1490 1491 if (tmds_char_rate > 297000000) 1492 bvb_rate = 300000000; 1493 else if (tmds_char_rate > 148500000) 1494 bvb_rate = 150000000; 1495 else 1496 bvb_rate = 75000000; 1497 1498 ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate); 1499 if (ret) { 1500 DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret); 1501 goto err_disable_pixel_clock; 1502 } 1503 1504 ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock); 1505 if (ret) { 1506 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret); 1507 goto err_disable_pixel_clock; 1508 } 1509 1510 if (vc4_hdmi->variant->phy_init) 1511 vc4_hdmi->variant->phy_init(vc4_hdmi, vc4_conn_state); 1512 1513 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1514 1515 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1516 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 1517 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT | 1518 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS); 1519 1520 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1521 1522 if (vc4_hdmi->variant->set_timings) 1523 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode); 1524 1525 drm_dev_exit(idx); 1526 1527 mutex_unlock(&vc4_hdmi->mutex); 1528 1529 return; 1530 1531 err_disable_pixel_clock: 1532 clk_disable_unprepare(vc4_hdmi->pixel_clock); 1533 err_put_runtime_pm: 1534 pm_runtime_put(&vc4_hdmi->pdev->dev); 1535 err_dev_exit: 1536 drm_dev_exit(idx); 1537 out: 1538 mutex_unlock(&vc4_hdmi->mutex); 1539 return; 1540 } 1541 1542 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder, 1543 struct drm_atomic_state *state) 1544 { 1545 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1546 struct drm_device *drm = vc4_hdmi->connector.dev; 1547 struct drm_connector *connector = &vc4_hdmi->connector; 1548 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1549 struct drm_connector_state *conn_state = 1550 drm_atomic_get_new_connector_state(state, connector); 1551 unsigned long flags; 1552 int idx; 1553 1554 mutex_lock(&vc4_hdmi->mutex); 1555 1556 if (!drm_dev_enter(drm, &idx)) 1557 goto out; 1558 1559 if (vc4_hdmi->variant->csc_setup) 1560 vc4_hdmi->variant->csc_setup(vc4_hdmi, conn_state, mode); 1561 1562 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1563 HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N); 1564 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1565 1566 drm_dev_exit(idx); 1567 1568 out: 1569 mutex_unlock(&vc4_hdmi->mutex); 1570 } 1571 1572 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder, 1573 struct drm_atomic_state *state) 1574 { 1575 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1576 struct drm_device *drm = vc4_hdmi->connector.dev; 1577 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1578 struct drm_display_info *display = &vc4_hdmi->connector.display_info; 1579 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 1580 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 1581 unsigned long flags; 1582 int ret; 1583 int idx; 1584 1585 mutex_lock(&vc4_hdmi->mutex); 1586 1587 if (!drm_dev_enter(drm, &idx)) 1588 goto out; 1589 1590 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1591 1592 HDMI_WRITE(HDMI_VID_CTL, 1593 VC4_HD_VID_CTL_ENABLE | 1594 VC4_HD_VID_CTL_CLRRGB | 1595 VC4_HD_VID_CTL_UNDERFLOW_ENABLE | 1596 VC4_HD_VID_CTL_FRAME_COUNTER_RESET | 1597 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) | 1598 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW)); 1599 1600 HDMI_WRITE(HDMI_VID_CTL, 1601 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX); 1602 1603 if (display->is_hdmi) { 1604 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1605 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 1606 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 1607 1608 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1609 1610 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1611 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000); 1612 WARN_ONCE(ret, "Timeout waiting for " 1613 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 1614 } else { 1615 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 1616 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & 1617 ~(VC4_HDMI_RAM_PACKET_ENABLE)); 1618 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1619 HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1620 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 1621 1622 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1623 1624 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1625 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000); 1626 WARN_ONCE(ret, "Timeout waiting for " 1627 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 1628 } 1629 1630 if (display->is_hdmi) { 1631 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1632 1633 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1634 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE)); 1635 1636 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 1637 VC4_HDMI_RAM_PACKET_ENABLE); 1638 1639 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1640 vc4_hdmi->packet_ram_enabled = true; 1641 1642 vc4_hdmi_set_infoframes(encoder); 1643 } 1644 1645 vc4_hdmi_recenter_fifo(vc4_hdmi); 1646 vc4_hdmi_enable_scrambling(encoder); 1647 1648 drm_dev_exit(idx); 1649 1650 out: 1651 mutex_unlock(&vc4_hdmi->mutex); 1652 } 1653 1654 static void vc4_hdmi_encoder_atomic_mode_set(struct drm_encoder *encoder, 1655 struct drm_crtc_state *crtc_state, 1656 struct drm_connector_state *conn_state) 1657 { 1658 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1659 struct vc4_hdmi_connector_state *vc4_state = 1660 conn_state_to_vc4_hdmi_conn_state(conn_state); 1661 1662 mutex_lock(&vc4_hdmi->mutex); 1663 drm_mode_copy(&vc4_hdmi->saved_adjusted_mode, 1664 &crtc_state->adjusted_mode); 1665 vc4_hdmi->output_bpc = vc4_state->output_bpc; 1666 vc4_hdmi->output_format = vc4_state->output_format; 1667 mutex_unlock(&vc4_hdmi->mutex); 1668 } 1669 1670 static bool 1671 vc4_hdmi_sink_supports_format_bpc(const struct vc4_hdmi *vc4_hdmi, 1672 const struct drm_display_info *info, 1673 const struct drm_display_mode *mode, 1674 unsigned int format, unsigned int bpc) 1675 { 1676 struct drm_device *dev = vc4_hdmi->connector.dev; 1677 u8 vic = drm_match_cea_mode(mode); 1678 1679 if (vic == 1 && bpc != 8) { 1680 drm_dbg(dev, "VIC1 requires a bpc of 8, got %u\n", bpc); 1681 return false; 1682 } 1683 1684 if (!info->is_hdmi && 1685 (format != VC4_HDMI_OUTPUT_RGB || bpc != 8)) { 1686 drm_dbg(dev, "DVI Monitors require an RGB output at 8 bpc\n"); 1687 return false; 1688 } 1689 1690 switch (format) { 1691 case VC4_HDMI_OUTPUT_RGB: 1692 drm_dbg(dev, "RGB Format, checking the constraints.\n"); 1693 1694 if (!(info->color_formats & DRM_COLOR_FORMAT_RGB444)) 1695 return false; 1696 1697 if (bpc == 10 && !(info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30)) { 1698 drm_dbg(dev, "10 BPC but sink doesn't support Deep Color 30.\n"); 1699 return false; 1700 } 1701 1702 if (bpc == 12 && !(info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36)) { 1703 drm_dbg(dev, "12 BPC but sink doesn't support Deep Color 36.\n"); 1704 return false; 1705 } 1706 1707 drm_dbg(dev, "RGB format supported in that configuration.\n"); 1708 1709 return true; 1710 1711 case VC4_HDMI_OUTPUT_YUV422: 1712 drm_dbg(dev, "YUV422 format, checking the constraints.\n"); 1713 1714 if (!(info->color_formats & DRM_COLOR_FORMAT_YCBCR422)) { 1715 drm_dbg(dev, "Sink doesn't support YUV422.\n"); 1716 return false; 1717 } 1718 1719 if (bpc != 12) { 1720 drm_dbg(dev, "YUV422 only supports 12 bpc.\n"); 1721 return false; 1722 } 1723 1724 drm_dbg(dev, "YUV422 format supported in that configuration.\n"); 1725 1726 return true; 1727 1728 case VC4_HDMI_OUTPUT_YUV444: 1729 drm_dbg(dev, "YUV444 format, checking the constraints.\n"); 1730 1731 if (!(info->color_formats & DRM_COLOR_FORMAT_YCBCR444)) { 1732 drm_dbg(dev, "Sink doesn't support YUV444.\n"); 1733 return false; 1734 } 1735 1736 if (bpc == 10 && !(info->edid_hdmi_ycbcr444_dc_modes & DRM_EDID_HDMI_DC_30)) { 1737 drm_dbg(dev, "10 BPC but sink doesn't support Deep Color 30.\n"); 1738 return false; 1739 } 1740 1741 if (bpc == 12 && !(info->edid_hdmi_ycbcr444_dc_modes & DRM_EDID_HDMI_DC_36)) { 1742 drm_dbg(dev, "12 BPC but sink doesn't support Deep Color 36.\n"); 1743 return false; 1744 } 1745 1746 drm_dbg(dev, "YUV444 format supported in that configuration.\n"); 1747 1748 return true; 1749 } 1750 1751 return false; 1752 } 1753 1754 static enum drm_mode_status 1755 vc4_hdmi_encoder_clock_valid(const struct vc4_hdmi *vc4_hdmi, 1756 const struct drm_display_mode *mode, 1757 unsigned long long clock) 1758 { 1759 const struct drm_connector *connector = &vc4_hdmi->connector; 1760 const struct drm_display_info *info = &connector->display_info; 1761 struct vc4_dev *vc4 = to_vc4_dev(connector->dev); 1762 1763 if (clock > vc4_hdmi->variant->max_pixel_clock) 1764 return MODE_CLOCK_HIGH; 1765 1766 if (!vc4->hvs->vc5_hdmi_enable_hdmi_20 && clock > HDMI_14_MAX_TMDS_CLK) 1767 return MODE_CLOCK_HIGH; 1768 1769 /* 4096x2160@60 is not reliable without overclocking core */ 1770 if (!vc4->hvs->vc5_hdmi_enable_4096by2160 && 1771 mode->hdisplay > 3840 && mode->vdisplay >= 2160 && 1772 drm_mode_vrefresh(mode) >= 50) 1773 return MODE_CLOCK_HIGH; 1774 1775 if (info->max_tmds_clock && clock > (info->max_tmds_clock * 1000)) 1776 return MODE_CLOCK_HIGH; 1777 1778 return MODE_OK; 1779 } 1780 1781 static unsigned long long 1782 vc4_hdmi_encoder_compute_mode_clock(const struct drm_display_mode *mode, 1783 unsigned int bpc, 1784 enum vc4_hdmi_output_format fmt) 1785 { 1786 unsigned long long clock = mode->clock * 1000ULL; 1787 1788 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 1789 clock = clock * 2; 1790 1791 if (fmt == VC4_HDMI_OUTPUT_YUV422) 1792 bpc = 8; 1793 1794 clock = clock * bpc; 1795 do_div(clock, 8); 1796 1797 return clock; 1798 } 1799 1800 static int 1801 vc4_hdmi_encoder_compute_clock(const struct vc4_hdmi *vc4_hdmi, 1802 struct vc4_hdmi_connector_state *vc4_state, 1803 const struct drm_display_mode *mode, 1804 unsigned int bpc, unsigned int fmt) 1805 { 1806 unsigned long long clock; 1807 1808 clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc, fmt); 1809 if (vc4_hdmi_encoder_clock_valid(vc4_hdmi, mode, clock) != MODE_OK) 1810 return -EINVAL; 1811 1812 vc4_state->tmds_char_rate = clock; 1813 1814 return 0; 1815 } 1816 1817 static int 1818 vc4_hdmi_encoder_compute_format(const struct vc4_hdmi *vc4_hdmi, 1819 struct vc4_hdmi_connector_state *vc4_state, 1820 const struct drm_display_mode *mode, 1821 unsigned int bpc) 1822 { 1823 struct drm_device *dev = vc4_hdmi->connector.dev; 1824 const struct drm_connector *connector = &vc4_hdmi->connector; 1825 const struct drm_display_info *info = &connector->display_info; 1826 unsigned int format; 1827 1828 drm_dbg(dev, "Trying with an RGB output\n"); 1829 1830 format = VC4_HDMI_OUTPUT_RGB; 1831 if (vc4_hdmi_sink_supports_format_bpc(vc4_hdmi, info, mode, format, bpc)) { 1832 int ret; 1833 1834 ret = vc4_hdmi_encoder_compute_clock(vc4_hdmi, vc4_state, 1835 mode, bpc, format); 1836 if (!ret) { 1837 vc4_state->output_format = format; 1838 return 0; 1839 } 1840 } 1841 1842 drm_dbg(dev, "Failed, Trying with an YUV422 output\n"); 1843 1844 format = VC4_HDMI_OUTPUT_YUV422; 1845 if (vc4_hdmi_sink_supports_format_bpc(vc4_hdmi, info, mode, format, bpc)) { 1846 int ret; 1847 1848 ret = vc4_hdmi_encoder_compute_clock(vc4_hdmi, vc4_state, 1849 mode, bpc, format); 1850 if (!ret) { 1851 vc4_state->output_format = format; 1852 return 0; 1853 } 1854 } 1855 1856 drm_dbg(dev, "Failed. No Format Supported for that bpc count.\n"); 1857 1858 return -EINVAL; 1859 } 1860 1861 static int 1862 vc4_hdmi_encoder_compute_config(const struct vc4_hdmi *vc4_hdmi, 1863 struct vc4_hdmi_connector_state *vc4_state, 1864 const struct drm_display_mode *mode) 1865 { 1866 struct drm_device *dev = vc4_hdmi->connector.dev; 1867 struct drm_connector_state *conn_state = &vc4_state->base; 1868 unsigned int max_bpc = clamp_t(unsigned int, conn_state->max_bpc, 8, 12); 1869 unsigned int bpc; 1870 int ret; 1871 1872 for (bpc = max_bpc; bpc >= 8; bpc -= 2) { 1873 drm_dbg(dev, "Trying with a %d bpc output\n", bpc); 1874 1875 ret = vc4_hdmi_encoder_compute_format(vc4_hdmi, vc4_state, 1876 mode, bpc); 1877 if (ret) 1878 continue; 1879 1880 vc4_state->output_bpc = bpc; 1881 1882 drm_dbg(dev, 1883 "Mode %ux%u @ %uHz: Found configuration: bpc: %u, fmt: %s, clock: %llu\n", 1884 mode->hdisplay, mode->vdisplay, drm_mode_vrefresh(mode), 1885 vc4_state->output_bpc, 1886 vc4_hdmi_output_fmt_str(vc4_state->output_format), 1887 vc4_state->tmds_char_rate); 1888 1889 break; 1890 } 1891 1892 return ret; 1893 } 1894 1895 #define WIFI_2_4GHz_CH1_MIN_FREQ 2400000000ULL 1896 #define WIFI_2_4GHz_CH1_MAX_FREQ 2422000000ULL 1897 1898 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder, 1899 struct drm_crtc_state *crtc_state, 1900 struct drm_connector_state *conn_state) 1901 { 1902 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1903 struct drm_connector *connector = &vc4_hdmi->connector; 1904 struct drm_connector_state *old_conn_state = 1905 drm_atomic_get_old_connector_state(conn_state->state, connector); 1906 struct vc4_hdmi_connector_state *old_vc4_state = 1907 conn_state_to_vc4_hdmi_conn_state(old_conn_state); 1908 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state); 1909 struct drm_display_mode *mode = &crtc_state->adjusted_mode; 1910 unsigned long long tmds_char_rate = mode->clock * 1000; 1911 unsigned long long tmds_bit_rate; 1912 int ret; 1913 1914 if (vc4_hdmi->variant->unsupported_odd_h_timings) { 1915 if (mode->flags & DRM_MODE_FLAG_DBLCLK) { 1916 /* Only try to fixup DBLCLK modes to get 480i and 576i 1917 * working. 1918 * A generic solution for all modes with odd horizontal 1919 * timing values seems impossible based on trying to 1920 * solve it for 1366x768 monitors. 1921 */ 1922 if ((mode->hsync_start - mode->hdisplay) & 1) 1923 mode->hsync_start--; 1924 if ((mode->hsync_end - mode->hsync_start) & 1) 1925 mode->hsync_end--; 1926 } 1927 1928 /* Now check whether we still have odd values remaining */ 1929 if ((mode->hdisplay % 2) || (mode->hsync_start % 2) || 1930 (mode->hsync_end % 2) || (mode->htotal % 2)) 1931 return -EINVAL; 1932 } 1933 1934 /* 1935 * The 1440p@60 pixel rate is in the same range than the first 1936 * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz 1937 * bandwidth). Slightly lower the frequency to bring it out of 1938 * the WiFi range. 1939 */ 1940 tmds_bit_rate = tmds_char_rate * 10; 1941 if (vc4_hdmi->disable_wifi_frequencies && 1942 (tmds_bit_rate >= WIFI_2_4GHz_CH1_MIN_FREQ && 1943 tmds_bit_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) { 1944 mode->clock = 238560; 1945 tmds_char_rate = mode->clock * 1000; 1946 } 1947 1948 ret = vc4_hdmi_encoder_compute_config(vc4_hdmi, vc4_state, mode); 1949 if (ret) 1950 return ret; 1951 1952 /* vc4_hdmi_encoder_compute_config may have changed output_bpc and/or output_format */ 1953 if (vc4_state->output_bpc != old_vc4_state->output_bpc || 1954 vc4_state->output_format != old_vc4_state->output_format) 1955 crtc_state->mode_changed = true; 1956 1957 return 0; 1958 } 1959 1960 static enum drm_mode_status 1961 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder, 1962 const struct drm_display_mode *mode) 1963 { 1964 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1965 1966 if (vc4_hdmi->variant->unsupported_odd_h_timings && 1967 !(mode->flags & DRM_MODE_FLAG_DBLCLK) && 1968 ((mode->hdisplay % 2) || (mode->hsync_start % 2) || 1969 (mode->hsync_end % 2) || (mode->htotal % 2))) 1970 return MODE_H_ILLEGAL; 1971 1972 return vc4_hdmi_encoder_clock_valid(vc4_hdmi, mode, mode->clock * 1000); 1973 } 1974 1975 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = { 1976 .atomic_check = vc4_hdmi_encoder_atomic_check, 1977 .atomic_mode_set = vc4_hdmi_encoder_atomic_mode_set, 1978 .mode_valid = vc4_hdmi_encoder_mode_valid, 1979 }; 1980 1981 static int vc4_hdmi_late_register(struct drm_encoder *encoder) 1982 { 1983 struct drm_device *drm = encoder->dev; 1984 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1985 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant; 1986 int ret; 1987 1988 ret = vc4_debugfs_add_file(drm->primary, variant->debugfs_name, 1989 vc4_hdmi_debugfs_regs, 1990 vc4_hdmi); 1991 if (ret) 1992 return ret; 1993 1994 return 0; 1995 } 1996 1997 static const struct drm_encoder_funcs vc4_hdmi_encoder_funcs = { 1998 .late_register = vc4_hdmi_late_register, 1999 }; 2000 2001 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask) 2002 { 2003 int i; 2004 u32 channel_map = 0; 2005 2006 for (i = 0; i < 8; i++) { 2007 if (channel_mask & BIT(i)) 2008 channel_map |= i << (3 * i); 2009 } 2010 return channel_map; 2011 } 2012 2013 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask) 2014 { 2015 int i; 2016 u32 channel_map = 0; 2017 2018 for (i = 0; i < 8; i++) { 2019 if (channel_mask & BIT(i)) 2020 channel_map |= i << (4 * i); 2021 } 2022 return channel_map; 2023 } 2024 2025 static bool vc5_hdmi_hp_detect(struct vc4_hdmi *vc4_hdmi) 2026 { 2027 struct drm_device *drm = vc4_hdmi->connector.dev; 2028 unsigned long flags; 2029 u32 hotplug; 2030 int idx; 2031 2032 if (!drm_dev_enter(drm, &idx)) 2033 return false; 2034 2035 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2036 hotplug = HDMI_READ(HDMI_HOTPLUG); 2037 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2038 2039 drm_dev_exit(idx); 2040 2041 return !!(hotplug & VC4_HDMI_HOTPLUG_CONNECTED); 2042 } 2043 2044 /* HDMI audio codec callbacks */ 2045 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi, 2046 unsigned int samplerate) 2047 { 2048 struct drm_device *drm = vc4_hdmi->connector.dev; 2049 u32 hsm_clock; 2050 unsigned long flags; 2051 unsigned long n, m; 2052 int idx; 2053 2054 if (!drm_dev_enter(drm, &idx)) 2055 return; 2056 2057 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock); 2058 rational_best_approximation(hsm_clock, samplerate, 2059 VC4_HD_MAI_SMP_N_MASK >> 2060 VC4_HD_MAI_SMP_N_SHIFT, 2061 (VC4_HD_MAI_SMP_M_MASK >> 2062 VC4_HD_MAI_SMP_M_SHIFT) + 1, 2063 &n, &m); 2064 2065 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2066 HDMI_WRITE(HDMI_MAI_SMP, 2067 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) | 2068 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M)); 2069 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2070 2071 drm_dev_exit(idx); 2072 } 2073 2074 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi, unsigned int samplerate) 2075 { 2076 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 2077 u32 n, cts; 2078 u64 tmp; 2079 2080 lockdep_assert_held(&vc4_hdmi->mutex); 2081 lockdep_assert_held(&vc4_hdmi->hw_lock); 2082 2083 n = 128 * samplerate / 1000; 2084 tmp = (u64)(mode->clock * 1000) * n; 2085 do_div(tmp, 128 * samplerate); 2086 cts = tmp; 2087 2088 HDMI_WRITE(HDMI_CRP_CFG, 2089 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN | 2090 VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N)); 2091 2092 /* 2093 * We could get slightly more accurate clocks in some cases by 2094 * providing a CTS_1 value. The two CTS values are alternated 2095 * between based on the period fields 2096 */ 2097 HDMI_WRITE(HDMI_CTS_0, cts); 2098 HDMI_WRITE(HDMI_CTS_1, cts); 2099 } 2100 2101 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai) 2102 { 2103 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai); 2104 2105 return snd_soc_card_get_drvdata(card); 2106 } 2107 2108 static bool vc4_hdmi_audio_can_stream(struct vc4_hdmi *vc4_hdmi) 2109 { 2110 struct drm_display_info *display = &vc4_hdmi->connector.display_info; 2111 2112 lockdep_assert_held(&vc4_hdmi->mutex); 2113 2114 /* 2115 * If the encoder is currently in DVI mode, treat the codec DAI 2116 * as missing. 2117 */ 2118 if (!display->is_hdmi) 2119 return false; 2120 2121 return true; 2122 } 2123 2124 static int vc4_hdmi_audio_startup(struct device *dev, void *data) 2125 { 2126 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 2127 struct drm_device *drm = vc4_hdmi->connector.dev; 2128 unsigned long flags; 2129 int ret = 0; 2130 int idx; 2131 2132 mutex_lock(&vc4_hdmi->mutex); 2133 2134 if (!drm_dev_enter(drm, &idx)) { 2135 ret = -ENODEV; 2136 goto out; 2137 } 2138 2139 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) { 2140 ret = -ENODEV; 2141 goto out_dev_exit; 2142 } 2143 2144 vc4_hdmi->audio.streaming = true; 2145 2146 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2147 HDMI_WRITE(HDMI_MAI_CTL, 2148 VC4_HD_MAI_CTL_RESET | 2149 VC4_HD_MAI_CTL_FLUSH | 2150 VC4_HD_MAI_CTL_DLATE | 2151 VC4_HD_MAI_CTL_ERRORE | 2152 VC4_HD_MAI_CTL_ERRORF); 2153 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2154 2155 if (vc4_hdmi->variant->phy_rng_enable) 2156 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi); 2157 2158 out_dev_exit: 2159 drm_dev_exit(idx); 2160 out: 2161 mutex_unlock(&vc4_hdmi->mutex); 2162 2163 return ret; 2164 } 2165 2166 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi) 2167 { 2168 struct drm_encoder *encoder = &vc4_hdmi->encoder.base; 2169 struct device *dev = &vc4_hdmi->pdev->dev; 2170 unsigned long flags; 2171 int ret; 2172 2173 lockdep_assert_held(&vc4_hdmi->mutex); 2174 2175 vc4_hdmi->audio.streaming = false; 2176 ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO, false); 2177 if (ret) 2178 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret); 2179 2180 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2181 2182 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET); 2183 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF); 2184 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH); 2185 2186 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2187 } 2188 2189 static void vc4_hdmi_audio_shutdown(struct device *dev, void *data) 2190 { 2191 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 2192 struct drm_device *drm = vc4_hdmi->connector.dev; 2193 unsigned long flags; 2194 int idx; 2195 2196 mutex_lock(&vc4_hdmi->mutex); 2197 2198 if (!drm_dev_enter(drm, &idx)) 2199 goto out; 2200 2201 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2202 2203 HDMI_WRITE(HDMI_MAI_CTL, 2204 VC4_HD_MAI_CTL_DLATE | 2205 VC4_HD_MAI_CTL_ERRORE | 2206 VC4_HD_MAI_CTL_ERRORF); 2207 2208 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2209 2210 if (vc4_hdmi->variant->phy_rng_disable) 2211 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi); 2212 2213 vc4_hdmi->audio.streaming = false; 2214 vc4_hdmi_audio_reset(vc4_hdmi); 2215 2216 drm_dev_exit(idx); 2217 2218 out: 2219 mutex_unlock(&vc4_hdmi->mutex); 2220 } 2221 2222 static int sample_rate_to_mai_fmt(int samplerate) 2223 { 2224 switch (samplerate) { 2225 case 8000: 2226 return VC4_HDMI_MAI_SAMPLE_RATE_8000; 2227 case 11025: 2228 return VC4_HDMI_MAI_SAMPLE_RATE_11025; 2229 case 12000: 2230 return VC4_HDMI_MAI_SAMPLE_RATE_12000; 2231 case 16000: 2232 return VC4_HDMI_MAI_SAMPLE_RATE_16000; 2233 case 22050: 2234 return VC4_HDMI_MAI_SAMPLE_RATE_22050; 2235 case 24000: 2236 return VC4_HDMI_MAI_SAMPLE_RATE_24000; 2237 case 32000: 2238 return VC4_HDMI_MAI_SAMPLE_RATE_32000; 2239 case 44100: 2240 return VC4_HDMI_MAI_SAMPLE_RATE_44100; 2241 case 48000: 2242 return VC4_HDMI_MAI_SAMPLE_RATE_48000; 2243 case 64000: 2244 return VC4_HDMI_MAI_SAMPLE_RATE_64000; 2245 case 88200: 2246 return VC4_HDMI_MAI_SAMPLE_RATE_88200; 2247 case 96000: 2248 return VC4_HDMI_MAI_SAMPLE_RATE_96000; 2249 case 128000: 2250 return VC4_HDMI_MAI_SAMPLE_RATE_128000; 2251 case 176400: 2252 return VC4_HDMI_MAI_SAMPLE_RATE_176400; 2253 case 192000: 2254 return VC4_HDMI_MAI_SAMPLE_RATE_192000; 2255 default: 2256 return VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED; 2257 } 2258 } 2259 2260 /* HDMI audio codec callbacks */ 2261 static int vc4_hdmi_audio_prepare(struct device *dev, void *data, 2262 struct hdmi_codec_daifmt *daifmt, 2263 struct hdmi_codec_params *params) 2264 { 2265 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 2266 struct drm_device *drm = vc4_hdmi->connector.dev; 2267 struct drm_encoder *encoder = &vc4_hdmi->encoder.base; 2268 unsigned int sample_rate = params->sample_rate; 2269 unsigned int channels = params->channels; 2270 unsigned long flags; 2271 u32 audio_packet_config, channel_mask; 2272 u32 channel_map; 2273 u32 mai_audio_format; 2274 u32 mai_sample_rate; 2275 int ret = 0; 2276 int idx; 2277 2278 dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__, 2279 sample_rate, params->sample_width, channels); 2280 2281 mutex_lock(&vc4_hdmi->mutex); 2282 2283 if (!drm_dev_enter(drm, &idx)) { 2284 ret = -ENODEV; 2285 goto out; 2286 } 2287 2288 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) { 2289 ret = -EINVAL; 2290 goto out_dev_exit; 2291 } 2292 2293 vc4_hdmi_audio_set_mai_clock(vc4_hdmi, sample_rate); 2294 2295 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2296 HDMI_WRITE(HDMI_MAI_CTL, 2297 VC4_SET_FIELD(channels, VC4_HD_MAI_CTL_CHNUM) | 2298 VC4_HD_MAI_CTL_WHOLSMP | 2299 VC4_HD_MAI_CTL_CHALIGN | 2300 VC4_HD_MAI_CTL_ENABLE); 2301 2302 mai_sample_rate = sample_rate_to_mai_fmt(sample_rate); 2303 if (params->iec.status[0] & IEC958_AES0_NONAUDIO && 2304 params->channels == 8) 2305 mai_audio_format = VC4_HDMI_MAI_FORMAT_HBR; 2306 else 2307 mai_audio_format = VC4_HDMI_MAI_FORMAT_PCM; 2308 HDMI_WRITE(HDMI_MAI_FMT, 2309 VC4_SET_FIELD(mai_sample_rate, 2310 VC4_HDMI_MAI_FORMAT_SAMPLE_RATE) | 2311 VC4_SET_FIELD(mai_audio_format, 2312 VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT)); 2313 2314 /* The B frame identifier should match the value used by alsa-lib (8) */ 2315 audio_packet_config = 2316 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT | 2317 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS | 2318 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER); 2319 2320 channel_mask = GENMASK(channels - 1, 0); 2321 audio_packet_config |= VC4_SET_FIELD(channel_mask, 2322 VC4_HDMI_AUDIO_PACKET_CEA_MASK); 2323 2324 /* Set the MAI threshold */ 2325 HDMI_WRITE(HDMI_MAI_THR, 2326 VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICHIGH) | 2327 VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICLOW) | 2328 VC4_SET_FIELD(0x06, VC4_HD_MAI_THR_DREQHIGH) | 2329 VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_DREQLOW)); 2330 2331 HDMI_WRITE(HDMI_MAI_CONFIG, 2332 VC4_HDMI_MAI_CONFIG_BIT_REVERSE | 2333 VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE | 2334 VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK)); 2335 2336 channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask); 2337 HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map); 2338 HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config); 2339 2340 vc4_hdmi_set_n_cts(vc4_hdmi, sample_rate); 2341 2342 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2343 2344 memcpy(&vc4_hdmi->audio.infoframe, ¶ms->cea, sizeof(params->cea)); 2345 vc4_hdmi_set_audio_infoframe(encoder); 2346 2347 out_dev_exit: 2348 drm_dev_exit(idx); 2349 out: 2350 mutex_unlock(&vc4_hdmi->mutex); 2351 2352 return ret; 2353 } 2354 2355 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = { 2356 .name = "vc4-hdmi-cpu-dai-component", 2357 .legacy_dai_naming = 1, 2358 }; 2359 2360 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai) 2361 { 2362 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai); 2363 2364 snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL); 2365 2366 return 0; 2367 } 2368 2369 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = { 2370 .name = "vc4-hdmi-cpu-dai", 2371 .probe = vc4_hdmi_audio_cpu_dai_probe, 2372 .playback = { 2373 .stream_name = "Playback", 2374 .channels_min = 1, 2375 .channels_max = 8, 2376 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 2377 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 2378 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 2379 SNDRV_PCM_RATE_192000, 2380 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 2381 }, 2382 }; 2383 2384 static const struct snd_dmaengine_pcm_config pcm_conf = { 2385 .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx", 2386 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 2387 }; 2388 2389 static int vc4_hdmi_audio_get_eld(struct device *dev, void *data, 2390 uint8_t *buf, size_t len) 2391 { 2392 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 2393 struct drm_connector *connector = &vc4_hdmi->connector; 2394 2395 mutex_lock(&vc4_hdmi->mutex); 2396 memcpy(buf, connector->eld, min(sizeof(connector->eld), len)); 2397 mutex_unlock(&vc4_hdmi->mutex); 2398 2399 return 0; 2400 } 2401 2402 static const struct hdmi_codec_ops vc4_hdmi_codec_ops = { 2403 .get_eld = vc4_hdmi_audio_get_eld, 2404 .prepare = vc4_hdmi_audio_prepare, 2405 .audio_shutdown = vc4_hdmi_audio_shutdown, 2406 .audio_startup = vc4_hdmi_audio_startup, 2407 }; 2408 2409 static struct hdmi_codec_pdata vc4_hdmi_codec_pdata = { 2410 .ops = &vc4_hdmi_codec_ops, 2411 .max_i2s_channels = 8, 2412 .i2s = 1, 2413 }; 2414 2415 static void vc4_hdmi_audio_codec_release(void *ptr) 2416 { 2417 struct vc4_hdmi *vc4_hdmi = ptr; 2418 2419 platform_device_unregister(vc4_hdmi->audio.codec_pdev); 2420 vc4_hdmi->audio.codec_pdev = NULL; 2421 } 2422 2423 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi) 2424 { 2425 const struct vc4_hdmi_register *mai_data = 2426 &vc4_hdmi->variant->registers[HDMI_MAI_DATA]; 2427 struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link; 2428 struct snd_soc_card *card = &vc4_hdmi->audio.card; 2429 struct device *dev = &vc4_hdmi->pdev->dev; 2430 struct platform_device *codec_pdev; 2431 const __be32 *addr; 2432 int index, len; 2433 int ret; 2434 2435 /* 2436 * ASoC makes it a bit hard to retrieve a pointer to the 2437 * vc4_hdmi structure. Registering the card will overwrite our 2438 * device drvdata with a pointer to the snd_soc_card structure, 2439 * which can then be used to retrieve whatever drvdata we want 2440 * to associate. 2441 * 2442 * However, that doesn't fly in the case where we wouldn't 2443 * register an ASoC card (because of an old DT that is missing 2444 * the dmas properties for example), then the card isn't 2445 * registered and the device drvdata wouldn't be set. 2446 * 2447 * We can deal with both cases by making sure a snd_soc_card 2448 * pointer and a vc4_hdmi structure are pointing to the same 2449 * memory address, so we can treat them indistinctly without any 2450 * issue. 2451 */ 2452 BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0); 2453 BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0); 2454 2455 if (!of_find_property(dev->of_node, "dmas", &len) || !len) { 2456 dev_warn(dev, 2457 "'dmas' DT property is missing or empty, no HDMI audio\n"); 2458 return 0; 2459 } 2460 2461 if (mai_data->reg != VC4_HD) { 2462 WARN_ONCE(true, "MAI isn't in the HD block\n"); 2463 return -EINVAL; 2464 } 2465 2466 /* 2467 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve 2468 * the bus address specified in the DT, because the physical address 2469 * (the one returned by platform_get_resource()) is not appropriate 2470 * for DMA transfers. 2471 * This VC/MMU should probably be exposed to avoid this kind of hacks. 2472 */ 2473 index = of_property_match_string(dev->of_node, "reg-names", "hd"); 2474 /* Before BCM2711, we don't have a named register range */ 2475 if (index < 0) 2476 index = 1; 2477 2478 addr = of_get_address(dev->of_node, index, NULL, NULL); 2479 2480 vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset; 2481 vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 2482 vc4_hdmi->audio.dma_data.maxburst = 2; 2483 2484 /* 2485 * NOTE: Strictly speaking, we should probably use a DRM-managed 2486 * registration there to avoid removing all the audio components 2487 * by the time the driver doesn't have any user anymore. 2488 * 2489 * However, the ASoC core uses a number of devm_kzalloc calls 2490 * when registering, even when using non-device-managed 2491 * functions (such as in snd_soc_register_component()). 2492 * 2493 * If we call snd_soc_unregister_component() in a DRM-managed 2494 * action, the device-managed actions have already been executed 2495 * and thus we would access memory that has been freed. 2496 * 2497 * Using device-managed hooks here probably leaves us open to a 2498 * bunch of issues if userspace still has a handle on the ALSA 2499 * device when the device is removed. However, this is mitigated 2500 * by the use of drm_dev_enter()/drm_dev_exit() in the audio 2501 * path to prevent the access to the device resources if it 2502 * isn't there anymore. 2503 * 2504 * Then, the vc4_hdmi structure is DRM-managed and thus only 2505 * freed whenever the last user has closed the DRM device file. 2506 * It should thus outlive ALSA in most situations. 2507 */ 2508 ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0); 2509 if (ret) { 2510 dev_err(dev, "Could not register PCM component: %d\n", ret); 2511 return ret; 2512 } 2513 2514 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp, 2515 &vc4_hdmi_audio_cpu_dai_drv, 1); 2516 if (ret) { 2517 dev_err(dev, "Could not register CPU DAI: %d\n", ret); 2518 return ret; 2519 } 2520 2521 codec_pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME, 2522 PLATFORM_DEVID_AUTO, 2523 &vc4_hdmi_codec_pdata, 2524 sizeof(vc4_hdmi_codec_pdata)); 2525 if (IS_ERR(codec_pdev)) { 2526 dev_err(dev, "Couldn't register the HDMI codec: %ld\n", PTR_ERR(codec_pdev)); 2527 return PTR_ERR(codec_pdev); 2528 } 2529 vc4_hdmi->audio.codec_pdev = codec_pdev; 2530 2531 ret = devm_add_action_or_reset(dev, vc4_hdmi_audio_codec_release, vc4_hdmi); 2532 if (ret) 2533 return ret; 2534 2535 dai_link->cpus = &vc4_hdmi->audio.cpu; 2536 dai_link->codecs = &vc4_hdmi->audio.codec; 2537 dai_link->platforms = &vc4_hdmi->audio.platform; 2538 2539 dai_link->num_cpus = 1; 2540 dai_link->num_codecs = 1; 2541 dai_link->num_platforms = 1; 2542 2543 dai_link->name = "MAI"; 2544 dai_link->stream_name = "MAI PCM"; 2545 dai_link->codecs->dai_name = "i2s-hifi"; 2546 dai_link->cpus->dai_name = dev_name(dev); 2547 dai_link->codecs->name = dev_name(&codec_pdev->dev); 2548 dai_link->platforms->name = dev_name(dev); 2549 2550 card->dai_link = dai_link; 2551 card->num_links = 1; 2552 card->name = vc4_hdmi->variant->card_name; 2553 card->driver_name = "vc4-hdmi"; 2554 card->dev = dev; 2555 card->owner = THIS_MODULE; 2556 2557 /* 2558 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and 2559 * stores a pointer to the snd card object in dev->driver_data. This 2560 * means we cannot use it for something else. The hdmi back-pointer is 2561 * now stored in card->drvdata and should be retrieved with 2562 * snd_soc_card_get_drvdata() if needed. 2563 */ 2564 snd_soc_card_set_drvdata(card, vc4_hdmi); 2565 ret = devm_snd_soc_register_card(dev, card); 2566 if (ret) 2567 dev_err_probe(dev, ret, "Could not register sound card\n"); 2568 2569 return ret; 2570 2571 } 2572 2573 static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv) 2574 { 2575 struct vc4_hdmi *vc4_hdmi = priv; 2576 struct drm_connector *connector = &vc4_hdmi->connector; 2577 struct drm_device *dev = connector->dev; 2578 2579 if (dev && dev->registered) 2580 drm_connector_helper_hpd_irq_event(connector); 2581 2582 return IRQ_HANDLED; 2583 } 2584 2585 static int vc4_hdmi_hotplug_init(struct vc4_hdmi *vc4_hdmi) 2586 { 2587 struct drm_connector *connector = &vc4_hdmi->connector; 2588 struct platform_device *pdev = vc4_hdmi->pdev; 2589 int ret; 2590 2591 if (vc4_hdmi->variant->external_irq_controller) { 2592 unsigned int hpd_con = platform_get_irq_byname(pdev, "hpd-connected"); 2593 unsigned int hpd_rm = platform_get_irq_byname(pdev, "hpd-removed"); 2594 2595 ret = devm_request_threaded_irq(&pdev->dev, hpd_con, 2596 NULL, 2597 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT, 2598 "vc4 hdmi hpd connected", vc4_hdmi); 2599 if (ret) 2600 return ret; 2601 2602 ret = devm_request_threaded_irq(&pdev->dev, hpd_rm, 2603 NULL, 2604 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT, 2605 "vc4 hdmi hpd disconnected", vc4_hdmi); 2606 if (ret) 2607 return ret; 2608 2609 connector->polled = DRM_CONNECTOR_POLL_HPD; 2610 } 2611 2612 return 0; 2613 } 2614 2615 #ifdef CONFIG_DRM_VC4_HDMI_CEC 2616 static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv) 2617 { 2618 struct vc4_hdmi *vc4_hdmi = priv; 2619 2620 if (vc4_hdmi->cec_rx_msg.len) 2621 cec_received_msg(vc4_hdmi->cec_adap, 2622 &vc4_hdmi->cec_rx_msg); 2623 2624 return IRQ_HANDLED; 2625 } 2626 2627 static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv) 2628 { 2629 struct vc4_hdmi *vc4_hdmi = priv; 2630 2631 if (vc4_hdmi->cec_tx_ok) { 2632 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK, 2633 0, 0, 0, 0); 2634 } else { 2635 /* 2636 * This CEC implementation makes 1 retry, so if we 2637 * get a NACK, then that means it made 2 attempts. 2638 */ 2639 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK, 2640 0, 2, 0, 0); 2641 } 2642 return IRQ_HANDLED; 2643 } 2644 2645 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv) 2646 { 2647 struct vc4_hdmi *vc4_hdmi = priv; 2648 irqreturn_t ret; 2649 2650 if (vc4_hdmi->cec_irq_was_rx) 2651 ret = vc4_cec_irq_handler_rx_thread(irq, priv); 2652 else 2653 ret = vc4_cec_irq_handler_tx_thread(irq, priv); 2654 2655 return ret; 2656 } 2657 2658 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1) 2659 { 2660 struct drm_device *dev = vc4_hdmi->connector.dev; 2661 struct cec_msg *msg = &vc4_hdmi->cec_rx_msg; 2662 unsigned int i; 2663 2664 lockdep_assert_held(&vc4_hdmi->hw_lock); 2665 2666 msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >> 2667 VC4_HDMI_CEC_REC_WRD_CNT_SHIFT); 2668 2669 if (msg->len > 16) { 2670 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len); 2671 return; 2672 } 2673 2674 for (i = 0; i < msg->len; i += 4) { 2675 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2)); 2676 2677 msg->msg[i] = val & 0xff; 2678 msg->msg[i + 1] = (val >> 8) & 0xff; 2679 msg->msg[i + 2] = (val >> 16) & 0xff; 2680 msg->msg[i + 3] = (val >> 24) & 0xff; 2681 } 2682 } 2683 2684 static irqreturn_t vc4_cec_irq_handler_tx_bare_locked(struct vc4_hdmi *vc4_hdmi) 2685 { 2686 u32 cntrl1; 2687 2688 /* 2689 * We don't need to protect the register access using 2690 * drm_dev_enter() there because the interrupt handler lifetime 2691 * is tied to the device itself, and not to the DRM device. 2692 * 2693 * So when the device will be gone, one of the first thing we 2694 * will be doing will be to unregister the interrupt handler, 2695 * and then unregister the DRM device. drm_dev_enter() would 2696 * thus always succeed if we are here. 2697 */ 2698 2699 lockdep_assert_held(&vc4_hdmi->hw_lock); 2700 2701 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1); 2702 vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD; 2703 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 2704 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 2705 2706 return IRQ_WAKE_THREAD; 2707 } 2708 2709 static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv) 2710 { 2711 struct vc4_hdmi *vc4_hdmi = priv; 2712 irqreturn_t ret; 2713 2714 spin_lock(&vc4_hdmi->hw_lock); 2715 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi); 2716 spin_unlock(&vc4_hdmi->hw_lock); 2717 2718 return ret; 2719 } 2720 2721 static irqreturn_t vc4_cec_irq_handler_rx_bare_locked(struct vc4_hdmi *vc4_hdmi) 2722 { 2723 u32 cntrl1; 2724 2725 lockdep_assert_held(&vc4_hdmi->hw_lock); 2726 2727 /* 2728 * We don't need to protect the register access using 2729 * drm_dev_enter() there because the interrupt handler lifetime 2730 * is tied to the device itself, and not to the DRM device. 2731 * 2732 * So when the device will be gone, one of the first thing we 2733 * will be doing will be to unregister the interrupt handler, 2734 * and then unregister the DRM device. drm_dev_enter() would 2735 * thus always succeed if we are here. 2736 */ 2737 2738 vc4_hdmi->cec_rx_msg.len = 0; 2739 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1); 2740 vc4_cec_read_msg(vc4_hdmi, cntrl1); 2741 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 2742 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 2743 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 2744 2745 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 2746 2747 return IRQ_WAKE_THREAD; 2748 } 2749 2750 static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv) 2751 { 2752 struct vc4_hdmi *vc4_hdmi = priv; 2753 irqreturn_t ret; 2754 2755 spin_lock(&vc4_hdmi->hw_lock); 2756 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi); 2757 spin_unlock(&vc4_hdmi->hw_lock); 2758 2759 return ret; 2760 } 2761 2762 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv) 2763 { 2764 struct vc4_hdmi *vc4_hdmi = priv; 2765 u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS); 2766 irqreturn_t ret; 2767 u32 cntrl5; 2768 2769 /* 2770 * We don't need to protect the register access using 2771 * drm_dev_enter() there because the interrupt handler lifetime 2772 * is tied to the device itself, and not to the DRM device. 2773 * 2774 * So when the device will be gone, one of the first thing we 2775 * will be doing will be to unregister the interrupt handler, 2776 * and then unregister the DRM device. drm_dev_enter() would 2777 * thus always succeed if we are here. 2778 */ 2779 2780 if (!(stat & VC4_HDMI_CPU_CEC)) 2781 return IRQ_NONE; 2782 2783 spin_lock(&vc4_hdmi->hw_lock); 2784 cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5); 2785 vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT; 2786 if (vc4_hdmi->cec_irq_was_rx) 2787 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi); 2788 else 2789 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi); 2790 2791 HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC); 2792 spin_unlock(&vc4_hdmi->hw_lock); 2793 2794 return ret; 2795 } 2796 2797 static int vc4_hdmi_cec_enable(struct cec_adapter *adap) 2798 { 2799 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 2800 struct drm_device *drm = vc4_hdmi->connector.dev; 2801 /* clock period in microseconds */ 2802 const u32 usecs = 1000000 / CEC_CLOCK_FREQ; 2803 unsigned long flags; 2804 u32 val; 2805 int ret; 2806 int idx; 2807 2808 if (!drm_dev_enter(drm, &idx)) 2809 /* 2810 * We can't return an error code, because the CEC 2811 * framework will emit WARN_ON messages at unbind 2812 * otherwise. 2813 */ 2814 return 0; 2815 2816 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev); 2817 if (ret) { 2818 drm_dev_exit(idx); 2819 return ret; 2820 } 2821 2822 mutex_lock(&vc4_hdmi->mutex); 2823 2824 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2825 2826 val = HDMI_READ(HDMI_CEC_CNTRL_5); 2827 val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET | 2828 VC4_HDMI_CEC_CNT_TO_4700_US_MASK | 2829 VC4_HDMI_CEC_CNT_TO_4500_US_MASK); 2830 val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) | 2831 ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT); 2832 2833 HDMI_WRITE(HDMI_CEC_CNTRL_5, val | 2834 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 2835 HDMI_WRITE(HDMI_CEC_CNTRL_5, val); 2836 HDMI_WRITE(HDMI_CEC_CNTRL_2, 2837 ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) | 2838 ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) | 2839 ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) | 2840 ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) | 2841 ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT)); 2842 HDMI_WRITE(HDMI_CEC_CNTRL_3, 2843 ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) | 2844 ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) | 2845 ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) | 2846 ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT)); 2847 HDMI_WRITE(HDMI_CEC_CNTRL_4, 2848 ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) | 2849 ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) | 2850 ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) | 2851 ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT)); 2852 2853 if (!vc4_hdmi->variant->external_irq_controller) 2854 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC); 2855 2856 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2857 2858 mutex_unlock(&vc4_hdmi->mutex); 2859 drm_dev_exit(idx); 2860 2861 return 0; 2862 } 2863 2864 static int vc4_hdmi_cec_disable(struct cec_adapter *adap) 2865 { 2866 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 2867 struct drm_device *drm = vc4_hdmi->connector.dev; 2868 unsigned long flags; 2869 int idx; 2870 2871 if (!drm_dev_enter(drm, &idx)) 2872 /* 2873 * We can't return an error code, because the CEC 2874 * framework will emit WARN_ON messages at unbind 2875 * otherwise. 2876 */ 2877 return 0; 2878 2879 mutex_lock(&vc4_hdmi->mutex); 2880 2881 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2882 2883 if (!vc4_hdmi->variant->external_irq_controller) 2884 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC); 2885 2886 HDMI_WRITE(HDMI_CEC_CNTRL_5, HDMI_READ(HDMI_CEC_CNTRL_5) | 2887 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 2888 2889 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2890 2891 mutex_unlock(&vc4_hdmi->mutex); 2892 2893 pm_runtime_put(&vc4_hdmi->pdev->dev); 2894 2895 drm_dev_exit(idx); 2896 2897 return 0; 2898 } 2899 2900 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable) 2901 { 2902 if (enable) 2903 return vc4_hdmi_cec_enable(adap); 2904 else 2905 return vc4_hdmi_cec_disable(adap); 2906 } 2907 2908 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr) 2909 { 2910 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 2911 struct drm_device *drm = vc4_hdmi->connector.dev; 2912 unsigned long flags; 2913 int idx; 2914 2915 if (!drm_dev_enter(drm, &idx)) 2916 /* 2917 * We can't return an error code, because the CEC 2918 * framework will emit WARN_ON messages at unbind 2919 * otherwise. 2920 */ 2921 return 0; 2922 2923 mutex_lock(&vc4_hdmi->mutex); 2924 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2925 HDMI_WRITE(HDMI_CEC_CNTRL_1, 2926 (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) | 2927 (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT); 2928 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2929 mutex_unlock(&vc4_hdmi->mutex); 2930 2931 drm_dev_exit(idx); 2932 2933 return 0; 2934 } 2935 2936 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts, 2937 u32 signal_free_time, struct cec_msg *msg) 2938 { 2939 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 2940 struct drm_device *dev = vc4_hdmi->connector.dev; 2941 unsigned long flags; 2942 u32 val; 2943 unsigned int i; 2944 int idx; 2945 2946 if (!drm_dev_enter(dev, &idx)) 2947 return -ENODEV; 2948 2949 if (msg->len > 16) { 2950 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len); 2951 drm_dev_exit(idx); 2952 return -ENOMEM; 2953 } 2954 2955 mutex_lock(&vc4_hdmi->mutex); 2956 2957 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2958 2959 for (i = 0; i < msg->len; i += 4) 2960 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2), 2961 (msg->msg[i]) | 2962 (msg->msg[i + 1] << 8) | 2963 (msg->msg[i + 2] << 16) | 2964 (msg->msg[i + 3] << 24)); 2965 2966 val = HDMI_READ(HDMI_CEC_CNTRL_1); 2967 val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 2968 HDMI_WRITE(HDMI_CEC_CNTRL_1, val); 2969 val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK; 2970 val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT; 2971 val |= VC4_HDMI_CEC_START_XMIT_BEGIN; 2972 2973 HDMI_WRITE(HDMI_CEC_CNTRL_1, val); 2974 2975 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2976 mutex_unlock(&vc4_hdmi->mutex); 2977 drm_dev_exit(idx); 2978 2979 return 0; 2980 } 2981 2982 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = { 2983 .adap_enable = vc4_hdmi_cec_adap_enable, 2984 .adap_log_addr = vc4_hdmi_cec_adap_log_addr, 2985 .adap_transmit = vc4_hdmi_cec_adap_transmit, 2986 }; 2987 2988 static void vc4_hdmi_cec_release(void *ptr) 2989 { 2990 struct vc4_hdmi *vc4_hdmi = ptr; 2991 2992 cec_unregister_adapter(vc4_hdmi->cec_adap); 2993 vc4_hdmi->cec_adap = NULL; 2994 } 2995 2996 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi) 2997 { 2998 struct cec_connector_info conn_info; 2999 struct platform_device *pdev = vc4_hdmi->pdev; 3000 struct device *dev = &pdev->dev; 3001 int ret; 3002 3003 if (!of_find_property(dev->of_node, "interrupts", NULL)) { 3004 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n"); 3005 return 0; 3006 } 3007 3008 vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops, 3009 vc4_hdmi, "vc4", 3010 CEC_CAP_DEFAULTS | 3011 CEC_CAP_CONNECTOR_INFO, 1); 3012 ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap); 3013 if (ret < 0) 3014 return ret; 3015 3016 cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector); 3017 cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info); 3018 3019 if (vc4_hdmi->variant->external_irq_controller) { 3020 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-rx"), 3021 vc4_cec_irq_handler_rx_bare, 3022 vc4_cec_irq_handler_rx_thread, 0, 3023 "vc4 hdmi cec rx", vc4_hdmi); 3024 if (ret) 3025 goto err_delete_cec_adap; 3026 3027 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-tx"), 3028 vc4_cec_irq_handler_tx_bare, 3029 vc4_cec_irq_handler_tx_thread, 0, 3030 "vc4 hdmi cec tx", vc4_hdmi); 3031 if (ret) 3032 goto err_delete_cec_adap; 3033 } else { 3034 ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0), 3035 vc4_cec_irq_handler, 3036 vc4_cec_irq_handler_thread, 0, 3037 "vc4 hdmi cec", vc4_hdmi); 3038 if (ret) 3039 goto err_delete_cec_adap; 3040 } 3041 3042 ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev); 3043 if (ret < 0) 3044 goto err_delete_cec_adap; 3045 3046 /* 3047 * NOTE: Strictly speaking, we should probably use a DRM-managed 3048 * registration there to avoid removing the CEC adapter by the 3049 * time the DRM driver doesn't have any user anymore. 3050 * 3051 * However, the CEC framework already cleans up the CEC adapter 3052 * only when the last user has closed its file descriptor, so we 3053 * don't need to handle it in DRM. 3054 * 3055 * By the time the device-managed hook is executed, we will give 3056 * up our reference to the CEC adapter and therefore don't 3057 * really care when it's actually freed. 3058 * 3059 * There's still a problematic sequence: if we unregister our 3060 * CEC adapter, but the userspace keeps a handle on the CEC 3061 * adapter but not the DRM device for some reason. In such a 3062 * case, our vc4_hdmi structure will be freed, but the 3063 * cec_adapter structure will have a dangling pointer to what 3064 * used to be our HDMI controller. If we get a CEC call at that 3065 * moment, we could end up with a use-after-free. Fortunately, 3066 * the CEC framework already handles this too, by calling 3067 * cec_is_registered() in cec_ioctl() and cec_poll(). 3068 */ 3069 ret = devm_add_action_or_reset(dev, vc4_hdmi_cec_release, vc4_hdmi); 3070 if (ret) 3071 return ret; 3072 3073 return 0; 3074 3075 err_delete_cec_adap: 3076 cec_delete_adapter(vc4_hdmi->cec_adap); 3077 3078 return ret; 3079 } 3080 #else 3081 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi) 3082 { 3083 return 0; 3084 } 3085 #endif 3086 3087 static void vc4_hdmi_free_regset(struct drm_device *drm, void *ptr) 3088 { 3089 struct debugfs_reg32 *regs = ptr; 3090 3091 kfree(regs); 3092 } 3093 3094 static int vc4_hdmi_build_regset(struct drm_device *drm, 3095 struct vc4_hdmi *vc4_hdmi, 3096 struct debugfs_regset32 *regset, 3097 enum vc4_hdmi_regs reg) 3098 { 3099 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant; 3100 struct debugfs_reg32 *regs, *new_regs; 3101 unsigned int count = 0; 3102 unsigned int i; 3103 int ret; 3104 3105 regs = kcalloc(variant->num_registers, sizeof(*regs), 3106 GFP_KERNEL); 3107 if (!regs) 3108 return -ENOMEM; 3109 3110 for (i = 0; i < variant->num_registers; i++) { 3111 const struct vc4_hdmi_register *field = &variant->registers[i]; 3112 3113 if (field->reg != reg) 3114 continue; 3115 3116 regs[count].name = field->name; 3117 regs[count].offset = field->offset; 3118 count++; 3119 } 3120 3121 new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL); 3122 if (!new_regs) 3123 return -ENOMEM; 3124 3125 regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg); 3126 regset->regs = new_regs; 3127 regset->nregs = count; 3128 3129 ret = drmm_add_action_or_reset(drm, vc4_hdmi_free_regset, new_regs); 3130 if (ret) 3131 return ret; 3132 3133 return 0; 3134 } 3135 3136 static int vc4_hdmi_init_resources(struct drm_device *drm, 3137 struct vc4_hdmi *vc4_hdmi) 3138 { 3139 struct platform_device *pdev = vc4_hdmi->pdev; 3140 struct device *dev = &pdev->dev; 3141 int ret; 3142 3143 vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0); 3144 if (IS_ERR(vc4_hdmi->hdmicore_regs)) 3145 return PTR_ERR(vc4_hdmi->hdmicore_regs); 3146 3147 vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1); 3148 if (IS_ERR(vc4_hdmi->hd_regs)) 3149 return PTR_ERR(vc4_hdmi->hd_regs); 3150 3151 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD); 3152 if (ret) 3153 return ret; 3154 3155 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI); 3156 if (ret) 3157 return ret; 3158 3159 vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel"); 3160 if (IS_ERR(vc4_hdmi->pixel_clock)) { 3161 ret = PTR_ERR(vc4_hdmi->pixel_clock); 3162 if (ret != -EPROBE_DEFER) 3163 DRM_ERROR("Failed to get pixel clock\n"); 3164 return ret; 3165 } 3166 3167 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); 3168 if (IS_ERR(vc4_hdmi->hsm_clock)) { 3169 DRM_ERROR("Failed to get HDMI state machine clock\n"); 3170 return PTR_ERR(vc4_hdmi->hsm_clock); 3171 } 3172 vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock; 3173 vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock; 3174 3175 return 0; 3176 } 3177 3178 static int vc5_hdmi_init_resources(struct drm_device *drm, 3179 struct vc4_hdmi *vc4_hdmi) 3180 { 3181 struct platform_device *pdev = vc4_hdmi->pdev; 3182 struct device *dev = &pdev->dev; 3183 struct resource *res; 3184 int ret; 3185 3186 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi"); 3187 if (!res) 3188 return -ENODEV; 3189 3190 vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start, 3191 resource_size(res)); 3192 if (!vc4_hdmi->hdmicore_regs) 3193 return -ENOMEM; 3194 3195 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd"); 3196 if (!res) 3197 return -ENODEV; 3198 3199 vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res)); 3200 if (!vc4_hdmi->hd_regs) 3201 return -ENOMEM; 3202 3203 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec"); 3204 if (!res) 3205 return -ENODEV; 3206 3207 vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res)); 3208 if (!vc4_hdmi->cec_regs) 3209 return -ENOMEM; 3210 3211 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc"); 3212 if (!res) 3213 return -ENODEV; 3214 3215 vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res)); 3216 if (!vc4_hdmi->csc_regs) 3217 return -ENOMEM; 3218 3219 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp"); 3220 if (!res) 3221 return -ENODEV; 3222 3223 vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res)); 3224 if (!vc4_hdmi->dvp_regs) 3225 return -ENOMEM; 3226 3227 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy"); 3228 if (!res) 3229 return -ENODEV; 3230 3231 vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res)); 3232 if (!vc4_hdmi->phy_regs) 3233 return -ENOMEM; 3234 3235 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet"); 3236 if (!res) 3237 return -ENODEV; 3238 3239 vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res)); 3240 if (!vc4_hdmi->ram_regs) 3241 return -ENOMEM; 3242 3243 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm"); 3244 if (!res) 3245 return -ENODEV; 3246 3247 vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res)); 3248 if (!vc4_hdmi->rm_regs) 3249 return -ENOMEM; 3250 3251 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); 3252 if (IS_ERR(vc4_hdmi->hsm_clock)) { 3253 DRM_ERROR("Failed to get HDMI state machine clock\n"); 3254 return PTR_ERR(vc4_hdmi->hsm_clock); 3255 } 3256 3257 vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb"); 3258 if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) { 3259 DRM_ERROR("Failed to get pixel bvb clock\n"); 3260 return PTR_ERR(vc4_hdmi->pixel_bvb_clock); 3261 } 3262 3263 vc4_hdmi->audio_clock = devm_clk_get(dev, "audio"); 3264 if (IS_ERR(vc4_hdmi->audio_clock)) { 3265 DRM_ERROR("Failed to get audio clock\n"); 3266 return PTR_ERR(vc4_hdmi->audio_clock); 3267 } 3268 3269 vc4_hdmi->cec_clock = devm_clk_get(dev, "cec"); 3270 if (IS_ERR(vc4_hdmi->cec_clock)) { 3271 DRM_ERROR("Failed to get CEC clock\n"); 3272 return PTR_ERR(vc4_hdmi->cec_clock); 3273 } 3274 3275 vc4_hdmi->reset = devm_reset_control_get(dev, NULL); 3276 if (IS_ERR(vc4_hdmi->reset)) { 3277 DRM_ERROR("Failed to get HDMI reset line\n"); 3278 return PTR_ERR(vc4_hdmi->reset); 3279 } 3280 3281 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI); 3282 if (ret) 3283 return ret; 3284 3285 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD); 3286 if (ret) 3287 return ret; 3288 3289 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->cec_regset, VC5_CEC); 3290 if (ret) 3291 return ret; 3292 3293 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->csc_regset, VC5_CSC); 3294 if (ret) 3295 return ret; 3296 3297 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->dvp_regset, VC5_DVP); 3298 if (ret) 3299 return ret; 3300 3301 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->phy_regset, VC5_PHY); 3302 if (ret) 3303 return ret; 3304 3305 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->ram_regset, VC5_RAM); 3306 if (ret) 3307 return ret; 3308 3309 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->rm_regset, VC5_RM); 3310 if (ret) 3311 return ret; 3312 3313 return 0; 3314 } 3315 3316 static int vc4_hdmi_runtime_suspend(struct device *dev) 3317 { 3318 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 3319 3320 clk_disable_unprepare(vc4_hdmi->hsm_clock); 3321 3322 return 0; 3323 } 3324 3325 static int vc4_hdmi_runtime_resume(struct device *dev) 3326 { 3327 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 3328 unsigned long __maybe_unused flags; 3329 u32 __maybe_unused value; 3330 unsigned long rate; 3331 int ret; 3332 3333 /* 3334 * The HSM clock is in the HDMI power domain, so we need to set 3335 * its frequency while the power domain is active so that it 3336 * keeps its rate. 3337 */ 3338 ret = clk_set_min_rate(vc4_hdmi->hsm_clock, HSM_MIN_CLOCK_FREQ); 3339 if (ret) 3340 return ret; 3341 3342 ret = clk_prepare_enable(vc4_hdmi->hsm_clock); 3343 if (ret) 3344 return ret; 3345 3346 /* 3347 * Whenever the RaspberryPi boots without an HDMI monitor 3348 * plugged in, the firmware won't have initialized the HSM clock 3349 * rate and it will be reported as 0. 3350 * 3351 * If we try to access a register of the controller in such a 3352 * case, it will lead to a silent CPU stall. Let's make sure we 3353 * prevent such a case. 3354 */ 3355 rate = clk_get_rate(vc4_hdmi->hsm_clock); 3356 if (!rate) { 3357 ret = -EINVAL; 3358 goto err_disable_clk; 3359 } 3360 3361 if (vc4_hdmi->variant->reset) 3362 vc4_hdmi->variant->reset(vc4_hdmi); 3363 3364 #ifdef CONFIG_DRM_VC4_HDMI_CEC 3365 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 3366 value = HDMI_READ(HDMI_CEC_CNTRL_1); 3367 /* Set the logical address to Unregistered */ 3368 value |= VC4_HDMI_CEC_ADDR_MASK; 3369 HDMI_WRITE(HDMI_CEC_CNTRL_1, value); 3370 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 3371 3372 vc4_hdmi_cec_update_clk_div(vc4_hdmi); 3373 3374 if (!vc4_hdmi->variant->external_irq_controller) { 3375 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 3376 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff); 3377 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 3378 } 3379 #endif 3380 3381 return 0; 3382 3383 err_disable_clk: 3384 clk_disable_unprepare(vc4_hdmi->hsm_clock); 3385 return ret; 3386 } 3387 3388 static void vc4_hdmi_put_ddc_device(void *ptr) 3389 { 3390 struct vc4_hdmi *vc4_hdmi = ptr; 3391 3392 put_device(&vc4_hdmi->ddc->dev); 3393 } 3394 3395 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data) 3396 { 3397 const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev); 3398 struct platform_device *pdev = to_platform_device(dev); 3399 struct drm_device *drm = dev_get_drvdata(master); 3400 struct vc4_hdmi *vc4_hdmi; 3401 struct drm_encoder *encoder; 3402 struct device_node *ddc_node; 3403 int ret; 3404 3405 vc4_hdmi = drmm_kzalloc(drm, sizeof(*vc4_hdmi), GFP_KERNEL); 3406 if (!vc4_hdmi) 3407 return -ENOMEM; 3408 3409 ret = drmm_mutex_init(drm, &vc4_hdmi->mutex); 3410 if (ret) 3411 return ret; 3412 3413 spin_lock_init(&vc4_hdmi->hw_lock); 3414 INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq); 3415 3416 dev_set_drvdata(dev, vc4_hdmi); 3417 encoder = &vc4_hdmi->encoder.base; 3418 vc4_hdmi->encoder.type = variant->encoder_type; 3419 vc4_hdmi->encoder.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure; 3420 vc4_hdmi->encoder.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable; 3421 vc4_hdmi->encoder.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable; 3422 vc4_hdmi->encoder.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable; 3423 vc4_hdmi->encoder.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown; 3424 vc4_hdmi->pdev = pdev; 3425 vc4_hdmi->variant = variant; 3426 3427 /* 3428 * Since we don't know the state of the controller and its 3429 * display (if any), let's assume it's always enabled. 3430 * vc4_hdmi_disable_scrambling() will thus run at boot, make 3431 * sure it's disabled, and avoid any inconsistency. 3432 */ 3433 if (variant->max_pixel_clock > HDMI_14_MAX_TMDS_CLK) 3434 vc4_hdmi->scdc_enabled = true; 3435 3436 ret = variant->init_resources(drm, vc4_hdmi); 3437 if (ret) 3438 return ret; 3439 3440 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0); 3441 if (!ddc_node) { 3442 DRM_ERROR("Failed to find ddc node in device tree\n"); 3443 return -ENODEV; 3444 } 3445 3446 vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node); 3447 of_node_put(ddc_node); 3448 if (!vc4_hdmi->ddc) { 3449 DRM_DEBUG("Failed to get ddc i2c adapter by node\n"); 3450 return -EPROBE_DEFER; 3451 } 3452 3453 ret = devm_add_action_or_reset(dev, vc4_hdmi_put_ddc_device, vc4_hdmi); 3454 if (ret) 3455 return ret; 3456 3457 /* Only use the GPIO HPD pin if present in the DT, otherwise 3458 * we'll use the HDMI core's register. 3459 */ 3460 vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN); 3461 if (IS_ERR(vc4_hdmi->hpd_gpio)) { 3462 return PTR_ERR(vc4_hdmi->hpd_gpio); 3463 } 3464 3465 vc4_hdmi->disable_wifi_frequencies = 3466 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence"); 3467 3468 ret = devm_pm_runtime_enable(dev); 3469 if (ret) 3470 return ret; 3471 3472 /* 3473 * We need to have the device powered up at this point to call 3474 * our reset hook and for the CEC init. 3475 */ 3476 ret = pm_runtime_resume_and_get(dev); 3477 if (ret) 3478 return ret; 3479 3480 if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") || 3481 of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1")) && 3482 HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) { 3483 clk_prepare_enable(vc4_hdmi->pixel_clock); 3484 clk_prepare_enable(vc4_hdmi->hsm_clock); 3485 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock); 3486 } 3487 3488 ret = drmm_encoder_init(drm, encoder, 3489 &vc4_hdmi_encoder_funcs, 3490 DRM_MODE_ENCODER_TMDS, 3491 NULL); 3492 if (ret) 3493 goto err_put_runtime_pm; 3494 3495 drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs); 3496 3497 ret = vc4_hdmi_connector_init(drm, vc4_hdmi); 3498 if (ret) 3499 goto err_put_runtime_pm; 3500 3501 ret = vc4_hdmi_hotplug_init(vc4_hdmi); 3502 if (ret) 3503 goto err_put_runtime_pm; 3504 3505 ret = vc4_hdmi_cec_init(vc4_hdmi); 3506 if (ret) 3507 goto err_put_runtime_pm; 3508 3509 ret = vc4_hdmi_audio_init(vc4_hdmi); 3510 if (ret) 3511 goto err_put_runtime_pm; 3512 3513 pm_runtime_put_sync(dev); 3514 3515 return 0; 3516 3517 err_put_runtime_pm: 3518 pm_runtime_put_sync(dev); 3519 3520 return ret; 3521 } 3522 3523 static const struct component_ops vc4_hdmi_ops = { 3524 .bind = vc4_hdmi_bind, 3525 }; 3526 3527 static int vc4_hdmi_dev_probe(struct platform_device *pdev) 3528 { 3529 return component_add(&pdev->dev, &vc4_hdmi_ops); 3530 } 3531 3532 static int vc4_hdmi_dev_remove(struct platform_device *pdev) 3533 { 3534 component_del(&pdev->dev, &vc4_hdmi_ops); 3535 return 0; 3536 } 3537 3538 static const struct vc4_hdmi_variant bcm2835_variant = { 3539 .encoder_type = VC4_ENCODER_TYPE_HDMI0, 3540 .debugfs_name = "hdmi_regs", 3541 .card_name = "vc4-hdmi", 3542 .max_pixel_clock = 162000000, 3543 .registers = vc4_hdmi_fields, 3544 .num_registers = ARRAY_SIZE(vc4_hdmi_fields), 3545 3546 .init_resources = vc4_hdmi_init_resources, 3547 .csc_setup = vc4_hdmi_csc_setup, 3548 .reset = vc4_hdmi_reset, 3549 .set_timings = vc4_hdmi_set_timings, 3550 .phy_init = vc4_hdmi_phy_init, 3551 .phy_disable = vc4_hdmi_phy_disable, 3552 .phy_rng_enable = vc4_hdmi_phy_rng_enable, 3553 .phy_rng_disable = vc4_hdmi_phy_rng_disable, 3554 .channel_map = vc4_hdmi_channel_map, 3555 .supports_hdr = false, 3556 }; 3557 3558 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = { 3559 .encoder_type = VC4_ENCODER_TYPE_HDMI0, 3560 .debugfs_name = "hdmi0_regs", 3561 .card_name = "vc4-hdmi-0", 3562 .max_pixel_clock = 600000000, 3563 .registers = vc5_hdmi_hdmi0_fields, 3564 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi0_fields), 3565 .phy_lane_mapping = { 3566 PHY_LANE_0, 3567 PHY_LANE_1, 3568 PHY_LANE_2, 3569 PHY_LANE_CK, 3570 }, 3571 .unsupported_odd_h_timings = true, 3572 .external_irq_controller = true, 3573 3574 .init_resources = vc5_hdmi_init_resources, 3575 .csc_setup = vc5_hdmi_csc_setup, 3576 .reset = vc5_hdmi_reset, 3577 .set_timings = vc5_hdmi_set_timings, 3578 .phy_init = vc5_hdmi_phy_init, 3579 .phy_disable = vc5_hdmi_phy_disable, 3580 .phy_rng_enable = vc5_hdmi_phy_rng_enable, 3581 .phy_rng_disable = vc5_hdmi_phy_rng_disable, 3582 .channel_map = vc5_hdmi_channel_map, 3583 .supports_hdr = true, 3584 .hp_detect = vc5_hdmi_hp_detect, 3585 }; 3586 3587 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = { 3588 .encoder_type = VC4_ENCODER_TYPE_HDMI1, 3589 .debugfs_name = "hdmi1_regs", 3590 .card_name = "vc4-hdmi-1", 3591 .max_pixel_clock = HDMI_14_MAX_TMDS_CLK, 3592 .registers = vc5_hdmi_hdmi1_fields, 3593 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi1_fields), 3594 .phy_lane_mapping = { 3595 PHY_LANE_1, 3596 PHY_LANE_0, 3597 PHY_LANE_CK, 3598 PHY_LANE_2, 3599 }, 3600 .unsupported_odd_h_timings = true, 3601 .external_irq_controller = true, 3602 3603 .init_resources = vc5_hdmi_init_resources, 3604 .csc_setup = vc5_hdmi_csc_setup, 3605 .reset = vc5_hdmi_reset, 3606 .set_timings = vc5_hdmi_set_timings, 3607 .phy_init = vc5_hdmi_phy_init, 3608 .phy_disable = vc5_hdmi_phy_disable, 3609 .phy_rng_enable = vc5_hdmi_phy_rng_enable, 3610 .phy_rng_disable = vc5_hdmi_phy_rng_disable, 3611 .channel_map = vc5_hdmi_channel_map, 3612 .supports_hdr = true, 3613 .hp_detect = vc5_hdmi_hp_detect, 3614 }; 3615 3616 static const struct of_device_id vc4_hdmi_dt_match[] = { 3617 { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant }, 3618 { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant }, 3619 { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant }, 3620 {} 3621 }; 3622 3623 static const struct dev_pm_ops vc4_hdmi_pm_ops = { 3624 SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend, 3625 vc4_hdmi_runtime_resume, 3626 NULL) 3627 }; 3628 3629 struct platform_driver vc4_hdmi_driver = { 3630 .probe = vc4_hdmi_dev_probe, 3631 .remove = vc4_hdmi_dev_remove, 3632 .driver = { 3633 .name = "vc4_hdmi", 3634 .of_match_table = vc4_hdmi_dt_match, 3635 .pm = &vc4_hdmi_pm_ops, 3636 }, 3637 }; 3638