1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 Broadcom 4 * Copyright (c) 2014 The Linux Foundation. All rights reserved. 5 * Copyright (C) 2013 Red Hat 6 * Author: Rob Clark <robdclark@gmail.com> 7 */ 8 9 /** 10 * DOC: VC4 Falcon HDMI module 11 * 12 * The HDMI core has a state machine and a PHY. On BCM2835, most of 13 * the unit operates off of the HSM clock from CPRMAN. It also 14 * internally uses the PLLH_PIX clock for the PHY. 15 * 16 * HDMI infoframes are kept within a small packet ram, where each 17 * packet can be individually enabled for including in a frame. 18 * 19 * HDMI audio is implemented entirely within the HDMI IP block. A 20 * register in the HDMI encoder takes SPDIF frames from the DMA engine 21 * and transfers them over an internal MAI (multi-channel audio 22 * interconnect) bus to the encoder side for insertion into the video 23 * blank regions. 24 * 25 * The driver's HDMI encoder does not yet support power management. 26 * The HDMI encoder's power domain and the HSM/pixel clocks are kept 27 * continuously running, and only the HDMI logic and packet ram are 28 * powered off/on at disable/enable time. 29 * 30 * The driver does not yet support CEC control, though the HDMI 31 * encoder block has CEC support. 32 */ 33 34 #include <drm/drm_atomic_helper.h> 35 #include <drm/drm_edid.h> 36 #include <drm/drm_probe_helper.h> 37 #include <drm/drm_simple_kms_helper.h> 38 #include <drm/drm_scdc_helper.h> 39 #include <linux/clk.h> 40 #include <linux/component.h> 41 #include <linux/i2c.h> 42 #include <linux/of_address.h> 43 #include <linux/of_gpio.h> 44 #include <linux/of_platform.h> 45 #include <linux/pm_runtime.h> 46 #include <linux/rational.h> 47 #include <linux/reset.h> 48 #include <sound/dmaengine_pcm.h> 49 #include <sound/pcm_drm_eld.h> 50 #include <sound/pcm_params.h> 51 #include <sound/soc.h> 52 #include "media/cec.h" 53 #include "vc4_drv.h" 54 #include "vc4_hdmi.h" 55 #include "vc4_hdmi_regs.h" 56 #include "vc4_regs.h" 57 58 #define VC5_HDMI_HORZA_HFP_SHIFT 16 59 #define VC5_HDMI_HORZA_HFP_MASK VC4_MASK(28, 16) 60 #define VC5_HDMI_HORZA_VPOS BIT(15) 61 #define VC5_HDMI_HORZA_HPOS BIT(14) 62 #define VC5_HDMI_HORZA_HAP_SHIFT 0 63 #define VC5_HDMI_HORZA_HAP_MASK VC4_MASK(13, 0) 64 65 #define VC5_HDMI_HORZB_HBP_SHIFT 16 66 #define VC5_HDMI_HORZB_HBP_MASK VC4_MASK(26, 16) 67 #define VC5_HDMI_HORZB_HSP_SHIFT 0 68 #define VC5_HDMI_HORZB_HSP_MASK VC4_MASK(10, 0) 69 70 #define VC5_HDMI_VERTA_VSP_SHIFT 24 71 #define VC5_HDMI_VERTA_VSP_MASK VC4_MASK(28, 24) 72 #define VC5_HDMI_VERTA_VFP_SHIFT 16 73 #define VC5_HDMI_VERTA_VFP_MASK VC4_MASK(22, 16) 74 #define VC5_HDMI_VERTA_VAL_SHIFT 0 75 #define VC5_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0) 76 77 #define VC5_HDMI_VERTB_VSPO_SHIFT 16 78 #define VC5_HDMI_VERTB_VSPO_MASK VC4_MASK(29, 16) 79 80 #define VC5_HDMI_SCRAMBLER_CTL_ENABLE BIT(0) 81 82 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT 8 83 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK VC4_MASK(10, 8) 84 85 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT 0 86 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK VC4_MASK(3, 0) 87 88 #define VC5_HDMI_GCP_CONFIG_GCP_ENABLE BIT(31) 89 90 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT 8 91 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK VC4_MASK(15, 8) 92 93 # define VC4_HD_M_SW_RST BIT(2) 94 # define VC4_HD_M_ENABLE BIT(0) 95 96 #define CEC_CLOCK_FREQ 40000 97 98 #define HDMI_14_MAX_TMDS_CLK (340 * 1000 * 1000) 99 100 static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode) 101 { 102 return (mode->clock * 1000) > HDMI_14_MAX_TMDS_CLK; 103 } 104 105 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused) 106 { 107 struct drm_info_node *node = (struct drm_info_node *)m->private; 108 struct vc4_hdmi *vc4_hdmi = node->info_ent->data; 109 struct drm_printer p = drm_seq_file_printer(m); 110 111 drm_print_regset32(&p, &vc4_hdmi->hdmi_regset); 112 drm_print_regset32(&p, &vc4_hdmi->hd_regset); 113 114 return 0; 115 } 116 117 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi) 118 { 119 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST); 120 udelay(1); 121 HDMI_WRITE(HDMI_M_CTL, 0); 122 123 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE); 124 125 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 126 VC4_HDMI_SW_RESET_HDMI | 127 VC4_HDMI_SW_RESET_FORMAT_DETECT); 128 129 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0); 130 } 131 132 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi) 133 { 134 reset_control_reset(vc4_hdmi->reset); 135 136 HDMI_WRITE(HDMI_DVP_CTL, 0); 137 138 HDMI_WRITE(HDMI_CLOCK_STOP, 139 HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL); 140 } 141 142 #ifdef CONFIG_DRM_VC4_HDMI_CEC 143 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) 144 { 145 u16 clk_cnt; 146 u32 value; 147 148 value = HDMI_READ(HDMI_CEC_CNTRL_1); 149 value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK; 150 151 /* 152 * Set the clock divider: the hsm_clock rate and this divider 153 * setting will give a 40 kHz CEC clock. 154 */ 155 clk_cnt = clk_get_rate(vc4_hdmi->cec_clock) / CEC_CLOCK_FREQ; 156 value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT; 157 HDMI_WRITE(HDMI_CEC_CNTRL_1, value); 158 } 159 #else 160 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {} 161 #endif 162 163 static enum drm_connector_status 164 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force) 165 { 166 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 167 bool connected = false; 168 169 if (vc4_hdmi->hpd_gpio && 170 gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio)) { 171 connected = true; 172 } else if (drm_probe_ddc(vc4_hdmi->ddc)) { 173 connected = true; 174 } else if (HDMI_READ(HDMI_HOTPLUG) & VC4_HDMI_HOTPLUG_CONNECTED) { 175 connected = true; 176 } 177 178 if (connected) { 179 if (connector->status != connector_status_connected) { 180 struct edid *edid = drm_get_edid(connector, vc4_hdmi->ddc); 181 182 if (edid) { 183 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid); 184 vc4_hdmi->encoder.hdmi_monitor = drm_detect_hdmi_monitor(edid); 185 kfree(edid); 186 } 187 } 188 189 return connector_status_connected; 190 } 191 192 cec_phys_addr_invalidate(vc4_hdmi->cec_adap); 193 return connector_status_disconnected; 194 } 195 196 static void vc4_hdmi_connector_destroy(struct drm_connector *connector) 197 { 198 drm_connector_unregister(connector); 199 drm_connector_cleanup(connector); 200 } 201 202 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector) 203 { 204 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 205 struct vc4_hdmi_encoder *vc4_encoder = &vc4_hdmi->encoder; 206 int ret = 0; 207 struct edid *edid; 208 209 edid = drm_get_edid(connector, vc4_hdmi->ddc); 210 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid); 211 if (!edid) 212 return -ENODEV; 213 214 vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid); 215 216 drm_connector_update_edid_property(connector, edid); 217 ret = drm_add_edid_modes(connector, edid); 218 kfree(edid); 219 220 if (vc4_hdmi->disable_4kp60) { 221 struct drm_device *drm = connector->dev; 222 struct drm_display_mode *mode; 223 224 list_for_each_entry(mode, &connector->probed_modes, head) { 225 if (vc4_hdmi_mode_needs_scrambling(mode)) { 226 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz."); 227 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60."); 228 } 229 } 230 } 231 232 return ret; 233 } 234 235 static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector, 236 struct drm_atomic_state *state) 237 { 238 struct drm_connector_state *old_state = 239 drm_atomic_get_old_connector_state(state, connector); 240 struct drm_connector_state *new_state = 241 drm_atomic_get_new_connector_state(state, connector); 242 struct drm_crtc *crtc = new_state->crtc; 243 244 if (!crtc) 245 return 0; 246 247 if (old_state->colorspace != new_state->colorspace || 248 !drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) { 249 struct drm_crtc_state *crtc_state; 250 251 crtc_state = drm_atomic_get_crtc_state(state, crtc); 252 if (IS_ERR(crtc_state)) 253 return PTR_ERR(crtc_state); 254 255 crtc_state->mode_changed = true; 256 } 257 258 return 0; 259 } 260 261 static void vc4_hdmi_connector_reset(struct drm_connector *connector) 262 { 263 struct vc4_hdmi_connector_state *old_state = 264 conn_state_to_vc4_hdmi_conn_state(connector->state); 265 struct vc4_hdmi_connector_state *new_state = 266 kzalloc(sizeof(*new_state), GFP_KERNEL); 267 268 if (connector->state) 269 __drm_atomic_helper_connector_destroy_state(connector->state); 270 271 kfree(old_state); 272 __drm_atomic_helper_connector_reset(connector, &new_state->base); 273 274 if (!new_state) 275 return; 276 277 new_state->base.max_bpc = 8; 278 new_state->base.max_requested_bpc = 8; 279 drm_atomic_helper_connector_tv_reset(connector); 280 } 281 282 static struct drm_connector_state * 283 vc4_hdmi_connector_duplicate_state(struct drm_connector *connector) 284 { 285 struct drm_connector_state *conn_state = connector->state; 286 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state); 287 struct vc4_hdmi_connector_state *new_state; 288 289 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL); 290 if (!new_state) 291 return NULL; 292 293 new_state->pixel_rate = vc4_state->pixel_rate; 294 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base); 295 296 return &new_state->base; 297 } 298 299 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = { 300 .detect = vc4_hdmi_connector_detect, 301 .fill_modes = drm_helper_probe_single_connector_modes, 302 .destroy = vc4_hdmi_connector_destroy, 303 .reset = vc4_hdmi_connector_reset, 304 .atomic_duplicate_state = vc4_hdmi_connector_duplicate_state, 305 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 306 }; 307 308 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = { 309 .get_modes = vc4_hdmi_connector_get_modes, 310 .atomic_check = vc4_hdmi_connector_atomic_check, 311 }; 312 313 static int vc4_hdmi_connector_init(struct drm_device *dev, 314 struct vc4_hdmi *vc4_hdmi) 315 { 316 struct drm_connector *connector = &vc4_hdmi->connector; 317 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base; 318 int ret; 319 320 drm_connector_init_with_ddc(dev, connector, 321 &vc4_hdmi_connector_funcs, 322 DRM_MODE_CONNECTOR_HDMIA, 323 vc4_hdmi->ddc); 324 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs); 325 326 /* 327 * Some of the properties below require access to state, like bpc. 328 * Allocate some default initial connector state with our reset helper. 329 */ 330 if (connector->funcs->reset) 331 connector->funcs->reset(connector); 332 333 /* Create and attach TV margin props to this connector. */ 334 ret = drm_mode_create_tv_margin_properties(dev); 335 if (ret) 336 return ret; 337 338 ret = drm_mode_create_hdmi_colorspace_property(connector); 339 if (ret) 340 return ret; 341 342 drm_connector_attach_colorspace_property(connector); 343 drm_connector_attach_tv_margin_properties(connector); 344 drm_connector_attach_max_bpc_property(connector, 8, 12); 345 346 connector->polled = (DRM_CONNECTOR_POLL_CONNECT | 347 DRM_CONNECTOR_POLL_DISCONNECT); 348 349 connector->interlace_allowed = 1; 350 connector->doublescan_allowed = 0; 351 352 if (vc4_hdmi->variant->supports_hdr) 353 drm_connector_attach_hdr_output_metadata_property(connector); 354 355 drm_connector_attach_encoder(connector, encoder); 356 357 return 0; 358 } 359 360 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder, 361 enum hdmi_infoframe_type type, 362 bool poll) 363 { 364 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 365 u32 packet_id = type - 0x80; 366 367 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 368 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id)); 369 370 if (!poll) 371 return 0; 372 373 return wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) & 374 BIT(packet_id)), 100); 375 } 376 377 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder, 378 union hdmi_infoframe *frame) 379 { 380 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 381 u32 packet_id = frame->any.type - 0x80; 382 const struct vc4_hdmi_register *ram_packet_start = 383 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START]; 384 u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id; 385 void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi, 386 ram_packet_start->reg); 387 uint8_t buffer[VC4_HDMI_PACKET_STRIDE]; 388 ssize_t len, i; 389 int ret; 390 391 WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) & 392 VC4_HDMI_RAM_PACKET_ENABLE), 393 "Packet RAM has to be on to store the packet."); 394 395 len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer)); 396 if (len < 0) 397 return; 398 399 ret = vc4_hdmi_stop_packet(encoder, frame->any.type, true); 400 if (ret) { 401 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret); 402 return; 403 } 404 405 for (i = 0; i < len; i += 7) { 406 writel(buffer[i + 0] << 0 | 407 buffer[i + 1] << 8 | 408 buffer[i + 2] << 16, 409 base + packet_reg); 410 packet_reg += 4; 411 412 writel(buffer[i + 3] << 0 | 413 buffer[i + 4] << 8 | 414 buffer[i + 5] << 16 | 415 buffer[i + 6] << 24, 416 base + packet_reg); 417 packet_reg += 4; 418 } 419 420 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 421 HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id)); 422 ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) & 423 BIT(packet_id)), 100); 424 if (ret) 425 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret); 426 } 427 428 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder) 429 { 430 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 431 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 432 struct drm_connector *connector = &vc4_hdmi->connector; 433 struct drm_connector_state *cstate = connector->state; 434 struct drm_crtc *crtc = encoder->crtc; 435 const struct drm_display_mode *mode = &crtc->state->adjusted_mode; 436 union hdmi_infoframe frame; 437 int ret; 438 439 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, 440 connector, mode); 441 if (ret < 0) { 442 DRM_ERROR("couldn't fill AVI infoframe\n"); 443 return; 444 } 445 446 drm_hdmi_avi_infoframe_quant_range(&frame.avi, 447 connector, mode, 448 vc4_encoder->limited_rgb_range ? 449 HDMI_QUANTIZATION_RANGE_LIMITED : 450 HDMI_QUANTIZATION_RANGE_FULL); 451 drm_hdmi_avi_infoframe_colorspace(&frame.avi, cstate); 452 drm_hdmi_avi_infoframe_bars(&frame.avi, cstate); 453 454 vc4_hdmi_write_infoframe(encoder, &frame); 455 } 456 457 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder) 458 { 459 union hdmi_infoframe frame; 460 int ret; 461 462 ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore"); 463 if (ret < 0) { 464 DRM_ERROR("couldn't fill SPD infoframe\n"); 465 return; 466 } 467 468 frame.spd.sdi = HDMI_SPD_SDI_PC; 469 470 vc4_hdmi_write_infoframe(encoder, &frame); 471 } 472 473 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder) 474 { 475 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 476 union hdmi_infoframe frame; 477 478 hdmi_audio_infoframe_init(&frame.audio); 479 480 frame.audio.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM; 481 frame.audio.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM; 482 frame.audio.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM; 483 frame.audio.channels = vc4_hdmi->audio.channels; 484 485 vc4_hdmi_write_infoframe(encoder, &frame); 486 } 487 488 static void vc4_hdmi_set_hdr_infoframe(struct drm_encoder *encoder) 489 { 490 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 491 struct drm_connector *connector = &vc4_hdmi->connector; 492 struct drm_connector_state *conn_state = connector->state; 493 union hdmi_infoframe frame; 494 495 if (!vc4_hdmi->variant->supports_hdr) 496 return; 497 498 if (!conn_state->hdr_output_metadata) 499 return; 500 501 if (drm_hdmi_infoframe_set_hdr_metadata(&frame.drm, conn_state)) 502 return; 503 504 vc4_hdmi_write_infoframe(encoder, &frame); 505 } 506 507 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder) 508 { 509 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 510 511 vc4_hdmi_set_avi_infoframe(encoder); 512 vc4_hdmi_set_spd_infoframe(encoder); 513 /* 514 * If audio was streaming, then we need to reenabled the audio 515 * infoframe here during encoder_enable. 516 */ 517 if (vc4_hdmi->audio.streaming) 518 vc4_hdmi_set_audio_infoframe(encoder); 519 520 vc4_hdmi_set_hdr_infoframe(encoder); 521 } 522 523 static bool vc4_hdmi_supports_scrambling(struct drm_encoder *encoder, 524 struct drm_display_mode *mode) 525 { 526 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 527 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 528 struct drm_display_info *display = &vc4_hdmi->connector.display_info; 529 530 if (!vc4_encoder->hdmi_monitor) 531 return false; 532 533 if (!display->hdmi.scdc.supported || 534 !display->hdmi.scdc.scrambling.supported) 535 return false; 536 537 return true; 538 } 539 540 #define SCRAMBLING_POLLING_DELAY_MS 1000 541 542 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder) 543 { 544 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; 545 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 546 547 if (!vc4_hdmi_supports_scrambling(encoder, mode)) 548 return; 549 550 if (!vc4_hdmi_mode_needs_scrambling(mode)) 551 return; 552 553 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true); 554 drm_scdc_set_scrambling(vc4_hdmi->ddc, true); 555 556 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) | 557 VC5_HDMI_SCRAMBLER_CTL_ENABLE); 558 559 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work, 560 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS)); 561 } 562 563 static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder) 564 { 565 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 566 struct drm_crtc *crtc = encoder->crtc; 567 568 /* 569 * At boot, encoder->crtc will be NULL. Since we don't know the 570 * state of the scrambler and in order to avoid any 571 * inconsistency, let's disable it all the time. 572 */ 573 if (crtc && !vc4_hdmi_supports_scrambling(encoder, &crtc->mode)) 574 return; 575 576 if (crtc && !vc4_hdmi_mode_needs_scrambling(&crtc->mode)) 577 return; 578 579 if (delayed_work_pending(&vc4_hdmi->scrambling_work)) 580 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work); 581 582 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) & 583 ~VC5_HDMI_SCRAMBLER_CTL_ENABLE); 584 585 drm_scdc_set_scrambling(vc4_hdmi->ddc, false); 586 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, false); 587 } 588 589 static void vc4_hdmi_scrambling_wq(struct work_struct *work) 590 { 591 struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work), 592 struct vc4_hdmi, 593 scrambling_work); 594 595 if (drm_scdc_get_scrambling_status(vc4_hdmi->ddc)) 596 return; 597 598 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true); 599 drm_scdc_set_scrambling(vc4_hdmi->ddc, true); 600 601 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work, 602 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS)); 603 } 604 605 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder, 606 struct drm_atomic_state *state) 607 { 608 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 609 610 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0); 611 612 HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | 613 VC4_HD_VID_CTL_CLRRGB | VC4_HD_VID_CTL_CLRSYNC); 614 615 HDMI_WRITE(HDMI_VID_CTL, 616 HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX); 617 618 vc4_hdmi_disable_scrambling(encoder); 619 } 620 621 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder, 622 struct drm_atomic_state *state) 623 { 624 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 625 int ret; 626 627 if (vc4_hdmi->variant->phy_disable) 628 vc4_hdmi->variant->phy_disable(vc4_hdmi); 629 630 HDMI_WRITE(HDMI_VID_CTL, 631 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE); 632 633 clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock); 634 clk_disable_unprepare(vc4_hdmi->hsm_clock); 635 clk_disable_unprepare(vc4_hdmi->pixel_clock); 636 637 ret = pm_runtime_put(&vc4_hdmi->pdev->dev); 638 if (ret < 0) 639 DRM_ERROR("Failed to release power domain: %d\n", ret); 640 } 641 642 static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder) 643 { 644 } 645 646 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable) 647 { 648 u32 csc_ctl; 649 650 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR, 651 VC4_HD_CSC_CTL_ORDER); 652 653 if (enable) { 654 /* CEA VICs other than #1 requre limited range RGB 655 * output unless overridden by an AVI infoframe. 656 * Apply a colorspace conversion to squash 0-255 down 657 * to 16-235. The matrix here is: 658 * 659 * [ 0 0 0.8594 16] 660 * [ 0 0.8594 0 16] 661 * [ 0.8594 0 0 16] 662 * [ 0 0 0 1] 663 */ 664 csc_ctl |= VC4_HD_CSC_CTL_ENABLE; 665 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC; 666 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM, 667 VC4_HD_CSC_CTL_MODE); 668 669 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000); 670 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0); 671 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000); 672 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000); 673 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0); 674 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000); 675 } 676 677 /* The RGB order applies even when CSC is disabled. */ 678 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl); 679 } 680 681 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable) 682 { 683 u32 csc_ctl; 684 685 csc_ctl = 0x07; /* RGB_CONVERT_MODE = custom matrix, || USE_RGB_TO_YCBCR */ 686 687 if (enable) { 688 /* CEA VICs other than #1 requre limited range RGB 689 * output unless overridden by an AVI infoframe. 690 * Apply a colorspace conversion to squash 0-255 down 691 * to 16-235. The matrix here is: 692 * 693 * [ 0.8594 0 0 16] 694 * [ 0 0.8594 0 16] 695 * [ 0 0 0.8594 16] 696 * [ 0 0 0 1] 697 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets 698 */ 699 HDMI_WRITE(HDMI_CSC_12_11, (0x0000 << 16) | 0x1b80); 700 HDMI_WRITE(HDMI_CSC_14_13, (0x0400 << 16) | 0x0000); 701 HDMI_WRITE(HDMI_CSC_22_21, (0x1b80 << 16) | 0x0000); 702 HDMI_WRITE(HDMI_CSC_24_23, (0x0400 << 16) | 0x0000); 703 HDMI_WRITE(HDMI_CSC_32_31, (0x0000 << 16) | 0x0000); 704 HDMI_WRITE(HDMI_CSC_34_33, (0x0400 << 16) | 0x1b80); 705 } else { 706 /* Still use the matrix for full range, but make it unity. 707 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets 708 */ 709 HDMI_WRITE(HDMI_CSC_12_11, (0x0000 << 16) | 0x2000); 710 HDMI_WRITE(HDMI_CSC_14_13, (0x0000 << 16) | 0x0000); 711 HDMI_WRITE(HDMI_CSC_22_21, (0x2000 << 16) | 0x0000); 712 HDMI_WRITE(HDMI_CSC_24_23, (0x0000 << 16) | 0x0000); 713 HDMI_WRITE(HDMI_CSC_32_31, (0x0000 << 16) | 0x0000); 714 HDMI_WRITE(HDMI_CSC_34_33, (0x0000 << 16) | 0x2000); 715 } 716 717 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl); 718 } 719 720 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi, 721 struct drm_connector_state *state, 722 struct drm_display_mode *mode) 723 { 724 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 725 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 726 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 727 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 728 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 729 VC4_HDMI_VERTA_VSP) | 730 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 731 VC4_HDMI_VERTA_VFP) | 732 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL)); 733 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 734 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end, 735 VC4_HDMI_VERTB_VBP)); 736 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 737 VC4_SET_FIELD(mode->crtc_vtotal - 738 mode->crtc_vsync_end - 739 interlaced, 740 VC4_HDMI_VERTB_VBP)); 741 742 HDMI_WRITE(HDMI_HORZA, 743 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) | 744 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) | 745 VC4_SET_FIELD(mode->hdisplay * pixel_rep, 746 VC4_HDMI_HORZA_HAP)); 747 748 HDMI_WRITE(HDMI_HORZB, 749 VC4_SET_FIELD((mode->htotal - 750 mode->hsync_end) * pixel_rep, 751 VC4_HDMI_HORZB_HBP) | 752 VC4_SET_FIELD((mode->hsync_end - 753 mode->hsync_start) * pixel_rep, 754 VC4_HDMI_HORZB_HSP) | 755 VC4_SET_FIELD((mode->hsync_start - 756 mode->hdisplay) * pixel_rep, 757 VC4_HDMI_HORZB_HFP)); 758 759 HDMI_WRITE(HDMI_VERTA0, verta); 760 HDMI_WRITE(HDMI_VERTA1, verta); 761 762 HDMI_WRITE(HDMI_VERTB0, vertb_even); 763 HDMI_WRITE(HDMI_VERTB1, vertb); 764 } 765 766 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi, 767 struct drm_connector_state *state, 768 struct drm_display_mode *mode) 769 { 770 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 771 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 772 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 773 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 774 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 775 VC5_HDMI_VERTA_VSP) | 776 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 777 VC5_HDMI_VERTA_VFP) | 778 VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL)); 779 u32 vertb = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) | 780 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end, 781 VC4_HDMI_VERTB_VBP)); 782 u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) | 783 VC4_SET_FIELD(mode->crtc_vtotal - 784 mode->crtc_vsync_end - 785 interlaced, 786 VC4_HDMI_VERTB_VBP)); 787 unsigned char gcp; 788 bool gcp_en; 789 u32 reg; 790 791 HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, 0x354021); 792 HDMI_WRITE(HDMI_HORZA, 793 (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) | 794 (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) | 795 VC4_SET_FIELD(mode->hdisplay * pixel_rep, 796 VC5_HDMI_HORZA_HAP) | 797 VC4_SET_FIELD((mode->hsync_start - 798 mode->hdisplay) * pixel_rep, 799 VC5_HDMI_HORZA_HFP)); 800 801 HDMI_WRITE(HDMI_HORZB, 802 VC4_SET_FIELD((mode->htotal - 803 mode->hsync_end) * pixel_rep, 804 VC5_HDMI_HORZB_HBP) | 805 VC4_SET_FIELD((mode->hsync_end - 806 mode->hsync_start) * pixel_rep, 807 VC5_HDMI_HORZB_HSP)); 808 809 HDMI_WRITE(HDMI_VERTA0, verta); 810 HDMI_WRITE(HDMI_VERTA1, verta); 811 812 HDMI_WRITE(HDMI_VERTB0, vertb_even); 813 HDMI_WRITE(HDMI_VERTB1, vertb); 814 815 switch (state->max_bpc) { 816 case 12: 817 gcp = 6; 818 gcp_en = true; 819 break; 820 case 10: 821 gcp = 5; 822 gcp_en = true; 823 break; 824 case 8: 825 default: 826 gcp = 4; 827 gcp_en = false; 828 break; 829 } 830 831 reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1); 832 reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK | 833 VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK); 834 reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) | 835 VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH); 836 HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg); 837 838 reg = HDMI_READ(HDMI_GCP_WORD_1); 839 reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK; 840 reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1); 841 HDMI_WRITE(HDMI_GCP_WORD_1, reg); 842 843 reg = HDMI_READ(HDMI_GCP_CONFIG); 844 reg &= ~VC5_HDMI_GCP_CONFIG_GCP_ENABLE; 845 reg |= gcp_en ? VC5_HDMI_GCP_CONFIG_GCP_ENABLE : 0; 846 HDMI_WRITE(HDMI_GCP_CONFIG, reg); 847 848 HDMI_WRITE(HDMI_CLOCK_STOP, 0); 849 } 850 851 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi) 852 { 853 u32 drift; 854 int ret; 855 856 drift = HDMI_READ(HDMI_FIFO_CTL); 857 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK; 858 859 HDMI_WRITE(HDMI_FIFO_CTL, 860 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 861 HDMI_WRITE(HDMI_FIFO_CTL, 862 drift | VC4_HDMI_FIFO_CTL_RECENTER); 863 usleep_range(1000, 1100); 864 HDMI_WRITE(HDMI_FIFO_CTL, 865 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 866 HDMI_WRITE(HDMI_FIFO_CTL, 867 drift | VC4_HDMI_FIFO_CTL_RECENTER); 868 869 ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) & 870 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1); 871 WARN_ONCE(ret, "Timeout waiting for " 872 "VC4_HDMI_FIFO_CTL_RECENTER_DONE"); 873 } 874 875 static struct drm_connector_state * 876 vc4_hdmi_encoder_get_connector_state(struct drm_encoder *encoder, 877 struct drm_atomic_state *state) 878 { 879 struct drm_connector_state *conn_state; 880 struct drm_connector *connector; 881 unsigned int i; 882 883 for_each_new_connector_in_state(state, connector, conn_state, i) { 884 if (conn_state->best_encoder == encoder) 885 return conn_state; 886 } 887 888 return NULL; 889 } 890 891 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder, 892 struct drm_atomic_state *state) 893 { 894 struct drm_connector_state *conn_state = 895 vc4_hdmi_encoder_get_connector_state(encoder, state); 896 struct vc4_hdmi_connector_state *vc4_conn_state = 897 conn_state_to_vc4_hdmi_conn_state(conn_state); 898 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; 899 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 900 unsigned long bvb_rate, pixel_rate, hsm_rate; 901 int ret; 902 903 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev); 904 if (ret < 0) { 905 DRM_ERROR("Failed to retain power domain: %d\n", ret); 906 return; 907 } 908 909 pixel_rate = vc4_conn_state->pixel_rate; 910 ret = clk_set_rate(vc4_hdmi->pixel_clock, pixel_rate); 911 if (ret) { 912 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret); 913 return; 914 } 915 916 ret = clk_prepare_enable(vc4_hdmi->pixel_clock); 917 if (ret) { 918 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret); 919 return; 920 } 921 922 /* 923 * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must 924 * be faster than pixel clock, infinitesimally faster, tested in 925 * simulation. Otherwise, exact value is unimportant for HDMI 926 * operation." This conflicts with bcm2835's vc4 documentation, which 927 * states HSM's clock has to be at least 108% of the pixel clock. 928 * 929 * Real life tests reveal that vc4's firmware statement holds up, and 930 * users are able to use pixel clocks closer to HSM's, namely for 931 * 1920x1200@60Hz. So it was decided to have leave a 1% margin between 932 * both clocks. Which, for RPi0-3 implies a maximum pixel clock of 933 * 162MHz. 934 * 935 * Additionally, the AXI clock needs to be at least 25% of 936 * pixel clock, but HSM ends up being the limiting factor. 937 */ 938 hsm_rate = max_t(unsigned long, 120000000, (pixel_rate / 100) * 101); 939 ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate); 940 if (ret) { 941 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret); 942 return; 943 } 944 945 ret = clk_prepare_enable(vc4_hdmi->hsm_clock); 946 if (ret) { 947 DRM_ERROR("Failed to turn on HSM clock: %d\n", ret); 948 clk_disable_unprepare(vc4_hdmi->pixel_clock); 949 return; 950 } 951 952 vc4_hdmi_cec_update_clk_div(vc4_hdmi); 953 954 if (pixel_rate > 297000000) 955 bvb_rate = 300000000; 956 else if (pixel_rate > 148500000) 957 bvb_rate = 150000000; 958 else 959 bvb_rate = 75000000; 960 961 ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate); 962 if (ret) { 963 DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret); 964 clk_disable_unprepare(vc4_hdmi->hsm_clock); 965 clk_disable_unprepare(vc4_hdmi->pixel_clock); 966 return; 967 } 968 969 ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock); 970 if (ret) { 971 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret); 972 clk_disable_unprepare(vc4_hdmi->hsm_clock); 973 clk_disable_unprepare(vc4_hdmi->pixel_clock); 974 return; 975 } 976 977 if (vc4_hdmi->variant->phy_init) 978 vc4_hdmi->variant->phy_init(vc4_hdmi, vc4_conn_state); 979 980 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 981 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 982 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT | 983 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS); 984 985 if (vc4_hdmi->variant->set_timings) 986 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode); 987 } 988 989 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder, 990 struct drm_atomic_state *state) 991 { 992 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; 993 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 994 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 995 996 if (vc4_encoder->hdmi_monitor && 997 drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_LIMITED) { 998 if (vc4_hdmi->variant->csc_setup) 999 vc4_hdmi->variant->csc_setup(vc4_hdmi, true); 1000 1001 vc4_encoder->limited_rgb_range = true; 1002 } else { 1003 if (vc4_hdmi->variant->csc_setup) 1004 vc4_hdmi->variant->csc_setup(vc4_hdmi, false); 1005 1006 vc4_encoder->limited_rgb_range = false; 1007 } 1008 1009 HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N); 1010 } 1011 1012 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder, 1013 struct drm_atomic_state *state) 1014 { 1015 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; 1016 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1017 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 1018 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 1019 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 1020 int ret; 1021 1022 HDMI_WRITE(HDMI_VID_CTL, 1023 VC4_HD_VID_CTL_ENABLE | 1024 VC4_HD_VID_CTL_UNDERFLOW_ENABLE | 1025 VC4_HD_VID_CTL_FRAME_COUNTER_RESET | 1026 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) | 1027 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW)); 1028 1029 HDMI_WRITE(HDMI_VID_CTL, 1030 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX); 1031 1032 if (vc4_encoder->hdmi_monitor) { 1033 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1034 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 1035 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 1036 1037 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1038 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000); 1039 WARN_ONCE(ret, "Timeout waiting for " 1040 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 1041 } else { 1042 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 1043 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & 1044 ~(VC4_HDMI_RAM_PACKET_ENABLE)); 1045 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1046 HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1047 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 1048 1049 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1050 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000); 1051 WARN_ONCE(ret, "Timeout waiting for " 1052 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 1053 } 1054 1055 if (vc4_encoder->hdmi_monitor) { 1056 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1057 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE)); 1058 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1059 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 1060 VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT); 1061 1062 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 1063 VC4_HDMI_RAM_PACKET_ENABLE); 1064 1065 vc4_hdmi_set_infoframes(encoder); 1066 } 1067 1068 vc4_hdmi_recenter_fifo(vc4_hdmi); 1069 vc4_hdmi_enable_scrambling(encoder); 1070 } 1071 1072 static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder) 1073 { 1074 } 1075 1076 #define WIFI_2_4GHz_CH1_MIN_FREQ 2400000000ULL 1077 #define WIFI_2_4GHz_CH1_MAX_FREQ 2422000000ULL 1078 1079 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder, 1080 struct drm_crtc_state *crtc_state, 1081 struct drm_connector_state *conn_state) 1082 { 1083 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state); 1084 struct drm_display_mode *mode = &crtc_state->adjusted_mode; 1085 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1086 unsigned long long pixel_rate = mode->clock * 1000; 1087 unsigned long long tmds_rate; 1088 1089 if (vc4_hdmi->variant->unsupported_odd_h_timings && 1090 ((mode->hdisplay % 2) || (mode->hsync_start % 2) || 1091 (mode->hsync_end % 2) || (mode->htotal % 2))) 1092 return -EINVAL; 1093 1094 /* 1095 * The 1440p@60 pixel rate is in the same range than the first 1096 * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz 1097 * bandwidth). Slightly lower the frequency to bring it out of 1098 * the WiFi range. 1099 */ 1100 tmds_rate = pixel_rate * 10; 1101 if (vc4_hdmi->disable_wifi_frequencies && 1102 (tmds_rate >= WIFI_2_4GHz_CH1_MIN_FREQ && 1103 tmds_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) { 1104 mode->clock = 238560; 1105 pixel_rate = mode->clock * 1000; 1106 } 1107 1108 if (conn_state->max_bpc == 12) { 1109 pixel_rate = pixel_rate * 150; 1110 do_div(pixel_rate, 100); 1111 } else if (conn_state->max_bpc == 10) { 1112 pixel_rate = pixel_rate * 125; 1113 do_div(pixel_rate, 100); 1114 } 1115 1116 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 1117 pixel_rate = pixel_rate * 2; 1118 1119 if (pixel_rate > vc4_hdmi->variant->max_pixel_clock) 1120 return -EINVAL; 1121 1122 if (vc4_hdmi->disable_4kp60 && (pixel_rate > HDMI_14_MAX_TMDS_CLK)) 1123 return -EINVAL; 1124 1125 vc4_state->pixel_rate = pixel_rate; 1126 1127 return 0; 1128 } 1129 1130 static enum drm_mode_status 1131 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder, 1132 const struct drm_display_mode *mode) 1133 { 1134 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1135 1136 if (vc4_hdmi->variant->unsupported_odd_h_timings && 1137 ((mode->hdisplay % 2) || (mode->hsync_start % 2) || 1138 (mode->hsync_end % 2) || (mode->htotal % 2))) 1139 return MODE_H_ILLEGAL; 1140 1141 if ((mode->clock * 1000) > vc4_hdmi->variant->max_pixel_clock) 1142 return MODE_CLOCK_HIGH; 1143 1144 if (vc4_hdmi->disable_4kp60 && vc4_hdmi_mode_needs_scrambling(mode)) 1145 return MODE_CLOCK_HIGH; 1146 1147 return MODE_OK; 1148 } 1149 1150 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = { 1151 .atomic_check = vc4_hdmi_encoder_atomic_check, 1152 .mode_valid = vc4_hdmi_encoder_mode_valid, 1153 .disable = vc4_hdmi_encoder_disable, 1154 .enable = vc4_hdmi_encoder_enable, 1155 }; 1156 1157 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask) 1158 { 1159 int i; 1160 u32 channel_map = 0; 1161 1162 for (i = 0; i < 8; i++) { 1163 if (channel_mask & BIT(i)) 1164 channel_map |= i << (3 * i); 1165 } 1166 return channel_map; 1167 } 1168 1169 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask) 1170 { 1171 int i; 1172 u32 channel_map = 0; 1173 1174 for (i = 0; i < 8; i++) { 1175 if (channel_mask & BIT(i)) 1176 channel_map |= i << (4 * i); 1177 } 1178 return channel_map; 1179 } 1180 1181 /* HDMI audio codec callbacks */ 1182 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi) 1183 { 1184 u32 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock); 1185 unsigned long n, m; 1186 1187 rational_best_approximation(hsm_clock, vc4_hdmi->audio.samplerate, 1188 VC4_HD_MAI_SMP_N_MASK >> 1189 VC4_HD_MAI_SMP_N_SHIFT, 1190 (VC4_HD_MAI_SMP_M_MASK >> 1191 VC4_HD_MAI_SMP_M_SHIFT) + 1, 1192 &n, &m); 1193 1194 HDMI_WRITE(HDMI_MAI_SMP, 1195 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) | 1196 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M)); 1197 } 1198 1199 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi) 1200 { 1201 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base; 1202 struct drm_crtc *crtc = encoder->crtc; 1203 const struct drm_display_mode *mode = &crtc->state->adjusted_mode; 1204 u32 samplerate = vc4_hdmi->audio.samplerate; 1205 u32 n, cts; 1206 u64 tmp; 1207 1208 n = 128 * samplerate / 1000; 1209 tmp = (u64)(mode->clock * 1000) * n; 1210 do_div(tmp, 128 * samplerate); 1211 cts = tmp; 1212 1213 HDMI_WRITE(HDMI_CRP_CFG, 1214 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN | 1215 VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N)); 1216 1217 /* 1218 * We could get slightly more accurate clocks in some cases by 1219 * providing a CTS_1 value. The two CTS values are alternated 1220 * between based on the period fields 1221 */ 1222 HDMI_WRITE(HDMI_CTS_0, cts); 1223 HDMI_WRITE(HDMI_CTS_1, cts); 1224 } 1225 1226 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai) 1227 { 1228 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai); 1229 1230 return snd_soc_card_get_drvdata(card); 1231 } 1232 1233 static int vc4_hdmi_audio_startup(struct snd_pcm_substream *substream, 1234 struct snd_soc_dai *dai) 1235 { 1236 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai); 1237 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base; 1238 struct drm_connector *connector = &vc4_hdmi->connector; 1239 int ret; 1240 1241 if (vc4_hdmi->audio.substream && vc4_hdmi->audio.substream != substream) 1242 return -EINVAL; 1243 1244 vc4_hdmi->audio.substream = substream; 1245 1246 /* 1247 * If the HDMI encoder hasn't probed, or the encoder is 1248 * currently in DVI mode, treat the codec dai as missing. 1249 */ 1250 if (!encoder->crtc || !(HDMI_READ(HDMI_RAM_PACKET_CONFIG) & 1251 VC4_HDMI_RAM_PACKET_ENABLE)) 1252 return -ENODEV; 1253 1254 ret = snd_pcm_hw_constraint_eld(substream->runtime, connector->eld); 1255 if (ret) 1256 return ret; 1257 1258 return 0; 1259 } 1260 1261 static int vc4_hdmi_audio_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 1262 { 1263 return 0; 1264 } 1265 1266 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi) 1267 { 1268 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base; 1269 struct device *dev = &vc4_hdmi->pdev->dev; 1270 int ret; 1271 1272 vc4_hdmi->audio.streaming = false; 1273 ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO, false); 1274 if (ret) 1275 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret); 1276 1277 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET); 1278 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF); 1279 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH); 1280 } 1281 1282 static void vc4_hdmi_audio_shutdown(struct snd_pcm_substream *substream, 1283 struct snd_soc_dai *dai) 1284 { 1285 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai); 1286 1287 if (substream != vc4_hdmi->audio.substream) 1288 return; 1289 1290 vc4_hdmi_audio_reset(vc4_hdmi); 1291 1292 vc4_hdmi->audio.substream = NULL; 1293 } 1294 1295 /* HDMI audio codec callbacks */ 1296 static int vc4_hdmi_audio_hw_params(struct snd_pcm_substream *substream, 1297 struct snd_pcm_hw_params *params, 1298 struct snd_soc_dai *dai) 1299 { 1300 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai); 1301 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base; 1302 struct device *dev = &vc4_hdmi->pdev->dev; 1303 u32 audio_packet_config, channel_mask; 1304 u32 channel_map; 1305 1306 if (substream != vc4_hdmi->audio.substream) 1307 return -EINVAL; 1308 1309 dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__, 1310 params_rate(params), params_width(params), 1311 params_channels(params)); 1312 1313 vc4_hdmi->audio.channels = params_channels(params); 1314 vc4_hdmi->audio.samplerate = params_rate(params); 1315 1316 HDMI_WRITE(HDMI_MAI_CTL, 1317 VC4_HD_MAI_CTL_RESET | 1318 VC4_HD_MAI_CTL_FLUSH | 1319 VC4_HD_MAI_CTL_DLATE | 1320 VC4_HD_MAI_CTL_ERRORE | 1321 VC4_HD_MAI_CTL_ERRORF); 1322 1323 vc4_hdmi_audio_set_mai_clock(vc4_hdmi); 1324 1325 /* The B frame identifier should match the value used by alsa-lib (8) */ 1326 audio_packet_config = 1327 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT | 1328 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS | 1329 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER); 1330 1331 channel_mask = GENMASK(vc4_hdmi->audio.channels - 1, 0); 1332 audio_packet_config |= VC4_SET_FIELD(channel_mask, 1333 VC4_HDMI_AUDIO_PACKET_CEA_MASK); 1334 1335 /* Set the MAI threshold. This logic mimics the firmware's. */ 1336 if (vc4_hdmi->audio.samplerate > 96000) { 1337 HDMI_WRITE(HDMI_MAI_THR, 1338 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQHIGH) | 1339 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW)); 1340 } else if (vc4_hdmi->audio.samplerate > 48000) { 1341 HDMI_WRITE(HDMI_MAI_THR, 1342 VC4_SET_FIELD(0x14, VC4_HD_MAI_THR_DREQHIGH) | 1343 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW)); 1344 } else { 1345 HDMI_WRITE(HDMI_MAI_THR, 1346 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) | 1347 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) | 1348 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQHIGH) | 1349 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQLOW)); 1350 } 1351 1352 HDMI_WRITE(HDMI_MAI_CONFIG, 1353 VC4_HDMI_MAI_CONFIG_BIT_REVERSE | 1354 VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK)); 1355 1356 channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask); 1357 HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map); 1358 HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config); 1359 vc4_hdmi_set_n_cts(vc4_hdmi); 1360 1361 vc4_hdmi_set_audio_infoframe(encoder); 1362 1363 return 0; 1364 } 1365 1366 static int vc4_hdmi_audio_trigger(struct snd_pcm_substream *substream, int cmd, 1367 struct snd_soc_dai *dai) 1368 { 1369 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai); 1370 1371 switch (cmd) { 1372 case SNDRV_PCM_TRIGGER_START: 1373 vc4_hdmi->audio.streaming = true; 1374 1375 if (vc4_hdmi->variant->phy_rng_enable) 1376 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi); 1377 1378 HDMI_WRITE(HDMI_MAI_CTL, 1379 VC4_SET_FIELD(vc4_hdmi->audio.channels, 1380 VC4_HD_MAI_CTL_CHNUM) | 1381 VC4_HD_MAI_CTL_ENABLE); 1382 break; 1383 case SNDRV_PCM_TRIGGER_STOP: 1384 HDMI_WRITE(HDMI_MAI_CTL, 1385 VC4_HD_MAI_CTL_DLATE | 1386 VC4_HD_MAI_CTL_ERRORE | 1387 VC4_HD_MAI_CTL_ERRORF); 1388 1389 if (vc4_hdmi->variant->phy_rng_disable) 1390 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi); 1391 1392 vc4_hdmi->audio.streaming = false; 1393 1394 break; 1395 default: 1396 break; 1397 } 1398 1399 return 0; 1400 } 1401 1402 static inline struct vc4_hdmi * 1403 snd_component_to_hdmi(struct snd_soc_component *component) 1404 { 1405 struct snd_soc_card *card = snd_soc_component_get_drvdata(component); 1406 1407 return snd_soc_card_get_drvdata(card); 1408 } 1409 1410 static int vc4_hdmi_audio_eld_ctl_info(struct snd_kcontrol *kcontrol, 1411 struct snd_ctl_elem_info *uinfo) 1412 { 1413 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1414 struct vc4_hdmi *vc4_hdmi = snd_component_to_hdmi(component); 1415 struct drm_connector *connector = &vc4_hdmi->connector; 1416 1417 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 1418 uinfo->count = sizeof(connector->eld); 1419 1420 return 0; 1421 } 1422 1423 static int vc4_hdmi_audio_eld_ctl_get(struct snd_kcontrol *kcontrol, 1424 struct snd_ctl_elem_value *ucontrol) 1425 { 1426 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1427 struct vc4_hdmi *vc4_hdmi = snd_component_to_hdmi(component); 1428 struct drm_connector *connector = &vc4_hdmi->connector; 1429 1430 memcpy(ucontrol->value.bytes.data, connector->eld, 1431 sizeof(connector->eld)); 1432 1433 return 0; 1434 } 1435 1436 static const struct snd_kcontrol_new vc4_hdmi_audio_controls[] = { 1437 { 1438 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1439 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1440 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1441 .name = "ELD", 1442 .info = vc4_hdmi_audio_eld_ctl_info, 1443 .get = vc4_hdmi_audio_eld_ctl_get, 1444 }, 1445 }; 1446 1447 static const struct snd_soc_dapm_widget vc4_hdmi_audio_widgets[] = { 1448 SND_SOC_DAPM_OUTPUT("TX"), 1449 }; 1450 1451 static const struct snd_soc_dapm_route vc4_hdmi_audio_routes[] = { 1452 { "TX", NULL, "Playback" }, 1453 }; 1454 1455 static const struct snd_soc_component_driver vc4_hdmi_audio_component_drv = { 1456 .name = "vc4-hdmi-codec-dai-component", 1457 .controls = vc4_hdmi_audio_controls, 1458 .num_controls = ARRAY_SIZE(vc4_hdmi_audio_controls), 1459 .dapm_widgets = vc4_hdmi_audio_widgets, 1460 .num_dapm_widgets = ARRAY_SIZE(vc4_hdmi_audio_widgets), 1461 .dapm_routes = vc4_hdmi_audio_routes, 1462 .num_dapm_routes = ARRAY_SIZE(vc4_hdmi_audio_routes), 1463 .idle_bias_on = 1, 1464 .use_pmdown_time = 1, 1465 .endianness = 1, 1466 .non_legacy_dai_naming = 1, 1467 }; 1468 1469 static const struct snd_soc_dai_ops vc4_hdmi_audio_dai_ops = { 1470 .startup = vc4_hdmi_audio_startup, 1471 .shutdown = vc4_hdmi_audio_shutdown, 1472 .hw_params = vc4_hdmi_audio_hw_params, 1473 .set_fmt = vc4_hdmi_audio_set_fmt, 1474 .trigger = vc4_hdmi_audio_trigger, 1475 }; 1476 1477 static struct snd_soc_dai_driver vc4_hdmi_audio_codec_dai_drv = { 1478 .name = "vc4-hdmi-hifi", 1479 .playback = { 1480 .stream_name = "Playback", 1481 .channels_min = 2, 1482 .channels_max = 8, 1483 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 1484 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 1485 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 1486 SNDRV_PCM_RATE_192000, 1487 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 1488 }, 1489 }; 1490 1491 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = { 1492 .name = "vc4-hdmi-cpu-dai-component", 1493 }; 1494 1495 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai) 1496 { 1497 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai); 1498 1499 snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL); 1500 1501 return 0; 1502 } 1503 1504 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = { 1505 .name = "vc4-hdmi-cpu-dai", 1506 .probe = vc4_hdmi_audio_cpu_dai_probe, 1507 .playback = { 1508 .stream_name = "Playback", 1509 .channels_min = 1, 1510 .channels_max = 8, 1511 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 1512 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 1513 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 1514 SNDRV_PCM_RATE_192000, 1515 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 1516 }, 1517 .ops = &vc4_hdmi_audio_dai_ops, 1518 }; 1519 1520 static const struct snd_dmaengine_pcm_config pcm_conf = { 1521 .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx", 1522 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 1523 }; 1524 1525 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi) 1526 { 1527 const struct vc4_hdmi_register *mai_data = 1528 &vc4_hdmi->variant->registers[HDMI_MAI_DATA]; 1529 struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link; 1530 struct snd_soc_card *card = &vc4_hdmi->audio.card; 1531 struct device *dev = &vc4_hdmi->pdev->dev; 1532 const __be32 *addr; 1533 int index; 1534 int ret; 1535 1536 if (!of_find_property(dev->of_node, "dmas", NULL)) { 1537 dev_warn(dev, 1538 "'dmas' DT property is missing, no HDMI audio\n"); 1539 return 0; 1540 } 1541 1542 if (mai_data->reg != VC4_HD) { 1543 WARN_ONCE(true, "MAI isn't in the HD block\n"); 1544 return -EINVAL; 1545 } 1546 1547 /* 1548 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve 1549 * the bus address specified in the DT, because the physical address 1550 * (the one returned by platform_get_resource()) is not appropriate 1551 * for DMA transfers. 1552 * This VC/MMU should probably be exposed to avoid this kind of hacks. 1553 */ 1554 index = of_property_match_string(dev->of_node, "reg-names", "hd"); 1555 /* Before BCM2711, we don't have a named register range */ 1556 if (index < 0) 1557 index = 1; 1558 1559 addr = of_get_address(dev->of_node, index, NULL, NULL); 1560 1561 vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset; 1562 vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1563 vc4_hdmi->audio.dma_data.maxburst = 2; 1564 1565 ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0); 1566 if (ret) { 1567 dev_err(dev, "Could not register PCM component: %d\n", ret); 1568 return ret; 1569 } 1570 1571 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp, 1572 &vc4_hdmi_audio_cpu_dai_drv, 1); 1573 if (ret) { 1574 dev_err(dev, "Could not register CPU DAI: %d\n", ret); 1575 return ret; 1576 } 1577 1578 /* register component and codec dai */ 1579 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_component_drv, 1580 &vc4_hdmi_audio_codec_dai_drv, 1); 1581 if (ret) { 1582 dev_err(dev, "Could not register component: %d\n", ret); 1583 return ret; 1584 } 1585 1586 dai_link->cpus = &vc4_hdmi->audio.cpu; 1587 dai_link->codecs = &vc4_hdmi->audio.codec; 1588 dai_link->platforms = &vc4_hdmi->audio.platform; 1589 1590 dai_link->num_cpus = 1; 1591 dai_link->num_codecs = 1; 1592 dai_link->num_platforms = 1; 1593 1594 dai_link->name = "MAI"; 1595 dai_link->stream_name = "MAI PCM"; 1596 dai_link->codecs->dai_name = vc4_hdmi_audio_codec_dai_drv.name; 1597 dai_link->cpus->dai_name = dev_name(dev); 1598 dai_link->codecs->name = dev_name(dev); 1599 dai_link->platforms->name = dev_name(dev); 1600 1601 card->dai_link = dai_link; 1602 card->num_links = 1; 1603 card->name = vc4_hdmi->variant->card_name; 1604 card->driver_name = "vc4-hdmi"; 1605 card->dev = dev; 1606 card->owner = THIS_MODULE; 1607 1608 /* 1609 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and 1610 * stores a pointer to the snd card object in dev->driver_data. This 1611 * means we cannot use it for something else. The hdmi back-pointer is 1612 * now stored in card->drvdata and should be retrieved with 1613 * snd_soc_card_get_drvdata() if needed. 1614 */ 1615 snd_soc_card_set_drvdata(card, vc4_hdmi); 1616 ret = devm_snd_soc_register_card(dev, card); 1617 if (ret) 1618 dev_err(dev, "Could not register sound card: %d\n", ret); 1619 1620 return ret; 1621 1622 } 1623 1624 #ifdef CONFIG_DRM_VC4_HDMI_CEC 1625 static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv) 1626 { 1627 struct vc4_hdmi *vc4_hdmi = priv; 1628 1629 if (vc4_hdmi->cec_rx_msg.len) 1630 cec_received_msg(vc4_hdmi->cec_adap, 1631 &vc4_hdmi->cec_rx_msg); 1632 1633 return IRQ_HANDLED; 1634 } 1635 1636 static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv) 1637 { 1638 struct vc4_hdmi *vc4_hdmi = priv; 1639 1640 if (vc4_hdmi->cec_tx_ok) { 1641 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK, 1642 0, 0, 0, 0); 1643 } else { 1644 /* 1645 * This CEC implementation makes 1 retry, so if we 1646 * get a NACK, then that means it made 2 attempts. 1647 */ 1648 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK, 1649 0, 2, 0, 0); 1650 } 1651 return IRQ_HANDLED; 1652 } 1653 1654 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv) 1655 { 1656 struct vc4_hdmi *vc4_hdmi = priv; 1657 irqreturn_t ret; 1658 1659 if (vc4_hdmi->cec_irq_was_rx) 1660 ret = vc4_cec_irq_handler_rx_thread(irq, priv); 1661 else 1662 ret = vc4_cec_irq_handler_tx_thread(irq, priv); 1663 1664 return ret; 1665 } 1666 1667 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1) 1668 { 1669 struct drm_device *dev = vc4_hdmi->connector.dev; 1670 struct cec_msg *msg = &vc4_hdmi->cec_rx_msg; 1671 unsigned int i; 1672 1673 msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >> 1674 VC4_HDMI_CEC_REC_WRD_CNT_SHIFT); 1675 1676 if (msg->len > 16) { 1677 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len); 1678 return; 1679 } 1680 1681 for (i = 0; i < msg->len; i += 4) { 1682 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2)); 1683 1684 msg->msg[i] = val & 0xff; 1685 msg->msg[i + 1] = (val >> 8) & 0xff; 1686 msg->msg[i + 2] = (val >> 16) & 0xff; 1687 msg->msg[i + 3] = (val >> 24) & 0xff; 1688 } 1689 } 1690 1691 static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv) 1692 { 1693 struct vc4_hdmi *vc4_hdmi = priv; 1694 u32 cntrl1; 1695 1696 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1); 1697 vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD; 1698 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 1699 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 1700 1701 return IRQ_WAKE_THREAD; 1702 } 1703 1704 static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv) 1705 { 1706 struct vc4_hdmi *vc4_hdmi = priv; 1707 u32 cntrl1; 1708 1709 vc4_hdmi->cec_rx_msg.len = 0; 1710 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1); 1711 vc4_cec_read_msg(vc4_hdmi, cntrl1); 1712 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 1713 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 1714 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 1715 1716 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 1717 1718 return IRQ_WAKE_THREAD; 1719 } 1720 1721 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv) 1722 { 1723 struct vc4_hdmi *vc4_hdmi = priv; 1724 u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS); 1725 irqreturn_t ret; 1726 u32 cntrl5; 1727 1728 if (!(stat & VC4_HDMI_CPU_CEC)) 1729 return IRQ_NONE; 1730 1731 cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5); 1732 vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT; 1733 if (vc4_hdmi->cec_irq_was_rx) 1734 ret = vc4_cec_irq_handler_rx_bare(irq, priv); 1735 else 1736 ret = vc4_cec_irq_handler_tx_bare(irq, priv); 1737 1738 HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC); 1739 return ret; 1740 } 1741 1742 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable) 1743 { 1744 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 1745 /* clock period in microseconds */ 1746 const u32 usecs = 1000000 / CEC_CLOCK_FREQ; 1747 u32 val = HDMI_READ(HDMI_CEC_CNTRL_5); 1748 1749 val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET | 1750 VC4_HDMI_CEC_CNT_TO_4700_US_MASK | 1751 VC4_HDMI_CEC_CNT_TO_4500_US_MASK); 1752 val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) | 1753 ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT); 1754 1755 if (enable) { 1756 HDMI_WRITE(HDMI_CEC_CNTRL_5, val | 1757 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 1758 HDMI_WRITE(HDMI_CEC_CNTRL_5, val); 1759 HDMI_WRITE(HDMI_CEC_CNTRL_2, 1760 ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) | 1761 ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) | 1762 ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) | 1763 ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) | 1764 ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT)); 1765 HDMI_WRITE(HDMI_CEC_CNTRL_3, 1766 ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) | 1767 ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) | 1768 ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) | 1769 ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT)); 1770 HDMI_WRITE(HDMI_CEC_CNTRL_4, 1771 ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) | 1772 ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) | 1773 ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) | 1774 ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT)); 1775 1776 if (!vc4_hdmi->variant->external_irq_controller) 1777 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC); 1778 } else { 1779 if (!vc4_hdmi->variant->external_irq_controller) 1780 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC); 1781 HDMI_WRITE(HDMI_CEC_CNTRL_5, val | 1782 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 1783 } 1784 return 0; 1785 } 1786 1787 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr) 1788 { 1789 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 1790 1791 HDMI_WRITE(HDMI_CEC_CNTRL_1, 1792 (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) | 1793 (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT); 1794 return 0; 1795 } 1796 1797 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts, 1798 u32 signal_free_time, struct cec_msg *msg) 1799 { 1800 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 1801 struct drm_device *dev = vc4_hdmi->connector.dev; 1802 u32 val; 1803 unsigned int i; 1804 1805 if (msg->len > 16) { 1806 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len); 1807 return -ENOMEM; 1808 } 1809 1810 for (i = 0; i < msg->len; i += 4) 1811 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2), 1812 (msg->msg[i]) | 1813 (msg->msg[i + 1] << 8) | 1814 (msg->msg[i + 2] << 16) | 1815 (msg->msg[i + 3] << 24)); 1816 1817 val = HDMI_READ(HDMI_CEC_CNTRL_1); 1818 val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 1819 HDMI_WRITE(HDMI_CEC_CNTRL_1, val); 1820 val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK; 1821 val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT; 1822 val |= VC4_HDMI_CEC_START_XMIT_BEGIN; 1823 1824 HDMI_WRITE(HDMI_CEC_CNTRL_1, val); 1825 return 0; 1826 } 1827 1828 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = { 1829 .adap_enable = vc4_hdmi_cec_adap_enable, 1830 .adap_log_addr = vc4_hdmi_cec_adap_log_addr, 1831 .adap_transmit = vc4_hdmi_cec_adap_transmit, 1832 }; 1833 1834 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi) 1835 { 1836 struct cec_connector_info conn_info; 1837 struct platform_device *pdev = vc4_hdmi->pdev; 1838 struct device *dev = &pdev->dev; 1839 u32 value; 1840 int ret; 1841 1842 if (!of_find_property(dev->of_node, "interrupts", NULL)) { 1843 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n"); 1844 return 0; 1845 } 1846 1847 vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops, 1848 vc4_hdmi, "vc4", 1849 CEC_CAP_DEFAULTS | 1850 CEC_CAP_CONNECTOR_INFO, 1); 1851 ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap); 1852 if (ret < 0) 1853 return ret; 1854 1855 cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector); 1856 cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info); 1857 1858 value = HDMI_READ(HDMI_CEC_CNTRL_1); 1859 /* Set the logical address to Unregistered */ 1860 value |= VC4_HDMI_CEC_ADDR_MASK; 1861 HDMI_WRITE(HDMI_CEC_CNTRL_1, value); 1862 1863 vc4_hdmi_cec_update_clk_div(vc4_hdmi); 1864 1865 if (vc4_hdmi->variant->external_irq_controller) { 1866 ret = devm_request_threaded_irq(&pdev->dev, 1867 platform_get_irq_byname(pdev, "cec-rx"), 1868 vc4_cec_irq_handler_rx_bare, 1869 vc4_cec_irq_handler_rx_thread, 0, 1870 "vc4 hdmi cec rx", vc4_hdmi); 1871 if (ret) 1872 goto err_delete_cec_adap; 1873 1874 ret = devm_request_threaded_irq(&pdev->dev, 1875 platform_get_irq_byname(pdev, "cec-tx"), 1876 vc4_cec_irq_handler_tx_bare, 1877 vc4_cec_irq_handler_tx_thread, 0, 1878 "vc4 hdmi cec tx", vc4_hdmi); 1879 if (ret) 1880 goto err_delete_cec_adap; 1881 } else { 1882 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff); 1883 1884 ret = devm_request_threaded_irq(&pdev->dev, platform_get_irq(pdev, 0), 1885 vc4_cec_irq_handler, 1886 vc4_cec_irq_handler_thread, 0, 1887 "vc4 hdmi cec", vc4_hdmi); 1888 if (ret) 1889 goto err_delete_cec_adap; 1890 } 1891 1892 ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev); 1893 if (ret < 0) 1894 goto err_delete_cec_adap; 1895 1896 return 0; 1897 1898 err_delete_cec_adap: 1899 cec_delete_adapter(vc4_hdmi->cec_adap); 1900 1901 return ret; 1902 } 1903 1904 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi) 1905 { 1906 cec_unregister_adapter(vc4_hdmi->cec_adap); 1907 } 1908 #else 1909 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi) 1910 { 1911 return 0; 1912 } 1913 1914 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi) {}; 1915 1916 #endif 1917 1918 static int vc4_hdmi_build_regset(struct vc4_hdmi *vc4_hdmi, 1919 struct debugfs_regset32 *regset, 1920 enum vc4_hdmi_regs reg) 1921 { 1922 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant; 1923 struct debugfs_reg32 *regs, *new_regs; 1924 unsigned int count = 0; 1925 unsigned int i; 1926 1927 regs = kcalloc(variant->num_registers, sizeof(*regs), 1928 GFP_KERNEL); 1929 if (!regs) 1930 return -ENOMEM; 1931 1932 for (i = 0; i < variant->num_registers; i++) { 1933 const struct vc4_hdmi_register *field = &variant->registers[i]; 1934 1935 if (field->reg != reg) 1936 continue; 1937 1938 regs[count].name = field->name; 1939 regs[count].offset = field->offset; 1940 count++; 1941 } 1942 1943 new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL); 1944 if (!new_regs) 1945 return -ENOMEM; 1946 1947 regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg); 1948 regset->regs = new_regs; 1949 regset->nregs = count; 1950 1951 return 0; 1952 } 1953 1954 static int vc4_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi) 1955 { 1956 struct platform_device *pdev = vc4_hdmi->pdev; 1957 struct device *dev = &pdev->dev; 1958 int ret; 1959 1960 vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0); 1961 if (IS_ERR(vc4_hdmi->hdmicore_regs)) 1962 return PTR_ERR(vc4_hdmi->hdmicore_regs); 1963 1964 vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1); 1965 if (IS_ERR(vc4_hdmi->hd_regs)) 1966 return PTR_ERR(vc4_hdmi->hd_regs); 1967 1968 ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD); 1969 if (ret) 1970 return ret; 1971 1972 ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI); 1973 if (ret) 1974 return ret; 1975 1976 vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel"); 1977 if (IS_ERR(vc4_hdmi->pixel_clock)) { 1978 ret = PTR_ERR(vc4_hdmi->pixel_clock); 1979 if (ret != -EPROBE_DEFER) 1980 DRM_ERROR("Failed to get pixel clock\n"); 1981 return ret; 1982 } 1983 1984 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); 1985 if (IS_ERR(vc4_hdmi->hsm_clock)) { 1986 DRM_ERROR("Failed to get HDMI state machine clock\n"); 1987 return PTR_ERR(vc4_hdmi->hsm_clock); 1988 } 1989 vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock; 1990 vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock; 1991 1992 return 0; 1993 } 1994 1995 static int vc5_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi) 1996 { 1997 struct platform_device *pdev = vc4_hdmi->pdev; 1998 struct device *dev = &pdev->dev; 1999 struct resource *res; 2000 2001 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi"); 2002 if (!res) 2003 return -ENODEV; 2004 2005 vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start, 2006 resource_size(res)); 2007 if (!vc4_hdmi->hdmicore_regs) 2008 return -ENOMEM; 2009 2010 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd"); 2011 if (!res) 2012 return -ENODEV; 2013 2014 vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res)); 2015 if (!vc4_hdmi->hd_regs) 2016 return -ENOMEM; 2017 2018 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec"); 2019 if (!res) 2020 return -ENODEV; 2021 2022 vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res)); 2023 if (!vc4_hdmi->cec_regs) 2024 return -ENOMEM; 2025 2026 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc"); 2027 if (!res) 2028 return -ENODEV; 2029 2030 vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res)); 2031 if (!vc4_hdmi->csc_regs) 2032 return -ENOMEM; 2033 2034 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp"); 2035 if (!res) 2036 return -ENODEV; 2037 2038 vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res)); 2039 if (!vc4_hdmi->dvp_regs) 2040 return -ENOMEM; 2041 2042 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy"); 2043 if (!res) 2044 return -ENODEV; 2045 2046 vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res)); 2047 if (!vc4_hdmi->phy_regs) 2048 return -ENOMEM; 2049 2050 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet"); 2051 if (!res) 2052 return -ENODEV; 2053 2054 vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res)); 2055 if (!vc4_hdmi->ram_regs) 2056 return -ENOMEM; 2057 2058 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm"); 2059 if (!res) 2060 return -ENODEV; 2061 2062 vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res)); 2063 if (!vc4_hdmi->rm_regs) 2064 return -ENOMEM; 2065 2066 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); 2067 if (IS_ERR(vc4_hdmi->hsm_clock)) { 2068 DRM_ERROR("Failed to get HDMI state machine clock\n"); 2069 return PTR_ERR(vc4_hdmi->hsm_clock); 2070 } 2071 2072 vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb"); 2073 if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) { 2074 DRM_ERROR("Failed to get pixel bvb clock\n"); 2075 return PTR_ERR(vc4_hdmi->pixel_bvb_clock); 2076 } 2077 2078 vc4_hdmi->audio_clock = devm_clk_get(dev, "audio"); 2079 if (IS_ERR(vc4_hdmi->audio_clock)) { 2080 DRM_ERROR("Failed to get audio clock\n"); 2081 return PTR_ERR(vc4_hdmi->audio_clock); 2082 } 2083 2084 vc4_hdmi->cec_clock = devm_clk_get(dev, "cec"); 2085 if (IS_ERR(vc4_hdmi->cec_clock)) { 2086 DRM_ERROR("Failed to get CEC clock\n"); 2087 return PTR_ERR(vc4_hdmi->cec_clock); 2088 } 2089 2090 vc4_hdmi->reset = devm_reset_control_get(dev, NULL); 2091 if (IS_ERR(vc4_hdmi->reset)) { 2092 DRM_ERROR("Failed to get HDMI reset line\n"); 2093 return PTR_ERR(vc4_hdmi->reset); 2094 } 2095 2096 return 0; 2097 } 2098 2099 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data) 2100 { 2101 const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev); 2102 struct platform_device *pdev = to_platform_device(dev); 2103 struct drm_device *drm = dev_get_drvdata(master); 2104 struct vc4_hdmi *vc4_hdmi; 2105 struct drm_encoder *encoder; 2106 struct device_node *ddc_node; 2107 int ret; 2108 2109 vc4_hdmi = devm_kzalloc(dev, sizeof(*vc4_hdmi), GFP_KERNEL); 2110 if (!vc4_hdmi) 2111 return -ENOMEM; 2112 INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq); 2113 2114 dev_set_drvdata(dev, vc4_hdmi); 2115 encoder = &vc4_hdmi->encoder.base.base; 2116 vc4_hdmi->encoder.base.type = variant->encoder_type; 2117 vc4_hdmi->encoder.base.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure; 2118 vc4_hdmi->encoder.base.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable; 2119 vc4_hdmi->encoder.base.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable; 2120 vc4_hdmi->encoder.base.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable; 2121 vc4_hdmi->encoder.base.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown; 2122 vc4_hdmi->pdev = pdev; 2123 vc4_hdmi->variant = variant; 2124 2125 ret = variant->init_resources(vc4_hdmi); 2126 if (ret) 2127 return ret; 2128 2129 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0); 2130 if (!ddc_node) { 2131 DRM_ERROR("Failed to find ddc node in device tree\n"); 2132 return -ENODEV; 2133 } 2134 2135 vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node); 2136 of_node_put(ddc_node); 2137 if (!vc4_hdmi->ddc) { 2138 DRM_DEBUG("Failed to get ddc i2c adapter by node\n"); 2139 return -EPROBE_DEFER; 2140 } 2141 2142 /* Only use the GPIO HPD pin if present in the DT, otherwise 2143 * we'll use the HDMI core's register. 2144 */ 2145 vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN); 2146 if (IS_ERR(vc4_hdmi->hpd_gpio)) { 2147 ret = PTR_ERR(vc4_hdmi->hpd_gpio); 2148 goto err_put_ddc; 2149 } 2150 2151 vc4_hdmi->disable_wifi_frequencies = 2152 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence"); 2153 2154 if (variant->max_pixel_clock == 600000000) { 2155 struct vc4_dev *vc4 = to_vc4_dev(drm); 2156 long max_rate = clk_round_rate(vc4->hvs->core_clk, 550000000); 2157 2158 if (max_rate < 550000000) 2159 vc4_hdmi->disable_4kp60 = true; 2160 } 2161 2162 if (vc4_hdmi->variant->reset) 2163 vc4_hdmi->variant->reset(vc4_hdmi); 2164 2165 if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") || 2166 of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1")) && 2167 HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) { 2168 clk_prepare_enable(vc4_hdmi->pixel_clock); 2169 clk_prepare_enable(vc4_hdmi->hsm_clock); 2170 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock); 2171 } 2172 2173 pm_runtime_enable(dev); 2174 2175 drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS); 2176 drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs); 2177 2178 ret = vc4_hdmi_connector_init(drm, vc4_hdmi); 2179 if (ret) 2180 goto err_destroy_encoder; 2181 2182 ret = vc4_hdmi_cec_init(vc4_hdmi); 2183 if (ret) 2184 goto err_destroy_conn; 2185 2186 ret = vc4_hdmi_audio_init(vc4_hdmi); 2187 if (ret) 2188 goto err_free_cec; 2189 2190 vc4_debugfs_add_file(drm, variant->debugfs_name, 2191 vc4_hdmi_debugfs_regs, 2192 vc4_hdmi); 2193 2194 return 0; 2195 2196 err_free_cec: 2197 vc4_hdmi_cec_exit(vc4_hdmi); 2198 err_destroy_conn: 2199 vc4_hdmi_connector_destroy(&vc4_hdmi->connector); 2200 err_destroy_encoder: 2201 drm_encoder_cleanup(encoder); 2202 pm_runtime_disable(dev); 2203 err_put_ddc: 2204 put_device(&vc4_hdmi->ddc->dev); 2205 2206 return ret; 2207 } 2208 2209 static void vc4_hdmi_unbind(struct device *dev, struct device *master, 2210 void *data) 2211 { 2212 struct vc4_hdmi *vc4_hdmi; 2213 2214 /* 2215 * ASoC makes it a bit hard to retrieve a pointer to the 2216 * vc4_hdmi structure. Registering the card will overwrite our 2217 * device drvdata with a pointer to the snd_soc_card structure, 2218 * which can then be used to retrieve whatever drvdata we want 2219 * to associate. 2220 * 2221 * However, that doesn't fly in the case where we wouldn't 2222 * register an ASoC card (because of an old DT that is missing 2223 * the dmas properties for example), then the card isn't 2224 * registered and the device drvdata wouldn't be set. 2225 * 2226 * We can deal with both cases by making sure a snd_soc_card 2227 * pointer and a vc4_hdmi structure are pointing to the same 2228 * memory address, so we can treat them indistinctly without any 2229 * issue. 2230 */ 2231 BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0); 2232 BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0); 2233 vc4_hdmi = dev_get_drvdata(dev); 2234 2235 kfree(vc4_hdmi->hdmi_regset.regs); 2236 kfree(vc4_hdmi->hd_regset.regs); 2237 2238 vc4_hdmi_cec_exit(vc4_hdmi); 2239 vc4_hdmi_connector_destroy(&vc4_hdmi->connector); 2240 drm_encoder_cleanup(&vc4_hdmi->encoder.base.base); 2241 2242 pm_runtime_disable(dev); 2243 2244 put_device(&vc4_hdmi->ddc->dev); 2245 } 2246 2247 static const struct component_ops vc4_hdmi_ops = { 2248 .bind = vc4_hdmi_bind, 2249 .unbind = vc4_hdmi_unbind, 2250 }; 2251 2252 static int vc4_hdmi_dev_probe(struct platform_device *pdev) 2253 { 2254 return component_add(&pdev->dev, &vc4_hdmi_ops); 2255 } 2256 2257 static int vc4_hdmi_dev_remove(struct platform_device *pdev) 2258 { 2259 component_del(&pdev->dev, &vc4_hdmi_ops); 2260 return 0; 2261 } 2262 2263 static const struct vc4_hdmi_variant bcm2835_variant = { 2264 .encoder_type = VC4_ENCODER_TYPE_HDMI0, 2265 .debugfs_name = "hdmi_regs", 2266 .card_name = "vc4-hdmi", 2267 .max_pixel_clock = 162000000, 2268 .registers = vc4_hdmi_fields, 2269 .num_registers = ARRAY_SIZE(vc4_hdmi_fields), 2270 2271 .init_resources = vc4_hdmi_init_resources, 2272 .csc_setup = vc4_hdmi_csc_setup, 2273 .reset = vc4_hdmi_reset, 2274 .set_timings = vc4_hdmi_set_timings, 2275 .phy_init = vc4_hdmi_phy_init, 2276 .phy_disable = vc4_hdmi_phy_disable, 2277 .phy_rng_enable = vc4_hdmi_phy_rng_enable, 2278 .phy_rng_disable = vc4_hdmi_phy_rng_disable, 2279 .channel_map = vc4_hdmi_channel_map, 2280 .supports_hdr = false, 2281 }; 2282 2283 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = { 2284 .encoder_type = VC4_ENCODER_TYPE_HDMI0, 2285 .debugfs_name = "hdmi0_regs", 2286 .card_name = "vc4-hdmi-0", 2287 .max_pixel_clock = HDMI_14_MAX_TMDS_CLK, 2288 .registers = vc5_hdmi_hdmi0_fields, 2289 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi0_fields), 2290 .phy_lane_mapping = { 2291 PHY_LANE_0, 2292 PHY_LANE_1, 2293 PHY_LANE_2, 2294 PHY_LANE_CK, 2295 }, 2296 .unsupported_odd_h_timings = true, 2297 .external_irq_controller = true, 2298 2299 .init_resources = vc5_hdmi_init_resources, 2300 .csc_setup = vc5_hdmi_csc_setup, 2301 .reset = vc5_hdmi_reset, 2302 .set_timings = vc5_hdmi_set_timings, 2303 .phy_init = vc5_hdmi_phy_init, 2304 .phy_disable = vc5_hdmi_phy_disable, 2305 .phy_rng_enable = vc5_hdmi_phy_rng_enable, 2306 .phy_rng_disable = vc5_hdmi_phy_rng_disable, 2307 .channel_map = vc5_hdmi_channel_map, 2308 .supports_hdr = true, 2309 }; 2310 2311 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = { 2312 .encoder_type = VC4_ENCODER_TYPE_HDMI1, 2313 .debugfs_name = "hdmi1_regs", 2314 .card_name = "vc4-hdmi-1", 2315 .max_pixel_clock = HDMI_14_MAX_TMDS_CLK, 2316 .registers = vc5_hdmi_hdmi1_fields, 2317 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi1_fields), 2318 .phy_lane_mapping = { 2319 PHY_LANE_1, 2320 PHY_LANE_0, 2321 PHY_LANE_CK, 2322 PHY_LANE_2, 2323 }, 2324 .unsupported_odd_h_timings = true, 2325 .external_irq_controller = true, 2326 2327 .init_resources = vc5_hdmi_init_resources, 2328 .csc_setup = vc5_hdmi_csc_setup, 2329 .reset = vc5_hdmi_reset, 2330 .set_timings = vc5_hdmi_set_timings, 2331 .phy_init = vc5_hdmi_phy_init, 2332 .phy_disable = vc5_hdmi_phy_disable, 2333 .phy_rng_enable = vc5_hdmi_phy_rng_enable, 2334 .phy_rng_disable = vc5_hdmi_phy_rng_disable, 2335 .channel_map = vc5_hdmi_channel_map, 2336 .supports_hdr = true, 2337 }; 2338 2339 static const struct of_device_id vc4_hdmi_dt_match[] = { 2340 { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant }, 2341 { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant }, 2342 { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant }, 2343 {} 2344 }; 2345 2346 struct platform_driver vc4_hdmi_driver = { 2347 .probe = vc4_hdmi_dev_probe, 2348 .remove = vc4_hdmi_dev_remove, 2349 .driver = { 2350 .name = "vc4_hdmi", 2351 .of_match_table = vc4_hdmi_dt_match, 2352 }, 2353 }; 2354