1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 Broadcom 4 * Copyright (c) 2014 The Linux Foundation. All rights reserved. 5 * Copyright (C) 2013 Red Hat 6 * Author: Rob Clark <robdclark@gmail.com> 7 */ 8 9 /** 10 * DOC: VC4 Falcon HDMI module 11 * 12 * The HDMI core has a state machine and a PHY. On BCM2835, most of 13 * the unit operates off of the HSM clock from CPRMAN. It also 14 * internally uses the PLLH_PIX clock for the PHY. 15 * 16 * HDMI infoframes are kept within a small packet ram, where each 17 * packet can be individually enabled for including in a frame. 18 * 19 * HDMI audio is implemented entirely within the HDMI IP block. A 20 * register in the HDMI encoder takes SPDIF frames from the DMA engine 21 * and transfers them over an internal MAI (multi-channel audio 22 * interconnect) bus to the encoder side for insertion into the video 23 * blank regions. 24 * 25 * The driver's HDMI encoder does not yet support power management. 26 * The HDMI encoder's power domain and the HSM/pixel clocks are kept 27 * continuously running, and only the HDMI logic and packet ram are 28 * powered off/on at disable/enable time. 29 * 30 * The driver does not yet support CEC control, though the HDMI 31 * encoder block has CEC support. 32 */ 33 34 #include <drm/drm_atomic_helper.h> 35 #include <drm/drm_edid.h> 36 #include <drm/drm_probe_helper.h> 37 #include <drm/drm_simple_kms_helper.h> 38 #include <drm/drm_scdc_helper.h> 39 #include <linux/clk.h> 40 #include <linux/component.h> 41 #include <linux/i2c.h> 42 #include <linux/of_address.h> 43 #include <linux/of_gpio.h> 44 #include <linux/of_platform.h> 45 #include <linux/pm_runtime.h> 46 #include <linux/rational.h> 47 #include <linux/reset.h> 48 #include <sound/dmaengine_pcm.h> 49 #include <sound/pcm_drm_eld.h> 50 #include <sound/pcm_params.h> 51 #include <sound/soc.h> 52 #include "media/cec.h" 53 #include "vc4_drv.h" 54 #include "vc4_hdmi.h" 55 #include "vc4_hdmi_regs.h" 56 #include "vc4_regs.h" 57 58 #define VC5_HDMI_HORZA_HFP_SHIFT 16 59 #define VC5_HDMI_HORZA_HFP_MASK VC4_MASK(28, 16) 60 #define VC5_HDMI_HORZA_VPOS BIT(15) 61 #define VC5_HDMI_HORZA_HPOS BIT(14) 62 #define VC5_HDMI_HORZA_HAP_SHIFT 0 63 #define VC5_HDMI_HORZA_HAP_MASK VC4_MASK(13, 0) 64 65 #define VC5_HDMI_HORZB_HBP_SHIFT 16 66 #define VC5_HDMI_HORZB_HBP_MASK VC4_MASK(26, 16) 67 #define VC5_HDMI_HORZB_HSP_SHIFT 0 68 #define VC5_HDMI_HORZB_HSP_MASK VC4_MASK(10, 0) 69 70 #define VC5_HDMI_VERTA_VSP_SHIFT 24 71 #define VC5_HDMI_VERTA_VSP_MASK VC4_MASK(28, 24) 72 #define VC5_HDMI_VERTA_VFP_SHIFT 16 73 #define VC5_HDMI_VERTA_VFP_MASK VC4_MASK(22, 16) 74 #define VC5_HDMI_VERTA_VAL_SHIFT 0 75 #define VC5_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0) 76 77 #define VC5_HDMI_VERTB_VSPO_SHIFT 16 78 #define VC5_HDMI_VERTB_VSPO_MASK VC4_MASK(29, 16) 79 80 #define VC5_HDMI_SCRAMBLER_CTL_ENABLE BIT(0) 81 82 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT 8 83 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK VC4_MASK(10, 8) 84 85 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT 0 86 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK VC4_MASK(3, 0) 87 88 #define VC5_HDMI_GCP_CONFIG_GCP_ENABLE BIT(31) 89 90 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT 8 91 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK VC4_MASK(15, 8) 92 93 # define VC4_HD_M_SW_RST BIT(2) 94 # define VC4_HD_M_ENABLE BIT(0) 95 96 #define CEC_CLOCK_FREQ 40000 97 98 #define HDMI_14_MAX_TMDS_CLK (340 * 1000 * 1000) 99 100 static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode) 101 { 102 return (mode->clock * 1000) > HDMI_14_MAX_TMDS_CLK; 103 } 104 105 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused) 106 { 107 struct drm_info_node *node = (struct drm_info_node *)m->private; 108 struct vc4_hdmi *vc4_hdmi = node->info_ent->data; 109 struct drm_printer p = drm_seq_file_printer(m); 110 111 drm_print_regset32(&p, &vc4_hdmi->hdmi_regset); 112 drm_print_regset32(&p, &vc4_hdmi->hd_regset); 113 114 return 0; 115 } 116 117 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi) 118 { 119 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST); 120 udelay(1); 121 HDMI_WRITE(HDMI_M_CTL, 0); 122 123 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE); 124 125 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 126 VC4_HDMI_SW_RESET_HDMI | 127 VC4_HDMI_SW_RESET_FORMAT_DETECT); 128 129 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0); 130 } 131 132 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi) 133 { 134 reset_control_reset(vc4_hdmi->reset); 135 136 HDMI_WRITE(HDMI_DVP_CTL, 0); 137 138 HDMI_WRITE(HDMI_CLOCK_STOP, 139 HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL); 140 } 141 142 #ifdef CONFIG_DRM_VC4_HDMI_CEC 143 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) 144 { 145 u16 clk_cnt; 146 u32 value; 147 148 value = HDMI_READ(HDMI_CEC_CNTRL_1); 149 value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK; 150 151 /* 152 * Set the clock divider: the hsm_clock rate and this divider 153 * setting will give a 40 kHz CEC clock. 154 */ 155 clk_cnt = clk_get_rate(vc4_hdmi->cec_clock) / CEC_CLOCK_FREQ; 156 value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT; 157 HDMI_WRITE(HDMI_CEC_CNTRL_1, value); 158 } 159 #else 160 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {} 161 #endif 162 163 static enum drm_connector_status 164 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force) 165 { 166 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 167 bool connected = false; 168 169 if (vc4_hdmi->hpd_gpio) { 170 if (gpio_get_value_cansleep(vc4_hdmi->hpd_gpio) ^ 171 vc4_hdmi->hpd_active_low) 172 connected = true; 173 } else if (drm_probe_ddc(vc4_hdmi->ddc)) { 174 connected = true; 175 } else if (HDMI_READ(HDMI_HOTPLUG) & VC4_HDMI_HOTPLUG_CONNECTED) { 176 connected = true; 177 } 178 179 if (connected) { 180 if (connector->status != connector_status_connected) { 181 struct edid *edid = drm_get_edid(connector, vc4_hdmi->ddc); 182 183 if (edid) { 184 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid); 185 vc4_hdmi->encoder.hdmi_monitor = drm_detect_hdmi_monitor(edid); 186 kfree(edid); 187 } 188 } 189 190 return connector_status_connected; 191 } 192 193 cec_phys_addr_invalidate(vc4_hdmi->cec_adap); 194 return connector_status_disconnected; 195 } 196 197 static void vc4_hdmi_connector_destroy(struct drm_connector *connector) 198 { 199 drm_connector_unregister(connector); 200 drm_connector_cleanup(connector); 201 } 202 203 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector) 204 { 205 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 206 struct vc4_hdmi_encoder *vc4_encoder = &vc4_hdmi->encoder; 207 int ret = 0; 208 struct edid *edid; 209 210 edid = drm_get_edid(connector, vc4_hdmi->ddc); 211 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid); 212 if (!edid) 213 return -ENODEV; 214 215 vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid); 216 217 drm_connector_update_edid_property(connector, edid); 218 ret = drm_add_edid_modes(connector, edid); 219 kfree(edid); 220 221 if (vc4_hdmi->disable_4kp60) { 222 struct drm_device *drm = connector->dev; 223 struct drm_display_mode *mode; 224 225 list_for_each_entry(mode, &connector->probed_modes, head) { 226 if (vc4_hdmi_mode_needs_scrambling(mode)) { 227 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz."); 228 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60."); 229 } 230 } 231 } 232 233 return ret; 234 } 235 236 static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector, 237 struct drm_atomic_state *state) 238 { 239 struct drm_connector_state *old_state = 240 drm_atomic_get_old_connector_state(state, connector); 241 struct drm_connector_state *new_state = 242 drm_atomic_get_new_connector_state(state, connector); 243 struct drm_crtc *crtc = new_state->crtc; 244 245 if (!crtc) 246 return 0; 247 248 if (old_state->colorspace != new_state->colorspace || 249 !drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) { 250 struct drm_crtc_state *crtc_state; 251 252 crtc_state = drm_atomic_get_crtc_state(state, crtc); 253 if (IS_ERR(crtc_state)) 254 return PTR_ERR(crtc_state); 255 256 crtc_state->mode_changed = true; 257 } 258 259 return 0; 260 } 261 262 static void vc4_hdmi_connector_reset(struct drm_connector *connector) 263 { 264 struct vc4_hdmi_connector_state *old_state = 265 conn_state_to_vc4_hdmi_conn_state(connector->state); 266 struct vc4_hdmi_connector_state *new_state = 267 kzalloc(sizeof(*new_state), GFP_KERNEL); 268 269 if (connector->state) 270 __drm_atomic_helper_connector_destroy_state(connector->state); 271 272 kfree(old_state); 273 __drm_atomic_helper_connector_reset(connector, &new_state->base); 274 275 if (!new_state) 276 return; 277 278 new_state->base.max_bpc = 8; 279 new_state->base.max_requested_bpc = 8; 280 drm_atomic_helper_connector_tv_reset(connector); 281 } 282 283 static struct drm_connector_state * 284 vc4_hdmi_connector_duplicate_state(struct drm_connector *connector) 285 { 286 struct drm_connector_state *conn_state = connector->state; 287 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state); 288 struct vc4_hdmi_connector_state *new_state; 289 290 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL); 291 if (!new_state) 292 return NULL; 293 294 new_state->pixel_rate = vc4_state->pixel_rate; 295 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base); 296 297 return &new_state->base; 298 } 299 300 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = { 301 .detect = vc4_hdmi_connector_detect, 302 .fill_modes = drm_helper_probe_single_connector_modes, 303 .destroy = vc4_hdmi_connector_destroy, 304 .reset = vc4_hdmi_connector_reset, 305 .atomic_duplicate_state = vc4_hdmi_connector_duplicate_state, 306 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 307 }; 308 309 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = { 310 .get_modes = vc4_hdmi_connector_get_modes, 311 .atomic_check = vc4_hdmi_connector_atomic_check, 312 }; 313 314 static int vc4_hdmi_connector_init(struct drm_device *dev, 315 struct vc4_hdmi *vc4_hdmi) 316 { 317 struct drm_connector *connector = &vc4_hdmi->connector; 318 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base; 319 int ret; 320 321 drm_connector_init_with_ddc(dev, connector, 322 &vc4_hdmi_connector_funcs, 323 DRM_MODE_CONNECTOR_HDMIA, 324 vc4_hdmi->ddc); 325 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs); 326 327 /* 328 * Some of the properties below require access to state, like bpc. 329 * Allocate some default initial connector state with our reset helper. 330 */ 331 if (connector->funcs->reset) 332 connector->funcs->reset(connector); 333 334 /* Create and attach TV margin props to this connector. */ 335 ret = drm_mode_create_tv_margin_properties(dev); 336 if (ret) 337 return ret; 338 339 ret = drm_mode_create_hdmi_colorspace_property(connector); 340 if (ret) 341 return ret; 342 343 drm_connector_attach_colorspace_property(connector); 344 drm_connector_attach_tv_margin_properties(connector); 345 drm_connector_attach_max_bpc_property(connector, 8, 12); 346 347 connector->polled = (DRM_CONNECTOR_POLL_CONNECT | 348 DRM_CONNECTOR_POLL_DISCONNECT); 349 350 connector->interlace_allowed = 1; 351 connector->doublescan_allowed = 0; 352 353 if (vc4_hdmi->variant->supports_hdr) 354 drm_connector_attach_hdr_output_metadata_property(connector); 355 356 drm_connector_attach_encoder(connector, encoder); 357 358 return 0; 359 } 360 361 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder, 362 enum hdmi_infoframe_type type, 363 bool poll) 364 { 365 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 366 u32 packet_id = type - 0x80; 367 368 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 369 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id)); 370 371 if (!poll) 372 return 0; 373 374 return wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) & 375 BIT(packet_id)), 100); 376 } 377 378 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder, 379 union hdmi_infoframe *frame) 380 { 381 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 382 u32 packet_id = frame->any.type - 0x80; 383 const struct vc4_hdmi_register *ram_packet_start = 384 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START]; 385 u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id; 386 void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi, 387 ram_packet_start->reg); 388 uint8_t buffer[VC4_HDMI_PACKET_STRIDE]; 389 ssize_t len, i; 390 int ret; 391 392 WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) & 393 VC4_HDMI_RAM_PACKET_ENABLE), 394 "Packet RAM has to be on to store the packet."); 395 396 len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer)); 397 if (len < 0) 398 return; 399 400 ret = vc4_hdmi_stop_packet(encoder, frame->any.type, true); 401 if (ret) { 402 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret); 403 return; 404 } 405 406 for (i = 0; i < len; i += 7) { 407 writel(buffer[i + 0] << 0 | 408 buffer[i + 1] << 8 | 409 buffer[i + 2] << 16, 410 base + packet_reg); 411 packet_reg += 4; 412 413 writel(buffer[i + 3] << 0 | 414 buffer[i + 4] << 8 | 415 buffer[i + 5] << 16 | 416 buffer[i + 6] << 24, 417 base + packet_reg); 418 packet_reg += 4; 419 } 420 421 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 422 HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id)); 423 ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) & 424 BIT(packet_id)), 100); 425 if (ret) 426 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret); 427 } 428 429 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder) 430 { 431 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 432 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 433 struct drm_connector *connector = &vc4_hdmi->connector; 434 struct drm_connector_state *cstate = connector->state; 435 struct drm_crtc *crtc = encoder->crtc; 436 const struct drm_display_mode *mode = &crtc->state->adjusted_mode; 437 union hdmi_infoframe frame; 438 int ret; 439 440 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, 441 connector, mode); 442 if (ret < 0) { 443 DRM_ERROR("couldn't fill AVI infoframe\n"); 444 return; 445 } 446 447 drm_hdmi_avi_infoframe_quant_range(&frame.avi, 448 connector, mode, 449 vc4_encoder->limited_rgb_range ? 450 HDMI_QUANTIZATION_RANGE_LIMITED : 451 HDMI_QUANTIZATION_RANGE_FULL); 452 drm_hdmi_avi_infoframe_colorspace(&frame.avi, cstate); 453 drm_hdmi_avi_infoframe_bars(&frame.avi, cstate); 454 455 vc4_hdmi_write_infoframe(encoder, &frame); 456 } 457 458 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder) 459 { 460 union hdmi_infoframe frame; 461 int ret; 462 463 ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore"); 464 if (ret < 0) { 465 DRM_ERROR("couldn't fill SPD infoframe\n"); 466 return; 467 } 468 469 frame.spd.sdi = HDMI_SPD_SDI_PC; 470 471 vc4_hdmi_write_infoframe(encoder, &frame); 472 } 473 474 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder) 475 { 476 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 477 union hdmi_infoframe frame; 478 479 hdmi_audio_infoframe_init(&frame.audio); 480 481 frame.audio.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM; 482 frame.audio.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM; 483 frame.audio.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM; 484 frame.audio.channels = vc4_hdmi->audio.channels; 485 486 vc4_hdmi_write_infoframe(encoder, &frame); 487 } 488 489 static void vc4_hdmi_set_hdr_infoframe(struct drm_encoder *encoder) 490 { 491 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 492 struct drm_connector *connector = &vc4_hdmi->connector; 493 struct drm_connector_state *conn_state = connector->state; 494 union hdmi_infoframe frame; 495 496 if (!vc4_hdmi->variant->supports_hdr) 497 return; 498 499 if (!conn_state->hdr_output_metadata) 500 return; 501 502 if (drm_hdmi_infoframe_set_hdr_metadata(&frame.drm, conn_state)) 503 return; 504 505 vc4_hdmi_write_infoframe(encoder, &frame); 506 } 507 508 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder) 509 { 510 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 511 512 vc4_hdmi_set_avi_infoframe(encoder); 513 vc4_hdmi_set_spd_infoframe(encoder); 514 /* 515 * If audio was streaming, then we need to reenabled the audio 516 * infoframe here during encoder_enable. 517 */ 518 if (vc4_hdmi->audio.streaming) 519 vc4_hdmi_set_audio_infoframe(encoder); 520 521 vc4_hdmi_set_hdr_infoframe(encoder); 522 } 523 524 static bool vc4_hdmi_supports_scrambling(struct drm_encoder *encoder, 525 struct drm_display_mode *mode) 526 { 527 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 528 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 529 struct drm_display_info *display = &vc4_hdmi->connector.display_info; 530 531 if (!vc4_encoder->hdmi_monitor) 532 return false; 533 534 if (!display->hdmi.scdc.supported || 535 !display->hdmi.scdc.scrambling.supported) 536 return false; 537 538 return true; 539 } 540 541 #define SCRAMBLING_POLLING_DELAY_MS 1000 542 543 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder) 544 { 545 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; 546 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 547 548 if (!vc4_hdmi_supports_scrambling(encoder, mode)) 549 return; 550 551 if (!vc4_hdmi_mode_needs_scrambling(mode)) 552 return; 553 554 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true); 555 drm_scdc_set_scrambling(vc4_hdmi->ddc, true); 556 557 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) | 558 VC5_HDMI_SCRAMBLER_CTL_ENABLE); 559 560 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work, 561 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS)); 562 } 563 564 static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder) 565 { 566 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 567 struct drm_crtc *crtc = encoder->crtc; 568 569 /* 570 * At boot, encoder->crtc will be NULL. Since we don't know the 571 * state of the scrambler and in order to avoid any 572 * inconsistency, let's disable it all the time. 573 */ 574 if (crtc && !vc4_hdmi_supports_scrambling(encoder, &crtc->mode)) 575 return; 576 577 if (crtc && !vc4_hdmi_mode_needs_scrambling(&crtc->mode)) 578 return; 579 580 if (delayed_work_pending(&vc4_hdmi->scrambling_work)) 581 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work); 582 583 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) & 584 ~VC5_HDMI_SCRAMBLER_CTL_ENABLE); 585 586 drm_scdc_set_scrambling(vc4_hdmi->ddc, false); 587 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, false); 588 } 589 590 static void vc4_hdmi_scrambling_wq(struct work_struct *work) 591 { 592 struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work), 593 struct vc4_hdmi, 594 scrambling_work); 595 596 if (drm_scdc_get_scrambling_status(vc4_hdmi->ddc)) 597 return; 598 599 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true); 600 drm_scdc_set_scrambling(vc4_hdmi->ddc, true); 601 602 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work, 603 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS)); 604 } 605 606 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder, 607 struct drm_atomic_state *state) 608 { 609 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 610 611 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0); 612 613 HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | 614 VC4_HD_VID_CTL_CLRRGB | VC4_HD_VID_CTL_CLRSYNC); 615 616 HDMI_WRITE(HDMI_VID_CTL, 617 HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX); 618 619 vc4_hdmi_disable_scrambling(encoder); 620 } 621 622 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder, 623 struct drm_atomic_state *state) 624 { 625 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 626 int ret; 627 628 if (vc4_hdmi->variant->phy_disable) 629 vc4_hdmi->variant->phy_disable(vc4_hdmi); 630 631 HDMI_WRITE(HDMI_VID_CTL, 632 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE); 633 634 clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock); 635 clk_disable_unprepare(vc4_hdmi->hsm_clock); 636 clk_disable_unprepare(vc4_hdmi->pixel_clock); 637 638 ret = pm_runtime_put(&vc4_hdmi->pdev->dev); 639 if (ret < 0) 640 DRM_ERROR("Failed to release power domain: %d\n", ret); 641 } 642 643 static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder) 644 { 645 } 646 647 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable) 648 { 649 u32 csc_ctl; 650 651 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR, 652 VC4_HD_CSC_CTL_ORDER); 653 654 if (enable) { 655 /* CEA VICs other than #1 requre limited range RGB 656 * output unless overridden by an AVI infoframe. 657 * Apply a colorspace conversion to squash 0-255 down 658 * to 16-235. The matrix here is: 659 * 660 * [ 0 0 0.8594 16] 661 * [ 0 0.8594 0 16] 662 * [ 0.8594 0 0 16] 663 * [ 0 0 0 1] 664 */ 665 csc_ctl |= VC4_HD_CSC_CTL_ENABLE; 666 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC; 667 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM, 668 VC4_HD_CSC_CTL_MODE); 669 670 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000); 671 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0); 672 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000); 673 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000); 674 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0); 675 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000); 676 } 677 678 /* The RGB order applies even when CSC is disabled. */ 679 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl); 680 } 681 682 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable) 683 { 684 u32 csc_ctl; 685 686 csc_ctl = 0x07; /* RGB_CONVERT_MODE = custom matrix, || USE_RGB_TO_YCBCR */ 687 688 if (enable) { 689 /* CEA VICs other than #1 requre limited range RGB 690 * output unless overridden by an AVI infoframe. 691 * Apply a colorspace conversion to squash 0-255 down 692 * to 16-235. The matrix here is: 693 * 694 * [ 0.8594 0 0 16] 695 * [ 0 0.8594 0 16] 696 * [ 0 0 0.8594 16] 697 * [ 0 0 0 1] 698 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets 699 */ 700 HDMI_WRITE(HDMI_CSC_12_11, (0x0000 << 16) | 0x1b80); 701 HDMI_WRITE(HDMI_CSC_14_13, (0x0400 << 16) | 0x0000); 702 HDMI_WRITE(HDMI_CSC_22_21, (0x1b80 << 16) | 0x0000); 703 HDMI_WRITE(HDMI_CSC_24_23, (0x0400 << 16) | 0x0000); 704 HDMI_WRITE(HDMI_CSC_32_31, (0x0000 << 16) | 0x0000); 705 HDMI_WRITE(HDMI_CSC_34_33, (0x0400 << 16) | 0x1b80); 706 } else { 707 /* Still use the matrix for full range, but make it unity. 708 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets 709 */ 710 HDMI_WRITE(HDMI_CSC_12_11, (0x0000 << 16) | 0x2000); 711 HDMI_WRITE(HDMI_CSC_14_13, (0x0000 << 16) | 0x0000); 712 HDMI_WRITE(HDMI_CSC_22_21, (0x2000 << 16) | 0x0000); 713 HDMI_WRITE(HDMI_CSC_24_23, (0x0000 << 16) | 0x0000); 714 HDMI_WRITE(HDMI_CSC_32_31, (0x0000 << 16) | 0x0000); 715 HDMI_WRITE(HDMI_CSC_34_33, (0x0000 << 16) | 0x2000); 716 } 717 718 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl); 719 } 720 721 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi, 722 struct drm_connector_state *state, 723 struct drm_display_mode *mode) 724 { 725 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 726 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 727 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 728 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 729 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 730 VC4_HDMI_VERTA_VSP) | 731 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 732 VC4_HDMI_VERTA_VFP) | 733 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL)); 734 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 735 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end, 736 VC4_HDMI_VERTB_VBP)); 737 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 738 VC4_SET_FIELD(mode->crtc_vtotal - 739 mode->crtc_vsync_end - 740 interlaced, 741 VC4_HDMI_VERTB_VBP)); 742 743 HDMI_WRITE(HDMI_HORZA, 744 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) | 745 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) | 746 VC4_SET_FIELD(mode->hdisplay * pixel_rep, 747 VC4_HDMI_HORZA_HAP)); 748 749 HDMI_WRITE(HDMI_HORZB, 750 VC4_SET_FIELD((mode->htotal - 751 mode->hsync_end) * pixel_rep, 752 VC4_HDMI_HORZB_HBP) | 753 VC4_SET_FIELD((mode->hsync_end - 754 mode->hsync_start) * pixel_rep, 755 VC4_HDMI_HORZB_HSP) | 756 VC4_SET_FIELD((mode->hsync_start - 757 mode->hdisplay) * pixel_rep, 758 VC4_HDMI_HORZB_HFP)); 759 760 HDMI_WRITE(HDMI_VERTA0, verta); 761 HDMI_WRITE(HDMI_VERTA1, verta); 762 763 HDMI_WRITE(HDMI_VERTB0, vertb_even); 764 HDMI_WRITE(HDMI_VERTB1, vertb); 765 } 766 767 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi, 768 struct drm_connector_state *state, 769 struct drm_display_mode *mode) 770 { 771 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 772 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 773 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 774 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 775 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 776 VC5_HDMI_VERTA_VSP) | 777 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 778 VC5_HDMI_VERTA_VFP) | 779 VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL)); 780 u32 vertb = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) | 781 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end, 782 VC4_HDMI_VERTB_VBP)); 783 u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) | 784 VC4_SET_FIELD(mode->crtc_vtotal - 785 mode->crtc_vsync_end - 786 interlaced, 787 VC4_HDMI_VERTB_VBP)); 788 unsigned char gcp; 789 bool gcp_en; 790 u32 reg; 791 792 HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, 0x354021); 793 HDMI_WRITE(HDMI_HORZA, 794 (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) | 795 (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) | 796 VC4_SET_FIELD(mode->hdisplay * pixel_rep, 797 VC5_HDMI_HORZA_HAP) | 798 VC4_SET_FIELD((mode->hsync_start - 799 mode->hdisplay) * pixel_rep, 800 VC5_HDMI_HORZA_HFP)); 801 802 HDMI_WRITE(HDMI_HORZB, 803 VC4_SET_FIELD((mode->htotal - 804 mode->hsync_end) * pixel_rep, 805 VC5_HDMI_HORZB_HBP) | 806 VC4_SET_FIELD((mode->hsync_end - 807 mode->hsync_start) * pixel_rep, 808 VC5_HDMI_HORZB_HSP)); 809 810 HDMI_WRITE(HDMI_VERTA0, verta); 811 HDMI_WRITE(HDMI_VERTA1, verta); 812 813 HDMI_WRITE(HDMI_VERTB0, vertb_even); 814 HDMI_WRITE(HDMI_VERTB1, vertb); 815 816 switch (state->max_bpc) { 817 case 12: 818 gcp = 6; 819 gcp_en = true; 820 break; 821 case 10: 822 gcp = 5; 823 gcp_en = true; 824 break; 825 case 8: 826 default: 827 gcp = 4; 828 gcp_en = false; 829 break; 830 } 831 832 reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1); 833 reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK | 834 VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK); 835 reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) | 836 VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH); 837 HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg); 838 839 reg = HDMI_READ(HDMI_GCP_WORD_1); 840 reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK; 841 reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1); 842 HDMI_WRITE(HDMI_GCP_WORD_1, reg); 843 844 reg = HDMI_READ(HDMI_GCP_CONFIG); 845 reg &= ~VC5_HDMI_GCP_CONFIG_GCP_ENABLE; 846 reg |= gcp_en ? VC5_HDMI_GCP_CONFIG_GCP_ENABLE : 0; 847 HDMI_WRITE(HDMI_GCP_CONFIG, reg); 848 849 HDMI_WRITE(HDMI_CLOCK_STOP, 0); 850 } 851 852 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi) 853 { 854 u32 drift; 855 int ret; 856 857 drift = HDMI_READ(HDMI_FIFO_CTL); 858 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK; 859 860 HDMI_WRITE(HDMI_FIFO_CTL, 861 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 862 HDMI_WRITE(HDMI_FIFO_CTL, 863 drift | VC4_HDMI_FIFO_CTL_RECENTER); 864 usleep_range(1000, 1100); 865 HDMI_WRITE(HDMI_FIFO_CTL, 866 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 867 HDMI_WRITE(HDMI_FIFO_CTL, 868 drift | VC4_HDMI_FIFO_CTL_RECENTER); 869 870 ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) & 871 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1); 872 WARN_ONCE(ret, "Timeout waiting for " 873 "VC4_HDMI_FIFO_CTL_RECENTER_DONE"); 874 } 875 876 static struct drm_connector_state * 877 vc4_hdmi_encoder_get_connector_state(struct drm_encoder *encoder, 878 struct drm_atomic_state *state) 879 { 880 struct drm_connector_state *conn_state; 881 struct drm_connector *connector; 882 unsigned int i; 883 884 for_each_new_connector_in_state(state, connector, conn_state, i) { 885 if (conn_state->best_encoder == encoder) 886 return conn_state; 887 } 888 889 return NULL; 890 } 891 892 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder, 893 struct drm_atomic_state *state) 894 { 895 struct drm_connector_state *conn_state = 896 vc4_hdmi_encoder_get_connector_state(encoder, state); 897 struct vc4_hdmi_connector_state *vc4_conn_state = 898 conn_state_to_vc4_hdmi_conn_state(conn_state); 899 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; 900 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 901 unsigned long bvb_rate, pixel_rate, hsm_rate; 902 int ret; 903 904 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev); 905 if (ret < 0) { 906 DRM_ERROR("Failed to retain power domain: %d\n", ret); 907 return; 908 } 909 910 pixel_rate = vc4_conn_state->pixel_rate; 911 ret = clk_set_rate(vc4_hdmi->pixel_clock, pixel_rate); 912 if (ret) { 913 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret); 914 return; 915 } 916 917 ret = clk_prepare_enable(vc4_hdmi->pixel_clock); 918 if (ret) { 919 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret); 920 return; 921 } 922 923 /* 924 * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must 925 * be faster than pixel clock, infinitesimally faster, tested in 926 * simulation. Otherwise, exact value is unimportant for HDMI 927 * operation." This conflicts with bcm2835's vc4 documentation, which 928 * states HSM's clock has to be at least 108% of the pixel clock. 929 * 930 * Real life tests reveal that vc4's firmware statement holds up, and 931 * users are able to use pixel clocks closer to HSM's, namely for 932 * 1920x1200@60Hz. So it was decided to have leave a 1% margin between 933 * both clocks. Which, for RPi0-3 implies a maximum pixel clock of 934 * 162MHz. 935 * 936 * Additionally, the AXI clock needs to be at least 25% of 937 * pixel clock, but HSM ends up being the limiting factor. 938 */ 939 hsm_rate = max_t(unsigned long, 120000000, (pixel_rate / 100) * 101); 940 ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate); 941 if (ret) { 942 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret); 943 return; 944 } 945 946 ret = clk_prepare_enable(vc4_hdmi->hsm_clock); 947 if (ret) { 948 DRM_ERROR("Failed to turn on HSM clock: %d\n", ret); 949 clk_disable_unprepare(vc4_hdmi->pixel_clock); 950 return; 951 } 952 953 vc4_hdmi_cec_update_clk_div(vc4_hdmi); 954 955 if (pixel_rate > 297000000) 956 bvb_rate = 300000000; 957 else if (pixel_rate > 148500000) 958 bvb_rate = 150000000; 959 else 960 bvb_rate = 75000000; 961 962 ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate); 963 if (ret) { 964 DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret); 965 clk_disable_unprepare(vc4_hdmi->hsm_clock); 966 clk_disable_unprepare(vc4_hdmi->pixel_clock); 967 return; 968 } 969 970 ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock); 971 if (ret) { 972 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret); 973 clk_disable_unprepare(vc4_hdmi->hsm_clock); 974 clk_disable_unprepare(vc4_hdmi->pixel_clock); 975 return; 976 } 977 978 if (vc4_hdmi->variant->phy_init) 979 vc4_hdmi->variant->phy_init(vc4_hdmi, vc4_conn_state); 980 981 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 982 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 983 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT | 984 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS); 985 986 if (vc4_hdmi->variant->set_timings) 987 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode); 988 } 989 990 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder, 991 struct drm_atomic_state *state) 992 { 993 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; 994 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 995 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 996 997 if (vc4_encoder->hdmi_monitor && 998 drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_LIMITED) { 999 if (vc4_hdmi->variant->csc_setup) 1000 vc4_hdmi->variant->csc_setup(vc4_hdmi, true); 1001 1002 vc4_encoder->limited_rgb_range = true; 1003 } else { 1004 if (vc4_hdmi->variant->csc_setup) 1005 vc4_hdmi->variant->csc_setup(vc4_hdmi, false); 1006 1007 vc4_encoder->limited_rgb_range = false; 1008 } 1009 1010 HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N); 1011 } 1012 1013 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder, 1014 struct drm_atomic_state *state) 1015 { 1016 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; 1017 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1018 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 1019 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 1020 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 1021 int ret; 1022 1023 HDMI_WRITE(HDMI_VID_CTL, 1024 VC4_HD_VID_CTL_ENABLE | 1025 VC4_HD_VID_CTL_UNDERFLOW_ENABLE | 1026 VC4_HD_VID_CTL_FRAME_COUNTER_RESET | 1027 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) | 1028 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW)); 1029 1030 HDMI_WRITE(HDMI_VID_CTL, 1031 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX); 1032 1033 if (vc4_encoder->hdmi_monitor) { 1034 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1035 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 1036 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 1037 1038 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1039 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000); 1040 WARN_ONCE(ret, "Timeout waiting for " 1041 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 1042 } else { 1043 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 1044 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & 1045 ~(VC4_HDMI_RAM_PACKET_ENABLE)); 1046 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1047 HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1048 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 1049 1050 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1051 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000); 1052 WARN_ONCE(ret, "Timeout waiting for " 1053 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 1054 } 1055 1056 if (vc4_encoder->hdmi_monitor) { 1057 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1058 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE)); 1059 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1060 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 1061 VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT); 1062 1063 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 1064 VC4_HDMI_RAM_PACKET_ENABLE); 1065 1066 vc4_hdmi_set_infoframes(encoder); 1067 } 1068 1069 vc4_hdmi_recenter_fifo(vc4_hdmi); 1070 vc4_hdmi_enable_scrambling(encoder); 1071 } 1072 1073 static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder) 1074 { 1075 } 1076 1077 #define WIFI_2_4GHz_CH1_MIN_FREQ 2400000000ULL 1078 #define WIFI_2_4GHz_CH1_MAX_FREQ 2422000000ULL 1079 1080 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder, 1081 struct drm_crtc_state *crtc_state, 1082 struct drm_connector_state *conn_state) 1083 { 1084 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state); 1085 struct drm_display_mode *mode = &crtc_state->adjusted_mode; 1086 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1087 unsigned long long pixel_rate = mode->clock * 1000; 1088 unsigned long long tmds_rate; 1089 1090 if (vc4_hdmi->variant->unsupported_odd_h_timings && 1091 ((mode->hdisplay % 2) || (mode->hsync_start % 2) || 1092 (mode->hsync_end % 2) || (mode->htotal % 2))) 1093 return -EINVAL; 1094 1095 /* 1096 * The 1440p@60 pixel rate is in the same range than the first 1097 * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz 1098 * bandwidth). Slightly lower the frequency to bring it out of 1099 * the WiFi range. 1100 */ 1101 tmds_rate = pixel_rate * 10; 1102 if (vc4_hdmi->disable_wifi_frequencies && 1103 (tmds_rate >= WIFI_2_4GHz_CH1_MIN_FREQ && 1104 tmds_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) { 1105 mode->clock = 238560; 1106 pixel_rate = mode->clock * 1000; 1107 } 1108 1109 if (conn_state->max_bpc == 12) { 1110 pixel_rate = pixel_rate * 150; 1111 do_div(pixel_rate, 100); 1112 } else if (conn_state->max_bpc == 10) { 1113 pixel_rate = pixel_rate * 125; 1114 do_div(pixel_rate, 100); 1115 } 1116 1117 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 1118 pixel_rate = pixel_rate * 2; 1119 1120 if (pixel_rate > vc4_hdmi->variant->max_pixel_clock) 1121 return -EINVAL; 1122 1123 if (vc4_hdmi->disable_4kp60 && (pixel_rate > HDMI_14_MAX_TMDS_CLK)) 1124 return -EINVAL; 1125 1126 vc4_state->pixel_rate = pixel_rate; 1127 1128 return 0; 1129 } 1130 1131 static enum drm_mode_status 1132 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder, 1133 const struct drm_display_mode *mode) 1134 { 1135 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1136 1137 if (vc4_hdmi->variant->unsupported_odd_h_timings && 1138 ((mode->hdisplay % 2) || (mode->hsync_start % 2) || 1139 (mode->hsync_end % 2) || (mode->htotal % 2))) 1140 return MODE_H_ILLEGAL; 1141 1142 if ((mode->clock * 1000) > vc4_hdmi->variant->max_pixel_clock) 1143 return MODE_CLOCK_HIGH; 1144 1145 if (vc4_hdmi->disable_4kp60 && vc4_hdmi_mode_needs_scrambling(mode)) 1146 return MODE_CLOCK_HIGH; 1147 1148 return MODE_OK; 1149 } 1150 1151 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = { 1152 .atomic_check = vc4_hdmi_encoder_atomic_check, 1153 .mode_valid = vc4_hdmi_encoder_mode_valid, 1154 .disable = vc4_hdmi_encoder_disable, 1155 .enable = vc4_hdmi_encoder_enable, 1156 }; 1157 1158 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask) 1159 { 1160 int i; 1161 u32 channel_map = 0; 1162 1163 for (i = 0; i < 8; i++) { 1164 if (channel_mask & BIT(i)) 1165 channel_map |= i << (3 * i); 1166 } 1167 return channel_map; 1168 } 1169 1170 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask) 1171 { 1172 int i; 1173 u32 channel_map = 0; 1174 1175 for (i = 0; i < 8; i++) { 1176 if (channel_mask & BIT(i)) 1177 channel_map |= i << (4 * i); 1178 } 1179 return channel_map; 1180 } 1181 1182 /* HDMI audio codec callbacks */ 1183 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi) 1184 { 1185 u32 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock); 1186 unsigned long n, m; 1187 1188 rational_best_approximation(hsm_clock, vc4_hdmi->audio.samplerate, 1189 VC4_HD_MAI_SMP_N_MASK >> 1190 VC4_HD_MAI_SMP_N_SHIFT, 1191 (VC4_HD_MAI_SMP_M_MASK >> 1192 VC4_HD_MAI_SMP_M_SHIFT) + 1, 1193 &n, &m); 1194 1195 HDMI_WRITE(HDMI_MAI_SMP, 1196 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) | 1197 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M)); 1198 } 1199 1200 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi) 1201 { 1202 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base; 1203 struct drm_crtc *crtc = encoder->crtc; 1204 const struct drm_display_mode *mode = &crtc->state->adjusted_mode; 1205 u32 samplerate = vc4_hdmi->audio.samplerate; 1206 u32 n, cts; 1207 u64 tmp; 1208 1209 n = 128 * samplerate / 1000; 1210 tmp = (u64)(mode->clock * 1000) * n; 1211 do_div(tmp, 128 * samplerate); 1212 cts = tmp; 1213 1214 HDMI_WRITE(HDMI_CRP_CFG, 1215 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN | 1216 VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N)); 1217 1218 /* 1219 * We could get slightly more accurate clocks in some cases by 1220 * providing a CTS_1 value. The two CTS values are alternated 1221 * between based on the period fields 1222 */ 1223 HDMI_WRITE(HDMI_CTS_0, cts); 1224 HDMI_WRITE(HDMI_CTS_1, cts); 1225 } 1226 1227 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai) 1228 { 1229 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai); 1230 1231 return snd_soc_card_get_drvdata(card); 1232 } 1233 1234 static int vc4_hdmi_audio_startup(struct snd_pcm_substream *substream, 1235 struct snd_soc_dai *dai) 1236 { 1237 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai); 1238 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base; 1239 struct drm_connector *connector = &vc4_hdmi->connector; 1240 int ret; 1241 1242 if (vc4_hdmi->audio.substream && vc4_hdmi->audio.substream != substream) 1243 return -EINVAL; 1244 1245 vc4_hdmi->audio.substream = substream; 1246 1247 /* 1248 * If the HDMI encoder hasn't probed, or the encoder is 1249 * currently in DVI mode, treat the codec dai as missing. 1250 */ 1251 if (!encoder->crtc || !(HDMI_READ(HDMI_RAM_PACKET_CONFIG) & 1252 VC4_HDMI_RAM_PACKET_ENABLE)) 1253 return -ENODEV; 1254 1255 ret = snd_pcm_hw_constraint_eld(substream->runtime, connector->eld); 1256 if (ret) 1257 return ret; 1258 1259 return 0; 1260 } 1261 1262 static int vc4_hdmi_audio_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 1263 { 1264 return 0; 1265 } 1266 1267 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi) 1268 { 1269 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base; 1270 struct device *dev = &vc4_hdmi->pdev->dev; 1271 int ret; 1272 1273 vc4_hdmi->audio.streaming = false; 1274 ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO, false); 1275 if (ret) 1276 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret); 1277 1278 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET); 1279 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF); 1280 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH); 1281 } 1282 1283 static void vc4_hdmi_audio_shutdown(struct snd_pcm_substream *substream, 1284 struct snd_soc_dai *dai) 1285 { 1286 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai); 1287 1288 if (substream != vc4_hdmi->audio.substream) 1289 return; 1290 1291 vc4_hdmi_audio_reset(vc4_hdmi); 1292 1293 vc4_hdmi->audio.substream = NULL; 1294 } 1295 1296 /* HDMI audio codec callbacks */ 1297 static int vc4_hdmi_audio_hw_params(struct snd_pcm_substream *substream, 1298 struct snd_pcm_hw_params *params, 1299 struct snd_soc_dai *dai) 1300 { 1301 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai); 1302 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base; 1303 struct device *dev = &vc4_hdmi->pdev->dev; 1304 u32 audio_packet_config, channel_mask; 1305 u32 channel_map; 1306 1307 if (substream != vc4_hdmi->audio.substream) 1308 return -EINVAL; 1309 1310 dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__, 1311 params_rate(params), params_width(params), 1312 params_channels(params)); 1313 1314 vc4_hdmi->audio.channels = params_channels(params); 1315 vc4_hdmi->audio.samplerate = params_rate(params); 1316 1317 HDMI_WRITE(HDMI_MAI_CTL, 1318 VC4_HD_MAI_CTL_RESET | 1319 VC4_HD_MAI_CTL_FLUSH | 1320 VC4_HD_MAI_CTL_DLATE | 1321 VC4_HD_MAI_CTL_ERRORE | 1322 VC4_HD_MAI_CTL_ERRORF); 1323 1324 vc4_hdmi_audio_set_mai_clock(vc4_hdmi); 1325 1326 /* The B frame identifier should match the value used by alsa-lib (8) */ 1327 audio_packet_config = 1328 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT | 1329 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS | 1330 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER); 1331 1332 channel_mask = GENMASK(vc4_hdmi->audio.channels - 1, 0); 1333 audio_packet_config |= VC4_SET_FIELD(channel_mask, 1334 VC4_HDMI_AUDIO_PACKET_CEA_MASK); 1335 1336 /* Set the MAI threshold. This logic mimics the firmware's. */ 1337 if (vc4_hdmi->audio.samplerate > 96000) { 1338 HDMI_WRITE(HDMI_MAI_THR, 1339 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQHIGH) | 1340 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW)); 1341 } else if (vc4_hdmi->audio.samplerate > 48000) { 1342 HDMI_WRITE(HDMI_MAI_THR, 1343 VC4_SET_FIELD(0x14, VC4_HD_MAI_THR_DREQHIGH) | 1344 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW)); 1345 } else { 1346 HDMI_WRITE(HDMI_MAI_THR, 1347 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) | 1348 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) | 1349 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQHIGH) | 1350 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQLOW)); 1351 } 1352 1353 HDMI_WRITE(HDMI_MAI_CONFIG, 1354 VC4_HDMI_MAI_CONFIG_BIT_REVERSE | 1355 VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK)); 1356 1357 channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask); 1358 HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map); 1359 HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config); 1360 vc4_hdmi_set_n_cts(vc4_hdmi); 1361 1362 vc4_hdmi_set_audio_infoframe(encoder); 1363 1364 return 0; 1365 } 1366 1367 static int vc4_hdmi_audio_trigger(struct snd_pcm_substream *substream, int cmd, 1368 struct snd_soc_dai *dai) 1369 { 1370 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai); 1371 1372 switch (cmd) { 1373 case SNDRV_PCM_TRIGGER_START: 1374 vc4_hdmi->audio.streaming = true; 1375 1376 if (vc4_hdmi->variant->phy_rng_enable) 1377 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi); 1378 1379 HDMI_WRITE(HDMI_MAI_CTL, 1380 VC4_SET_FIELD(vc4_hdmi->audio.channels, 1381 VC4_HD_MAI_CTL_CHNUM) | 1382 VC4_HD_MAI_CTL_ENABLE); 1383 break; 1384 case SNDRV_PCM_TRIGGER_STOP: 1385 HDMI_WRITE(HDMI_MAI_CTL, 1386 VC4_HD_MAI_CTL_DLATE | 1387 VC4_HD_MAI_CTL_ERRORE | 1388 VC4_HD_MAI_CTL_ERRORF); 1389 1390 if (vc4_hdmi->variant->phy_rng_disable) 1391 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi); 1392 1393 vc4_hdmi->audio.streaming = false; 1394 1395 break; 1396 default: 1397 break; 1398 } 1399 1400 return 0; 1401 } 1402 1403 static inline struct vc4_hdmi * 1404 snd_component_to_hdmi(struct snd_soc_component *component) 1405 { 1406 struct snd_soc_card *card = snd_soc_component_get_drvdata(component); 1407 1408 return snd_soc_card_get_drvdata(card); 1409 } 1410 1411 static int vc4_hdmi_audio_eld_ctl_info(struct snd_kcontrol *kcontrol, 1412 struct snd_ctl_elem_info *uinfo) 1413 { 1414 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1415 struct vc4_hdmi *vc4_hdmi = snd_component_to_hdmi(component); 1416 struct drm_connector *connector = &vc4_hdmi->connector; 1417 1418 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 1419 uinfo->count = sizeof(connector->eld); 1420 1421 return 0; 1422 } 1423 1424 static int vc4_hdmi_audio_eld_ctl_get(struct snd_kcontrol *kcontrol, 1425 struct snd_ctl_elem_value *ucontrol) 1426 { 1427 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1428 struct vc4_hdmi *vc4_hdmi = snd_component_to_hdmi(component); 1429 struct drm_connector *connector = &vc4_hdmi->connector; 1430 1431 memcpy(ucontrol->value.bytes.data, connector->eld, 1432 sizeof(connector->eld)); 1433 1434 return 0; 1435 } 1436 1437 static const struct snd_kcontrol_new vc4_hdmi_audio_controls[] = { 1438 { 1439 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1440 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1441 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1442 .name = "ELD", 1443 .info = vc4_hdmi_audio_eld_ctl_info, 1444 .get = vc4_hdmi_audio_eld_ctl_get, 1445 }, 1446 }; 1447 1448 static const struct snd_soc_dapm_widget vc4_hdmi_audio_widgets[] = { 1449 SND_SOC_DAPM_OUTPUT("TX"), 1450 }; 1451 1452 static const struct snd_soc_dapm_route vc4_hdmi_audio_routes[] = { 1453 { "TX", NULL, "Playback" }, 1454 }; 1455 1456 static const struct snd_soc_component_driver vc4_hdmi_audio_component_drv = { 1457 .name = "vc4-hdmi-codec-dai-component", 1458 .controls = vc4_hdmi_audio_controls, 1459 .num_controls = ARRAY_SIZE(vc4_hdmi_audio_controls), 1460 .dapm_widgets = vc4_hdmi_audio_widgets, 1461 .num_dapm_widgets = ARRAY_SIZE(vc4_hdmi_audio_widgets), 1462 .dapm_routes = vc4_hdmi_audio_routes, 1463 .num_dapm_routes = ARRAY_SIZE(vc4_hdmi_audio_routes), 1464 .idle_bias_on = 1, 1465 .use_pmdown_time = 1, 1466 .endianness = 1, 1467 .non_legacy_dai_naming = 1, 1468 }; 1469 1470 static const struct snd_soc_dai_ops vc4_hdmi_audio_dai_ops = { 1471 .startup = vc4_hdmi_audio_startup, 1472 .shutdown = vc4_hdmi_audio_shutdown, 1473 .hw_params = vc4_hdmi_audio_hw_params, 1474 .set_fmt = vc4_hdmi_audio_set_fmt, 1475 .trigger = vc4_hdmi_audio_trigger, 1476 }; 1477 1478 static struct snd_soc_dai_driver vc4_hdmi_audio_codec_dai_drv = { 1479 .name = "vc4-hdmi-hifi", 1480 .playback = { 1481 .stream_name = "Playback", 1482 .channels_min = 2, 1483 .channels_max = 8, 1484 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 1485 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 1486 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 1487 SNDRV_PCM_RATE_192000, 1488 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 1489 }, 1490 }; 1491 1492 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = { 1493 .name = "vc4-hdmi-cpu-dai-component", 1494 }; 1495 1496 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai) 1497 { 1498 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai); 1499 1500 snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL); 1501 1502 return 0; 1503 } 1504 1505 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = { 1506 .name = "vc4-hdmi-cpu-dai", 1507 .probe = vc4_hdmi_audio_cpu_dai_probe, 1508 .playback = { 1509 .stream_name = "Playback", 1510 .channels_min = 1, 1511 .channels_max = 8, 1512 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 1513 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 1514 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 1515 SNDRV_PCM_RATE_192000, 1516 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 1517 }, 1518 .ops = &vc4_hdmi_audio_dai_ops, 1519 }; 1520 1521 static const struct snd_dmaengine_pcm_config pcm_conf = { 1522 .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx", 1523 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 1524 }; 1525 1526 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi) 1527 { 1528 const struct vc4_hdmi_register *mai_data = 1529 &vc4_hdmi->variant->registers[HDMI_MAI_DATA]; 1530 struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link; 1531 struct snd_soc_card *card = &vc4_hdmi->audio.card; 1532 struct device *dev = &vc4_hdmi->pdev->dev; 1533 const __be32 *addr; 1534 int index; 1535 int ret; 1536 1537 if (!of_find_property(dev->of_node, "dmas", NULL)) { 1538 dev_warn(dev, 1539 "'dmas' DT property is missing, no HDMI audio\n"); 1540 return 0; 1541 } 1542 1543 if (mai_data->reg != VC4_HD) { 1544 WARN_ONCE(true, "MAI isn't in the HD block\n"); 1545 return -EINVAL; 1546 } 1547 1548 /* 1549 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve 1550 * the bus address specified in the DT, because the physical address 1551 * (the one returned by platform_get_resource()) is not appropriate 1552 * for DMA transfers. 1553 * This VC/MMU should probably be exposed to avoid this kind of hacks. 1554 */ 1555 index = of_property_match_string(dev->of_node, "reg-names", "hd"); 1556 /* Before BCM2711, we don't have a named register range */ 1557 if (index < 0) 1558 index = 1; 1559 1560 addr = of_get_address(dev->of_node, index, NULL, NULL); 1561 1562 vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset; 1563 vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1564 vc4_hdmi->audio.dma_data.maxburst = 2; 1565 1566 ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0); 1567 if (ret) { 1568 dev_err(dev, "Could not register PCM component: %d\n", ret); 1569 return ret; 1570 } 1571 1572 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp, 1573 &vc4_hdmi_audio_cpu_dai_drv, 1); 1574 if (ret) { 1575 dev_err(dev, "Could not register CPU DAI: %d\n", ret); 1576 return ret; 1577 } 1578 1579 /* register component and codec dai */ 1580 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_component_drv, 1581 &vc4_hdmi_audio_codec_dai_drv, 1); 1582 if (ret) { 1583 dev_err(dev, "Could not register component: %d\n", ret); 1584 return ret; 1585 } 1586 1587 dai_link->cpus = &vc4_hdmi->audio.cpu; 1588 dai_link->codecs = &vc4_hdmi->audio.codec; 1589 dai_link->platforms = &vc4_hdmi->audio.platform; 1590 1591 dai_link->num_cpus = 1; 1592 dai_link->num_codecs = 1; 1593 dai_link->num_platforms = 1; 1594 1595 dai_link->name = "MAI"; 1596 dai_link->stream_name = "MAI PCM"; 1597 dai_link->codecs->dai_name = vc4_hdmi_audio_codec_dai_drv.name; 1598 dai_link->cpus->dai_name = dev_name(dev); 1599 dai_link->codecs->name = dev_name(dev); 1600 dai_link->platforms->name = dev_name(dev); 1601 1602 card->dai_link = dai_link; 1603 card->num_links = 1; 1604 card->name = vc4_hdmi->variant->card_name; 1605 card->driver_name = "vc4-hdmi"; 1606 card->dev = dev; 1607 card->owner = THIS_MODULE; 1608 1609 /* 1610 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and 1611 * stores a pointer to the snd card object in dev->driver_data. This 1612 * means we cannot use it for something else. The hdmi back-pointer is 1613 * now stored in card->drvdata and should be retrieved with 1614 * snd_soc_card_get_drvdata() if needed. 1615 */ 1616 snd_soc_card_set_drvdata(card, vc4_hdmi); 1617 ret = devm_snd_soc_register_card(dev, card); 1618 if (ret) 1619 dev_err(dev, "Could not register sound card: %d\n", ret); 1620 1621 return ret; 1622 1623 } 1624 1625 #ifdef CONFIG_DRM_VC4_HDMI_CEC 1626 static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv) 1627 { 1628 struct vc4_hdmi *vc4_hdmi = priv; 1629 1630 if (vc4_hdmi->cec_rx_msg.len) 1631 cec_received_msg(vc4_hdmi->cec_adap, 1632 &vc4_hdmi->cec_rx_msg); 1633 1634 return IRQ_HANDLED; 1635 } 1636 1637 static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv) 1638 { 1639 struct vc4_hdmi *vc4_hdmi = priv; 1640 1641 if (vc4_hdmi->cec_tx_ok) { 1642 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK, 1643 0, 0, 0, 0); 1644 } else { 1645 /* 1646 * This CEC implementation makes 1 retry, so if we 1647 * get a NACK, then that means it made 2 attempts. 1648 */ 1649 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK, 1650 0, 2, 0, 0); 1651 } 1652 return IRQ_HANDLED; 1653 } 1654 1655 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv) 1656 { 1657 struct vc4_hdmi *vc4_hdmi = priv; 1658 irqreturn_t ret; 1659 1660 if (vc4_hdmi->cec_irq_was_rx) 1661 ret = vc4_cec_irq_handler_rx_thread(irq, priv); 1662 else 1663 ret = vc4_cec_irq_handler_tx_thread(irq, priv); 1664 1665 return ret; 1666 } 1667 1668 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1) 1669 { 1670 struct drm_device *dev = vc4_hdmi->connector.dev; 1671 struct cec_msg *msg = &vc4_hdmi->cec_rx_msg; 1672 unsigned int i; 1673 1674 msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >> 1675 VC4_HDMI_CEC_REC_WRD_CNT_SHIFT); 1676 1677 if (msg->len > 16) { 1678 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len); 1679 return; 1680 } 1681 1682 for (i = 0; i < msg->len; i += 4) { 1683 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2)); 1684 1685 msg->msg[i] = val & 0xff; 1686 msg->msg[i + 1] = (val >> 8) & 0xff; 1687 msg->msg[i + 2] = (val >> 16) & 0xff; 1688 msg->msg[i + 3] = (val >> 24) & 0xff; 1689 } 1690 } 1691 1692 static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv) 1693 { 1694 struct vc4_hdmi *vc4_hdmi = priv; 1695 u32 cntrl1; 1696 1697 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1); 1698 vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD; 1699 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 1700 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 1701 1702 return IRQ_WAKE_THREAD; 1703 } 1704 1705 static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv) 1706 { 1707 struct vc4_hdmi *vc4_hdmi = priv; 1708 u32 cntrl1; 1709 1710 vc4_hdmi->cec_rx_msg.len = 0; 1711 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1); 1712 vc4_cec_read_msg(vc4_hdmi, cntrl1); 1713 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 1714 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 1715 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 1716 1717 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 1718 1719 return IRQ_WAKE_THREAD; 1720 } 1721 1722 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv) 1723 { 1724 struct vc4_hdmi *vc4_hdmi = priv; 1725 u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS); 1726 irqreturn_t ret; 1727 u32 cntrl5; 1728 1729 if (!(stat & VC4_HDMI_CPU_CEC)) 1730 return IRQ_NONE; 1731 1732 cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5); 1733 vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT; 1734 if (vc4_hdmi->cec_irq_was_rx) 1735 ret = vc4_cec_irq_handler_rx_bare(irq, priv); 1736 else 1737 ret = vc4_cec_irq_handler_tx_bare(irq, priv); 1738 1739 HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC); 1740 return ret; 1741 } 1742 1743 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable) 1744 { 1745 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 1746 /* clock period in microseconds */ 1747 const u32 usecs = 1000000 / CEC_CLOCK_FREQ; 1748 u32 val = HDMI_READ(HDMI_CEC_CNTRL_5); 1749 1750 val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET | 1751 VC4_HDMI_CEC_CNT_TO_4700_US_MASK | 1752 VC4_HDMI_CEC_CNT_TO_4500_US_MASK); 1753 val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) | 1754 ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT); 1755 1756 if (enable) { 1757 HDMI_WRITE(HDMI_CEC_CNTRL_5, val | 1758 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 1759 HDMI_WRITE(HDMI_CEC_CNTRL_5, val); 1760 HDMI_WRITE(HDMI_CEC_CNTRL_2, 1761 ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) | 1762 ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) | 1763 ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) | 1764 ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) | 1765 ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT)); 1766 HDMI_WRITE(HDMI_CEC_CNTRL_3, 1767 ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) | 1768 ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) | 1769 ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) | 1770 ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT)); 1771 HDMI_WRITE(HDMI_CEC_CNTRL_4, 1772 ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) | 1773 ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) | 1774 ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) | 1775 ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT)); 1776 1777 if (!vc4_hdmi->variant->external_irq_controller) 1778 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC); 1779 } else { 1780 if (!vc4_hdmi->variant->external_irq_controller) 1781 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC); 1782 HDMI_WRITE(HDMI_CEC_CNTRL_5, val | 1783 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 1784 } 1785 return 0; 1786 } 1787 1788 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr) 1789 { 1790 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 1791 1792 HDMI_WRITE(HDMI_CEC_CNTRL_1, 1793 (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) | 1794 (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT); 1795 return 0; 1796 } 1797 1798 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts, 1799 u32 signal_free_time, struct cec_msg *msg) 1800 { 1801 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 1802 struct drm_device *dev = vc4_hdmi->connector.dev; 1803 u32 val; 1804 unsigned int i; 1805 1806 if (msg->len > 16) { 1807 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len); 1808 return -ENOMEM; 1809 } 1810 1811 for (i = 0; i < msg->len; i += 4) 1812 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2), 1813 (msg->msg[i]) | 1814 (msg->msg[i + 1] << 8) | 1815 (msg->msg[i + 2] << 16) | 1816 (msg->msg[i + 3] << 24)); 1817 1818 val = HDMI_READ(HDMI_CEC_CNTRL_1); 1819 val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 1820 HDMI_WRITE(HDMI_CEC_CNTRL_1, val); 1821 val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK; 1822 val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT; 1823 val |= VC4_HDMI_CEC_START_XMIT_BEGIN; 1824 1825 HDMI_WRITE(HDMI_CEC_CNTRL_1, val); 1826 return 0; 1827 } 1828 1829 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = { 1830 .adap_enable = vc4_hdmi_cec_adap_enable, 1831 .adap_log_addr = vc4_hdmi_cec_adap_log_addr, 1832 .adap_transmit = vc4_hdmi_cec_adap_transmit, 1833 }; 1834 1835 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi) 1836 { 1837 struct cec_connector_info conn_info; 1838 struct platform_device *pdev = vc4_hdmi->pdev; 1839 struct device *dev = &pdev->dev; 1840 u32 value; 1841 int ret; 1842 1843 if (!of_find_property(dev->of_node, "interrupts", NULL)) { 1844 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n"); 1845 return 0; 1846 } 1847 1848 vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops, 1849 vc4_hdmi, "vc4", 1850 CEC_CAP_DEFAULTS | 1851 CEC_CAP_CONNECTOR_INFO, 1); 1852 ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap); 1853 if (ret < 0) 1854 return ret; 1855 1856 cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector); 1857 cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info); 1858 1859 value = HDMI_READ(HDMI_CEC_CNTRL_1); 1860 /* Set the logical address to Unregistered */ 1861 value |= VC4_HDMI_CEC_ADDR_MASK; 1862 HDMI_WRITE(HDMI_CEC_CNTRL_1, value); 1863 1864 vc4_hdmi_cec_update_clk_div(vc4_hdmi); 1865 1866 if (vc4_hdmi->variant->external_irq_controller) { 1867 ret = devm_request_threaded_irq(&pdev->dev, 1868 platform_get_irq_byname(pdev, "cec-rx"), 1869 vc4_cec_irq_handler_rx_bare, 1870 vc4_cec_irq_handler_rx_thread, 0, 1871 "vc4 hdmi cec rx", vc4_hdmi); 1872 if (ret) 1873 goto err_delete_cec_adap; 1874 1875 ret = devm_request_threaded_irq(&pdev->dev, 1876 platform_get_irq_byname(pdev, "cec-tx"), 1877 vc4_cec_irq_handler_tx_bare, 1878 vc4_cec_irq_handler_tx_thread, 0, 1879 "vc4 hdmi cec tx", vc4_hdmi); 1880 if (ret) 1881 goto err_delete_cec_adap; 1882 } else { 1883 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff); 1884 1885 ret = devm_request_threaded_irq(&pdev->dev, platform_get_irq(pdev, 0), 1886 vc4_cec_irq_handler, 1887 vc4_cec_irq_handler_thread, 0, 1888 "vc4 hdmi cec", vc4_hdmi); 1889 if (ret) 1890 goto err_delete_cec_adap; 1891 } 1892 1893 ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev); 1894 if (ret < 0) 1895 goto err_delete_cec_adap; 1896 1897 return 0; 1898 1899 err_delete_cec_adap: 1900 cec_delete_adapter(vc4_hdmi->cec_adap); 1901 1902 return ret; 1903 } 1904 1905 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi) 1906 { 1907 cec_unregister_adapter(vc4_hdmi->cec_adap); 1908 } 1909 #else 1910 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi) 1911 { 1912 return 0; 1913 } 1914 1915 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi) {}; 1916 1917 #endif 1918 1919 static int vc4_hdmi_build_regset(struct vc4_hdmi *vc4_hdmi, 1920 struct debugfs_regset32 *regset, 1921 enum vc4_hdmi_regs reg) 1922 { 1923 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant; 1924 struct debugfs_reg32 *regs, *new_regs; 1925 unsigned int count = 0; 1926 unsigned int i; 1927 1928 regs = kcalloc(variant->num_registers, sizeof(*regs), 1929 GFP_KERNEL); 1930 if (!regs) 1931 return -ENOMEM; 1932 1933 for (i = 0; i < variant->num_registers; i++) { 1934 const struct vc4_hdmi_register *field = &variant->registers[i]; 1935 1936 if (field->reg != reg) 1937 continue; 1938 1939 regs[count].name = field->name; 1940 regs[count].offset = field->offset; 1941 count++; 1942 } 1943 1944 new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL); 1945 if (!new_regs) 1946 return -ENOMEM; 1947 1948 regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg); 1949 regset->regs = new_regs; 1950 regset->nregs = count; 1951 1952 return 0; 1953 } 1954 1955 static int vc4_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi) 1956 { 1957 struct platform_device *pdev = vc4_hdmi->pdev; 1958 struct device *dev = &pdev->dev; 1959 int ret; 1960 1961 vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0); 1962 if (IS_ERR(vc4_hdmi->hdmicore_regs)) 1963 return PTR_ERR(vc4_hdmi->hdmicore_regs); 1964 1965 vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1); 1966 if (IS_ERR(vc4_hdmi->hd_regs)) 1967 return PTR_ERR(vc4_hdmi->hd_regs); 1968 1969 ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD); 1970 if (ret) 1971 return ret; 1972 1973 ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI); 1974 if (ret) 1975 return ret; 1976 1977 vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel"); 1978 if (IS_ERR(vc4_hdmi->pixel_clock)) { 1979 ret = PTR_ERR(vc4_hdmi->pixel_clock); 1980 if (ret != -EPROBE_DEFER) 1981 DRM_ERROR("Failed to get pixel clock\n"); 1982 return ret; 1983 } 1984 1985 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); 1986 if (IS_ERR(vc4_hdmi->hsm_clock)) { 1987 DRM_ERROR("Failed to get HDMI state machine clock\n"); 1988 return PTR_ERR(vc4_hdmi->hsm_clock); 1989 } 1990 vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock; 1991 vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock; 1992 1993 return 0; 1994 } 1995 1996 static int vc5_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi) 1997 { 1998 struct platform_device *pdev = vc4_hdmi->pdev; 1999 struct device *dev = &pdev->dev; 2000 struct resource *res; 2001 2002 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi"); 2003 if (!res) 2004 return -ENODEV; 2005 2006 vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start, 2007 resource_size(res)); 2008 if (!vc4_hdmi->hdmicore_regs) 2009 return -ENOMEM; 2010 2011 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd"); 2012 if (!res) 2013 return -ENODEV; 2014 2015 vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res)); 2016 if (!vc4_hdmi->hd_regs) 2017 return -ENOMEM; 2018 2019 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec"); 2020 if (!res) 2021 return -ENODEV; 2022 2023 vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res)); 2024 if (!vc4_hdmi->cec_regs) 2025 return -ENOMEM; 2026 2027 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc"); 2028 if (!res) 2029 return -ENODEV; 2030 2031 vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res)); 2032 if (!vc4_hdmi->csc_regs) 2033 return -ENOMEM; 2034 2035 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp"); 2036 if (!res) 2037 return -ENODEV; 2038 2039 vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res)); 2040 if (!vc4_hdmi->dvp_regs) 2041 return -ENOMEM; 2042 2043 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy"); 2044 if (!res) 2045 return -ENODEV; 2046 2047 vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res)); 2048 if (!vc4_hdmi->phy_regs) 2049 return -ENOMEM; 2050 2051 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet"); 2052 if (!res) 2053 return -ENODEV; 2054 2055 vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res)); 2056 if (!vc4_hdmi->ram_regs) 2057 return -ENOMEM; 2058 2059 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm"); 2060 if (!res) 2061 return -ENODEV; 2062 2063 vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res)); 2064 if (!vc4_hdmi->rm_regs) 2065 return -ENOMEM; 2066 2067 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); 2068 if (IS_ERR(vc4_hdmi->hsm_clock)) { 2069 DRM_ERROR("Failed to get HDMI state machine clock\n"); 2070 return PTR_ERR(vc4_hdmi->hsm_clock); 2071 } 2072 2073 vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb"); 2074 if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) { 2075 DRM_ERROR("Failed to get pixel bvb clock\n"); 2076 return PTR_ERR(vc4_hdmi->pixel_bvb_clock); 2077 } 2078 2079 vc4_hdmi->audio_clock = devm_clk_get(dev, "audio"); 2080 if (IS_ERR(vc4_hdmi->audio_clock)) { 2081 DRM_ERROR("Failed to get audio clock\n"); 2082 return PTR_ERR(vc4_hdmi->audio_clock); 2083 } 2084 2085 vc4_hdmi->cec_clock = devm_clk_get(dev, "cec"); 2086 if (IS_ERR(vc4_hdmi->cec_clock)) { 2087 DRM_ERROR("Failed to get CEC clock\n"); 2088 return PTR_ERR(vc4_hdmi->cec_clock); 2089 } 2090 2091 vc4_hdmi->reset = devm_reset_control_get(dev, NULL); 2092 if (IS_ERR(vc4_hdmi->reset)) { 2093 DRM_ERROR("Failed to get HDMI reset line\n"); 2094 return PTR_ERR(vc4_hdmi->reset); 2095 } 2096 2097 return 0; 2098 } 2099 2100 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data) 2101 { 2102 const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev); 2103 struct platform_device *pdev = to_platform_device(dev); 2104 struct drm_device *drm = dev_get_drvdata(master); 2105 struct vc4_hdmi *vc4_hdmi; 2106 struct drm_encoder *encoder; 2107 struct device_node *ddc_node; 2108 u32 value; 2109 int ret; 2110 2111 vc4_hdmi = devm_kzalloc(dev, sizeof(*vc4_hdmi), GFP_KERNEL); 2112 if (!vc4_hdmi) 2113 return -ENOMEM; 2114 INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq); 2115 2116 dev_set_drvdata(dev, vc4_hdmi); 2117 encoder = &vc4_hdmi->encoder.base.base; 2118 vc4_hdmi->encoder.base.type = variant->encoder_type; 2119 vc4_hdmi->encoder.base.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure; 2120 vc4_hdmi->encoder.base.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable; 2121 vc4_hdmi->encoder.base.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable; 2122 vc4_hdmi->encoder.base.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable; 2123 vc4_hdmi->encoder.base.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown; 2124 vc4_hdmi->pdev = pdev; 2125 vc4_hdmi->variant = variant; 2126 2127 ret = variant->init_resources(vc4_hdmi); 2128 if (ret) 2129 return ret; 2130 2131 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0); 2132 if (!ddc_node) { 2133 DRM_ERROR("Failed to find ddc node in device tree\n"); 2134 return -ENODEV; 2135 } 2136 2137 vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node); 2138 of_node_put(ddc_node); 2139 if (!vc4_hdmi->ddc) { 2140 DRM_DEBUG("Failed to get ddc i2c adapter by node\n"); 2141 return -EPROBE_DEFER; 2142 } 2143 2144 /* Only use the GPIO HPD pin if present in the DT, otherwise 2145 * we'll use the HDMI core's register. 2146 */ 2147 if (of_find_property(dev->of_node, "hpd-gpios", &value)) { 2148 enum of_gpio_flags hpd_gpio_flags; 2149 2150 vc4_hdmi->hpd_gpio = of_get_named_gpio_flags(dev->of_node, 2151 "hpd-gpios", 0, 2152 &hpd_gpio_flags); 2153 if (vc4_hdmi->hpd_gpio < 0) { 2154 ret = vc4_hdmi->hpd_gpio; 2155 goto err_unprepare_hsm; 2156 } 2157 2158 vc4_hdmi->hpd_active_low = hpd_gpio_flags & OF_GPIO_ACTIVE_LOW; 2159 } 2160 2161 vc4_hdmi->disable_wifi_frequencies = 2162 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence"); 2163 2164 if (variant->max_pixel_clock == 600000000) { 2165 struct vc4_dev *vc4 = to_vc4_dev(drm); 2166 long max_rate = clk_round_rate(vc4->hvs->core_clk, 550000000); 2167 2168 if (max_rate < 550000000) 2169 vc4_hdmi->disable_4kp60 = true; 2170 } 2171 2172 if (vc4_hdmi->variant->reset) 2173 vc4_hdmi->variant->reset(vc4_hdmi); 2174 2175 if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") || 2176 of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1")) && 2177 HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) { 2178 clk_prepare_enable(vc4_hdmi->pixel_clock); 2179 clk_prepare_enable(vc4_hdmi->hsm_clock); 2180 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock); 2181 } 2182 2183 pm_runtime_enable(dev); 2184 2185 drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS); 2186 drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs); 2187 2188 ret = vc4_hdmi_connector_init(drm, vc4_hdmi); 2189 if (ret) 2190 goto err_destroy_encoder; 2191 2192 ret = vc4_hdmi_cec_init(vc4_hdmi); 2193 if (ret) 2194 goto err_destroy_conn; 2195 2196 ret = vc4_hdmi_audio_init(vc4_hdmi); 2197 if (ret) 2198 goto err_free_cec; 2199 2200 vc4_debugfs_add_file(drm, variant->debugfs_name, 2201 vc4_hdmi_debugfs_regs, 2202 vc4_hdmi); 2203 2204 return 0; 2205 2206 err_free_cec: 2207 vc4_hdmi_cec_exit(vc4_hdmi); 2208 err_destroy_conn: 2209 vc4_hdmi_connector_destroy(&vc4_hdmi->connector); 2210 err_destroy_encoder: 2211 drm_encoder_cleanup(encoder); 2212 err_unprepare_hsm: 2213 pm_runtime_disable(dev); 2214 put_device(&vc4_hdmi->ddc->dev); 2215 2216 return ret; 2217 } 2218 2219 static void vc4_hdmi_unbind(struct device *dev, struct device *master, 2220 void *data) 2221 { 2222 struct vc4_hdmi *vc4_hdmi; 2223 2224 /* 2225 * ASoC makes it a bit hard to retrieve a pointer to the 2226 * vc4_hdmi structure. Registering the card will overwrite our 2227 * device drvdata with a pointer to the snd_soc_card structure, 2228 * which can then be used to retrieve whatever drvdata we want 2229 * to associate. 2230 * 2231 * However, that doesn't fly in the case where we wouldn't 2232 * register an ASoC card (because of an old DT that is missing 2233 * the dmas properties for example), then the card isn't 2234 * registered and the device drvdata wouldn't be set. 2235 * 2236 * We can deal with both cases by making sure a snd_soc_card 2237 * pointer and a vc4_hdmi structure are pointing to the same 2238 * memory address, so we can treat them indistinctly without any 2239 * issue. 2240 */ 2241 BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0); 2242 BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0); 2243 vc4_hdmi = dev_get_drvdata(dev); 2244 2245 kfree(vc4_hdmi->hdmi_regset.regs); 2246 kfree(vc4_hdmi->hd_regset.regs); 2247 2248 vc4_hdmi_cec_exit(vc4_hdmi); 2249 vc4_hdmi_connector_destroy(&vc4_hdmi->connector); 2250 drm_encoder_cleanup(&vc4_hdmi->encoder.base.base); 2251 2252 pm_runtime_disable(dev); 2253 2254 put_device(&vc4_hdmi->ddc->dev); 2255 } 2256 2257 static const struct component_ops vc4_hdmi_ops = { 2258 .bind = vc4_hdmi_bind, 2259 .unbind = vc4_hdmi_unbind, 2260 }; 2261 2262 static int vc4_hdmi_dev_probe(struct platform_device *pdev) 2263 { 2264 return component_add(&pdev->dev, &vc4_hdmi_ops); 2265 } 2266 2267 static int vc4_hdmi_dev_remove(struct platform_device *pdev) 2268 { 2269 component_del(&pdev->dev, &vc4_hdmi_ops); 2270 return 0; 2271 } 2272 2273 static const struct vc4_hdmi_variant bcm2835_variant = { 2274 .encoder_type = VC4_ENCODER_TYPE_HDMI0, 2275 .debugfs_name = "hdmi_regs", 2276 .card_name = "vc4-hdmi", 2277 .max_pixel_clock = 162000000, 2278 .registers = vc4_hdmi_fields, 2279 .num_registers = ARRAY_SIZE(vc4_hdmi_fields), 2280 2281 .init_resources = vc4_hdmi_init_resources, 2282 .csc_setup = vc4_hdmi_csc_setup, 2283 .reset = vc4_hdmi_reset, 2284 .set_timings = vc4_hdmi_set_timings, 2285 .phy_init = vc4_hdmi_phy_init, 2286 .phy_disable = vc4_hdmi_phy_disable, 2287 .phy_rng_enable = vc4_hdmi_phy_rng_enable, 2288 .phy_rng_disable = vc4_hdmi_phy_rng_disable, 2289 .channel_map = vc4_hdmi_channel_map, 2290 .supports_hdr = false, 2291 }; 2292 2293 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = { 2294 .encoder_type = VC4_ENCODER_TYPE_HDMI0, 2295 .debugfs_name = "hdmi0_regs", 2296 .card_name = "vc4-hdmi-0", 2297 .max_pixel_clock = HDMI_14_MAX_TMDS_CLK, 2298 .registers = vc5_hdmi_hdmi0_fields, 2299 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi0_fields), 2300 .phy_lane_mapping = { 2301 PHY_LANE_0, 2302 PHY_LANE_1, 2303 PHY_LANE_2, 2304 PHY_LANE_CK, 2305 }, 2306 .unsupported_odd_h_timings = true, 2307 .external_irq_controller = true, 2308 2309 .init_resources = vc5_hdmi_init_resources, 2310 .csc_setup = vc5_hdmi_csc_setup, 2311 .reset = vc5_hdmi_reset, 2312 .set_timings = vc5_hdmi_set_timings, 2313 .phy_init = vc5_hdmi_phy_init, 2314 .phy_disable = vc5_hdmi_phy_disable, 2315 .phy_rng_enable = vc5_hdmi_phy_rng_enable, 2316 .phy_rng_disable = vc5_hdmi_phy_rng_disable, 2317 .channel_map = vc5_hdmi_channel_map, 2318 .supports_hdr = true, 2319 }; 2320 2321 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = { 2322 .encoder_type = VC4_ENCODER_TYPE_HDMI1, 2323 .debugfs_name = "hdmi1_regs", 2324 .card_name = "vc4-hdmi-1", 2325 .max_pixel_clock = HDMI_14_MAX_TMDS_CLK, 2326 .registers = vc5_hdmi_hdmi1_fields, 2327 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi1_fields), 2328 .phy_lane_mapping = { 2329 PHY_LANE_1, 2330 PHY_LANE_0, 2331 PHY_LANE_CK, 2332 PHY_LANE_2, 2333 }, 2334 .unsupported_odd_h_timings = true, 2335 .external_irq_controller = true, 2336 2337 .init_resources = vc5_hdmi_init_resources, 2338 .csc_setup = vc5_hdmi_csc_setup, 2339 .reset = vc5_hdmi_reset, 2340 .set_timings = vc5_hdmi_set_timings, 2341 .phy_init = vc5_hdmi_phy_init, 2342 .phy_disable = vc5_hdmi_phy_disable, 2343 .phy_rng_enable = vc5_hdmi_phy_rng_enable, 2344 .phy_rng_disable = vc5_hdmi_phy_rng_disable, 2345 .channel_map = vc5_hdmi_channel_map, 2346 .supports_hdr = true, 2347 }; 2348 2349 static const struct of_device_id vc4_hdmi_dt_match[] = { 2350 { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant }, 2351 { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant }, 2352 { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant }, 2353 {} 2354 }; 2355 2356 struct platform_driver vc4_hdmi_driver = { 2357 .probe = vc4_hdmi_dev_probe, 2358 .remove = vc4_hdmi_dev_remove, 2359 .driver = { 2360 .name = "vc4_hdmi", 2361 .of_match_table = vc4_hdmi_dt_match, 2362 }, 2363 }; 2364