1 /* 2 * Copyright (C) 2015 Broadcom 3 * Copyright (c) 2014 The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License version 2 as published by 9 * the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 /** 21 * DOC: VC4 Falcon HDMI module 22 * 23 * The HDMI core has a state machine and a PHY. On BCM2835, most of 24 * the unit operates off of the HSM clock from CPRMAN. It also 25 * internally uses the PLLH_PIX clock for the PHY. 26 * 27 * HDMI infoframes are kept within a small packet ram, where each 28 * packet can be individually enabled for including in a frame. 29 * 30 * HDMI audio is implemented entirely within the HDMI IP block. A 31 * register in the HDMI encoder takes SPDIF frames from the DMA engine 32 * and transfers them over an internal MAI (multi-channel audio 33 * interconnect) bus to the encoder side for insertion into the video 34 * blank regions. 35 * 36 * The driver's HDMI encoder does not yet support power management. 37 * The HDMI encoder's power domain and the HSM/pixel clocks are kept 38 * continuously running, and only the HDMI logic and packet ram are 39 * powered off/on at disable/enable time. 40 * 41 * The driver does not yet support CEC control, though the HDMI 42 * encoder block has CEC support. 43 */ 44 45 #include <drm/drm_atomic_helper.h> 46 #include <drm/drm_edid.h> 47 #include <drm/drm_probe_helper.h> 48 #include <linux/clk.h> 49 #include <linux/component.h> 50 #include <linux/i2c.h> 51 #include <linux/of_address.h> 52 #include <linux/of_gpio.h> 53 #include <linux/of_platform.h> 54 #include <linux/pm_runtime.h> 55 #include <linux/rational.h> 56 #include <sound/dmaengine_pcm.h> 57 #include <sound/pcm_drm_eld.h> 58 #include <sound/pcm_params.h> 59 #include <sound/soc.h> 60 #include "media/cec.h" 61 #include "vc4_drv.h" 62 #include "vc4_regs.h" 63 64 #define HSM_CLOCK_FREQ 163682864 65 #define CEC_CLOCK_FREQ 40000 66 #define CEC_CLOCK_DIV (HSM_CLOCK_FREQ / CEC_CLOCK_FREQ) 67 68 /* HDMI audio information */ 69 struct vc4_hdmi_audio { 70 struct snd_soc_card card; 71 struct snd_soc_dai_link link; 72 int samplerate; 73 int channels; 74 struct snd_dmaengine_dai_dma_data dma_data; 75 struct snd_pcm_substream *substream; 76 }; 77 78 /* General HDMI hardware state. */ 79 struct vc4_hdmi { 80 struct platform_device *pdev; 81 82 struct drm_encoder *encoder; 83 struct drm_connector *connector; 84 85 struct vc4_hdmi_audio audio; 86 87 struct i2c_adapter *ddc; 88 void __iomem *hdmicore_regs; 89 void __iomem *hd_regs; 90 int hpd_gpio; 91 bool hpd_active_low; 92 93 struct cec_adapter *cec_adap; 94 struct cec_msg cec_rx_msg; 95 bool cec_tx_ok; 96 bool cec_irq_was_rx; 97 98 struct clk *pixel_clock; 99 struct clk *hsm_clock; 100 101 struct debugfs_regset32 hdmi_regset; 102 struct debugfs_regset32 hd_regset; 103 }; 104 105 #define HDMI_READ(offset) readl(vc4->hdmi->hdmicore_regs + offset) 106 #define HDMI_WRITE(offset, val) writel(val, vc4->hdmi->hdmicore_regs + offset) 107 #define HD_READ(offset) readl(vc4->hdmi->hd_regs + offset) 108 #define HD_WRITE(offset, val) writel(val, vc4->hdmi->hd_regs + offset) 109 110 /* VC4 HDMI encoder KMS struct */ 111 struct vc4_hdmi_encoder { 112 struct vc4_encoder base; 113 bool hdmi_monitor; 114 bool limited_rgb_range; 115 }; 116 117 static inline struct vc4_hdmi_encoder * 118 to_vc4_hdmi_encoder(struct drm_encoder *encoder) 119 { 120 return container_of(encoder, struct vc4_hdmi_encoder, base.base); 121 } 122 123 /* VC4 HDMI connector KMS struct */ 124 struct vc4_hdmi_connector { 125 struct drm_connector base; 126 127 /* Since the connector is attached to just the one encoder, 128 * this is the reference to it so we can do the best_encoder() 129 * hook. 130 */ 131 struct drm_encoder *encoder; 132 }; 133 134 static inline struct vc4_hdmi_connector * 135 to_vc4_hdmi_connector(struct drm_connector *connector) 136 { 137 return container_of(connector, struct vc4_hdmi_connector, base); 138 } 139 140 static const struct debugfs_reg32 hdmi_regs[] = { 141 VC4_REG32(VC4_HDMI_CORE_REV), 142 VC4_REG32(VC4_HDMI_SW_RESET_CONTROL), 143 VC4_REG32(VC4_HDMI_HOTPLUG_INT), 144 VC4_REG32(VC4_HDMI_HOTPLUG), 145 VC4_REG32(VC4_HDMI_MAI_CHANNEL_MAP), 146 VC4_REG32(VC4_HDMI_MAI_CONFIG), 147 VC4_REG32(VC4_HDMI_MAI_FORMAT), 148 VC4_REG32(VC4_HDMI_AUDIO_PACKET_CONFIG), 149 VC4_REG32(VC4_HDMI_RAM_PACKET_CONFIG), 150 VC4_REG32(VC4_HDMI_HORZA), 151 VC4_REG32(VC4_HDMI_HORZB), 152 VC4_REG32(VC4_HDMI_FIFO_CTL), 153 VC4_REG32(VC4_HDMI_SCHEDULER_CONTROL), 154 VC4_REG32(VC4_HDMI_VERTA0), 155 VC4_REG32(VC4_HDMI_VERTA1), 156 VC4_REG32(VC4_HDMI_VERTB0), 157 VC4_REG32(VC4_HDMI_VERTB1), 158 VC4_REG32(VC4_HDMI_TX_PHY_RESET_CTL), 159 VC4_REG32(VC4_HDMI_TX_PHY_CTL0), 160 161 VC4_REG32(VC4_HDMI_CEC_CNTRL_1), 162 VC4_REG32(VC4_HDMI_CEC_CNTRL_2), 163 VC4_REG32(VC4_HDMI_CEC_CNTRL_3), 164 VC4_REG32(VC4_HDMI_CEC_CNTRL_4), 165 VC4_REG32(VC4_HDMI_CEC_CNTRL_5), 166 VC4_REG32(VC4_HDMI_CPU_STATUS), 167 VC4_REG32(VC4_HDMI_CPU_MASK_STATUS), 168 169 VC4_REG32(VC4_HDMI_CEC_RX_DATA_1), 170 VC4_REG32(VC4_HDMI_CEC_RX_DATA_2), 171 VC4_REG32(VC4_HDMI_CEC_RX_DATA_3), 172 VC4_REG32(VC4_HDMI_CEC_RX_DATA_4), 173 VC4_REG32(VC4_HDMI_CEC_TX_DATA_1), 174 VC4_REG32(VC4_HDMI_CEC_TX_DATA_2), 175 VC4_REG32(VC4_HDMI_CEC_TX_DATA_3), 176 VC4_REG32(VC4_HDMI_CEC_TX_DATA_4), 177 }; 178 179 static const struct debugfs_reg32 hd_regs[] = { 180 VC4_REG32(VC4_HD_M_CTL), 181 VC4_REG32(VC4_HD_MAI_CTL), 182 VC4_REG32(VC4_HD_MAI_THR), 183 VC4_REG32(VC4_HD_MAI_FMT), 184 VC4_REG32(VC4_HD_MAI_SMP), 185 VC4_REG32(VC4_HD_VID_CTL), 186 VC4_REG32(VC4_HD_CSC_CTL), 187 VC4_REG32(VC4_HD_FRAME_COUNT), 188 }; 189 190 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused) 191 { 192 struct drm_info_node *node = (struct drm_info_node *)m->private; 193 struct drm_device *dev = node->minor->dev; 194 struct vc4_dev *vc4 = to_vc4_dev(dev); 195 struct vc4_hdmi *hdmi = vc4->hdmi; 196 struct drm_printer p = drm_seq_file_printer(m); 197 198 drm_print_regset32(&p, &hdmi->hdmi_regset); 199 drm_print_regset32(&p, &hdmi->hd_regset); 200 201 return 0; 202 } 203 204 static enum drm_connector_status 205 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force) 206 { 207 struct drm_device *dev = connector->dev; 208 struct vc4_dev *vc4 = to_vc4_dev(dev); 209 210 if (vc4->hdmi->hpd_gpio) { 211 if (gpio_get_value_cansleep(vc4->hdmi->hpd_gpio) ^ 212 vc4->hdmi->hpd_active_low) 213 return connector_status_connected; 214 cec_phys_addr_invalidate(vc4->hdmi->cec_adap); 215 return connector_status_disconnected; 216 } 217 218 if (drm_probe_ddc(vc4->hdmi->ddc)) 219 return connector_status_connected; 220 221 if (HDMI_READ(VC4_HDMI_HOTPLUG) & VC4_HDMI_HOTPLUG_CONNECTED) 222 return connector_status_connected; 223 cec_phys_addr_invalidate(vc4->hdmi->cec_adap); 224 return connector_status_disconnected; 225 } 226 227 static void vc4_hdmi_connector_destroy(struct drm_connector *connector) 228 { 229 drm_connector_unregister(connector); 230 drm_connector_cleanup(connector); 231 } 232 233 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector) 234 { 235 struct vc4_hdmi_connector *vc4_connector = 236 to_vc4_hdmi_connector(connector); 237 struct drm_encoder *encoder = vc4_connector->encoder; 238 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 239 struct drm_device *dev = connector->dev; 240 struct vc4_dev *vc4 = to_vc4_dev(dev); 241 int ret = 0; 242 struct edid *edid; 243 244 edid = drm_get_edid(connector, vc4->hdmi->ddc); 245 cec_s_phys_addr_from_edid(vc4->hdmi->cec_adap, edid); 246 if (!edid) 247 return -ENODEV; 248 249 vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid); 250 251 drm_connector_update_edid_property(connector, edid); 252 ret = drm_add_edid_modes(connector, edid); 253 kfree(edid); 254 255 return ret; 256 } 257 258 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = { 259 .detect = vc4_hdmi_connector_detect, 260 .fill_modes = drm_helper_probe_single_connector_modes, 261 .destroy = vc4_hdmi_connector_destroy, 262 .reset = drm_atomic_helper_connector_reset, 263 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 264 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 265 }; 266 267 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = { 268 .get_modes = vc4_hdmi_connector_get_modes, 269 }; 270 271 static struct drm_connector *vc4_hdmi_connector_init(struct drm_device *dev, 272 struct drm_encoder *encoder) 273 { 274 struct drm_connector *connector; 275 struct vc4_hdmi_connector *hdmi_connector; 276 int ret; 277 278 hdmi_connector = devm_kzalloc(dev->dev, sizeof(*hdmi_connector), 279 GFP_KERNEL); 280 if (!hdmi_connector) 281 return ERR_PTR(-ENOMEM); 282 connector = &hdmi_connector->base; 283 284 hdmi_connector->encoder = encoder; 285 286 drm_connector_init(dev, connector, &vc4_hdmi_connector_funcs, 287 DRM_MODE_CONNECTOR_HDMIA); 288 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs); 289 290 /* Create and attach TV margin props to this connector. */ 291 ret = drm_mode_create_tv_margin_properties(dev); 292 if (ret) 293 return ERR_PTR(ret); 294 295 drm_connector_attach_tv_margin_properties(connector); 296 297 connector->polled = (DRM_CONNECTOR_POLL_CONNECT | 298 DRM_CONNECTOR_POLL_DISCONNECT); 299 300 connector->interlace_allowed = 1; 301 connector->doublescan_allowed = 0; 302 303 drm_connector_attach_encoder(connector, encoder); 304 305 return connector; 306 } 307 308 static void vc4_hdmi_encoder_destroy(struct drm_encoder *encoder) 309 { 310 drm_encoder_cleanup(encoder); 311 } 312 313 static const struct drm_encoder_funcs vc4_hdmi_encoder_funcs = { 314 .destroy = vc4_hdmi_encoder_destroy, 315 }; 316 317 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder, 318 enum hdmi_infoframe_type type) 319 { 320 struct drm_device *dev = encoder->dev; 321 struct vc4_dev *vc4 = to_vc4_dev(dev); 322 u32 packet_id = type - 0x80; 323 324 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, 325 HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id)); 326 327 return wait_for(!(HDMI_READ(VC4_HDMI_RAM_PACKET_STATUS) & 328 BIT(packet_id)), 100); 329 } 330 331 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder, 332 union hdmi_infoframe *frame) 333 { 334 struct drm_device *dev = encoder->dev; 335 struct vc4_dev *vc4 = to_vc4_dev(dev); 336 u32 packet_id = frame->any.type - 0x80; 337 u32 packet_reg = VC4_HDMI_RAM_PACKET(packet_id); 338 uint8_t buffer[VC4_HDMI_PACKET_STRIDE]; 339 ssize_t len, i; 340 int ret; 341 342 WARN_ONCE(!(HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) & 343 VC4_HDMI_RAM_PACKET_ENABLE), 344 "Packet RAM has to be on to store the packet."); 345 346 len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer)); 347 if (len < 0) 348 return; 349 350 ret = vc4_hdmi_stop_packet(encoder, frame->any.type); 351 if (ret) { 352 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret); 353 return; 354 } 355 356 for (i = 0; i < len; i += 7) { 357 HDMI_WRITE(packet_reg, 358 buffer[i + 0] << 0 | 359 buffer[i + 1] << 8 | 360 buffer[i + 2] << 16); 361 packet_reg += 4; 362 363 HDMI_WRITE(packet_reg, 364 buffer[i + 3] << 0 | 365 buffer[i + 4] << 8 | 366 buffer[i + 5] << 16 | 367 buffer[i + 6] << 24); 368 packet_reg += 4; 369 } 370 371 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, 372 HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) | BIT(packet_id)); 373 ret = wait_for((HDMI_READ(VC4_HDMI_RAM_PACKET_STATUS) & 374 BIT(packet_id)), 100); 375 if (ret) 376 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret); 377 } 378 379 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder) 380 { 381 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 382 struct vc4_dev *vc4 = encoder->dev->dev_private; 383 struct vc4_hdmi *hdmi = vc4->hdmi; 384 struct drm_connector_state *cstate = hdmi->connector->state; 385 struct drm_crtc *crtc = encoder->crtc; 386 const struct drm_display_mode *mode = &crtc->state->adjusted_mode; 387 union hdmi_infoframe frame; 388 int ret; 389 390 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, 391 hdmi->connector, mode); 392 if (ret < 0) { 393 DRM_ERROR("couldn't fill AVI infoframe\n"); 394 return; 395 } 396 397 drm_hdmi_avi_infoframe_quant_range(&frame.avi, 398 hdmi->connector, mode, 399 vc4_encoder->limited_rgb_range ? 400 HDMI_QUANTIZATION_RANGE_LIMITED : 401 HDMI_QUANTIZATION_RANGE_FULL); 402 403 frame.avi.right_bar = cstate->tv.margins.right; 404 frame.avi.left_bar = cstate->tv.margins.left; 405 frame.avi.top_bar = cstate->tv.margins.top; 406 frame.avi.bottom_bar = cstate->tv.margins.bottom; 407 408 vc4_hdmi_write_infoframe(encoder, &frame); 409 } 410 411 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder) 412 { 413 union hdmi_infoframe frame; 414 int ret; 415 416 ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore"); 417 if (ret < 0) { 418 DRM_ERROR("couldn't fill SPD infoframe\n"); 419 return; 420 } 421 422 frame.spd.sdi = HDMI_SPD_SDI_PC; 423 424 vc4_hdmi_write_infoframe(encoder, &frame); 425 } 426 427 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder) 428 { 429 struct drm_device *drm = encoder->dev; 430 struct vc4_dev *vc4 = drm->dev_private; 431 struct vc4_hdmi *hdmi = vc4->hdmi; 432 union hdmi_infoframe frame; 433 int ret; 434 435 ret = hdmi_audio_infoframe_init(&frame.audio); 436 437 frame.audio.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM; 438 frame.audio.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM; 439 frame.audio.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM; 440 frame.audio.channels = hdmi->audio.channels; 441 442 vc4_hdmi_write_infoframe(encoder, &frame); 443 } 444 445 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder) 446 { 447 vc4_hdmi_set_avi_infoframe(encoder); 448 vc4_hdmi_set_spd_infoframe(encoder); 449 } 450 451 static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder) 452 { 453 struct drm_device *dev = encoder->dev; 454 struct vc4_dev *vc4 = to_vc4_dev(dev); 455 struct vc4_hdmi *hdmi = vc4->hdmi; 456 int ret; 457 458 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, 0); 459 460 HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16); 461 HD_WRITE(VC4_HD_VID_CTL, 462 HD_READ(VC4_HD_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE); 463 464 clk_disable_unprepare(hdmi->pixel_clock); 465 466 ret = pm_runtime_put(&hdmi->pdev->dev); 467 if (ret < 0) 468 DRM_ERROR("Failed to release power domain: %d\n", ret); 469 } 470 471 static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder) 472 { 473 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; 474 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 475 struct drm_device *dev = encoder->dev; 476 struct vc4_dev *vc4 = to_vc4_dev(dev); 477 struct vc4_hdmi *hdmi = vc4->hdmi; 478 bool debug_dump_regs = false; 479 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 480 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 481 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 482 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 483 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 484 VC4_HDMI_VERTA_VSP) | 485 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 486 VC4_HDMI_VERTA_VFP) | 487 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL)); 488 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 489 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end, 490 VC4_HDMI_VERTB_VBP)); 491 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 492 VC4_SET_FIELD(mode->crtc_vtotal - 493 mode->crtc_vsync_end - 494 interlaced, 495 VC4_HDMI_VERTB_VBP)); 496 u32 csc_ctl; 497 int ret; 498 499 ret = pm_runtime_get_sync(&hdmi->pdev->dev); 500 if (ret < 0) { 501 DRM_ERROR("Failed to retain power domain: %d\n", ret); 502 return; 503 } 504 505 ret = clk_set_rate(hdmi->pixel_clock, 506 mode->clock * 1000 * 507 ((mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1)); 508 if (ret) { 509 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret); 510 return; 511 } 512 513 ret = clk_prepare_enable(hdmi->pixel_clock); 514 if (ret) { 515 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret); 516 return; 517 } 518 519 HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL, 520 VC4_HDMI_SW_RESET_HDMI | 521 VC4_HDMI_SW_RESET_FORMAT_DETECT); 522 523 HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL, 0); 524 525 /* PHY should be in reset, like 526 * vc4_hdmi_encoder_disable() does. 527 */ 528 HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16); 529 530 HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0); 531 532 if (debug_dump_regs) { 533 struct drm_printer p = drm_info_printer(&hdmi->pdev->dev); 534 535 dev_info(&hdmi->pdev->dev, "HDMI regs before:\n"); 536 drm_print_regset32(&p, &hdmi->hdmi_regset); 537 drm_print_regset32(&p, &hdmi->hd_regset); 538 } 539 540 HD_WRITE(VC4_HD_VID_CTL, 0); 541 542 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL, 543 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) | 544 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT | 545 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS); 546 547 HDMI_WRITE(VC4_HDMI_HORZA, 548 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) | 549 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) | 550 VC4_SET_FIELD(mode->hdisplay * pixel_rep, 551 VC4_HDMI_HORZA_HAP)); 552 553 HDMI_WRITE(VC4_HDMI_HORZB, 554 VC4_SET_FIELD((mode->htotal - 555 mode->hsync_end) * pixel_rep, 556 VC4_HDMI_HORZB_HBP) | 557 VC4_SET_FIELD((mode->hsync_end - 558 mode->hsync_start) * pixel_rep, 559 VC4_HDMI_HORZB_HSP) | 560 VC4_SET_FIELD((mode->hsync_start - 561 mode->hdisplay) * pixel_rep, 562 VC4_HDMI_HORZB_HFP)); 563 564 HDMI_WRITE(VC4_HDMI_VERTA0, verta); 565 HDMI_WRITE(VC4_HDMI_VERTA1, verta); 566 567 HDMI_WRITE(VC4_HDMI_VERTB0, vertb_even); 568 HDMI_WRITE(VC4_HDMI_VERTB1, vertb); 569 570 HD_WRITE(VC4_HD_VID_CTL, 571 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) | 572 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW)); 573 574 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR, 575 VC4_HD_CSC_CTL_ORDER); 576 577 if (vc4_encoder->hdmi_monitor && 578 drm_default_rgb_quant_range(mode) == 579 HDMI_QUANTIZATION_RANGE_LIMITED) { 580 /* CEA VICs other than #1 requre limited range RGB 581 * output unless overridden by an AVI infoframe. 582 * Apply a colorspace conversion to squash 0-255 down 583 * to 16-235. The matrix here is: 584 * 585 * [ 0 0 0.8594 16] 586 * [ 0 0.8594 0 16] 587 * [ 0.8594 0 0 16] 588 * [ 0 0 0 1] 589 */ 590 csc_ctl |= VC4_HD_CSC_CTL_ENABLE; 591 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC; 592 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM, 593 VC4_HD_CSC_CTL_MODE); 594 595 HD_WRITE(VC4_HD_CSC_12_11, (0x000 << 16) | 0x000); 596 HD_WRITE(VC4_HD_CSC_14_13, (0x100 << 16) | 0x6e0); 597 HD_WRITE(VC4_HD_CSC_22_21, (0x6e0 << 16) | 0x000); 598 HD_WRITE(VC4_HD_CSC_24_23, (0x100 << 16) | 0x000); 599 HD_WRITE(VC4_HD_CSC_32_31, (0x000 << 16) | 0x6e0); 600 HD_WRITE(VC4_HD_CSC_34_33, (0x100 << 16) | 0x000); 601 vc4_encoder->limited_rgb_range = true; 602 } else { 603 vc4_encoder->limited_rgb_range = false; 604 } 605 606 /* The RGB order applies even when CSC is disabled. */ 607 HD_WRITE(VC4_HD_CSC_CTL, csc_ctl); 608 609 HDMI_WRITE(VC4_HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N); 610 611 if (debug_dump_regs) { 612 struct drm_printer p = drm_info_printer(&hdmi->pdev->dev); 613 614 dev_info(&hdmi->pdev->dev, "HDMI regs after:\n"); 615 drm_print_regset32(&p, &hdmi->hdmi_regset); 616 drm_print_regset32(&p, &hdmi->hd_regset); 617 } 618 619 HD_WRITE(VC4_HD_VID_CTL, 620 HD_READ(VC4_HD_VID_CTL) | 621 VC4_HD_VID_CTL_ENABLE | 622 VC4_HD_VID_CTL_UNDERFLOW_ENABLE | 623 VC4_HD_VID_CTL_FRAME_COUNTER_RESET); 624 625 if (vc4_encoder->hdmi_monitor) { 626 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL, 627 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) | 628 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 629 630 ret = wait_for(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) & 631 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000); 632 WARN_ONCE(ret, "Timeout waiting for " 633 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 634 } else { 635 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, 636 HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) & 637 ~(VC4_HDMI_RAM_PACKET_ENABLE)); 638 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL, 639 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) & 640 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 641 642 ret = wait_for(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) & 643 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000); 644 WARN_ONCE(ret, "Timeout waiting for " 645 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 646 } 647 648 if (vc4_encoder->hdmi_monitor) { 649 u32 drift; 650 651 WARN_ON(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) & 652 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE)); 653 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL, 654 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) | 655 VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT); 656 657 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, 658 VC4_HDMI_RAM_PACKET_ENABLE); 659 660 vc4_hdmi_set_infoframes(encoder); 661 662 drift = HDMI_READ(VC4_HDMI_FIFO_CTL); 663 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK; 664 665 HDMI_WRITE(VC4_HDMI_FIFO_CTL, 666 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 667 HDMI_WRITE(VC4_HDMI_FIFO_CTL, 668 drift | VC4_HDMI_FIFO_CTL_RECENTER); 669 usleep_range(1000, 1100); 670 HDMI_WRITE(VC4_HDMI_FIFO_CTL, 671 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 672 HDMI_WRITE(VC4_HDMI_FIFO_CTL, 673 drift | VC4_HDMI_FIFO_CTL_RECENTER); 674 675 ret = wait_for(HDMI_READ(VC4_HDMI_FIFO_CTL) & 676 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1); 677 WARN_ONCE(ret, "Timeout waiting for " 678 "VC4_HDMI_FIFO_CTL_RECENTER_DONE"); 679 } 680 } 681 682 static enum drm_mode_status 683 vc4_hdmi_encoder_mode_valid(struct drm_encoder *crtc, 684 const struct drm_display_mode *mode) 685 { 686 /* HSM clock must be 108% of the pixel clock. Additionally, 687 * the AXI clock needs to be at least 25% of pixel clock, but 688 * HSM ends up being the limiting factor. 689 */ 690 if (mode->clock > HSM_CLOCK_FREQ / (1000 * 108 / 100)) 691 return MODE_CLOCK_HIGH; 692 693 return MODE_OK; 694 } 695 696 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = { 697 .mode_valid = vc4_hdmi_encoder_mode_valid, 698 .disable = vc4_hdmi_encoder_disable, 699 .enable = vc4_hdmi_encoder_enable, 700 }; 701 702 /* HDMI audio codec callbacks */ 703 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *hdmi) 704 { 705 struct drm_device *drm = hdmi->encoder->dev; 706 struct vc4_dev *vc4 = to_vc4_dev(drm); 707 u32 hsm_clock = clk_get_rate(hdmi->hsm_clock); 708 unsigned long n, m; 709 710 rational_best_approximation(hsm_clock, hdmi->audio.samplerate, 711 VC4_HD_MAI_SMP_N_MASK >> 712 VC4_HD_MAI_SMP_N_SHIFT, 713 (VC4_HD_MAI_SMP_M_MASK >> 714 VC4_HD_MAI_SMP_M_SHIFT) + 1, 715 &n, &m); 716 717 HD_WRITE(VC4_HD_MAI_SMP, 718 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) | 719 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M)); 720 } 721 722 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *hdmi) 723 { 724 struct drm_encoder *encoder = hdmi->encoder; 725 struct drm_crtc *crtc = encoder->crtc; 726 struct drm_device *drm = encoder->dev; 727 struct vc4_dev *vc4 = to_vc4_dev(drm); 728 const struct drm_display_mode *mode = &crtc->state->adjusted_mode; 729 u32 samplerate = hdmi->audio.samplerate; 730 u32 n, cts; 731 u64 tmp; 732 733 n = 128 * samplerate / 1000; 734 tmp = (u64)(mode->clock * 1000) * n; 735 do_div(tmp, 128 * samplerate); 736 cts = tmp; 737 738 HDMI_WRITE(VC4_HDMI_CRP_CFG, 739 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN | 740 VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N)); 741 742 /* 743 * We could get slightly more accurate clocks in some cases by 744 * providing a CTS_1 value. The two CTS values are alternated 745 * between based on the period fields 746 */ 747 HDMI_WRITE(VC4_HDMI_CTS_0, cts); 748 HDMI_WRITE(VC4_HDMI_CTS_1, cts); 749 } 750 751 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai) 752 { 753 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai); 754 755 return snd_soc_card_get_drvdata(card); 756 } 757 758 static int vc4_hdmi_audio_startup(struct snd_pcm_substream *substream, 759 struct snd_soc_dai *dai) 760 { 761 struct vc4_hdmi *hdmi = dai_to_hdmi(dai); 762 struct drm_encoder *encoder = hdmi->encoder; 763 struct vc4_dev *vc4 = to_vc4_dev(encoder->dev); 764 int ret; 765 766 if (hdmi->audio.substream && hdmi->audio.substream != substream) 767 return -EINVAL; 768 769 hdmi->audio.substream = substream; 770 771 /* 772 * If the HDMI encoder hasn't probed, or the encoder is 773 * currently in DVI mode, treat the codec dai as missing. 774 */ 775 if (!encoder->crtc || !(HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) & 776 VC4_HDMI_RAM_PACKET_ENABLE)) 777 return -ENODEV; 778 779 ret = snd_pcm_hw_constraint_eld(substream->runtime, 780 hdmi->connector->eld); 781 if (ret) 782 return ret; 783 784 return 0; 785 } 786 787 static int vc4_hdmi_audio_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 788 { 789 return 0; 790 } 791 792 static void vc4_hdmi_audio_reset(struct vc4_hdmi *hdmi) 793 { 794 struct drm_encoder *encoder = hdmi->encoder; 795 struct drm_device *drm = encoder->dev; 796 struct device *dev = &hdmi->pdev->dev; 797 struct vc4_dev *vc4 = to_vc4_dev(drm); 798 int ret; 799 800 ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO); 801 if (ret) 802 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret); 803 804 HD_WRITE(VC4_HD_MAI_CTL, VC4_HD_MAI_CTL_RESET); 805 HD_WRITE(VC4_HD_MAI_CTL, VC4_HD_MAI_CTL_ERRORF); 806 HD_WRITE(VC4_HD_MAI_CTL, VC4_HD_MAI_CTL_FLUSH); 807 } 808 809 static void vc4_hdmi_audio_shutdown(struct snd_pcm_substream *substream, 810 struct snd_soc_dai *dai) 811 { 812 struct vc4_hdmi *hdmi = dai_to_hdmi(dai); 813 814 if (substream != hdmi->audio.substream) 815 return; 816 817 vc4_hdmi_audio_reset(hdmi); 818 819 hdmi->audio.substream = NULL; 820 } 821 822 /* HDMI audio codec callbacks */ 823 static int vc4_hdmi_audio_hw_params(struct snd_pcm_substream *substream, 824 struct snd_pcm_hw_params *params, 825 struct snd_soc_dai *dai) 826 { 827 struct vc4_hdmi *hdmi = dai_to_hdmi(dai); 828 struct drm_encoder *encoder = hdmi->encoder; 829 struct drm_device *drm = encoder->dev; 830 struct device *dev = &hdmi->pdev->dev; 831 struct vc4_dev *vc4 = to_vc4_dev(drm); 832 u32 audio_packet_config, channel_mask; 833 u32 channel_map, i; 834 835 if (substream != hdmi->audio.substream) 836 return -EINVAL; 837 838 dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__, 839 params_rate(params), params_width(params), 840 params_channels(params)); 841 842 hdmi->audio.channels = params_channels(params); 843 hdmi->audio.samplerate = params_rate(params); 844 845 HD_WRITE(VC4_HD_MAI_CTL, 846 VC4_HD_MAI_CTL_RESET | 847 VC4_HD_MAI_CTL_FLUSH | 848 VC4_HD_MAI_CTL_DLATE | 849 VC4_HD_MAI_CTL_ERRORE | 850 VC4_HD_MAI_CTL_ERRORF); 851 852 vc4_hdmi_audio_set_mai_clock(hdmi); 853 854 audio_packet_config = 855 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT | 856 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS | 857 VC4_SET_FIELD(0xf, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER); 858 859 channel_mask = GENMASK(hdmi->audio.channels - 1, 0); 860 audio_packet_config |= VC4_SET_FIELD(channel_mask, 861 VC4_HDMI_AUDIO_PACKET_CEA_MASK); 862 863 /* Set the MAI threshold. This logic mimics the firmware's. */ 864 if (hdmi->audio.samplerate > 96000) { 865 HD_WRITE(VC4_HD_MAI_THR, 866 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQHIGH) | 867 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW)); 868 } else if (hdmi->audio.samplerate > 48000) { 869 HD_WRITE(VC4_HD_MAI_THR, 870 VC4_SET_FIELD(0x14, VC4_HD_MAI_THR_DREQHIGH) | 871 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW)); 872 } else { 873 HD_WRITE(VC4_HD_MAI_THR, 874 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) | 875 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) | 876 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQHIGH) | 877 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQLOW)); 878 } 879 880 HDMI_WRITE(VC4_HDMI_MAI_CONFIG, 881 VC4_HDMI_MAI_CONFIG_BIT_REVERSE | 882 VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK)); 883 884 channel_map = 0; 885 for (i = 0; i < 8; i++) { 886 if (channel_mask & BIT(i)) 887 channel_map |= i << (3 * i); 888 } 889 890 HDMI_WRITE(VC4_HDMI_MAI_CHANNEL_MAP, channel_map); 891 HDMI_WRITE(VC4_HDMI_AUDIO_PACKET_CONFIG, audio_packet_config); 892 vc4_hdmi_set_n_cts(hdmi); 893 894 return 0; 895 } 896 897 static int vc4_hdmi_audio_trigger(struct snd_pcm_substream *substream, int cmd, 898 struct snd_soc_dai *dai) 899 { 900 struct vc4_hdmi *hdmi = dai_to_hdmi(dai); 901 struct drm_encoder *encoder = hdmi->encoder; 902 struct drm_device *drm = encoder->dev; 903 struct vc4_dev *vc4 = to_vc4_dev(drm); 904 905 switch (cmd) { 906 case SNDRV_PCM_TRIGGER_START: 907 vc4_hdmi_set_audio_infoframe(encoder); 908 HDMI_WRITE(VC4_HDMI_TX_PHY_CTL0, 909 HDMI_READ(VC4_HDMI_TX_PHY_CTL0) & 910 ~VC4_HDMI_TX_PHY_RNG_PWRDN); 911 HD_WRITE(VC4_HD_MAI_CTL, 912 VC4_SET_FIELD(hdmi->audio.channels, 913 VC4_HD_MAI_CTL_CHNUM) | 914 VC4_HD_MAI_CTL_ENABLE); 915 break; 916 case SNDRV_PCM_TRIGGER_STOP: 917 HD_WRITE(VC4_HD_MAI_CTL, 918 VC4_HD_MAI_CTL_DLATE | 919 VC4_HD_MAI_CTL_ERRORE | 920 VC4_HD_MAI_CTL_ERRORF); 921 HDMI_WRITE(VC4_HDMI_TX_PHY_CTL0, 922 HDMI_READ(VC4_HDMI_TX_PHY_CTL0) | 923 VC4_HDMI_TX_PHY_RNG_PWRDN); 924 break; 925 default: 926 break; 927 } 928 929 return 0; 930 } 931 932 static inline struct vc4_hdmi * 933 snd_component_to_hdmi(struct snd_soc_component *component) 934 { 935 struct snd_soc_card *card = snd_soc_component_get_drvdata(component); 936 937 return snd_soc_card_get_drvdata(card); 938 } 939 940 static int vc4_hdmi_audio_eld_ctl_info(struct snd_kcontrol *kcontrol, 941 struct snd_ctl_elem_info *uinfo) 942 { 943 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 944 struct vc4_hdmi *hdmi = snd_component_to_hdmi(component); 945 946 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 947 uinfo->count = sizeof(hdmi->connector->eld); 948 949 return 0; 950 } 951 952 static int vc4_hdmi_audio_eld_ctl_get(struct snd_kcontrol *kcontrol, 953 struct snd_ctl_elem_value *ucontrol) 954 { 955 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 956 struct vc4_hdmi *hdmi = snd_component_to_hdmi(component); 957 958 memcpy(ucontrol->value.bytes.data, hdmi->connector->eld, 959 sizeof(hdmi->connector->eld)); 960 961 return 0; 962 } 963 964 static const struct snd_kcontrol_new vc4_hdmi_audio_controls[] = { 965 { 966 .access = SNDRV_CTL_ELEM_ACCESS_READ | 967 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 968 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 969 .name = "ELD", 970 .info = vc4_hdmi_audio_eld_ctl_info, 971 .get = vc4_hdmi_audio_eld_ctl_get, 972 }, 973 }; 974 975 static const struct snd_soc_dapm_widget vc4_hdmi_audio_widgets[] = { 976 SND_SOC_DAPM_OUTPUT("TX"), 977 }; 978 979 static const struct snd_soc_dapm_route vc4_hdmi_audio_routes[] = { 980 { "TX", NULL, "Playback" }, 981 }; 982 983 static const struct snd_soc_component_driver vc4_hdmi_audio_component_drv = { 984 .controls = vc4_hdmi_audio_controls, 985 .num_controls = ARRAY_SIZE(vc4_hdmi_audio_controls), 986 .dapm_widgets = vc4_hdmi_audio_widgets, 987 .num_dapm_widgets = ARRAY_SIZE(vc4_hdmi_audio_widgets), 988 .dapm_routes = vc4_hdmi_audio_routes, 989 .num_dapm_routes = ARRAY_SIZE(vc4_hdmi_audio_routes), 990 .idle_bias_on = 1, 991 .use_pmdown_time = 1, 992 .endianness = 1, 993 .non_legacy_dai_naming = 1, 994 }; 995 996 static const struct snd_soc_dai_ops vc4_hdmi_audio_dai_ops = { 997 .startup = vc4_hdmi_audio_startup, 998 .shutdown = vc4_hdmi_audio_shutdown, 999 .hw_params = vc4_hdmi_audio_hw_params, 1000 .set_fmt = vc4_hdmi_audio_set_fmt, 1001 .trigger = vc4_hdmi_audio_trigger, 1002 }; 1003 1004 static struct snd_soc_dai_driver vc4_hdmi_audio_codec_dai_drv = { 1005 .name = "vc4-hdmi-hifi", 1006 .playback = { 1007 .stream_name = "Playback", 1008 .channels_min = 2, 1009 .channels_max = 8, 1010 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 1011 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 1012 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 1013 SNDRV_PCM_RATE_192000, 1014 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 1015 }, 1016 }; 1017 1018 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = { 1019 .name = "vc4-hdmi-cpu-dai-component", 1020 }; 1021 1022 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai) 1023 { 1024 struct vc4_hdmi *hdmi = dai_to_hdmi(dai); 1025 1026 snd_soc_dai_init_dma_data(dai, &hdmi->audio.dma_data, NULL); 1027 1028 return 0; 1029 } 1030 1031 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = { 1032 .name = "vc4-hdmi-cpu-dai", 1033 .probe = vc4_hdmi_audio_cpu_dai_probe, 1034 .playback = { 1035 .stream_name = "Playback", 1036 .channels_min = 1, 1037 .channels_max = 8, 1038 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 1039 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 1040 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 1041 SNDRV_PCM_RATE_192000, 1042 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 1043 }, 1044 .ops = &vc4_hdmi_audio_dai_ops, 1045 }; 1046 1047 static const struct snd_dmaengine_pcm_config pcm_conf = { 1048 .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx", 1049 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 1050 }; 1051 1052 static int vc4_hdmi_audio_init(struct vc4_hdmi *hdmi) 1053 { 1054 struct snd_soc_dai_link *dai_link = &hdmi->audio.link; 1055 struct snd_soc_card *card = &hdmi->audio.card; 1056 struct device *dev = &hdmi->pdev->dev; 1057 const __be32 *addr; 1058 int ret; 1059 1060 if (!of_find_property(dev->of_node, "dmas", NULL)) { 1061 dev_warn(dev, 1062 "'dmas' DT property is missing, no HDMI audio\n"); 1063 return 0; 1064 } 1065 1066 /* 1067 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve 1068 * the bus address specified in the DT, because the physical address 1069 * (the one returned by platform_get_resource()) is not appropriate 1070 * for DMA transfers. 1071 * This VC/MMU should probably be exposed to avoid this kind of hacks. 1072 */ 1073 addr = of_get_address(dev->of_node, 1, NULL, NULL); 1074 hdmi->audio.dma_data.addr = be32_to_cpup(addr) + VC4_HD_MAI_DATA; 1075 hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1076 hdmi->audio.dma_data.maxburst = 2; 1077 1078 ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0); 1079 if (ret) { 1080 dev_err(dev, "Could not register PCM component: %d\n", ret); 1081 return ret; 1082 } 1083 1084 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp, 1085 &vc4_hdmi_audio_cpu_dai_drv, 1); 1086 if (ret) { 1087 dev_err(dev, "Could not register CPU DAI: %d\n", ret); 1088 return ret; 1089 } 1090 1091 /* register component and codec dai */ 1092 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_component_drv, 1093 &vc4_hdmi_audio_codec_dai_drv, 1); 1094 if (ret) { 1095 dev_err(dev, "Could not register component: %d\n", ret); 1096 return ret; 1097 } 1098 1099 dai_link->name = "MAI"; 1100 dai_link->stream_name = "MAI PCM"; 1101 dai_link->codec_dai_name = vc4_hdmi_audio_codec_dai_drv.name; 1102 dai_link->cpu_dai_name = dev_name(dev); 1103 dai_link->codec_name = dev_name(dev); 1104 dai_link->platform_name = dev_name(dev); 1105 1106 card->dai_link = dai_link; 1107 card->num_links = 1; 1108 card->name = "vc4-hdmi"; 1109 card->dev = dev; 1110 1111 /* 1112 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and 1113 * stores a pointer to the snd card object in dev->driver_data. This 1114 * means we cannot use it for something else. The hdmi back-pointer is 1115 * now stored in card->drvdata and should be retrieved with 1116 * snd_soc_card_get_drvdata() if needed. 1117 */ 1118 snd_soc_card_set_drvdata(card, hdmi); 1119 ret = devm_snd_soc_register_card(dev, card); 1120 if (ret) 1121 dev_err(dev, "Could not register sound card: %d\n", ret); 1122 1123 return ret; 1124 1125 } 1126 1127 #ifdef CONFIG_DRM_VC4_HDMI_CEC 1128 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv) 1129 { 1130 struct vc4_dev *vc4 = priv; 1131 struct vc4_hdmi *hdmi = vc4->hdmi; 1132 1133 if (hdmi->cec_irq_was_rx) { 1134 if (hdmi->cec_rx_msg.len) 1135 cec_received_msg(hdmi->cec_adap, &hdmi->cec_rx_msg); 1136 } else if (hdmi->cec_tx_ok) { 1137 cec_transmit_done(hdmi->cec_adap, CEC_TX_STATUS_OK, 1138 0, 0, 0, 0); 1139 } else { 1140 /* 1141 * This CEC implementation makes 1 retry, so if we 1142 * get a NACK, then that means it made 2 attempts. 1143 */ 1144 cec_transmit_done(hdmi->cec_adap, CEC_TX_STATUS_NACK, 1145 0, 2, 0, 0); 1146 } 1147 return IRQ_HANDLED; 1148 } 1149 1150 static void vc4_cec_read_msg(struct vc4_dev *vc4, u32 cntrl1) 1151 { 1152 struct cec_msg *msg = &vc4->hdmi->cec_rx_msg; 1153 unsigned int i; 1154 1155 msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >> 1156 VC4_HDMI_CEC_REC_WRD_CNT_SHIFT); 1157 for (i = 0; i < msg->len; i += 4) { 1158 u32 val = HDMI_READ(VC4_HDMI_CEC_RX_DATA_1 + i); 1159 1160 msg->msg[i] = val & 0xff; 1161 msg->msg[i + 1] = (val >> 8) & 0xff; 1162 msg->msg[i + 2] = (val >> 16) & 0xff; 1163 msg->msg[i + 3] = (val >> 24) & 0xff; 1164 } 1165 } 1166 1167 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv) 1168 { 1169 struct vc4_dev *vc4 = priv; 1170 struct vc4_hdmi *hdmi = vc4->hdmi; 1171 u32 stat = HDMI_READ(VC4_HDMI_CPU_STATUS); 1172 u32 cntrl1, cntrl5; 1173 1174 if (!(stat & VC4_HDMI_CPU_CEC)) 1175 return IRQ_NONE; 1176 hdmi->cec_rx_msg.len = 0; 1177 cntrl1 = HDMI_READ(VC4_HDMI_CEC_CNTRL_1); 1178 cntrl5 = HDMI_READ(VC4_HDMI_CEC_CNTRL_5); 1179 hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT; 1180 if (hdmi->cec_irq_was_rx) { 1181 vc4_cec_read_msg(vc4, cntrl1); 1182 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 1183 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, cntrl1); 1184 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 1185 } else { 1186 hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD; 1187 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 1188 } 1189 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, cntrl1); 1190 HDMI_WRITE(VC4_HDMI_CPU_CLEAR, VC4_HDMI_CPU_CEC); 1191 1192 return IRQ_WAKE_THREAD; 1193 } 1194 1195 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable) 1196 { 1197 struct vc4_dev *vc4 = cec_get_drvdata(adap); 1198 /* clock period in microseconds */ 1199 const u32 usecs = 1000000 / CEC_CLOCK_FREQ; 1200 u32 val = HDMI_READ(VC4_HDMI_CEC_CNTRL_5); 1201 1202 val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET | 1203 VC4_HDMI_CEC_CNT_TO_4700_US_MASK | 1204 VC4_HDMI_CEC_CNT_TO_4500_US_MASK); 1205 val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) | 1206 ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT); 1207 1208 if (enable) { 1209 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_5, val | 1210 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 1211 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_5, val); 1212 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_2, 1213 ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) | 1214 ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) | 1215 ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) | 1216 ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) | 1217 ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT)); 1218 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_3, 1219 ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) | 1220 ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) | 1221 ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) | 1222 ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT)); 1223 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_4, 1224 ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) | 1225 ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) | 1226 ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) | 1227 ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT)); 1228 1229 HDMI_WRITE(VC4_HDMI_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC); 1230 } else { 1231 HDMI_WRITE(VC4_HDMI_CPU_MASK_SET, VC4_HDMI_CPU_CEC); 1232 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_5, val | 1233 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 1234 } 1235 return 0; 1236 } 1237 1238 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr) 1239 { 1240 struct vc4_dev *vc4 = cec_get_drvdata(adap); 1241 1242 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, 1243 (HDMI_READ(VC4_HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) | 1244 (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT); 1245 return 0; 1246 } 1247 1248 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts, 1249 u32 signal_free_time, struct cec_msg *msg) 1250 { 1251 struct vc4_dev *vc4 = cec_get_drvdata(adap); 1252 u32 val; 1253 unsigned int i; 1254 1255 for (i = 0; i < msg->len; i += 4) 1256 HDMI_WRITE(VC4_HDMI_CEC_TX_DATA_1 + i, 1257 (msg->msg[i]) | 1258 (msg->msg[i + 1] << 8) | 1259 (msg->msg[i + 2] << 16) | 1260 (msg->msg[i + 3] << 24)); 1261 1262 val = HDMI_READ(VC4_HDMI_CEC_CNTRL_1); 1263 val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 1264 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, val); 1265 val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK; 1266 val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT; 1267 val |= VC4_HDMI_CEC_START_XMIT_BEGIN; 1268 1269 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, val); 1270 return 0; 1271 } 1272 1273 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = { 1274 .adap_enable = vc4_hdmi_cec_adap_enable, 1275 .adap_log_addr = vc4_hdmi_cec_adap_log_addr, 1276 .adap_transmit = vc4_hdmi_cec_adap_transmit, 1277 }; 1278 #endif 1279 1280 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data) 1281 { 1282 struct platform_device *pdev = to_platform_device(dev); 1283 struct drm_device *drm = dev_get_drvdata(master); 1284 struct vc4_dev *vc4 = drm->dev_private; 1285 struct vc4_hdmi *hdmi; 1286 struct vc4_hdmi_encoder *vc4_hdmi_encoder; 1287 struct device_node *ddc_node; 1288 u32 value; 1289 int ret; 1290 1291 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); 1292 if (!hdmi) 1293 return -ENOMEM; 1294 1295 vc4_hdmi_encoder = devm_kzalloc(dev, sizeof(*vc4_hdmi_encoder), 1296 GFP_KERNEL); 1297 if (!vc4_hdmi_encoder) 1298 return -ENOMEM; 1299 vc4_hdmi_encoder->base.type = VC4_ENCODER_TYPE_HDMI; 1300 hdmi->encoder = &vc4_hdmi_encoder->base.base; 1301 1302 hdmi->pdev = pdev; 1303 hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0); 1304 if (IS_ERR(hdmi->hdmicore_regs)) 1305 return PTR_ERR(hdmi->hdmicore_regs); 1306 1307 hdmi->hd_regs = vc4_ioremap_regs(pdev, 1); 1308 if (IS_ERR(hdmi->hd_regs)) 1309 return PTR_ERR(hdmi->hd_regs); 1310 1311 hdmi->hdmi_regset.base = hdmi->hdmicore_regs; 1312 hdmi->hdmi_regset.regs = hdmi_regs; 1313 hdmi->hdmi_regset.nregs = ARRAY_SIZE(hdmi_regs); 1314 hdmi->hd_regset.base = hdmi->hd_regs; 1315 hdmi->hd_regset.regs = hd_regs; 1316 hdmi->hd_regset.nregs = ARRAY_SIZE(hd_regs); 1317 1318 hdmi->pixel_clock = devm_clk_get(dev, "pixel"); 1319 if (IS_ERR(hdmi->pixel_clock)) { 1320 DRM_ERROR("Failed to get pixel clock\n"); 1321 return PTR_ERR(hdmi->pixel_clock); 1322 } 1323 hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); 1324 if (IS_ERR(hdmi->hsm_clock)) { 1325 DRM_ERROR("Failed to get HDMI state machine clock\n"); 1326 return PTR_ERR(hdmi->hsm_clock); 1327 } 1328 1329 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0); 1330 if (!ddc_node) { 1331 DRM_ERROR("Failed to find ddc node in device tree\n"); 1332 return -ENODEV; 1333 } 1334 1335 hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node); 1336 of_node_put(ddc_node); 1337 if (!hdmi->ddc) { 1338 DRM_DEBUG("Failed to get ddc i2c adapter by node\n"); 1339 return -EPROBE_DEFER; 1340 } 1341 1342 /* This is the rate that is set by the firmware. The number 1343 * needs to be a bit higher than the pixel clock rate 1344 * (generally 148.5Mhz). 1345 */ 1346 ret = clk_set_rate(hdmi->hsm_clock, HSM_CLOCK_FREQ); 1347 if (ret) { 1348 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret); 1349 goto err_put_i2c; 1350 } 1351 1352 ret = clk_prepare_enable(hdmi->hsm_clock); 1353 if (ret) { 1354 DRM_ERROR("Failed to turn on HDMI state machine clock: %d\n", 1355 ret); 1356 goto err_put_i2c; 1357 } 1358 1359 /* Only use the GPIO HPD pin if present in the DT, otherwise 1360 * we'll use the HDMI core's register. 1361 */ 1362 if (of_find_property(dev->of_node, "hpd-gpios", &value)) { 1363 enum of_gpio_flags hpd_gpio_flags; 1364 1365 hdmi->hpd_gpio = of_get_named_gpio_flags(dev->of_node, 1366 "hpd-gpios", 0, 1367 &hpd_gpio_flags); 1368 if (hdmi->hpd_gpio < 0) { 1369 ret = hdmi->hpd_gpio; 1370 goto err_unprepare_hsm; 1371 } 1372 1373 hdmi->hpd_active_low = hpd_gpio_flags & OF_GPIO_ACTIVE_LOW; 1374 } 1375 1376 vc4->hdmi = hdmi; 1377 1378 /* HDMI core must be enabled. */ 1379 if (!(HD_READ(VC4_HD_M_CTL) & VC4_HD_M_ENABLE)) { 1380 HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_SW_RST); 1381 udelay(1); 1382 HD_WRITE(VC4_HD_M_CTL, 0); 1383 1384 HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_ENABLE); 1385 } 1386 pm_runtime_enable(dev); 1387 1388 drm_encoder_init(drm, hdmi->encoder, &vc4_hdmi_encoder_funcs, 1389 DRM_MODE_ENCODER_TMDS, NULL); 1390 drm_encoder_helper_add(hdmi->encoder, &vc4_hdmi_encoder_helper_funcs); 1391 1392 hdmi->connector = vc4_hdmi_connector_init(drm, hdmi->encoder); 1393 if (IS_ERR(hdmi->connector)) { 1394 ret = PTR_ERR(hdmi->connector); 1395 goto err_destroy_encoder; 1396 } 1397 #ifdef CONFIG_DRM_VC4_HDMI_CEC 1398 hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops, 1399 vc4, "vc4", 1400 CEC_CAP_TRANSMIT | 1401 CEC_CAP_LOG_ADDRS | 1402 CEC_CAP_PASSTHROUGH | 1403 CEC_CAP_RC, 1); 1404 ret = PTR_ERR_OR_ZERO(hdmi->cec_adap); 1405 if (ret < 0) 1406 goto err_destroy_conn; 1407 HDMI_WRITE(VC4_HDMI_CPU_MASK_SET, 0xffffffff); 1408 value = HDMI_READ(VC4_HDMI_CEC_CNTRL_1); 1409 value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK; 1410 /* 1411 * Set the logical address to Unregistered and set the clock 1412 * divider: the hsm_clock rate and this divider setting will 1413 * give a 40 kHz CEC clock. 1414 */ 1415 value |= VC4_HDMI_CEC_ADDR_MASK | 1416 (4091 << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT); 1417 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, value); 1418 ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0), 1419 vc4_cec_irq_handler, 1420 vc4_cec_irq_handler_thread, 0, 1421 "vc4 hdmi cec", vc4); 1422 if (ret) 1423 goto err_delete_cec_adap; 1424 ret = cec_register_adapter(hdmi->cec_adap, dev); 1425 if (ret < 0) 1426 goto err_delete_cec_adap; 1427 #endif 1428 1429 ret = vc4_hdmi_audio_init(hdmi); 1430 if (ret) 1431 goto err_destroy_encoder; 1432 1433 vc4_debugfs_add_file(drm, "hdmi_regs", vc4_hdmi_debugfs_regs, hdmi); 1434 1435 return 0; 1436 1437 #ifdef CONFIG_DRM_VC4_HDMI_CEC 1438 err_delete_cec_adap: 1439 cec_delete_adapter(hdmi->cec_adap); 1440 err_destroy_conn: 1441 vc4_hdmi_connector_destroy(hdmi->connector); 1442 #endif 1443 err_destroy_encoder: 1444 vc4_hdmi_encoder_destroy(hdmi->encoder); 1445 err_unprepare_hsm: 1446 clk_disable_unprepare(hdmi->hsm_clock); 1447 pm_runtime_disable(dev); 1448 err_put_i2c: 1449 put_device(&hdmi->ddc->dev); 1450 1451 return ret; 1452 } 1453 1454 static void vc4_hdmi_unbind(struct device *dev, struct device *master, 1455 void *data) 1456 { 1457 struct drm_device *drm = dev_get_drvdata(master); 1458 struct vc4_dev *vc4 = drm->dev_private; 1459 struct vc4_hdmi *hdmi = vc4->hdmi; 1460 1461 cec_unregister_adapter(hdmi->cec_adap); 1462 vc4_hdmi_connector_destroy(hdmi->connector); 1463 vc4_hdmi_encoder_destroy(hdmi->encoder); 1464 1465 clk_disable_unprepare(hdmi->hsm_clock); 1466 pm_runtime_disable(dev); 1467 1468 put_device(&hdmi->ddc->dev); 1469 1470 vc4->hdmi = NULL; 1471 } 1472 1473 static const struct component_ops vc4_hdmi_ops = { 1474 .bind = vc4_hdmi_bind, 1475 .unbind = vc4_hdmi_unbind, 1476 }; 1477 1478 static int vc4_hdmi_dev_probe(struct platform_device *pdev) 1479 { 1480 return component_add(&pdev->dev, &vc4_hdmi_ops); 1481 } 1482 1483 static int vc4_hdmi_dev_remove(struct platform_device *pdev) 1484 { 1485 component_del(&pdev->dev, &vc4_hdmi_ops); 1486 return 0; 1487 } 1488 1489 static const struct of_device_id vc4_hdmi_dt_match[] = { 1490 { .compatible = "brcm,bcm2835-hdmi" }, 1491 {} 1492 }; 1493 1494 struct platform_driver vc4_hdmi_driver = { 1495 .probe = vc4_hdmi_dev_probe, 1496 .remove = vc4_hdmi_dev_remove, 1497 .driver = { 1498 .name = "vc4_hdmi", 1499 .of_match_table = vc4_hdmi_dt_match, 1500 }, 1501 }; 1502