1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 Broadcom 4 * Copyright (c) 2014 The Linux Foundation. All rights reserved. 5 * Copyright (C) 2013 Red Hat 6 * Author: Rob Clark <robdclark@gmail.com> 7 */ 8 9 /** 10 * DOC: VC4 Falcon HDMI module 11 * 12 * The HDMI core has a state machine and a PHY. On BCM2835, most of 13 * the unit operates off of the HSM clock from CPRMAN. It also 14 * internally uses the PLLH_PIX clock for the PHY. 15 * 16 * HDMI infoframes are kept within a small packet ram, where each 17 * packet can be individually enabled for including in a frame. 18 * 19 * HDMI audio is implemented entirely within the HDMI IP block. A 20 * register in the HDMI encoder takes SPDIF frames from the DMA engine 21 * and transfers them over an internal MAI (multi-channel audio 22 * interconnect) bus to the encoder side for insertion into the video 23 * blank regions. 24 * 25 * The driver's HDMI encoder does not yet support power management. 26 * The HDMI encoder's power domain and the HSM/pixel clocks are kept 27 * continuously running, and only the HDMI logic and packet ram are 28 * powered off/on at disable/enable time. 29 * 30 * The driver does not yet support CEC control, though the HDMI 31 * encoder block has CEC support. 32 */ 33 34 #include <drm/drm_atomic_helper.h> 35 #include <drm/drm_edid.h> 36 #include <drm/drm_probe_helper.h> 37 #include <drm/drm_simple_kms_helper.h> 38 #include <drm/drm_scdc_helper.h> 39 #include <linux/clk.h> 40 #include <linux/component.h> 41 #include <linux/i2c.h> 42 #include <linux/of_address.h> 43 #include <linux/of_gpio.h> 44 #include <linux/of_platform.h> 45 #include <linux/pm_runtime.h> 46 #include <linux/rational.h> 47 #include <linux/reset.h> 48 #include <sound/dmaengine_pcm.h> 49 #include <sound/pcm_drm_eld.h> 50 #include <sound/pcm_params.h> 51 #include <sound/soc.h> 52 #include "media/cec.h" 53 #include "vc4_drv.h" 54 #include "vc4_hdmi.h" 55 #include "vc4_hdmi_regs.h" 56 #include "vc4_regs.h" 57 58 #define VC5_HDMI_HORZA_HFP_SHIFT 16 59 #define VC5_HDMI_HORZA_HFP_MASK VC4_MASK(28, 16) 60 #define VC5_HDMI_HORZA_VPOS BIT(15) 61 #define VC5_HDMI_HORZA_HPOS BIT(14) 62 #define VC5_HDMI_HORZA_HAP_SHIFT 0 63 #define VC5_HDMI_HORZA_HAP_MASK VC4_MASK(13, 0) 64 65 #define VC5_HDMI_HORZB_HBP_SHIFT 16 66 #define VC5_HDMI_HORZB_HBP_MASK VC4_MASK(26, 16) 67 #define VC5_HDMI_HORZB_HSP_SHIFT 0 68 #define VC5_HDMI_HORZB_HSP_MASK VC4_MASK(10, 0) 69 70 #define VC5_HDMI_VERTA_VSP_SHIFT 24 71 #define VC5_HDMI_VERTA_VSP_MASK VC4_MASK(28, 24) 72 #define VC5_HDMI_VERTA_VFP_SHIFT 16 73 #define VC5_HDMI_VERTA_VFP_MASK VC4_MASK(22, 16) 74 #define VC5_HDMI_VERTA_VAL_SHIFT 0 75 #define VC5_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0) 76 77 #define VC5_HDMI_VERTB_VSPO_SHIFT 16 78 #define VC5_HDMI_VERTB_VSPO_MASK VC4_MASK(29, 16) 79 80 #define VC5_HDMI_SCRAMBLER_CTL_ENABLE BIT(0) 81 82 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT 8 83 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK VC4_MASK(10, 8) 84 85 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT 0 86 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK VC4_MASK(3, 0) 87 88 #define VC5_HDMI_GCP_CONFIG_GCP_ENABLE BIT(31) 89 90 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT 8 91 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK VC4_MASK(15, 8) 92 93 # define VC4_HD_M_SW_RST BIT(2) 94 # define VC4_HD_M_ENABLE BIT(0) 95 96 #define CEC_CLOCK_FREQ 40000 97 98 #define HDMI_14_MAX_TMDS_CLK (340 * 1000 * 1000) 99 100 static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode) 101 { 102 return (mode->clock * 1000) > HDMI_14_MAX_TMDS_CLK; 103 } 104 105 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused) 106 { 107 struct drm_info_node *node = (struct drm_info_node *)m->private; 108 struct vc4_hdmi *vc4_hdmi = node->info_ent->data; 109 struct drm_printer p = drm_seq_file_printer(m); 110 111 drm_print_regset32(&p, &vc4_hdmi->hdmi_regset); 112 drm_print_regset32(&p, &vc4_hdmi->hd_regset); 113 114 return 0; 115 } 116 117 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi) 118 { 119 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST); 120 udelay(1); 121 HDMI_WRITE(HDMI_M_CTL, 0); 122 123 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE); 124 125 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 126 VC4_HDMI_SW_RESET_HDMI | 127 VC4_HDMI_SW_RESET_FORMAT_DETECT); 128 129 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0); 130 } 131 132 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi) 133 { 134 reset_control_reset(vc4_hdmi->reset); 135 136 HDMI_WRITE(HDMI_DVP_CTL, 0); 137 138 HDMI_WRITE(HDMI_CLOCK_STOP, 139 HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL); 140 } 141 142 #ifdef CONFIG_DRM_VC4_HDMI_CEC 143 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) 144 { 145 u16 clk_cnt; 146 u32 value; 147 148 value = HDMI_READ(HDMI_CEC_CNTRL_1); 149 value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK; 150 151 /* 152 * Set the clock divider: the hsm_clock rate and this divider 153 * setting will give a 40 kHz CEC clock. 154 */ 155 clk_cnt = clk_get_rate(vc4_hdmi->cec_clock) / CEC_CLOCK_FREQ; 156 value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT; 157 HDMI_WRITE(HDMI_CEC_CNTRL_1, value); 158 } 159 #else 160 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {} 161 #endif 162 163 static enum drm_connector_status 164 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force) 165 { 166 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 167 bool connected = false; 168 169 WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev)); 170 171 if (vc4_hdmi->hpd_gpio && 172 gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio)) { 173 connected = true; 174 } else if (drm_probe_ddc(vc4_hdmi->ddc)) { 175 connected = true; 176 } else if (HDMI_READ(HDMI_HOTPLUG) & VC4_HDMI_HOTPLUG_CONNECTED) { 177 connected = true; 178 } 179 180 if (connected) { 181 if (connector->status != connector_status_connected) { 182 struct edid *edid = drm_get_edid(connector, vc4_hdmi->ddc); 183 184 if (edid) { 185 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid); 186 vc4_hdmi->encoder.hdmi_monitor = drm_detect_hdmi_monitor(edid); 187 kfree(edid); 188 } 189 } 190 191 pm_runtime_put(&vc4_hdmi->pdev->dev); 192 return connector_status_connected; 193 } 194 195 cec_phys_addr_invalidate(vc4_hdmi->cec_adap); 196 pm_runtime_put(&vc4_hdmi->pdev->dev); 197 return connector_status_disconnected; 198 } 199 200 static void vc4_hdmi_connector_destroy(struct drm_connector *connector) 201 { 202 drm_connector_unregister(connector); 203 drm_connector_cleanup(connector); 204 } 205 206 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector) 207 { 208 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 209 struct vc4_hdmi_encoder *vc4_encoder = &vc4_hdmi->encoder; 210 int ret = 0; 211 struct edid *edid; 212 213 edid = drm_get_edid(connector, vc4_hdmi->ddc); 214 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid); 215 if (!edid) 216 return -ENODEV; 217 218 vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid); 219 220 drm_connector_update_edid_property(connector, edid); 221 ret = drm_add_edid_modes(connector, edid); 222 kfree(edid); 223 224 if (vc4_hdmi->disable_4kp60) { 225 struct drm_device *drm = connector->dev; 226 struct drm_display_mode *mode; 227 228 list_for_each_entry(mode, &connector->probed_modes, head) { 229 if (vc4_hdmi_mode_needs_scrambling(mode)) { 230 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz."); 231 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60."); 232 } 233 } 234 } 235 236 return ret; 237 } 238 239 static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector, 240 struct drm_atomic_state *state) 241 { 242 struct drm_connector_state *old_state = 243 drm_atomic_get_old_connector_state(state, connector); 244 struct drm_connector_state *new_state = 245 drm_atomic_get_new_connector_state(state, connector); 246 struct drm_crtc *crtc = new_state->crtc; 247 248 if (!crtc) 249 return 0; 250 251 if (old_state->colorspace != new_state->colorspace || 252 !drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) { 253 struct drm_crtc_state *crtc_state; 254 255 crtc_state = drm_atomic_get_crtc_state(state, crtc); 256 if (IS_ERR(crtc_state)) 257 return PTR_ERR(crtc_state); 258 259 crtc_state->mode_changed = true; 260 } 261 262 return 0; 263 } 264 265 static void vc4_hdmi_connector_reset(struct drm_connector *connector) 266 { 267 struct vc4_hdmi_connector_state *old_state = 268 conn_state_to_vc4_hdmi_conn_state(connector->state); 269 struct vc4_hdmi_connector_state *new_state = 270 kzalloc(sizeof(*new_state), GFP_KERNEL); 271 272 if (connector->state) 273 __drm_atomic_helper_connector_destroy_state(connector->state); 274 275 kfree(old_state); 276 __drm_atomic_helper_connector_reset(connector, &new_state->base); 277 278 if (!new_state) 279 return; 280 281 new_state->base.max_bpc = 8; 282 new_state->base.max_requested_bpc = 8; 283 drm_atomic_helper_connector_tv_reset(connector); 284 } 285 286 static struct drm_connector_state * 287 vc4_hdmi_connector_duplicate_state(struct drm_connector *connector) 288 { 289 struct drm_connector_state *conn_state = connector->state; 290 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state); 291 struct vc4_hdmi_connector_state *new_state; 292 293 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL); 294 if (!new_state) 295 return NULL; 296 297 new_state->pixel_rate = vc4_state->pixel_rate; 298 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base); 299 300 return &new_state->base; 301 } 302 303 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = { 304 .detect = vc4_hdmi_connector_detect, 305 .fill_modes = drm_helper_probe_single_connector_modes, 306 .destroy = vc4_hdmi_connector_destroy, 307 .reset = vc4_hdmi_connector_reset, 308 .atomic_duplicate_state = vc4_hdmi_connector_duplicate_state, 309 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 310 }; 311 312 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = { 313 .get_modes = vc4_hdmi_connector_get_modes, 314 .atomic_check = vc4_hdmi_connector_atomic_check, 315 }; 316 317 static int vc4_hdmi_connector_init(struct drm_device *dev, 318 struct vc4_hdmi *vc4_hdmi) 319 { 320 struct drm_connector *connector = &vc4_hdmi->connector; 321 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base; 322 int ret; 323 324 drm_connector_init_with_ddc(dev, connector, 325 &vc4_hdmi_connector_funcs, 326 DRM_MODE_CONNECTOR_HDMIA, 327 vc4_hdmi->ddc); 328 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs); 329 330 /* 331 * Some of the properties below require access to state, like bpc. 332 * Allocate some default initial connector state with our reset helper. 333 */ 334 if (connector->funcs->reset) 335 connector->funcs->reset(connector); 336 337 /* Create and attach TV margin props to this connector. */ 338 ret = drm_mode_create_tv_margin_properties(dev); 339 if (ret) 340 return ret; 341 342 ret = drm_mode_create_hdmi_colorspace_property(connector); 343 if (ret) 344 return ret; 345 346 drm_connector_attach_colorspace_property(connector); 347 drm_connector_attach_tv_margin_properties(connector); 348 drm_connector_attach_max_bpc_property(connector, 8, 12); 349 350 connector->polled = (DRM_CONNECTOR_POLL_CONNECT | 351 DRM_CONNECTOR_POLL_DISCONNECT); 352 353 connector->interlace_allowed = 1; 354 connector->doublescan_allowed = 0; 355 356 if (vc4_hdmi->variant->supports_hdr) 357 drm_connector_attach_hdr_output_metadata_property(connector); 358 359 drm_connector_attach_encoder(connector, encoder); 360 361 return 0; 362 } 363 364 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder, 365 enum hdmi_infoframe_type type, 366 bool poll) 367 { 368 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 369 u32 packet_id = type - 0x80; 370 371 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 372 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id)); 373 374 if (!poll) 375 return 0; 376 377 return wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) & 378 BIT(packet_id)), 100); 379 } 380 381 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder, 382 union hdmi_infoframe *frame) 383 { 384 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 385 u32 packet_id = frame->any.type - 0x80; 386 const struct vc4_hdmi_register *ram_packet_start = 387 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START]; 388 u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id; 389 void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi, 390 ram_packet_start->reg); 391 uint8_t buffer[VC4_HDMI_PACKET_STRIDE]; 392 ssize_t len, i; 393 int ret; 394 395 WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) & 396 VC4_HDMI_RAM_PACKET_ENABLE), 397 "Packet RAM has to be on to store the packet."); 398 399 len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer)); 400 if (len < 0) 401 return; 402 403 ret = vc4_hdmi_stop_packet(encoder, frame->any.type, true); 404 if (ret) { 405 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret); 406 return; 407 } 408 409 for (i = 0; i < len; i += 7) { 410 writel(buffer[i + 0] << 0 | 411 buffer[i + 1] << 8 | 412 buffer[i + 2] << 16, 413 base + packet_reg); 414 packet_reg += 4; 415 416 writel(buffer[i + 3] << 0 | 417 buffer[i + 4] << 8 | 418 buffer[i + 5] << 16 | 419 buffer[i + 6] << 24, 420 base + packet_reg); 421 packet_reg += 4; 422 } 423 424 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 425 HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id)); 426 ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) & 427 BIT(packet_id)), 100); 428 if (ret) 429 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret); 430 } 431 432 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder) 433 { 434 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 435 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 436 struct drm_connector *connector = &vc4_hdmi->connector; 437 struct drm_connector_state *cstate = connector->state; 438 struct drm_crtc *crtc = encoder->crtc; 439 const struct drm_display_mode *mode = &crtc->state->adjusted_mode; 440 union hdmi_infoframe frame; 441 int ret; 442 443 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, 444 connector, mode); 445 if (ret < 0) { 446 DRM_ERROR("couldn't fill AVI infoframe\n"); 447 return; 448 } 449 450 drm_hdmi_avi_infoframe_quant_range(&frame.avi, 451 connector, mode, 452 vc4_encoder->limited_rgb_range ? 453 HDMI_QUANTIZATION_RANGE_LIMITED : 454 HDMI_QUANTIZATION_RANGE_FULL); 455 drm_hdmi_avi_infoframe_colorspace(&frame.avi, cstate); 456 drm_hdmi_avi_infoframe_bars(&frame.avi, cstate); 457 458 vc4_hdmi_write_infoframe(encoder, &frame); 459 } 460 461 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder) 462 { 463 union hdmi_infoframe frame; 464 int ret; 465 466 ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore"); 467 if (ret < 0) { 468 DRM_ERROR("couldn't fill SPD infoframe\n"); 469 return; 470 } 471 472 frame.spd.sdi = HDMI_SPD_SDI_PC; 473 474 vc4_hdmi_write_infoframe(encoder, &frame); 475 } 476 477 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder) 478 { 479 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 480 union hdmi_infoframe frame; 481 482 hdmi_audio_infoframe_init(&frame.audio); 483 484 frame.audio.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM; 485 frame.audio.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM; 486 frame.audio.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM; 487 frame.audio.channels = vc4_hdmi->audio.channels; 488 489 vc4_hdmi_write_infoframe(encoder, &frame); 490 } 491 492 static void vc4_hdmi_set_hdr_infoframe(struct drm_encoder *encoder) 493 { 494 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 495 struct drm_connector *connector = &vc4_hdmi->connector; 496 struct drm_connector_state *conn_state = connector->state; 497 union hdmi_infoframe frame; 498 499 if (!vc4_hdmi->variant->supports_hdr) 500 return; 501 502 if (!conn_state->hdr_output_metadata) 503 return; 504 505 if (drm_hdmi_infoframe_set_hdr_metadata(&frame.drm, conn_state)) 506 return; 507 508 vc4_hdmi_write_infoframe(encoder, &frame); 509 } 510 511 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder) 512 { 513 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 514 515 vc4_hdmi_set_avi_infoframe(encoder); 516 vc4_hdmi_set_spd_infoframe(encoder); 517 /* 518 * If audio was streaming, then we need to reenabled the audio 519 * infoframe here during encoder_enable. 520 */ 521 if (vc4_hdmi->audio.streaming) 522 vc4_hdmi_set_audio_infoframe(encoder); 523 524 vc4_hdmi_set_hdr_infoframe(encoder); 525 } 526 527 static bool vc4_hdmi_supports_scrambling(struct drm_encoder *encoder, 528 struct drm_display_mode *mode) 529 { 530 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 531 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 532 struct drm_display_info *display = &vc4_hdmi->connector.display_info; 533 534 if (!vc4_encoder->hdmi_monitor) 535 return false; 536 537 if (!display->hdmi.scdc.supported || 538 !display->hdmi.scdc.scrambling.supported) 539 return false; 540 541 return true; 542 } 543 544 #define SCRAMBLING_POLLING_DELAY_MS 1000 545 546 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder) 547 { 548 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; 549 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 550 551 if (!vc4_hdmi_supports_scrambling(encoder, mode)) 552 return; 553 554 if (!vc4_hdmi_mode_needs_scrambling(mode)) 555 return; 556 557 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true); 558 drm_scdc_set_scrambling(vc4_hdmi->ddc, true); 559 560 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) | 561 VC5_HDMI_SCRAMBLER_CTL_ENABLE); 562 563 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work, 564 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS)); 565 } 566 567 static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder) 568 { 569 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 570 struct drm_crtc *crtc = encoder->crtc; 571 572 /* 573 * At boot, encoder->crtc will be NULL. Since we don't know the 574 * state of the scrambler and in order to avoid any 575 * inconsistency, let's disable it all the time. 576 */ 577 if (crtc && !vc4_hdmi_supports_scrambling(encoder, &crtc->mode)) 578 return; 579 580 if (crtc && !vc4_hdmi_mode_needs_scrambling(&crtc->mode)) 581 return; 582 583 if (delayed_work_pending(&vc4_hdmi->scrambling_work)) 584 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work); 585 586 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) & 587 ~VC5_HDMI_SCRAMBLER_CTL_ENABLE); 588 589 drm_scdc_set_scrambling(vc4_hdmi->ddc, false); 590 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, false); 591 } 592 593 static void vc4_hdmi_scrambling_wq(struct work_struct *work) 594 { 595 struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work), 596 struct vc4_hdmi, 597 scrambling_work); 598 599 if (drm_scdc_get_scrambling_status(vc4_hdmi->ddc)) 600 return; 601 602 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true); 603 drm_scdc_set_scrambling(vc4_hdmi->ddc, true); 604 605 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work, 606 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS)); 607 } 608 609 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder, 610 struct drm_atomic_state *state) 611 { 612 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 613 614 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0); 615 616 HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | 617 VC4_HD_VID_CTL_CLRRGB | VC4_HD_VID_CTL_CLRSYNC); 618 619 HDMI_WRITE(HDMI_VID_CTL, 620 HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX); 621 622 vc4_hdmi_disable_scrambling(encoder); 623 } 624 625 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder, 626 struct drm_atomic_state *state) 627 { 628 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 629 int ret; 630 631 if (vc4_hdmi->variant->phy_disable) 632 vc4_hdmi->variant->phy_disable(vc4_hdmi); 633 634 HDMI_WRITE(HDMI_VID_CTL, 635 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE); 636 637 clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock); 638 clk_disable_unprepare(vc4_hdmi->pixel_clock); 639 640 ret = pm_runtime_put(&vc4_hdmi->pdev->dev); 641 if (ret < 0) 642 DRM_ERROR("Failed to release power domain: %d\n", ret); 643 } 644 645 static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder) 646 { 647 } 648 649 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable) 650 { 651 u32 csc_ctl; 652 653 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR, 654 VC4_HD_CSC_CTL_ORDER); 655 656 if (enable) { 657 /* CEA VICs other than #1 requre limited range RGB 658 * output unless overridden by an AVI infoframe. 659 * Apply a colorspace conversion to squash 0-255 down 660 * to 16-235. The matrix here is: 661 * 662 * [ 0 0 0.8594 16] 663 * [ 0 0.8594 0 16] 664 * [ 0.8594 0 0 16] 665 * [ 0 0 0 1] 666 */ 667 csc_ctl |= VC4_HD_CSC_CTL_ENABLE; 668 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC; 669 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM, 670 VC4_HD_CSC_CTL_MODE); 671 672 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000); 673 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0); 674 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000); 675 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000); 676 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0); 677 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000); 678 } 679 680 /* The RGB order applies even when CSC is disabled. */ 681 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl); 682 } 683 684 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable) 685 { 686 u32 csc_ctl; 687 688 csc_ctl = 0x07; /* RGB_CONVERT_MODE = custom matrix, || USE_RGB_TO_YCBCR */ 689 690 if (enable) { 691 /* CEA VICs other than #1 requre limited range RGB 692 * output unless overridden by an AVI infoframe. 693 * Apply a colorspace conversion to squash 0-255 down 694 * to 16-235. The matrix here is: 695 * 696 * [ 0.8594 0 0 16] 697 * [ 0 0.8594 0 16] 698 * [ 0 0 0.8594 16] 699 * [ 0 0 0 1] 700 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets 701 */ 702 HDMI_WRITE(HDMI_CSC_12_11, (0x0000 << 16) | 0x1b80); 703 HDMI_WRITE(HDMI_CSC_14_13, (0x0400 << 16) | 0x0000); 704 HDMI_WRITE(HDMI_CSC_22_21, (0x1b80 << 16) | 0x0000); 705 HDMI_WRITE(HDMI_CSC_24_23, (0x0400 << 16) | 0x0000); 706 HDMI_WRITE(HDMI_CSC_32_31, (0x0000 << 16) | 0x0000); 707 HDMI_WRITE(HDMI_CSC_34_33, (0x0400 << 16) | 0x1b80); 708 } else { 709 /* Still use the matrix for full range, but make it unity. 710 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets 711 */ 712 HDMI_WRITE(HDMI_CSC_12_11, (0x0000 << 16) | 0x2000); 713 HDMI_WRITE(HDMI_CSC_14_13, (0x0000 << 16) | 0x0000); 714 HDMI_WRITE(HDMI_CSC_22_21, (0x2000 << 16) | 0x0000); 715 HDMI_WRITE(HDMI_CSC_24_23, (0x0000 << 16) | 0x0000); 716 HDMI_WRITE(HDMI_CSC_32_31, (0x0000 << 16) | 0x0000); 717 HDMI_WRITE(HDMI_CSC_34_33, (0x0000 << 16) | 0x2000); 718 } 719 720 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl); 721 } 722 723 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi, 724 struct drm_connector_state *state, 725 struct drm_display_mode *mode) 726 { 727 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 728 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 729 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 730 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 731 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 732 VC4_HDMI_VERTA_VSP) | 733 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 734 VC4_HDMI_VERTA_VFP) | 735 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL)); 736 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 737 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end, 738 VC4_HDMI_VERTB_VBP)); 739 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 740 VC4_SET_FIELD(mode->crtc_vtotal - 741 mode->crtc_vsync_end - 742 interlaced, 743 VC4_HDMI_VERTB_VBP)); 744 745 HDMI_WRITE(HDMI_HORZA, 746 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) | 747 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) | 748 VC4_SET_FIELD(mode->hdisplay * pixel_rep, 749 VC4_HDMI_HORZA_HAP)); 750 751 HDMI_WRITE(HDMI_HORZB, 752 VC4_SET_FIELD((mode->htotal - 753 mode->hsync_end) * pixel_rep, 754 VC4_HDMI_HORZB_HBP) | 755 VC4_SET_FIELD((mode->hsync_end - 756 mode->hsync_start) * pixel_rep, 757 VC4_HDMI_HORZB_HSP) | 758 VC4_SET_FIELD((mode->hsync_start - 759 mode->hdisplay) * pixel_rep, 760 VC4_HDMI_HORZB_HFP)); 761 762 HDMI_WRITE(HDMI_VERTA0, verta); 763 HDMI_WRITE(HDMI_VERTA1, verta); 764 765 HDMI_WRITE(HDMI_VERTB0, vertb_even); 766 HDMI_WRITE(HDMI_VERTB1, vertb); 767 } 768 769 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi, 770 struct drm_connector_state *state, 771 struct drm_display_mode *mode) 772 { 773 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 774 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 775 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 776 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 777 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 778 VC5_HDMI_VERTA_VSP) | 779 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 780 VC5_HDMI_VERTA_VFP) | 781 VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL)); 782 u32 vertb = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) | 783 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end, 784 VC4_HDMI_VERTB_VBP)); 785 u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) | 786 VC4_SET_FIELD(mode->crtc_vtotal - 787 mode->crtc_vsync_end - 788 interlaced, 789 VC4_HDMI_VERTB_VBP)); 790 unsigned char gcp; 791 bool gcp_en; 792 u32 reg; 793 794 HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, 0x354021); 795 HDMI_WRITE(HDMI_HORZA, 796 (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) | 797 (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) | 798 VC4_SET_FIELD(mode->hdisplay * pixel_rep, 799 VC5_HDMI_HORZA_HAP) | 800 VC4_SET_FIELD((mode->hsync_start - 801 mode->hdisplay) * pixel_rep, 802 VC5_HDMI_HORZA_HFP)); 803 804 HDMI_WRITE(HDMI_HORZB, 805 VC4_SET_FIELD((mode->htotal - 806 mode->hsync_end) * pixel_rep, 807 VC5_HDMI_HORZB_HBP) | 808 VC4_SET_FIELD((mode->hsync_end - 809 mode->hsync_start) * pixel_rep, 810 VC5_HDMI_HORZB_HSP)); 811 812 HDMI_WRITE(HDMI_VERTA0, verta); 813 HDMI_WRITE(HDMI_VERTA1, verta); 814 815 HDMI_WRITE(HDMI_VERTB0, vertb_even); 816 HDMI_WRITE(HDMI_VERTB1, vertb); 817 818 switch (state->max_bpc) { 819 case 12: 820 gcp = 6; 821 gcp_en = true; 822 break; 823 case 10: 824 gcp = 5; 825 gcp_en = true; 826 break; 827 case 8: 828 default: 829 gcp = 4; 830 gcp_en = false; 831 break; 832 } 833 834 reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1); 835 reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK | 836 VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK); 837 reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) | 838 VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH); 839 HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg); 840 841 reg = HDMI_READ(HDMI_GCP_WORD_1); 842 reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK; 843 reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1); 844 HDMI_WRITE(HDMI_GCP_WORD_1, reg); 845 846 reg = HDMI_READ(HDMI_GCP_CONFIG); 847 reg &= ~VC5_HDMI_GCP_CONFIG_GCP_ENABLE; 848 reg |= gcp_en ? VC5_HDMI_GCP_CONFIG_GCP_ENABLE : 0; 849 HDMI_WRITE(HDMI_GCP_CONFIG, reg); 850 851 HDMI_WRITE(HDMI_CLOCK_STOP, 0); 852 } 853 854 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi) 855 { 856 u32 drift; 857 int ret; 858 859 drift = HDMI_READ(HDMI_FIFO_CTL); 860 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK; 861 862 HDMI_WRITE(HDMI_FIFO_CTL, 863 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 864 HDMI_WRITE(HDMI_FIFO_CTL, 865 drift | VC4_HDMI_FIFO_CTL_RECENTER); 866 usleep_range(1000, 1100); 867 HDMI_WRITE(HDMI_FIFO_CTL, 868 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 869 HDMI_WRITE(HDMI_FIFO_CTL, 870 drift | VC4_HDMI_FIFO_CTL_RECENTER); 871 872 ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) & 873 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1); 874 WARN_ONCE(ret, "Timeout waiting for " 875 "VC4_HDMI_FIFO_CTL_RECENTER_DONE"); 876 } 877 878 static struct drm_connector_state * 879 vc4_hdmi_encoder_get_connector_state(struct drm_encoder *encoder, 880 struct drm_atomic_state *state) 881 { 882 struct drm_connector_state *conn_state; 883 struct drm_connector *connector; 884 unsigned int i; 885 886 for_each_new_connector_in_state(state, connector, conn_state, i) { 887 if (conn_state->best_encoder == encoder) 888 return conn_state; 889 } 890 891 return NULL; 892 } 893 894 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder, 895 struct drm_atomic_state *state) 896 { 897 struct drm_connector_state *conn_state = 898 vc4_hdmi_encoder_get_connector_state(encoder, state); 899 struct vc4_hdmi_connector_state *vc4_conn_state = 900 conn_state_to_vc4_hdmi_conn_state(conn_state); 901 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; 902 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 903 unsigned long bvb_rate, pixel_rate, hsm_rate; 904 int ret; 905 906 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev); 907 if (ret < 0) { 908 DRM_ERROR("Failed to retain power domain: %d\n", ret); 909 return; 910 } 911 912 pixel_rate = vc4_conn_state->pixel_rate; 913 ret = clk_set_rate(vc4_hdmi->pixel_clock, pixel_rate); 914 if (ret) { 915 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret); 916 return; 917 } 918 919 ret = clk_prepare_enable(vc4_hdmi->pixel_clock); 920 if (ret) { 921 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret); 922 return; 923 } 924 925 /* 926 * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must 927 * be faster than pixel clock, infinitesimally faster, tested in 928 * simulation. Otherwise, exact value is unimportant for HDMI 929 * operation." This conflicts with bcm2835's vc4 documentation, which 930 * states HSM's clock has to be at least 108% of the pixel clock. 931 * 932 * Real life tests reveal that vc4's firmware statement holds up, and 933 * users are able to use pixel clocks closer to HSM's, namely for 934 * 1920x1200@60Hz. So it was decided to have leave a 1% margin between 935 * both clocks. Which, for RPi0-3 implies a maximum pixel clock of 936 * 162MHz. 937 * 938 * Additionally, the AXI clock needs to be at least 25% of 939 * pixel clock, but HSM ends up being the limiting factor. 940 */ 941 hsm_rate = max_t(unsigned long, 120000000, (pixel_rate / 100) * 101); 942 ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate); 943 if (ret) { 944 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret); 945 return; 946 } 947 948 vc4_hdmi_cec_update_clk_div(vc4_hdmi); 949 950 if (pixel_rate > 297000000) 951 bvb_rate = 300000000; 952 else if (pixel_rate > 148500000) 953 bvb_rate = 150000000; 954 else 955 bvb_rate = 75000000; 956 957 ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate); 958 if (ret) { 959 DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret); 960 clk_disable_unprepare(vc4_hdmi->pixel_clock); 961 return; 962 } 963 964 ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock); 965 if (ret) { 966 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret); 967 clk_disable_unprepare(vc4_hdmi->pixel_clock); 968 return; 969 } 970 971 if (vc4_hdmi->variant->phy_init) 972 vc4_hdmi->variant->phy_init(vc4_hdmi, vc4_conn_state); 973 974 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 975 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 976 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT | 977 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS); 978 979 if (vc4_hdmi->variant->set_timings) 980 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode); 981 } 982 983 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder, 984 struct drm_atomic_state *state) 985 { 986 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; 987 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 988 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 989 990 if (vc4_encoder->hdmi_monitor && 991 drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_LIMITED) { 992 if (vc4_hdmi->variant->csc_setup) 993 vc4_hdmi->variant->csc_setup(vc4_hdmi, true); 994 995 vc4_encoder->limited_rgb_range = true; 996 } else { 997 if (vc4_hdmi->variant->csc_setup) 998 vc4_hdmi->variant->csc_setup(vc4_hdmi, false); 999 1000 vc4_encoder->limited_rgb_range = false; 1001 } 1002 1003 HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N); 1004 } 1005 1006 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder, 1007 struct drm_atomic_state *state) 1008 { 1009 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; 1010 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1011 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 1012 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 1013 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 1014 int ret; 1015 1016 HDMI_WRITE(HDMI_VID_CTL, 1017 VC4_HD_VID_CTL_ENABLE | 1018 VC4_HD_VID_CTL_UNDERFLOW_ENABLE | 1019 VC4_HD_VID_CTL_FRAME_COUNTER_RESET | 1020 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) | 1021 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW)); 1022 1023 HDMI_WRITE(HDMI_VID_CTL, 1024 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX); 1025 1026 if (vc4_encoder->hdmi_monitor) { 1027 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1028 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 1029 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 1030 1031 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1032 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000); 1033 WARN_ONCE(ret, "Timeout waiting for " 1034 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 1035 } else { 1036 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 1037 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & 1038 ~(VC4_HDMI_RAM_PACKET_ENABLE)); 1039 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1040 HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1041 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 1042 1043 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1044 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000); 1045 WARN_ONCE(ret, "Timeout waiting for " 1046 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 1047 } 1048 1049 if (vc4_encoder->hdmi_monitor) { 1050 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1051 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE)); 1052 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1053 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 1054 VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT); 1055 1056 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 1057 VC4_HDMI_RAM_PACKET_ENABLE); 1058 1059 vc4_hdmi_set_infoframes(encoder); 1060 } 1061 1062 vc4_hdmi_recenter_fifo(vc4_hdmi); 1063 vc4_hdmi_enable_scrambling(encoder); 1064 } 1065 1066 static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder) 1067 { 1068 } 1069 1070 #define WIFI_2_4GHz_CH1_MIN_FREQ 2400000000ULL 1071 #define WIFI_2_4GHz_CH1_MAX_FREQ 2422000000ULL 1072 1073 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder, 1074 struct drm_crtc_state *crtc_state, 1075 struct drm_connector_state *conn_state) 1076 { 1077 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state); 1078 struct drm_display_mode *mode = &crtc_state->adjusted_mode; 1079 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1080 unsigned long long pixel_rate = mode->clock * 1000; 1081 unsigned long long tmds_rate; 1082 1083 if (vc4_hdmi->variant->unsupported_odd_h_timings && 1084 ((mode->hdisplay % 2) || (mode->hsync_start % 2) || 1085 (mode->hsync_end % 2) || (mode->htotal % 2))) 1086 return -EINVAL; 1087 1088 /* 1089 * The 1440p@60 pixel rate is in the same range than the first 1090 * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz 1091 * bandwidth). Slightly lower the frequency to bring it out of 1092 * the WiFi range. 1093 */ 1094 tmds_rate = pixel_rate * 10; 1095 if (vc4_hdmi->disable_wifi_frequencies && 1096 (tmds_rate >= WIFI_2_4GHz_CH1_MIN_FREQ && 1097 tmds_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) { 1098 mode->clock = 238560; 1099 pixel_rate = mode->clock * 1000; 1100 } 1101 1102 if (conn_state->max_bpc == 12) { 1103 pixel_rate = pixel_rate * 150; 1104 do_div(pixel_rate, 100); 1105 } else if (conn_state->max_bpc == 10) { 1106 pixel_rate = pixel_rate * 125; 1107 do_div(pixel_rate, 100); 1108 } 1109 1110 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 1111 pixel_rate = pixel_rate * 2; 1112 1113 if (pixel_rate > vc4_hdmi->variant->max_pixel_clock) 1114 return -EINVAL; 1115 1116 if (vc4_hdmi->disable_4kp60 && (pixel_rate > HDMI_14_MAX_TMDS_CLK)) 1117 return -EINVAL; 1118 1119 vc4_state->pixel_rate = pixel_rate; 1120 1121 return 0; 1122 } 1123 1124 static enum drm_mode_status 1125 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder, 1126 const struct drm_display_mode *mode) 1127 { 1128 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1129 1130 if (vc4_hdmi->variant->unsupported_odd_h_timings && 1131 ((mode->hdisplay % 2) || (mode->hsync_start % 2) || 1132 (mode->hsync_end % 2) || (mode->htotal % 2))) 1133 return MODE_H_ILLEGAL; 1134 1135 if ((mode->clock * 1000) > vc4_hdmi->variant->max_pixel_clock) 1136 return MODE_CLOCK_HIGH; 1137 1138 if (vc4_hdmi->disable_4kp60 && vc4_hdmi_mode_needs_scrambling(mode)) 1139 return MODE_CLOCK_HIGH; 1140 1141 return MODE_OK; 1142 } 1143 1144 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = { 1145 .atomic_check = vc4_hdmi_encoder_atomic_check, 1146 .mode_valid = vc4_hdmi_encoder_mode_valid, 1147 .disable = vc4_hdmi_encoder_disable, 1148 .enable = vc4_hdmi_encoder_enable, 1149 }; 1150 1151 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask) 1152 { 1153 int i; 1154 u32 channel_map = 0; 1155 1156 for (i = 0; i < 8; i++) { 1157 if (channel_mask & BIT(i)) 1158 channel_map |= i << (3 * i); 1159 } 1160 return channel_map; 1161 } 1162 1163 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask) 1164 { 1165 int i; 1166 u32 channel_map = 0; 1167 1168 for (i = 0; i < 8; i++) { 1169 if (channel_mask & BIT(i)) 1170 channel_map |= i << (4 * i); 1171 } 1172 return channel_map; 1173 } 1174 1175 /* HDMI audio codec callbacks */ 1176 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi) 1177 { 1178 u32 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock); 1179 unsigned long n, m; 1180 1181 rational_best_approximation(hsm_clock, vc4_hdmi->audio.samplerate, 1182 VC4_HD_MAI_SMP_N_MASK >> 1183 VC4_HD_MAI_SMP_N_SHIFT, 1184 (VC4_HD_MAI_SMP_M_MASK >> 1185 VC4_HD_MAI_SMP_M_SHIFT) + 1, 1186 &n, &m); 1187 1188 HDMI_WRITE(HDMI_MAI_SMP, 1189 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) | 1190 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M)); 1191 } 1192 1193 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi) 1194 { 1195 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base; 1196 struct drm_crtc *crtc = encoder->crtc; 1197 const struct drm_display_mode *mode = &crtc->state->adjusted_mode; 1198 u32 samplerate = vc4_hdmi->audio.samplerate; 1199 u32 n, cts; 1200 u64 tmp; 1201 1202 n = 128 * samplerate / 1000; 1203 tmp = (u64)(mode->clock * 1000) * n; 1204 do_div(tmp, 128 * samplerate); 1205 cts = tmp; 1206 1207 HDMI_WRITE(HDMI_CRP_CFG, 1208 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN | 1209 VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N)); 1210 1211 /* 1212 * We could get slightly more accurate clocks in some cases by 1213 * providing a CTS_1 value. The two CTS values are alternated 1214 * between based on the period fields 1215 */ 1216 HDMI_WRITE(HDMI_CTS_0, cts); 1217 HDMI_WRITE(HDMI_CTS_1, cts); 1218 } 1219 1220 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai) 1221 { 1222 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai); 1223 1224 return snd_soc_card_get_drvdata(card); 1225 } 1226 1227 static int vc4_hdmi_audio_startup(struct snd_pcm_substream *substream, 1228 struct snd_soc_dai *dai) 1229 { 1230 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai); 1231 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base; 1232 struct drm_connector *connector = &vc4_hdmi->connector; 1233 int ret; 1234 1235 if (vc4_hdmi->audio.substream && vc4_hdmi->audio.substream != substream) 1236 return -EINVAL; 1237 1238 vc4_hdmi->audio.substream = substream; 1239 1240 /* 1241 * If the HDMI encoder hasn't probed, or the encoder is 1242 * currently in DVI mode, treat the codec dai as missing. 1243 */ 1244 if (!encoder->crtc || !(HDMI_READ(HDMI_RAM_PACKET_CONFIG) & 1245 VC4_HDMI_RAM_PACKET_ENABLE)) 1246 return -ENODEV; 1247 1248 ret = snd_pcm_hw_constraint_eld(substream->runtime, connector->eld); 1249 if (ret) 1250 return ret; 1251 1252 return 0; 1253 } 1254 1255 static int vc4_hdmi_audio_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 1256 { 1257 return 0; 1258 } 1259 1260 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi) 1261 { 1262 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base; 1263 struct device *dev = &vc4_hdmi->pdev->dev; 1264 int ret; 1265 1266 vc4_hdmi->audio.streaming = false; 1267 ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO, false); 1268 if (ret) 1269 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret); 1270 1271 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET); 1272 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF); 1273 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH); 1274 } 1275 1276 static void vc4_hdmi_audio_shutdown(struct snd_pcm_substream *substream, 1277 struct snd_soc_dai *dai) 1278 { 1279 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai); 1280 1281 if (substream != vc4_hdmi->audio.substream) 1282 return; 1283 1284 vc4_hdmi_audio_reset(vc4_hdmi); 1285 1286 vc4_hdmi->audio.substream = NULL; 1287 } 1288 1289 /* HDMI audio codec callbacks */ 1290 static int vc4_hdmi_audio_hw_params(struct snd_pcm_substream *substream, 1291 struct snd_pcm_hw_params *params, 1292 struct snd_soc_dai *dai) 1293 { 1294 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai); 1295 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base; 1296 struct device *dev = &vc4_hdmi->pdev->dev; 1297 u32 audio_packet_config, channel_mask; 1298 u32 channel_map; 1299 1300 if (substream != vc4_hdmi->audio.substream) 1301 return -EINVAL; 1302 1303 dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__, 1304 params_rate(params), params_width(params), 1305 params_channels(params)); 1306 1307 vc4_hdmi->audio.channels = params_channels(params); 1308 vc4_hdmi->audio.samplerate = params_rate(params); 1309 1310 HDMI_WRITE(HDMI_MAI_CTL, 1311 VC4_HD_MAI_CTL_RESET | 1312 VC4_HD_MAI_CTL_FLUSH | 1313 VC4_HD_MAI_CTL_DLATE | 1314 VC4_HD_MAI_CTL_ERRORE | 1315 VC4_HD_MAI_CTL_ERRORF); 1316 1317 vc4_hdmi_audio_set_mai_clock(vc4_hdmi); 1318 1319 /* The B frame identifier should match the value used by alsa-lib (8) */ 1320 audio_packet_config = 1321 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT | 1322 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS | 1323 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER); 1324 1325 channel_mask = GENMASK(vc4_hdmi->audio.channels - 1, 0); 1326 audio_packet_config |= VC4_SET_FIELD(channel_mask, 1327 VC4_HDMI_AUDIO_PACKET_CEA_MASK); 1328 1329 /* Set the MAI threshold. This logic mimics the firmware's. */ 1330 if (vc4_hdmi->audio.samplerate > 96000) { 1331 HDMI_WRITE(HDMI_MAI_THR, 1332 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQHIGH) | 1333 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW)); 1334 } else if (vc4_hdmi->audio.samplerate > 48000) { 1335 HDMI_WRITE(HDMI_MAI_THR, 1336 VC4_SET_FIELD(0x14, VC4_HD_MAI_THR_DREQHIGH) | 1337 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW)); 1338 } else { 1339 HDMI_WRITE(HDMI_MAI_THR, 1340 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) | 1341 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) | 1342 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQHIGH) | 1343 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQLOW)); 1344 } 1345 1346 HDMI_WRITE(HDMI_MAI_CONFIG, 1347 VC4_HDMI_MAI_CONFIG_BIT_REVERSE | 1348 VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK)); 1349 1350 channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask); 1351 HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map); 1352 HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config); 1353 vc4_hdmi_set_n_cts(vc4_hdmi); 1354 1355 vc4_hdmi_set_audio_infoframe(encoder); 1356 1357 return 0; 1358 } 1359 1360 static int vc4_hdmi_audio_trigger(struct snd_pcm_substream *substream, int cmd, 1361 struct snd_soc_dai *dai) 1362 { 1363 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai); 1364 1365 switch (cmd) { 1366 case SNDRV_PCM_TRIGGER_START: 1367 vc4_hdmi->audio.streaming = true; 1368 1369 if (vc4_hdmi->variant->phy_rng_enable) 1370 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi); 1371 1372 HDMI_WRITE(HDMI_MAI_CTL, 1373 VC4_SET_FIELD(vc4_hdmi->audio.channels, 1374 VC4_HD_MAI_CTL_CHNUM) | 1375 VC4_HD_MAI_CTL_ENABLE); 1376 break; 1377 case SNDRV_PCM_TRIGGER_STOP: 1378 HDMI_WRITE(HDMI_MAI_CTL, 1379 VC4_HD_MAI_CTL_DLATE | 1380 VC4_HD_MAI_CTL_ERRORE | 1381 VC4_HD_MAI_CTL_ERRORF); 1382 1383 if (vc4_hdmi->variant->phy_rng_disable) 1384 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi); 1385 1386 vc4_hdmi->audio.streaming = false; 1387 1388 break; 1389 default: 1390 break; 1391 } 1392 1393 return 0; 1394 } 1395 1396 static inline struct vc4_hdmi * 1397 snd_component_to_hdmi(struct snd_soc_component *component) 1398 { 1399 struct snd_soc_card *card = snd_soc_component_get_drvdata(component); 1400 1401 return snd_soc_card_get_drvdata(card); 1402 } 1403 1404 static int vc4_hdmi_audio_eld_ctl_info(struct snd_kcontrol *kcontrol, 1405 struct snd_ctl_elem_info *uinfo) 1406 { 1407 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1408 struct vc4_hdmi *vc4_hdmi = snd_component_to_hdmi(component); 1409 struct drm_connector *connector = &vc4_hdmi->connector; 1410 1411 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 1412 uinfo->count = sizeof(connector->eld); 1413 1414 return 0; 1415 } 1416 1417 static int vc4_hdmi_audio_eld_ctl_get(struct snd_kcontrol *kcontrol, 1418 struct snd_ctl_elem_value *ucontrol) 1419 { 1420 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1421 struct vc4_hdmi *vc4_hdmi = snd_component_to_hdmi(component); 1422 struct drm_connector *connector = &vc4_hdmi->connector; 1423 1424 memcpy(ucontrol->value.bytes.data, connector->eld, 1425 sizeof(connector->eld)); 1426 1427 return 0; 1428 } 1429 1430 static const struct snd_kcontrol_new vc4_hdmi_audio_controls[] = { 1431 { 1432 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1433 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1434 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1435 .name = "ELD", 1436 .info = vc4_hdmi_audio_eld_ctl_info, 1437 .get = vc4_hdmi_audio_eld_ctl_get, 1438 }, 1439 }; 1440 1441 static const struct snd_soc_dapm_widget vc4_hdmi_audio_widgets[] = { 1442 SND_SOC_DAPM_OUTPUT("TX"), 1443 }; 1444 1445 static const struct snd_soc_dapm_route vc4_hdmi_audio_routes[] = { 1446 { "TX", NULL, "Playback" }, 1447 }; 1448 1449 static const struct snd_soc_component_driver vc4_hdmi_audio_component_drv = { 1450 .name = "vc4-hdmi-codec-dai-component", 1451 .controls = vc4_hdmi_audio_controls, 1452 .num_controls = ARRAY_SIZE(vc4_hdmi_audio_controls), 1453 .dapm_widgets = vc4_hdmi_audio_widgets, 1454 .num_dapm_widgets = ARRAY_SIZE(vc4_hdmi_audio_widgets), 1455 .dapm_routes = vc4_hdmi_audio_routes, 1456 .num_dapm_routes = ARRAY_SIZE(vc4_hdmi_audio_routes), 1457 .idle_bias_on = 1, 1458 .use_pmdown_time = 1, 1459 .endianness = 1, 1460 .non_legacy_dai_naming = 1, 1461 }; 1462 1463 static const struct snd_soc_dai_ops vc4_hdmi_audio_dai_ops = { 1464 .startup = vc4_hdmi_audio_startup, 1465 .shutdown = vc4_hdmi_audio_shutdown, 1466 .hw_params = vc4_hdmi_audio_hw_params, 1467 .set_fmt = vc4_hdmi_audio_set_fmt, 1468 .trigger = vc4_hdmi_audio_trigger, 1469 }; 1470 1471 static struct snd_soc_dai_driver vc4_hdmi_audio_codec_dai_drv = { 1472 .name = "vc4-hdmi-hifi", 1473 .playback = { 1474 .stream_name = "Playback", 1475 .channels_min = 2, 1476 .channels_max = 8, 1477 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 1478 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 1479 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 1480 SNDRV_PCM_RATE_192000, 1481 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 1482 }, 1483 }; 1484 1485 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = { 1486 .name = "vc4-hdmi-cpu-dai-component", 1487 }; 1488 1489 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai) 1490 { 1491 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai); 1492 1493 snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL); 1494 1495 return 0; 1496 } 1497 1498 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = { 1499 .name = "vc4-hdmi-cpu-dai", 1500 .probe = vc4_hdmi_audio_cpu_dai_probe, 1501 .playback = { 1502 .stream_name = "Playback", 1503 .channels_min = 1, 1504 .channels_max = 8, 1505 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 1506 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 1507 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 1508 SNDRV_PCM_RATE_192000, 1509 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 1510 }, 1511 .ops = &vc4_hdmi_audio_dai_ops, 1512 }; 1513 1514 static const struct snd_dmaengine_pcm_config pcm_conf = { 1515 .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx", 1516 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 1517 }; 1518 1519 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi) 1520 { 1521 const struct vc4_hdmi_register *mai_data = 1522 &vc4_hdmi->variant->registers[HDMI_MAI_DATA]; 1523 struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link; 1524 struct snd_soc_card *card = &vc4_hdmi->audio.card; 1525 struct device *dev = &vc4_hdmi->pdev->dev; 1526 const __be32 *addr; 1527 int index; 1528 int ret; 1529 1530 if (!of_find_property(dev->of_node, "dmas", NULL)) { 1531 dev_warn(dev, 1532 "'dmas' DT property is missing, no HDMI audio\n"); 1533 return 0; 1534 } 1535 1536 if (mai_data->reg != VC4_HD) { 1537 WARN_ONCE(true, "MAI isn't in the HD block\n"); 1538 return -EINVAL; 1539 } 1540 1541 /* 1542 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve 1543 * the bus address specified in the DT, because the physical address 1544 * (the one returned by platform_get_resource()) is not appropriate 1545 * for DMA transfers. 1546 * This VC/MMU should probably be exposed to avoid this kind of hacks. 1547 */ 1548 index = of_property_match_string(dev->of_node, "reg-names", "hd"); 1549 /* Before BCM2711, we don't have a named register range */ 1550 if (index < 0) 1551 index = 1; 1552 1553 addr = of_get_address(dev->of_node, index, NULL, NULL); 1554 1555 vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset; 1556 vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1557 vc4_hdmi->audio.dma_data.maxburst = 2; 1558 1559 ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0); 1560 if (ret) { 1561 dev_err(dev, "Could not register PCM component: %d\n", ret); 1562 return ret; 1563 } 1564 1565 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp, 1566 &vc4_hdmi_audio_cpu_dai_drv, 1); 1567 if (ret) { 1568 dev_err(dev, "Could not register CPU DAI: %d\n", ret); 1569 return ret; 1570 } 1571 1572 /* register component and codec dai */ 1573 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_component_drv, 1574 &vc4_hdmi_audio_codec_dai_drv, 1); 1575 if (ret) { 1576 dev_err(dev, "Could not register component: %d\n", ret); 1577 return ret; 1578 } 1579 1580 dai_link->cpus = &vc4_hdmi->audio.cpu; 1581 dai_link->codecs = &vc4_hdmi->audio.codec; 1582 dai_link->platforms = &vc4_hdmi->audio.platform; 1583 1584 dai_link->num_cpus = 1; 1585 dai_link->num_codecs = 1; 1586 dai_link->num_platforms = 1; 1587 1588 dai_link->name = "MAI"; 1589 dai_link->stream_name = "MAI PCM"; 1590 dai_link->codecs->dai_name = vc4_hdmi_audio_codec_dai_drv.name; 1591 dai_link->cpus->dai_name = dev_name(dev); 1592 dai_link->codecs->name = dev_name(dev); 1593 dai_link->platforms->name = dev_name(dev); 1594 1595 card->dai_link = dai_link; 1596 card->num_links = 1; 1597 card->name = vc4_hdmi->variant->card_name; 1598 card->driver_name = "vc4-hdmi"; 1599 card->dev = dev; 1600 card->owner = THIS_MODULE; 1601 1602 /* 1603 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and 1604 * stores a pointer to the snd card object in dev->driver_data. This 1605 * means we cannot use it for something else. The hdmi back-pointer is 1606 * now stored in card->drvdata and should be retrieved with 1607 * snd_soc_card_get_drvdata() if needed. 1608 */ 1609 snd_soc_card_set_drvdata(card, vc4_hdmi); 1610 ret = devm_snd_soc_register_card(dev, card); 1611 if (ret) 1612 dev_err(dev, "Could not register sound card: %d\n", ret); 1613 1614 return ret; 1615 1616 } 1617 1618 #ifdef CONFIG_DRM_VC4_HDMI_CEC 1619 static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv) 1620 { 1621 struct vc4_hdmi *vc4_hdmi = priv; 1622 1623 if (vc4_hdmi->cec_rx_msg.len) 1624 cec_received_msg(vc4_hdmi->cec_adap, 1625 &vc4_hdmi->cec_rx_msg); 1626 1627 return IRQ_HANDLED; 1628 } 1629 1630 static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv) 1631 { 1632 struct vc4_hdmi *vc4_hdmi = priv; 1633 1634 if (vc4_hdmi->cec_tx_ok) { 1635 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK, 1636 0, 0, 0, 0); 1637 } else { 1638 /* 1639 * This CEC implementation makes 1 retry, so if we 1640 * get a NACK, then that means it made 2 attempts. 1641 */ 1642 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK, 1643 0, 2, 0, 0); 1644 } 1645 return IRQ_HANDLED; 1646 } 1647 1648 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv) 1649 { 1650 struct vc4_hdmi *vc4_hdmi = priv; 1651 irqreturn_t ret; 1652 1653 if (vc4_hdmi->cec_irq_was_rx) 1654 ret = vc4_cec_irq_handler_rx_thread(irq, priv); 1655 else 1656 ret = vc4_cec_irq_handler_tx_thread(irq, priv); 1657 1658 return ret; 1659 } 1660 1661 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1) 1662 { 1663 struct drm_device *dev = vc4_hdmi->connector.dev; 1664 struct cec_msg *msg = &vc4_hdmi->cec_rx_msg; 1665 unsigned int i; 1666 1667 msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >> 1668 VC4_HDMI_CEC_REC_WRD_CNT_SHIFT); 1669 1670 if (msg->len > 16) { 1671 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len); 1672 return; 1673 } 1674 1675 for (i = 0; i < msg->len; i += 4) { 1676 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2)); 1677 1678 msg->msg[i] = val & 0xff; 1679 msg->msg[i + 1] = (val >> 8) & 0xff; 1680 msg->msg[i + 2] = (val >> 16) & 0xff; 1681 msg->msg[i + 3] = (val >> 24) & 0xff; 1682 } 1683 } 1684 1685 static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv) 1686 { 1687 struct vc4_hdmi *vc4_hdmi = priv; 1688 u32 cntrl1; 1689 1690 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1); 1691 vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD; 1692 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 1693 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 1694 1695 return IRQ_WAKE_THREAD; 1696 } 1697 1698 static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv) 1699 { 1700 struct vc4_hdmi *vc4_hdmi = priv; 1701 u32 cntrl1; 1702 1703 vc4_hdmi->cec_rx_msg.len = 0; 1704 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1); 1705 vc4_cec_read_msg(vc4_hdmi, cntrl1); 1706 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 1707 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 1708 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 1709 1710 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 1711 1712 return IRQ_WAKE_THREAD; 1713 } 1714 1715 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv) 1716 { 1717 struct vc4_hdmi *vc4_hdmi = priv; 1718 u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS); 1719 irqreturn_t ret; 1720 u32 cntrl5; 1721 1722 if (!(stat & VC4_HDMI_CPU_CEC)) 1723 return IRQ_NONE; 1724 1725 cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5); 1726 vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT; 1727 if (vc4_hdmi->cec_irq_was_rx) 1728 ret = vc4_cec_irq_handler_rx_bare(irq, priv); 1729 else 1730 ret = vc4_cec_irq_handler_tx_bare(irq, priv); 1731 1732 HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC); 1733 return ret; 1734 } 1735 1736 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable) 1737 { 1738 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 1739 /* clock period in microseconds */ 1740 const u32 usecs = 1000000 / CEC_CLOCK_FREQ; 1741 u32 val = HDMI_READ(HDMI_CEC_CNTRL_5); 1742 1743 val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET | 1744 VC4_HDMI_CEC_CNT_TO_4700_US_MASK | 1745 VC4_HDMI_CEC_CNT_TO_4500_US_MASK); 1746 val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) | 1747 ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT); 1748 1749 if (enable) { 1750 HDMI_WRITE(HDMI_CEC_CNTRL_5, val | 1751 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 1752 HDMI_WRITE(HDMI_CEC_CNTRL_5, val); 1753 HDMI_WRITE(HDMI_CEC_CNTRL_2, 1754 ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) | 1755 ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) | 1756 ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) | 1757 ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) | 1758 ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT)); 1759 HDMI_WRITE(HDMI_CEC_CNTRL_3, 1760 ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) | 1761 ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) | 1762 ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) | 1763 ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT)); 1764 HDMI_WRITE(HDMI_CEC_CNTRL_4, 1765 ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) | 1766 ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) | 1767 ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) | 1768 ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT)); 1769 1770 if (!vc4_hdmi->variant->external_irq_controller) 1771 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC); 1772 } else { 1773 if (!vc4_hdmi->variant->external_irq_controller) 1774 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC); 1775 HDMI_WRITE(HDMI_CEC_CNTRL_5, val | 1776 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 1777 } 1778 return 0; 1779 } 1780 1781 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr) 1782 { 1783 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 1784 1785 HDMI_WRITE(HDMI_CEC_CNTRL_1, 1786 (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) | 1787 (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT); 1788 return 0; 1789 } 1790 1791 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts, 1792 u32 signal_free_time, struct cec_msg *msg) 1793 { 1794 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 1795 struct drm_device *dev = vc4_hdmi->connector.dev; 1796 u32 val; 1797 unsigned int i; 1798 1799 if (msg->len > 16) { 1800 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len); 1801 return -ENOMEM; 1802 } 1803 1804 for (i = 0; i < msg->len; i += 4) 1805 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2), 1806 (msg->msg[i]) | 1807 (msg->msg[i + 1] << 8) | 1808 (msg->msg[i + 2] << 16) | 1809 (msg->msg[i + 3] << 24)); 1810 1811 val = HDMI_READ(HDMI_CEC_CNTRL_1); 1812 val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 1813 HDMI_WRITE(HDMI_CEC_CNTRL_1, val); 1814 val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK; 1815 val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT; 1816 val |= VC4_HDMI_CEC_START_XMIT_BEGIN; 1817 1818 HDMI_WRITE(HDMI_CEC_CNTRL_1, val); 1819 return 0; 1820 } 1821 1822 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = { 1823 .adap_enable = vc4_hdmi_cec_adap_enable, 1824 .adap_log_addr = vc4_hdmi_cec_adap_log_addr, 1825 .adap_transmit = vc4_hdmi_cec_adap_transmit, 1826 }; 1827 1828 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi) 1829 { 1830 struct cec_connector_info conn_info; 1831 struct platform_device *pdev = vc4_hdmi->pdev; 1832 struct device *dev = &pdev->dev; 1833 u32 value; 1834 int ret; 1835 1836 if (!of_find_property(dev->of_node, "interrupts", NULL)) { 1837 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n"); 1838 return 0; 1839 } 1840 1841 vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops, 1842 vc4_hdmi, "vc4", 1843 CEC_CAP_DEFAULTS | 1844 CEC_CAP_CONNECTOR_INFO, 1); 1845 ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap); 1846 if (ret < 0) 1847 return ret; 1848 1849 cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector); 1850 cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info); 1851 1852 value = HDMI_READ(HDMI_CEC_CNTRL_1); 1853 /* Set the logical address to Unregistered */ 1854 value |= VC4_HDMI_CEC_ADDR_MASK; 1855 HDMI_WRITE(HDMI_CEC_CNTRL_1, value); 1856 1857 vc4_hdmi_cec_update_clk_div(vc4_hdmi); 1858 1859 if (vc4_hdmi->variant->external_irq_controller) { 1860 ret = devm_request_threaded_irq(&pdev->dev, 1861 platform_get_irq_byname(pdev, "cec-rx"), 1862 vc4_cec_irq_handler_rx_bare, 1863 vc4_cec_irq_handler_rx_thread, 0, 1864 "vc4 hdmi cec rx", vc4_hdmi); 1865 if (ret) 1866 goto err_delete_cec_adap; 1867 1868 ret = devm_request_threaded_irq(&pdev->dev, 1869 platform_get_irq_byname(pdev, "cec-tx"), 1870 vc4_cec_irq_handler_tx_bare, 1871 vc4_cec_irq_handler_tx_thread, 0, 1872 "vc4 hdmi cec tx", vc4_hdmi); 1873 if (ret) 1874 goto err_delete_cec_adap; 1875 } else { 1876 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff); 1877 1878 ret = devm_request_threaded_irq(&pdev->dev, platform_get_irq(pdev, 0), 1879 vc4_cec_irq_handler, 1880 vc4_cec_irq_handler_thread, 0, 1881 "vc4 hdmi cec", vc4_hdmi); 1882 if (ret) 1883 goto err_delete_cec_adap; 1884 } 1885 1886 ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev); 1887 if (ret < 0) 1888 goto err_delete_cec_adap; 1889 1890 return 0; 1891 1892 err_delete_cec_adap: 1893 cec_delete_adapter(vc4_hdmi->cec_adap); 1894 1895 return ret; 1896 } 1897 1898 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi) 1899 { 1900 cec_unregister_adapter(vc4_hdmi->cec_adap); 1901 } 1902 #else 1903 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi) 1904 { 1905 return 0; 1906 } 1907 1908 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi) {}; 1909 1910 #endif 1911 1912 static int vc4_hdmi_build_regset(struct vc4_hdmi *vc4_hdmi, 1913 struct debugfs_regset32 *regset, 1914 enum vc4_hdmi_regs reg) 1915 { 1916 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant; 1917 struct debugfs_reg32 *regs, *new_regs; 1918 unsigned int count = 0; 1919 unsigned int i; 1920 1921 regs = kcalloc(variant->num_registers, sizeof(*regs), 1922 GFP_KERNEL); 1923 if (!regs) 1924 return -ENOMEM; 1925 1926 for (i = 0; i < variant->num_registers; i++) { 1927 const struct vc4_hdmi_register *field = &variant->registers[i]; 1928 1929 if (field->reg != reg) 1930 continue; 1931 1932 regs[count].name = field->name; 1933 regs[count].offset = field->offset; 1934 count++; 1935 } 1936 1937 new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL); 1938 if (!new_regs) 1939 return -ENOMEM; 1940 1941 regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg); 1942 regset->regs = new_regs; 1943 regset->nregs = count; 1944 1945 return 0; 1946 } 1947 1948 static int vc4_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi) 1949 { 1950 struct platform_device *pdev = vc4_hdmi->pdev; 1951 struct device *dev = &pdev->dev; 1952 int ret; 1953 1954 vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0); 1955 if (IS_ERR(vc4_hdmi->hdmicore_regs)) 1956 return PTR_ERR(vc4_hdmi->hdmicore_regs); 1957 1958 vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1); 1959 if (IS_ERR(vc4_hdmi->hd_regs)) 1960 return PTR_ERR(vc4_hdmi->hd_regs); 1961 1962 ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD); 1963 if (ret) 1964 return ret; 1965 1966 ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI); 1967 if (ret) 1968 return ret; 1969 1970 vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel"); 1971 if (IS_ERR(vc4_hdmi->pixel_clock)) { 1972 ret = PTR_ERR(vc4_hdmi->pixel_clock); 1973 if (ret != -EPROBE_DEFER) 1974 DRM_ERROR("Failed to get pixel clock\n"); 1975 return ret; 1976 } 1977 1978 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); 1979 if (IS_ERR(vc4_hdmi->hsm_clock)) { 1980 DRM_ERROR("Failed to get HDMI state machine clock\n"); 1981 return PTR_ERR(vc4_hdmi->hsm_clock); 1982 } 1983 vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock; 1984 vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock; 1985 1986 return 0; 1987 } 1988 1989 static int vc5_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi) 1990 { 1991 struct platform_device *pdev = vc4_hdmi->pdev; 1992 struct device *dev = &pdev->dev; 1993 struct resource *res; 1994 1995 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi"); 1996 if (!res) 1997 return -ENODEV; 1998 1999 vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start, 2000 resource_size(res)); 2001 if (!vc4_hdmi->hdmicore_regs) 2002 return -ENOMEM; 2003 2004 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd"); 2005 if (!res) 2006 return -ENODEV; 2007 2008 vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res)); 2009 if (!vc4_hdmi->hd_regs) 2010 return -ENOMEM; 2011 2012 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec"); 2013 if (!res) 2014 return -ENODEV; 2015 2016 vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res)); 2017 if (!vc4_hdmi->cec_regs) 2018 return -ENOMEM; 2019 2020 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc"); 2021 if (!res) 2022 return -ENODEV; 2023 2024 vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res)); 2025 if (!vc4_hdmi->csc_regs) 2026 return -ENOMEM; 2027 2028 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp"); 2029 if (!res) 2030 return -ENODEV; 2031 2032 vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res)); 2033 if (!vc4_hdmi->dvp_regs) 2034 return -ENOMEM; 2035 2036 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy"); 2037 if (!res) 2038 return -ENODEV; 2039 2040 vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res)); 2041 if (!vc4_hdmi->phy_regs) 2042 return -ENOMEM; 2043 2044 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet"); 2045 if (!res) 2046 return -ENODEV; 2047 2048 vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res)); 2049 if (!vc4_hdmi->ram_regs) 2050 return -ENOMEM; 2051 2052 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm"); 2053 if (!res) 2054 return -ENODEV; 2055 2056 vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res)); 2057 if (!vc4_hdmi->rm_regs) 2058 return -ENOMEM; 2059 2060 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); 2061 if (IS_ERR(vc4_hdmi->hsm_clock)) { 2062 DRM_ERROR("Failed to get HDMI state machine clock\n"); 2063 return PTR_ERR(vc4_hdmi->hsm_clock); 2064 } 2065 2066 vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb"); 2067 if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) { 2068 DRM_ERROR("Failed to get pixel bvb clock\n"); 2069 return PTR_ERR(vc4_hdmi->pixel_bvb_clock); 2070 } 2071 2072 vc4_hdmi->audio_clock = devm_clk_get(dev, "audio"); 2073 if (IS_ERR(vc4_hdmi->audio_clock)) { 2074 DRM_ERROR("Failed to get audio clock\n"); 2075 return PTR_ERR(vc4_hdmi->audio_clock); 2076 } 2077 2078 vc4_hdmi->cec_clock = devm_clk_get(dev, "cec"); 2079 if (IS_ERR(vc4_hdmi->cec_clock)) { 2080 DRM_ERROR("Failed to get CEC clock\n"); 2081 return PTR_ERR(vc4_hdmi->cec_clock); 2082 } 2083 2084 vc4_hdmi->reset = devm_reset_control_get(dev, NULL); 2085 if (IS_ERR(vc4_hdmi->reset)) { 2086 DRM_ERROR("Failed to get HDMI reset line\n"); 2087 return PTR_ERR(vc4_hdmi->reset); 2088 } 2089 2090 return 0; 2091 } 2092 2093 #ifdef CONFIG_PM 2094 static int vc4_hdmi_runtime_suspend(struct device *dev) 2095 { 2096 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 2097 2098 clk_disable_unprepare(vc4_hdmi->hsm_clock); 2099 2100 return 0; 2101 } 2102 2103 static int vc4_hdmi_runtime_resume(struct device *dev) 2104 { 2105 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 2106 int ret; 2107 2108 ret = clk_prepare_enable(vc4_hdmi->hsm_clock); 2109 if (ret) 2110 return ret; 2111 2112 return 0; 2113 } 2114 #endif 2115 2116 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data) 2117 { 2118 const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev); 2119 struct platform_device *pdev = to_platform_device(dev); 2120 struct drm_device *drm = dev_get_drvdata(master); 2121 struct vc4_hdmi *vc4_hdmi; 2122 struct drm_encoder *encoder; 2123 struct device_node *ddc_node; 2124 int ret; 2125 2126 vc4_hdmi = devm_kzalloc(dev, sizeof(*vc4_hdmi), GFP_KERNEL); 2127 if (!vc4_hdmi) 2128 return -ENOMEM; 2129 INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq); 2130 2131 dev_set_drvdata(dev, vc4_hdmi); 2132 encoder = &vc4_hdmi->encoder.base.base; 2133 vc4_hdmi->encoder.base.type = variant->encoder_type; 2134 vc4_hdmi->encoder.base.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure; 2135 vc4_hdmi->encoder.base.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable; 2136 vc4_hdmi->encoder.base.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable; 2137 vc4_hdmi->encoder.base.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable; 2138 vc4_hdmi->encoder.base.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown; 2139 vc4_hdmi->pdev = pdev; 2140 vc4_hdmi->variant = variant; 2141 2142 ret = variant->init_resources(vc4_hdmi); 2143 if (ret) 2144 return ret; 2145 2146 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0); 2147 if (!ddc_node) { 2148 DRM_ERROR("Failed to find ddc node in device tree\n"); 2149 return -ENODEV; 2150 } 2151 2152 vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node); 2153 of_node_put(ddc_node); 2154 if (!vc4_hdmi->ddc) { 2155 DRM_DEBUG("Failed to get ddc i2c adapter by node\n"); 2156 return -EPROBE_DEFER; 2157 } 2158 2159 /* Only use the GPIO HPD pin if present in the DT, otherwise 2160 * we'll use the HDMI core's register. 2161 */ 2162 vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN); 2163 if (IS_ERR(vc4_hdmi->hpd_gpio)) { 2164 ret = PTR_ERR(vc4_hdmi->hpd_gpio); 2165 goto err_put_ddc; 2166 } 2167 2168 vc4_hdmi->disable_wifi_frequencies = 2169 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence"); 2170 2171 if (variant->max_pixel_clock == 600000000) { 2172 struct vc4_dev *vc4 = to_vc4_dev(drm); 2173 long max_rate = clk_round_rate(vc4->hvs->core_clk, 550000000); 2174 2175 if (max_rate < 550000000) 2176 vc4_hdmi->disable_4kp60 = true; 2177 } 2178 2179 if (vc4_hdmi->variant->reset) 2180 vc4_hdmi->variant->reset(vc4_hdmi); 2181 2182 if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") || 2183 of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1")) && 2184 HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) { 2185 clk_prepare_enable(vc4_hdmi->pixel_clock); 2186 clk_prepare_enable(vc4_hdmi->hsm_clock); 2187 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock); 2188 } 2189 2190 pm_runtime_enable(dev); 2191 2192 drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS); 2193 drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs); 2194 2195 ret = vc4_hdmi_connector_init(drm, vc4_hdmi); 2196 if (ret) 2197 goto err_destroy_encoder; 2198 2199 ret = vc4_hdmi_cec_init(vc4_hdmi); 2200 if (ret) 2201 goto err_destroy_conn; 2202 2203 ret = vc4_hdmi_audio_init(vc4_hdmi); 2204 if (ret) 2205 goto err_free_cec; 2206 2207 vc4_debugfs_add_file(drm, variant->debugfs_name, 2208 vc4_hdmi_debugfs_regs, 2209 vc4_hdmi); 2210 2211 return 0; 2212 2213 err_free_cec: 2214 vc4_hdmi_cec_exit(vc4_hdmi); 2215 err_destroy_conn: 2216 vc4_hdmi_connector_destroy(&vc4_hdmi->connector); 2217 err_destroy_encoder: 2218 drm_encoder_cleanup(encoder); 2219 pm_runtime_disable(dev); 2220 err_put_ddc: 2221 put_device(&vc4_hdmi->ddc->dev); 2222 2223 return ret; 2224 } 2225 2226 static void vc4_hdmi_unbind(struct device *dev, struct device *master, 2227 void *data) 2228 { 2229 struct vc4_hdmi *vc4_hdmi; 2230 2231 /* 2232 * ASoC makes it a bit hard to retrieve a pointer to the 2233 * vc4_hdmi structure. Registering the card will overwrite our 2234 * device drvdata with a pointer to the snd_soc_card structure, 2235 * which can then be used to retrieve whatever drvdata we want 2236 * to associate. 2237 * 2238 * However, that doesn't fly in the case where we wouldn't 2239 * register an ASoC card (because of an old DT that is missing 2240 * the dmas properties for example), then the card isn't 2241 * registered and the device drvdata wouldn't be set. 2242 * 2243 * We can deal with both cases by making sure a snd_soc_card 2244 * pointer and a vc4_hdmi structure are pointing to the same 2245 * memory address, so we can treat them indistinctly without any 2246 * issue. 2247 */ 2248 BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0); 2249 BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0); 2250 vc4_hdmi = dev_get_drvdata(dev); 2251 2252 kfree(vc4_hdmi->hdmi_regset.regs); 2253 kfree(vc4_hdmi->hd_regset.regs); 2254 2255 vc4_hdmi_cec_exit(vc4_hdmi); 2256 vc4_hdmi_connector_destroy(&vc4_hdmi->connector); 2257 drm_encoder_cleanup(&vc4_hdmi->encoder.base.base); 2258 2259 pm_runtime_disable(dev); 2260 2261 put_device(&vc4_hdmi->ddc->dev); 2262 } 2263 2264 static const struct component_ops vc4_hdmi_ops = { 2265 .bind = vc4_hdmi_bind, 2266 .unbind = vc4_hdmi_unbind, 2267 }; 2268 2269 static int vc4_hdmi_dev_probe(struct platform_device *pdev) 2270 { 2271 return component_add(&pdev->dev, &vc4_hdmi_ops); 2272 } 2273 2274 static int vc4_hdmi_dev_remove(struct platform_device *pdev) 2275 { 2276 component_del(&pdev->dev, &vc4_hdmi_ops); 2277 return 0; 2278 } 2279 2280 static const struct vc4_hdmi_variant bcm2835_variant = { 2281 .encoder_type = VC4_ENCODER_TYPE_HDMI0, 2282 .debugfs_name = "hdmi_regs", 2283 .card_name = "vc4-hdmi", 2284 .max_pixel_clock = 162000000, 2285 .registers = vc4_hdmi_fields, 2286 .num_registers = ARRAY_SIZE(vc4_hdmi_fields), 2287 2288 .init_resources = vc4_hdmi_init_resources, 2289 .csc_setup = vc4_hdmi_csc_setup, 2290 .reset = vc4_hdmi_reset, 2291 .set_timings = vc4_hdmi_set_timings, 2292 .phy_init = vc4_hdmi_phy_init, 2293 .phy_disable = vc4_hdmi_phy_disable, 2294 .phy_rng_enable = vc4_hdmi_phy_rng_enable, 2295 .phy_rng_disable = vc4_hdmi_phy_rng_disable, 2296 .channel_map = vc4_hdmi_channel_map, 2297 .supports_hdr = false, 2298 }; 2299 2300 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = { 2301 .encoder_type = VC4_ENCODER_TYPE_HDMI0, 2302 .debugfs_name = "hdmi0_regs", 2303 .card_name = "vc4-hdmi-0", 2304 .max_pixel_clock = HDMI_14_MAX_TMDS_CLK, 2305 .registers = vc5_hdmi_hdmi0_fields, 2306 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi0_fields), 2307 .phy_lane_mapping = { 2308 PHY_LANE_0, 2309 PHY_LANE_1, 2310 PHY_LANE_2, 2311 PHY_LANE_CK, 2312 }, 2313 .unsupported_odd_h_timings = true, 2314 .external_irq_controller = true, 2315 2316 .init_resources = vc5_hdmi_init_resources, 2317 .csc_setup = vc5_hdmi_csc_setup, 2318 .reset = vc5_hdmi_reset, 2319 .set_timings = vc5_hdmi_set_timings, 2320 .phy_init = vc5_hdmi_phy_init, 2321 .phy_disable = vc5_hdmi_phy_disable, 2322 .phy_rng_enable = vc5_hdmi_phy_rng_enable, 2323 .phy_rng_disable = vc5_hdmi_phy_rng_disable, 2324 .channel_map = vc5_hdmi_channel_map, 2325 .supports_hdr = true, 2326 }; 2327 2328 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = { 2329 .encoder_type = VC4_ENCODER_TYPE_HDMI1, 2330 .debugfs_name = "hdmi1_regs", 2331 .card_name = "vc4-hdmi-1", 2332 .max_pixel_clock = HDMI_14_MAX_TMDS_CLK, 2333 .registers = vc5_hdmi_hdmi1_fields, 2334 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi1_fields), 2335 .phy_lane_mapping = { 2336 PHY_LANE_1, 2337 PHY_LANE_0, 2338 PHY_LANE_CK, 2339 PHY_LANE_2, 2340 }, 2341 .unsupported_odd_h_timings = true, 2342 .external_irq_controller = true, 2343 2344 .init_resources = vc5_hdmi_init_resources, 2345 .csc_setup = vc5_hdmi_csc_setup, 2346 .reset = vc5_hdmi_reset, 2347 .set_timings = vc5_hdmi_set_timings, 2348 .phy_init = vc5_hdmi_phy_init, 2349 .phy_disable = vc5_hdmi_phy_disable, 2350 .phy_rng_enable = vc5_hdmi_phy_rng_enable, 2351 .phy_rng_disable = vc5_hdmi_phy_rng_disable, 2352 .channel_map = vc5_hdmi_channel_map, 2353 .supports_hdr = true, 2354 }; 2355 2356 static const struct of_device_id vc4_hdmi_dt_match[] = { 2357 { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant }, 2358 { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant }, 2359 { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant }, 2360 {} 2361 }; 2362 2363 static const struct dev_pm_ops vc4_hdmi_pm_ops = { 2364 SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend, 2365 vc4_hdmi_runtime_resume, 2366 NULL) 2367 }; 2368 2369 struct platform_driver vc4_hdmi_driver = { 2370 .probe = vc4_hdmi_dev_probe, 2371 .remove = vc4_hdmi_dev_remove, 2372 .driver = { 2373 .name = "vc4_hdmi", 2374 .of_match_table = vc4_hdmi_dt_match, 2375 .pm = &vc4_hdmi_pm_ops, 2376 }, 2377 }; 2378