1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 Broadcom 4 * Copyright (c) 2014 The Linux Foundation. All rights reserved. 5 * Copyright (C) 2013 Red Hat 6 * Author: Rob Clark <robdclark@gmail.com> 7 */ 8 9 /** 10 * DOC: VC4 Falcon HDMI module 11 * 12 * The HDMI core has a state machine and a PHY. On BCM2835, most of 13 * the unit operates off of the HSM clock from CPRMAN. It also 14 * internally uses the PLLH_PIX clock for the PHY. 15 * 16 * HDMI infoframes are kept within a small packet ram, where each 17 * packet can be individually enabled for including in a frame. 18 * 19 * HDMI audio is implemented entirely within the HDMI IP block. A 20 * register in the HDMI encoder takes SPDIF frames from the DMA engine 21 * and transfers them over an internal MAI (multi-channel audio 22 * interconnect) bus to the encoder side for insertion into the video 23 * blank regions. 24 * 25 * The driver's HDMI encoder does not yet support power management. 26 * The HDMI encoder's power domain and the HSM/pixel clocks are kept 27 * continuously running, and only the HDMI logic and packet ram are 28 * powered off/on at disable/enable time. 29 * 30 * The driver does not yet support CEC control, though the HDMI 31 * encoder block has CEC support. 32 */ 33 34 #include <drm/display/drm_hdmi_helper.h> 35 #include <drm/display/drm_scdc_helper.h> 36 #include <drm/drm_atomic_helper.h> 37 #include <drm/drm_probe_helper.h> 38 #include <drm/drm_simple_kms_helper.h> 39 #include <linux/clk.h> 40 #include <linux/component.h> 41 #include <linux/i2c.h> 42 #include <linux/of_address.h> 43 #include <linux/of_gpio.h> 44 #include <linux/of_platform.h> 45 #include <linux/pm_runtime.h> 46 #include <linux/rational.h> 47 #include <linux/reset.h> 48 #include <sound/dmaengine_pcm.h> 49 #include <sound/hdmi-codec.h> 50 #include <sound/pcm_drm_eld.h> 51 #include <sound/pcm_params.h> 52 #include <sound/soc.h> 53 #include "media/cec.h" 54 #include "vc4_drv.h" 55 #include "vc4_hdmi.h" 56 #include "vc4_hdmi_regs.h" 57 #include "vc4_regs.h" 58 59 #define VC5_HDMI_HORZA_HFP_SHIFT 16 60 #define VC5_HDMI_HORZA_HFP_MASK VC4_MASK(28, 16) 61 #define VC5_HDMI_HORZA_VPOS BIT(15) 62 #define VC5_HDMI_HORZA_HPOS BIT(14) 63 #define VC5_HDMI_HORZA_HAP_SHIFT 0 64 #define VC5_HDMI_HORZA_HAP_MASK VC4_MASK(13, 0) 65 66 #define VC5_HDMI_HORZB_HBP_SHIFT 16 67 #define VC5_HDMI_HORZB_HBP_MASK VC4_MASK(26, 16) 68 #define VC5_HDMI_HORZB_HSP_SHIFT 0 69 #define VC5_HDMI_HORZB_HSP_MASK VC4_MASK(10, 0) 70 71 #define VC5_HDMI_VERTA_VSP_SHIFT 24 72 #define VC5_HDMI_VERTA_VSP_MASK VC4_MASK(28, 24) 73 #define VC5_HDMI_VERTA_VFP_SHIFT 16 74 #define VC5_HDMI_VERTA_VFP_MASK VC4_MASK(22, 16) 75 #define VC5_HDMI_VERTA_VAL_SHIFT 0 76 #define VC5_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0) 77 78 #define VC5_HDMI_VERTB_VSPO_SHIFT 16 79 #define VC5_HDMI_VERTB_VSPO_MASK VC4_MASK(29, 16) 80 81 #define VC5_HDMI_SCRAMBLER_CTL_ENABLE BIT(0) 82 83 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT 8 84 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK VC4_MASK(10, 8) 85 86 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT 0 87 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK VC4_MASK(3, 0) 88 89 #define VC5_HDMI_GCP_CONFIG_GCP_ENABLE BIT(31) 90 91 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT 8 92 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK VC4_MASK(15, 8) 93 94 # define VC4_HD_M_SW_RST BIT(2) 95 # define VC4_HD_M_ENABLE BIT(0) 96 97 #define HSM_MIN_CLOCK_FREQ 120000000 98 #define CEC_CLOCK_FREQ 40000 99 100 #define HDMI_14_MAX_TMDS_CLK (340 * 1000 * 1000) 101 102 static const char * const output_format_str[] = { 103 [VC4_HDMI_OUTPUT_RGB] = "RGB", 104 [VC4_HDMI_OUTPUT_YUV420] = "YUV 4:2:0", 105 [VC4_HDMI_OUTPUT_YUV422] = "YUV 4:2:2", 106 [VC4_HDMI_OUTPUT_YUV444] = "YUV 4:4:4", 107 }; 108 109 static const char *vc4_hdmi_output_fmt_str(enum vc4_hdmi_output_format fmt) 110 { 111 if (fmt >= ARRAY_SIZE(output_format_str)) 112 return "invalid"; 113 114 return output_format_str[fmt]; 115 } 116 117 static unsigned long long 118 vc4_hdmi_encoder_compute_mode_clock(const struct drm_display_mode *mode, 119 unsigned int bpc, enum vc4_hdmi_output_format fmt); 120 121 static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode, 122 unsigned int bpc, 123 enum vc4_hdmi_output_format fmt) 124 { 125 unsigned long long clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc, fmt); 126 127 return clock > HDMI_14_MAX_TMDS_CLK; 128 } 129 130 static bool vc4_hdmi_is_full_range_rgb(struct vc4_hdmi *vc4_hdmi, 131 const struct drm_display_mode *mode) 132 { 133 struct drm_display_info *display = &vc4_hdmi->connector.display_info; 134 135 return !display->is_hdmi || 136 drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_FULL; 137 } 138 139 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused) 140 { 141 struct drm_info_node *node = (struct drm_info_node *)m->private; 142 struct vc4_hdmi *vc4_hdmi = node->info_ent->data; 143 struct drm_printer p = drm_seq_file_printer(m); 144 145 drm_print_regset32(&p, &vc4_hdmi->hdmi_regset); 146 drm_print_regset32(&p, &vc4_hdmi->hd_regset); 147 148 return 0; 149 } 150 151 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi) 152 { 153 unsigned long flags; 154 155 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 156 157 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST); 158 udelay(1); 159 HDMI_WRITE(HDMI_M_CTL, 0); 160 161 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE); 162 163 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 164 VC4_HDMI_SW_RESET_HDMI | 165 VC4_HDMI_SW_RESET_FORMAT_DETECT); 166 167 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0); 168 169 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 170 } 171 172 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi) 173 { 174 unsigned long flags; 175 176 reset_control_reset(vc4_hdmi->reset); 177 178 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 179 180 HDMI_WRITE(HDMI_DVP_CTL, 0); 181 182 HDMI_WRITE(HDMI_CLOCK_STOP, 183 HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL); 184 185 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 186 } 187 188 #ifdef CONFIG_DRM_VC4_HDMI_CEC 189 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) 190 { 191 unsigned long cec_rate = clk_get_rate(vc4_hdmi->cec_clock); 192 unsigned long flags; 193 u16 clk_cnt; 194 u32 value; 195 196 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 197 198 value = HDMI_READ(HDMI_CEC_CNTRL_1); 199 value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK; 200 201 /* 202 * Set the clock divider: the hsm_clock rate and this divider 203 * setting will give a 40 kHz CEC clock. 204 */ 205 clk_cnt = cec_rate / CEC_CLOCK_FREQ; 206 value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT; 207 HDMI_WRITE(HDMI_CEC_CNTRL_1, value); 208 209 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 210 } 211 #else 212 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {} 213 #endif 214 215 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder); 216 217 static enum drm_connector_status 218 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force) 219 { 220 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 221 bool connected = false; 222 223 mutex_lock(&vc4_hdmi->mutex); 224 225 WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev)); 226 227 if (vc4_hdmi->hpd_gpio) { 228 if (gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio)) 229 connected = true; 230 } else { 231 if (vc4_hdmi->variant->hp_detect && 232 vc4_hdmi->variant->hp_detect(vc4_hdmi)) 233 connected = true; 234 } 235 236 if (connected) { 237 if (connector->status != connector_status_connected) { 238 struct edid *edid = drm_get_edid(connector, vc4_hdmi->ddc); 239 240 if (edid) { 241 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid); 242 kfree(edid); 243 } 244 } 245 246 vc4_hdmi_enable_scrambling(&vc4_hdmi->encoder.base); 247 pm_runtime_put(&vc4_hdmi->pdev->dev); 248 mutex_unlock(&vc4_hdmi->mutex); 249 return connector_status_connected; 250 } 251 252 cec_phys_addr_invalidate(vc4_hdmi->cec_adap); 253 pm_runtime_put(&vc4_hdmi->pdev->dev); 254 mutex_unlock(&vc4_hdmi->mutex); 255 return connector_status_disconnected; 256 } 257 258 static void vc4_hdmi_connector_destroy(struct drm_connector *connector) 259 { 260 drm_connector_unregister(connector); 261 drm_connector_cleanup(connector); 262 } 263 264 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector) 265 { 266 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 267 int ret = 0; 268 struct edid *edid; 269 270 mutex_lock(&vc4_hdmi->mutex); 271 272 edid = drm_get_edid(connector, vc4_hdmi->ddc); 273 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid); 274 if (!edid) { 275 ret = -ENODEV; 276 goto out; 277 } 278 279 drm_connector_update_edid_property(connector, edid); 280 ret = drm_add_edid_modes(connector, edid); 281 kfree(edid); 282 283 if (vc4_hdmi->disable_4kp60) { 284 struct drm_device *drm = connector->dev; 285 struct drm_display_mode *mode; 286 287 list_for_each_entry(mode, &connector->probed_modes, head) { 288 if (vc4_hdmi_mode_needs_scrambling(mode, 8, VC4_HDMI_OUTPUT_RGB)) { 289 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz."); 290 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60."); 291 } 292 } 293 } 294 295 out: 296 mutex_unlock(&vc4_hdmi->mutex); 297 298 return ret; 299 } 300 301 static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector, 302 struct drm_atomic_state *state) 303 { 304 struct drm_connector_state *old_state = 305 drm_atomic_get_old_connector_state(state, connector); 306 struct drm_connector_state *new_state = 307 drm_atomic_get_new_connector_state(state, connector); 308 struct drm_crtc *crtc = new_state->crtc; 309 310 if (!crtc) 311 return 0; 312 313 if (old_state->colorspace != new_state->colorspace || 314 !drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) { 315 struct drm_crtc_state *crtc_state; 316 317 crtc_state = drm_atomic_get_crtc_state(state, crtc); 318 if (IS_ERR(crtc_state)) 319 return PTR_ERR(crtc_state); 320 321 crtc_state->mode_changed = true; 322 } 323 324 return 0; 325 } 326 327 static void vc4_hdmi_connector_reset(struct drm_connector *connector) 328 { 329 struct vc4_hdmi_connector_state *old_state = 330 conn_state_to_vc4_hdmi_conn_state(connector->state); 331 struct vc4_hdmi_connector_state *new_state = 332 kzalloc(sizeof(*new_state), GFP_KERNEL); 333 334 if (connector->state) 335 __drm_atomic_helper_connector_destroy_state(connector->state); 336 337 kfree(old_state); 338 __drm_atomic_helper_connector_reset(connector, &new_state->base); 339 340 if (!new_state) 341 return; 342 343 new_state->base.max_bpc = 8; 344 new_state->base.max_requested_bpc = 8; 345 new_state->output_format = VC4_HDMI_OUTPUT_RGB; 346 drm_atomic_helper_connector_tv_reset(connector); 347 } 348 349 static struct drm_connector_state * 350 vc4_hdmi_connector_duplicate_state(struct drm_connector *connector) 351 { 352 struct drm_connector_state *conn_state = connector->state; 353 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state); 354 struct vc4_hdmi_connector_state *new_state; 355 356 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL); 357 if (!new_state) 358 return NULL; 359 360 new_state->tmds_char_rate = vc4_state->tmds_char_rate; 361 new_state->output_bpc = vc4_state->output_bpc; 362 new_state->output_format = vc4_state->output_format; 363 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base); 364 365 return &new_state->base; 366 } 367 368 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = { 369 .detect = vc4_hdmi_connector_detect, 370 .fill_modes = drm_helper_probe_single_connector_modes, 371 .destroy = vc4_hdmi_connector_destroy, 372 .reset = vc4_hdmi_connector_reset, 373 .atomic_duplicate_state = vc4_hdmi_connector_duplicate_state, 374 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 375 }; 376 377 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = { 378 .get_modes = vc4_hdmi_connector_get_modes, 379 .atomic_check = vc4_hdmi_connector_atomic_check, 380 }; 381 382 static int vc4_hdmi_connector_init(struct drm_device *dev, 383 struct vc4_hdmi *vc4_hdmi) 384 { 385 struct drm_connector *connector = &vc4_hdmi->connector; 386 struct drm_encoder *encoder = &vc4_hdmi->encoder.base; 387 int ret; 388 389 drm_connector_init_with_ddc(dev, connector, 390 &vc4_hdmi_connector_funcs, 391 DRM_MODE_CONNECTOR_HDMIA, 392 vc4_hdmi->ddc); 393 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs); 394 395 /* 396 * Some of the properties below require access to state, like bpc. 397 * Allocate some default initial connector state with our reset helper. 398 */ 399 if (connector->funcs->reset) 400 connector->funcs->reset(connector); 401 402 /* Create and attach TV margin props to this connector. */ 403 ret = drm_mode_create_tv_margin_properties(dev); 404 if (ret) 405 return ret; 406 407 ret = drm_mode_create_hdmi_colorspace_property(connector); 408 if (ret) 409 return ret; 410 411 drm_connector_attach_colorspace_property(connector); 412 drm_connector_attach_tv_margin_properties(connector); 413 drm_connector_attach_max_bpc_property(connector, 8, 12); 414 415 connector->polled = (DRM_CONNECTOR_POLL_CONNECT | 416 DRM_CONNECTOR_POLL_DISCONNECT); 417 418 connector->interlace_allowed = 1; 419 connector->doublescan_allowed = 0; 420 421 if (vc4_hdmi->variant->supports_hdr) 422 drm_connector_attach_hdr_output_metadata_property(connector); 423 424 drm_connector_attach_encoder(connector, encoder); 425 426 return 0; 427 } 428 429 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder, 430 enum hdmi_infoframe_type type, 431 bool poll) 432 { 433 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 434 u32 packet_id = type - 0x80; 435 unsigned long flags; 436 437 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 438 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 439 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id)); 440 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 441 442 if (!poll) 443 return 0; 444 445 return wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) & 446 BIT(packet_id)), 100); 447 } 448 449 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder, 450 union hdmi_infoframe *frame) 451 { 452 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 453 u32 packet_id = frame->any.type - 0x80; 454 const struct vc4_hdmi_register *ram_packet_start = 455 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START]; 456 u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id; 457 void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi, 458 ram_packet_start->reg); 459 uint8_t buffer[VC4_HDMI_PACKET_STRIDE]; 460 unsigned long flags; 461 ssize_t len, i; 462 int ret; 463 464 WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) & 465 VC4_HDMI_RAM_PACKET_ENABLE), 466 "Packet RAM has to be on to store the packet."); 467 468 len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer)); 469 if (len < 0) 470 return; 471 472 ret = vc4_hdmi_stop_packet(encoder, frame->any.type, true); 473 if (ret) { 474 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret); 475 return; 476 } 477 478 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 479 480 for (i = 0; i < len; i += 7) { 481 writel(buffer[i + 0] << 0 | 482 buffer[i + 1] << 8 | 483 buffer[i + 2] << 16, 484 base + packet_reg); 485 packet_reg += 4; 486 487 writel(buffer[i + 3] << 0 | 488 buffer[i + 4] << 8 | 489 buffer[i + 5] << 16 | 490 buffer[i + 6] << 24, 491 base + packet_reg); 492 packet_reg += 4; 493 } 494 495 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 496 HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id)); 497 498 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 499 500 ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) & 501 BIT(packet_id)), 100); 502 if (ret) 503 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret); 504 } 505 506 static void vc4_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame, 507 enum vc4_hdmi_output_format fmt) 508 { 509 switch (fmt) { 510 case VC4_HDMI_OUTPUT_RGB: 511 frame->colorspace = HDMI_COLORSPACE_RGB; 512 break; 513 514 case VC4_HDMI_OUTPUT_YUV420: 515 frame->colorspace = HDMI_COLORSPACE_YUV420; 516 break; 517 518 case VC4_HDMI_OUTPUT_YUV422: 519 frame->colorspace = HDMI_COLORSPACE_YUV422; 520 break; 521 522 case VC4_HDMI_OUTPUT_YUV444: 523 frame->colorspace = HDMI_COLORSPACE_YUV444; 524 break; 525 526 default: 527 break; 528 } 529 } 530 531 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder) 532 { 533 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 534 struct drm_connector *connector = &vc4_hdmi->connector; 535 struct drm_connector_state *cstate = connector->state; 536 struct vc4_hdmi_connector_state *vc4_state = 537 conn_state_to_vc4_hdmi_conn_state(cstate); 538 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 539 union hdmi_infoframe frame; 540 int ret; 541 542 lockdep_assert_held(&vc4_hdmi->mutex); 543 544 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, 545 connector, mode); 546 if (ret < 0) { 547 DRM_ERROR("couldn't fill AVI infoframe\n"); 548 return; 549 } 550 551 drm_hdmi_avi_infoframe_quant_range(&frame.avi, 552 connector, mode, 553 vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode) ? 554 HDMI_QUANTIZATION_RANGE_FULL : 555 HDMI_QUANTIZATION_RANGE_LIMITED); 556 drm_hdmi_avi_infoframe_colorimetry(&frame.avi, cstate); 557 vc4_hdmi_avi_infoframe_colorspace(&frame.avi, vc4_state->output_format); 558 drm_hdmi_avi_infoframe_bars(&frame.avi, cstate); 559 560 vc4_hdmi_write_infoframe(encoder, &frame); 561 } 562 563 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder) 564 { 565 union hdmi_infoframe frame; 566 int ret; 567 568 ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore"); 569 if (ret < 0) { 570 DRM_ERROR("couldn't fill SPD infoframe\n"); 571 return; 572 } 573 574 frame.spd.sdi = HDMI_SPD_SDI_PC; 575 576 vc4_hdmi_write_infoframe(encoder, &frame); 577 } 578 579 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder) 580 { 581 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 582 struct hdmi_audio_infoframe *audio = &vc4_hdmi->audio.infoframe; 583 union hdmi_infoframe frame; 584 585 memcpy(&frame.audio, audio, sizeof(*audio)); 586 vc4_hdmi_write_infoframe(encoder, &frame); 587 } 588 589 static void vc4_hdmi_set_hdr_infoframe(struct drm_encoder *encoder) 590 { 591 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 592 struct drm_connector *connector = &vc4_hdmi->connector; 593 struct drm_connector_state *conn_state = connector->state; 594 union hdmi_infoframe frame; 595 596 lockdep_assert_held(&vc4_hdmi->mutex); 597 598 if (!vc4_hdmi->variant->supports_hdr) 599 return; 600 601 if (!conn_state->hdr_output_metadata) 602 return; 603 604 if (drm_hdmi_infoframe_set_hdr_metadata(&frame.drm, conn_state)) 605 return; 606 607 vc4_hdmi_write_infoframe(encoder, &frame); 608 } 609 610 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder) 611 { 612 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 613 614 lockdep_assert_held(&vc4_hdmi->mutex); 615 616 vc4_hdmi_set_avi_infoframe(encoder); 617 vc4_hdmi_set_spd_infoframe(encoder); 618 /* 619 * If audio was streaming, then we need to reenabled the audio 620 * infoframe here during encoder_enable. 621 */ 622 if (vc4_hdmi->audio.streaming) 623 vc4_hdmi_set_audio_infoframe(encoder); 624 625 vc4_hdmi_set_hdr_infoframe(encoder); 626 } 627 628 static bool vc4_hdmi_supports_scrambling(struct drm_encoder *encoder, 629 struct drm_display_mode *mode) 630 { 631 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 632 struct drm_display_info *display = &vc4_hdmi->connector.display_info; 633 634 lockdep_assert_held(&vc4_hdmi->mutex); 635 636 if (!display->is_hdmi) 637 return false; 638 639 if (!display->hdmi.scdc.supported || 640 !display->hdmi.scdc.scrambling.supported) 641 return false; 642 643 return true; 644 } 645 646 #define SCRAMBLING_POLLING_DELAY_MS 1000 647 648 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder) 649 { 650 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 651 struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 652 unsigned long flags; 653 654 lockdep_assert_held(&vc4_hdmi->mutex); 655 656 if (!vc4_hdmi_supports_scrambling(encoder, mode)) 657 return; 658 659 if (!vc4_hdmi_mode_needs_scrambling(mode, 660 vc4_hdmi->output_bpc, 661 vc4_hdmi->output_format)) 662 return; 663 664 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true); 665 drm_scdc_set_scrambling(vc4_hdmi->ddc, true); 666 667 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 668 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) | 669 VC5_HDMI_SCRAMBLER_CTL_ENABLE); 670 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 671 672 vc4_hdmi->scdc_enabled = true; 673 674 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work, 675 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS)); 676 } 677 678 static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder) 679 { 680 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 681 unsigned long flags; 682 683 lockdep_assert_held(&vc4_hdmi->mutex); 684 685 if (!vc4_hdmi->scdc_enabled) 686 return; 687 688 vc4_hdmi->scdc_enabled = false; 689 690 if (delayed_work_pending(&vc4_hdmi->scrambling_work)) 691 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work); 692 693 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 694 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) & 695 ~VC5_HDMI_SCRAMBLER_CTL_ENABLE); 696 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 697 698 drm_scdc_set_scrambling(vc4_hdmi->ddc, false); 699 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, false); 700 } 701 702 static void vc4_hdmi_scrambling_wq(struct work_struct *work) 703 { 704 struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work), 705 struct vc4_hdmi, 706 scrambling_work); 707 708 if (drm_scdc_get_scrambling_status(vc4_hdmi->ddc)) 709 return; 710 711 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true); 712 drm_scdc_set_scrambling(vc4_hdmi->ddc, true); 713 714 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work, 715 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS)); 716 } 717 718 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder, 719 struct drm_atomic_state *state) 720 { 721 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 722 unsigned long flags; 723 724 mutex_lock(&vc4_hdmi->mutex); 725 726 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 727 728 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0); 729 730 HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB); 731 732 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 733 734 mdelay(1); 735 736 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 737 HDMI_WRITE(HDMI_VID_CTL, 738 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE); 739 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 740 741 vc4_hdmi_disable_scrambling(encoder); 742 743 mutex_unlock(&vc4_hdmi->mutex); 744 } 745 746 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder, 747 struct drm_atomic_state *state) 748 { 749 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 750 unsigned long flags; 751 int ret; 752 753 mutex_lock(&vc4_hdmi->mutex); 754 755 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 756 HDMI_WRITE(HDMI_VID_CTL, 757 HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX); 758 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 759 760 if (vc4_hdmi->variant->phy_disable) 761 vc4_hdmi->variant->phy_disable(vc4_hdmi); 762 763 clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock); 764 clk_disable_unprepare(vc4_hdmi->pixel_clock); 765 766 ret = pm_runtime_put(&vc4_hdmi->pdev->dev); 767 if (ret < 0) 768 DRM_ERROR("Failed to release power domain: %d\n", ret); 769 770 mutex_unlock(&vc4_hdmi->mutex); 771 } 772 773 static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder) 774 { 775 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 776 777 mutex_lock(&vc4_hdmi->mutex); 778 vc4_hdmi->output_enabled = false; 779 mutex_unlock(&vc4_hdmi->mutex); 780 } 781 782 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, 783 struct drm_connector_state *state, 784 const struct drm_display_mode *mode) 785 { 786 unsigned long flags; 787 u32 csc_ctl; 788 789 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 790 791 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR, 792 VC4_HD_CSC_CTL_ORDER); 793 794 if (!vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode)) { 795 /* CEA VICs other than #1 requre limited range RGB 796 * output unless overridden by an AVI infoframe. 797 * Apply a colorspace conversion to squash 0-255 down 798 * to 16-235. The matrix here is: 799 * 800 * [ 0 0 0.8594 16] 801 * [ 0 0.8594 0 16] 802 * [ 0.8594 0 0 16] 803 * [ 0 0 0 1] 804 */ 805 csc_ctl |= VC4_HD_CSC_CTL_ENABLE; 806 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC; 807 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM, 808 VC4_HD_CSC_CTL_MODE); 809 810 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000); 811 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0); 812 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000); 813 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000); 814 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0); 815 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000); 816 } 817 818 /* The RGB order applies even when CSC is disabled. */ 819 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl); 820 821 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 822 } 823 824 /* 825 * If we need to output Full Range RGB, then use the unity matrix 826 * 827 * [ 1 0 0 0] 828 * [ 0 1 0 0] 829 * [ 0 0 1 0] 830 * 831 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets 832 */ 833 static const u16 vc5_hdmi_csc_full_rgb_unity[3][4] = { 834 { 0x2000, 0x0000, 0x0000, 0x0000 }, 835 { 0x0000, 0x2000, 0x0000, 0x0000 }, 836 { 0x0000, 0x0000, 0x2000, 0x0000 }, 837 }; 838 839 /* 840 * CEA VICs other than #1 require limited range RGB output unless 841 * overridden by an AVI infoframe. Apply a colorspace conversion to 842 * squash 0-255 down to 16-235. The matrix here is: 843 * 844 * [ 0.8594 0 0 16] 845 * [ 0 0.8594 0 16] 846 * [ 0 0 0.8594 16] 847 * 848 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets 849 */ 850 static const u16 vc5_hdmi_csc_full_rgb_to_limited_rgb[3][4] = { 851 { 0x1b80, 0x0000, 0x0000, 0x0400 }, 852 { 0x0000, 0x1b80, 0x0000, 0x0400 }, 853 { 0x0000, 0x0000, 0x1b80, 0x0400 }, 854 }; 855 856 /* 857 * Conversion between Full Range RGB and Full Range YUV422 using the 858 * BT.709 Colorspace 859 * 860 * 861 * [ 0.181906 0.611804 0.061758 16 ] 862 * [ -0.100268 -0.337232 0.437500 128 ] 863 * [ 0.437500 -0.397386 -0.040114 128 ] 864 * 865 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets 866 */ 867 static const u16 vc5_hdmi_csc_full_rgb_to_limited_yuv422_bt709[3][4] = { 868 { 0x05d2, 0x1394, 0x01fa, 0x0400 }, 869 { 0xfccc, 0xf536, 0x0e00, 0x2000 }, 870 { 0x0e00, 0xf34a, 0xfeb8, 0x2000 }, 871 }; 872 873 /* 874 * Conversion between Full Range RGB and Full Range YUV444 using the 875 * BT.709 Colorspace 876 * 877 * [ -0.100268 -0.337232 0.437500 128 ] 878 * [ 0.437500 -0.397386 -0.040114 128 ] 879 * [ 0.181906 0.611804 0.061758 16 ] 880 * 881 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets 882 */ 883 static const u16 vc5_hdmi_csc_full_rgb_to_limited_yuv444_bt709[3][4] = { 884 { 0xfccc, 0xf536, 0x0e00, 0x2000 }, 885 { 0x0e00, 0xf34a, 0xfeb8, 0x2000 }, 886 { 0x05d2, 0x1394, 0x01fa, 0x0400 }, 887 }; 888 889 static void vc5_hdmi_set_csc_coeffs(struct vc4_hdmi *vc4_hdmi, 890 const u16 coeffs[3][4]) 891 { 892 lockdep_assert_held(&vc4_hdmi->hw_lock); 893 894 HDMI_WRITE(HDMI_CSC_12_11, (coeffs[0][1] << 16) | coeffs[0][0]); 895 HDMI_WRITE(HDMI_CSC_14_13, (coeffs[0][3] << 16) | coeffs[0][2]); 896 HDMI_WRITE(HDMI_CSC_22_21, (coeffs[1][1] << 16) | coeffs[1][0]); 897 HDMI_WRITE(HDMI_CSC_24_23, (coeffs[1][3] << 16) | coeffs[1][2]); 898 HDMI_WRITE(HDMI_CSC_32_31, (coeffs[2][1] << 16) | coeffs[2][0]); 899 HDMI_WRITE(HDMI_CSC_34_33, (coeffs[2][3] << 16) | coeffs[2][2]); 900 } 901 902 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, 903 struct drm_connector_state *state, 904 const struct drm_display_mode *mode) 905 { 906 struct vc4_hdmi_connector_state *vc4_state = 907 conn_state_to_vc4_hdmi_conn_state(state); 908 unsigned long flags; 909 u32 if_cfg = 0; 910 u32 if_xbar = 0x543210; 911 u32 csc_chan_ctl = 0; 912 u32 csc_ctl = VC5_MT_CP_CSC_CTL_ENABLE | VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM, 913 VC5_MT_CP_CSC_CTL_MODE); 914 915 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 916 917 switch (vc4_state->output_format) { 918 case VC4_HDMI_OUTPUT_YUV444: 919 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_limited_yuv444_bt709); 920 break; 921 922 case VC4_HDMI_OUTPUT_YUV422: 923 csc_ctl |= VC4_SET_FIELD(VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422_STANDARD, 924 VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422) | 925 VC5_MT_CP_CSC_CTL_USE_444_TO_422 | 926 VC5_MT_CP_CSC_CTL_USE_RNG_SUPPRESSION; 927 928 csc_chan_ctl |= VC4_SET_FIELD(VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP_LEGACY_STYLE, 929 VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP); 930 931 if_cfg |= VC4_SET_FIELD(VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422_FORMAT_422_LEGACY, 932 VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422); 933 934 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_limited_yuv422_bt709); 935 break; 936 937 case VC4_HDMI_OUTPUT_RGB: 938 if_xbar = 0x354021; 939 940 if (!vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode)) 941 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_limited_rgb); 942 else 943 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_unity); 944 break; 945 946 default: 947 break; 948 } 949 950 HDMI_WRITE(HDMI_VEC_INTERFACE_CFG, if_cfg); 951 HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, if_xbar); 952 HDMI_WRITE(HDMI_CSC_CHANNEL_CTL, csc_chan_ctl); 953 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl); 954 955 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 956 } 957 958 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi, 959 struct drm_connector_state *state, 960 struct drm_display_mode *mode) 961 { 962 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 963 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 964 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 965 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 966 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 967 VC4_HDMI_VERTA_VSP) | 968 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 969 VC4_HDMI_VERTA_VFP) | 970 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL)); 971 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 972 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end, 973 VC4_HDMI_VERTB_VBP)); 974 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 975 VC4_SET_FIELD(mode->crtc_vtotal - 976 mode->crtc_vsync_end - 977 interlaced, 978 VC4_HDMI_VERTB_VBP)); 979 unsigned long flags; 980 981 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 982 983 HDMI_WRITE(HDMI_HORZA, 984 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) | 985 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) | 986 VC4_SET_FIELD(mode->hdisplay * pixel_rep, 987 VC4_HDMI_HORZA_HAP)); 988 989 HDMI_WRITE(HDMI_HORZB, 990 VC4_SET_FIELD((mode->htotal - 991 mode->hsync_end) * pixel_rep, 992 VC4_HDMI_HORZB_HBP) | 993 VC4_SET_FIELD((mode->hsync_end - 994 mode->hsync_start) * pixel_rep, 995 VC4_HDMI_HORZB_HSP) | 996 VC4_SET_FIELD((mode->hsync_start - 997 mode->hdisplay) * pixel_rep, 998 VC4_HDMI_HORZB_HFP)); 999 1000 HDMI_WRITE(HDMI_VERTA0, verta); 1001 HDMI_WRITE(HDMI_VERTA1, verta); 1002 1003 HDMI_WRITE(HDMI_VERTB0, vertb_even); 1004 HDMI_WRITE(HDMI_VERTB1, vertb); 1005 1006 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1007 } 1008 1009 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi, 1010 struct drm_connector_state *state, 1011 struct drm_display_mode *mode) 1012 { 1013 const struct vc4_hdmi_connector_state *vc4_state = 1014 conn_state_to_vc4_hdmi_conn_state(state); 1015 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 1016 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 1017 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 1018 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 1019 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 1020 VC5_HDMI_VERTA_VSP) | 1021 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 1022 VC5_HDMI_VERTA_VFP) | 1023 VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL)); 1024 u32 vertb = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) | 1025 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end, 1026 VC4_HDMI_VERTB_VBP)); 1027 u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) | 1028 VC4_SET_FIELD(mode->crtc_vtotal - 1029 mode->crtc_vsync_end - 1030 interlaced, 1031 VC4_HDMI_VERTB_VBP)); 1032 unsigned long flags; 1033 unsigned char gcp; 1034 bool gcp_en; 1035 u32 reg; 1036 1037 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1038 1039 HDMI_WRITE(HDMI_HORZA, 1040 (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) | 1041 (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) | 1042 VC4_SET_FIELD(mode->hdisplay * pixel_rep, 1043 VC5_HDMI_HORZA_HAP) | 1044 VC4_SET_FIELD((mode->hsync_start - 1045 mode->hdisplay) * pixel_rep, 1046 VC5_HDMI_HORZA_HFP)); 1047 1048 HDMI_WRITE(HDMI_HORZB, 1049 VC4_SET_FIELD((mode->htotal - 1050 mode->hsync_end) * pixel_rep, 1051 VC5_HDMI_HORZB_HBP) | 1052 VC4_SET_FIELD((mode->hsync_end - 1053 mode->hsync_start) * pixel_rep, 1054 VC5_HDMI_HORZB_HSP)); 1055 1056 HDMI_WRITE(HDMI_VERTA0, verta); 1057 HDMI_WRITE(HDMI_VERTA1, verta); 1058 1059 HDMI_WRITE(HDMI_VERTB0, vertb_even); 1060 HDMI_WRITE(HDMI_VERTB1, vertb); 1061 1062 switch (vc4_state->output_bpc) { 1063 case 12: 1064 gcp = 6; 1065 gcp_en = true; 1066 break; 1067 case 10: 1068 gcp = 5; 1069 gcp_en = true; 1070 break; 1071 case 8: 1072 default: 1073 gcp = 4; 1074 gcp_en = false; 1075 break; 1076 } 1077 1078 /* 1079 * YCC422 is always 36-bit and not considered deep colour so 1080 * doesn't signal in GCP. 1081 */ 1082 if (vc4_state->output_format == VC4_HDMI_OUTPUT_YUV422) { 1083 gcp = 4; 1084 gcp_en = false; 1085 } 1086 1087 reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1); 1088 reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK | 1089 VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK); 1090 reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) | 1091 VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH); 1092 HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg); 1093 1094 reg = HDMI_READ(HDMI_GCP_WORD_1); 1095 reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK; 1096 reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1); 1097 HDMI_WRITE(HDMI_GCP_WORD_1, reg); 1098 1099 reg = HDMI_READ(HDMI_GCP_CONFIG); 1100 reg &= ~VC5_HDMI_GCP_CONFIG_GCP_ENABLE; 1101 reg |= gcp_en ? VC5_HDMI_GCP_CONFIG_GCP_ENABLE : 0; 1102 HDMI_WRITE(HDMI_GCP_CONFIG, reg); 1103 1104 HDMI_WRITE(HDMI_CLOCK_STOP, 0); 1105 1106 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1107 } 1108 1109 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi) 1110 { 1111 unsigned long flags; 1112 u32 drift; 1113 int ret; 1114 1115 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1116 1117 drift = HDMI_READ(HDMI_FIFO_CTL); 1118 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK; 1119 1120 HDMI_WRITE(HDMI_FIFO_CTL, 1121 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 1122 HDMI_WRITE(HDMI_FIFO_CTL, 1123 drift | VC4_HDMI_FIFO_CTL_RECENTER); 1124 1125 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1126 1127 usleep_range(1000, 1100); 1128 1129 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1130 1131 HDMI_WRITE(HDMI_FIFO_CTL, 1132 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 1133 HDMI_WRITE(HDMI_FIFO_CTL, 1134 drift | VC4_HDMI_FIFO_CTL_RECENTER); 1135 1136 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1137 1138 ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) & 1139 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1); 1140 WARN_ONCE(ret, "Timeout waiting for " 1141 "VC4_HDMI_FIFO_CTL_RECENTER_DONE"); 1142 } 1143 1144 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder, 1145 struct drm_atomic_state *state) 1146 { 1147 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1148 struct drm_connector *connector = &vc4_hdmi->connector; 1149 struct drm_connector_state *conn_state = 1150 drm_atomic_get_new_connector_state(state, connector); 1151 struct vc4_hdmi_connector_state *vc4_conn_state = 1152 conn_state_to_vc4_hdmi_conn_state(conn_state); 1153 struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1154 unsigned long tmds_char_rate = vc4_conn_state->tmds_char_rate; 1155 unsigned long bvb_rate, hsm_rate; 1156 unsigned long flags; 1157 int ret; 1158 1159 mutex_lock(&vc4_hdmi->mutex); 1160 1161 /* 1162 * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must 1163 * be faster than pixel clock, infinitesimally faster, tested in 1164 * simulation. Otherwise, exact value is unimportant for HDMI 1165 * operation." This conflicts with bcm2835's vc4 documentation, which 1166 * states HSM's clock has to be at least 108% of the pixel clock. 1167 * 1168 * Real life tests reveal that vc4's firmware statement holds up, and 1169 * users are able to use pixel clocks closer to HSM's, namely for 1170 * 1920x1200@60Hz. So it was decided to have leave a 1% margin between 1171 * both clocks. Which, for RPi0-3 implies a maximum pixel clock of 1172 * 162MHz. 1173 * 1174 * Additionally, the AXI clock needs to be at least 25% of 1175 * pixel clock, but HSM ends up being the limiting factor. 1176 */ 1177 hsm_rate = max_t(unsigned long, 120000000, (tmds_char_rate / 100) * 101); 1178 ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate); 1179 if (ret) { 1180 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret); 1181 goto out; 1182 } 1183 1184 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev); 1185 if (ret < 0) { 1186 DRM_ERROR("Failed to retain power domain: %d\n", ret); 1187 goto out; 1188 } 1189 1190 ret = clk_set_rate(vc4_hdmi->pixel_clock, tmds_char_rate); 1191 if (ret) { 1192 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret); 1193 goto err_put_runtime_pm; 1194 } 1195 1196 ret = clk_prepare_enable(vc4_hdmi->pixel_clock); 1197 if (ret) { 1198 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret); 1199 goto err_put_runtime_pm; 1200 } 1201 1202 1203 vc4_hdmi_cec_update_clk_div(vc4_hdmi); 1204 1205 if (tmds_char_rate > 297000000) 1206 bvb_rate = 300000000; 1207 else if (tmds_char_rate > 148500000) 1208 bvb_rate = 150000000; 1209 else 1210 bvb_rate = 75000000; 1211 1212 ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate); 1213 if (ret) { 1214 DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret); 1215 goto err_disable_pixel_clock; 1216 } 1217 1218 ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock); 1219 if (ret) { 1220 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret); 1221 goto err_disable_pixel_clock; 1222 } 1223 1224 if (vc4_hdmi->variant->phy_init) 1225 vc4_hdmi->variant->phy_init(vc4_hdmi, vc4_conn_state); 1226 1227 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1228 1229 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1230 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 1231 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT | 1232 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS); 1233 1234 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1235 1236 if (vc4_hdmi->variant->set_timings) 1237 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode); 1238 1239 mutex_unlock(&vc4_hdmi->mutex); 1240 1241 return; 1242 1243 err_disable_pixel_clock: 1244 clk_disable_unprepare(vc4_hdmi->pixel_clock); 1245 err_put_runtime_pm: 1246 pm_runtime_put(&vc4_hdmi->pdev->dev); 1247 out: 1248 mutex_unlock(&vc4_hdmi->mutex); 1249 return; 1250 } 1251 1252 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder, 1253 struct drm_atomic_state *state) 1254 { 1255 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1256 struct drm_connector *connector = &vc4_hdmi->connector; 1257 struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1258 struct drm_connector_state *conn_state = 1259 drm_atomic_get_new_connector_state(state, connector); 1260 unsigned long flags; 1261 1262 mutex_lock(&vc4_hdmi->mutex); 1263 1264 if (vc4_hdmi->variant->csc_setup) 1265 vc4_hdmi->variant->csc_setup(vc4_hdmi, conn_state, mode); 1266 1267 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1268 HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N); 1269 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1270 1271 mutex_unlock(&vc4_hdmi->mutex); 1272 } 1273 1274 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder, 1275 struct drm_atomic_state *state) 1276 { 1277 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1278 struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1279 struct drm_display_info *display = &vc4_hdmi->connector.display_info; 1280 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 1281 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 1282 unsigned long flags; 1283 int ret; 1284 1285 mutex_lock(&vc4_hdmi->mutex); 1286 1287 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1288 1289 HDMI_WRITE(HDMI_VID_CTL, 1290 VC4_HD_VID_CTL_ENABLE | 1291 VC4_HD_VID_CTL_CLRRGB | 1292 VC4_HD_VID_CTL_UNDERFLOW_ENABLE | 1293 VC4_HD_VID_CTL_FRAME_COUNTER_RESET | 1294 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) | 1295 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW)); 1296 1297 HDMI_WRITE(HDMI_VID_CTL, 1298 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX); 1299 1300 if (display->is_hdmi) { 1301 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1302 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 1303 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 1304 1305 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1306 1307 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1308 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000); 1309 WARN_ONCE(ret, "Timeout waiting for " 1310 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 1311 } else { 1312 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 1313 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & 1314 ~(VC4_HDMI_RAM_PACKET_ENABLE)); 1315 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1316 HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1317 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 1318 1319 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1320 1321 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1322 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000); 1323 WARN_ONCE(ret, "Timeout waiting for " 1324 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 1325 } 1326 1327 if (display->is_hdmi) { 1328 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1329 1330 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1331 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE)); 1332 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1333 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 1334 VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT); 1335 1336 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 1337 VC4_HDMI_RAM_PACKET_ENABLE); 1338 1339 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1340 1341 vc4_hdmi_set_infoframes(encoder); 1342 } 1343 1344 vc4_hdmi_recenter_fifo(vc4_hdmi); 1345 vc4_hdmi_enable_scrambling(encoder); 1346 1347 mutex_unlock(&vc4_hdmi->mutex); 1348 } 1349 1350 static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder) 1351 { 1352 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1353 1354 mutex_lock(&vc4_hdmi->mutex); 1355 vc4_hdmi->output_enabled = true; 1356 mutex_unlock(&vc4_hdmi->mutex); 1357 } 1358 1359 static void vc4_hdmi_encoder_atomic_mode_set(struct drm_encoder *encoder, 1360 struct drm_crtc_state *crtc_state, 1361 struct drm_connector_state *conn_state) 1362 { 1363 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1364 struct vc4_hdmi_connector_state *vc4_state = 1365 conn_state_to_vc4_hdmi_conn_state(conn_state); 1366 1367 mutex_lock(&vc4_hdmi->mutex); 1368 drm_mode_copy(&vc4_hdmi->saved_adjusted_mode, 1369 &crtc_state->adjusted_mode); 1370 vc4_hdmi->output_bpc = vc4_state->output_bpc; 1371 vc4_hdmi->output_format = vc4_state->output_format; 1372 mutex_unlock(&vc4_hdmi->mutex); 1373 } 1374 1375 static bool 1376 vc4_hdmi_sink_supports_format_bpc(const struct vc4_hdmi *vc4_hdmi, 1377 const struct drm_display_info *info, 1378 const struct drm_display_mode *mode, 1379 unsigned int format, unsigned int bpc) 1380 { 1381 struct drm_device *dev = vc4_hdmi->connector.dev; 1382 u8 vic = drm_match_cea_mode(mode); 1383 1384 if (vic == 1 && bpc != 8) { 1385 drm_dbg(dev, "VIC1 requires a bpc of 8, got %u\n", bpc); 1386 return false; 1387 } 1388 1389 if (!info->is_hdmi && 1390 (format != VC4_HDMI_OUTPUT_RGB || bpc != 8)) { 1391 drm_dbg(dev, "DVI Monitors require an RGB output at 8 bpc\n"); 1392 return false; 1393 } 1394 1395 switch (format) { 1396 case VC4_HDMI_OUTPUT_RGB: 1397 drm_dbg(dev, "RGB Format, checking the constraints.\n"); 1398 1399 if (!(info->color_formats & DRM_COLOR_FORMAT_RGB444)) 1400 return false; 1401 1402 if (bpc == 10 && !(info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30)) { 1403 drm_dbg(dev, "10 BPC but sink doesn't support Deep Color 30.\n"); 1404 return false; 1405 } 1406 1407 if (bpc == 12 && !(info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36)) { 1408 drm_dbg(dev, "12 BPC but sink doesn't support Deep Color 36.\n"); 1409 return false; 1410 } 1411 1412 drm_dbg(dev, "RGB format supported in that configuration.\n"); 1413 1414 return true; 1415 1416 case VC4_HDMI_OUTPUT_YUV422: 1417 drm_dbg(dev, "YUV422 format, checking the constraints.\n"); 1418 1419 if (!(info->color_formats & DRM_COLOR_FORMAT_YCBCR422)) { 1420 drm_dbg(dev, "Sink doesn't support YUV422.\n"); 1421 return false; 1422 } 1423 1424 if (bpc != 12) { 1425 drm_dbg(dev, "YUV422 only supports 12 bpc.\n"); 1426 return false; 1427 } 1428 1429 drm_dbg(dev, "YUV422 format supported in that configuration.\n"); 1430 1431 return true; 1432 1433 case VC4_HDMI_OUTPUT_YUV444: 1434 drm_dbg(dev, "YUV444 format, checking the constraints.\n"); 1435 1436 if (!(info->color_formats & DRM_COLOR_FORMAT_YCBCR444)) { 1437 drm_dbg(dev, "Sink doesn't support YUV444.\n"); 1438 return false; 1439 } 1440 1441 if (bpc == 10 && !(info->edid_hdmi_ycbcr444_dc_modes & DRM_EDID_HDMI_DC_30)) { 1442 drm_dbg(dev, "10 BPC but sink doesn't support Deep Color 30.\n"); 1443 return false; 1444 } 1445 1446 if (bpc == 12 && !(info->edid_hdmi_ycbcr444_dc_modes & DRM_EDID_HDMI_DC_36)) { 1447 drm_dbg(dev, "12 BPC but sink doesn't support Deep Color 36.\n"); 1448 return false; 1449 } 1450 1451 drm_dbg(dev, "YUV444 format supported in that configuration.\n"); 1452 1453 return true; 1454 } 1455 1456 return false; 1457 } 1458 1459 static enum drm_mode_status 1460 vc4_hdmi_encoder_clock_valid(const struct vc4_hdmi *vc4_hdmi, 1461 unsigned long long clock) 1462 { 1463 const struct drm_connector *connector = &vc4_hdmi->connector; 1464 const struct drm_display_info *info = &connector->display_info; 1465 1466 if (clock > vc4_hdmi->variant->max_pixel_clock) 1467 return MODE_CLOCK_HIGH; 1468 1469 if (vc4_hdmi->disable_4kp60 && clock > HDMI_14_MAX_TMDS_CLK) 1470 return MODE_CLOCK_HIGH; 1471 1472 if (info->max_tmds_clock && clock > (info->max_tmds_clock * 1000)) 1473 return MODE_CLOCK_HIGH; 1474 1475 return MODE_OK; 1476 } 1477 1478 static unsigned long long 1479 vc4_hdmi_encoder_compute_mode_clock(const struct drm_display_mode *mode, 1480 unsigned int bpc, 1481 enum vc4_hdmi_output_format fmt) 1482 { 1483 unsigned long long clock = mode->clock * 1000; 1484 1485 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 1486 clock = clock * 2; 1487 1488 if (fmt == VC4_HDMI_OUTPUT_YUV422) 1489 bpc = 8; 1490 1491 clock = clock * bpc; 1492 do_div(clock, 8); 1493 1494 return clock; 1495 } 1496 1497 static int 1498 vc4_hdmi_encoder_compute_clock(const struct vc4_hdmi *vc4_hdmi, 1499 struct vc4_hdmi_connector_state *vc4_state, 1500 const struct drm_display_mode *mode, 1501 unsigned int bpc, unsigned int fmt) 1502 { 1503 unsigned long long clock; 1504 1505 clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc, fmt); 1506 if (vc4_hdmi_encoder_clock_valid(vc4_hdmi, clock) != MODE_OK) 1507 return -EINVAL; 1508 1509 vc4_state->tmds_char_rate = clock; 1510 1511 return 0; 1512 } 1513 1514 static int 1515 vc4_hdmi_encoder_compute_format(const struct vc4_hdmi *vc4_hdmi, 1516 struct vc4_hdmi_connector_state *vc4_state, 1517 const struct drm_display_mode *mode, 1518 unsigned int bpc) 1519 { 1520 struct drm_device *dev = vc4_hdmi->connector.dev; 1521 const struct drm_connector *connector = &vc4_hdmi->connector; 1522 const struct drm_display_info *info = &connector->display_info; 1523 unsigned int format; 1524 1525 drm_dbg(dev, "Trying with an RGB output\n"); 1526 1527 format = VC4_HDMI_OUTPUT_RGB; 1528 if (vc4_hdmi_sink_supports_format_bpc(vc4_hdmi, info, mode, format, bpc)) { 1529 int ret; 1530 1531 ret = vc4_hdmi_encoder_compute_clock(vc4_hdmi, vc4_state, 1532 mode, bpc, format); 1533 if (!ret) { 1534 vc4_state->output_format = format; 1535 return 0; 1536 } 1537 } 1538 1539 drm_dbg(dev, "Failed, Trying with an YUV422 output\n"); 1540 1541 format = VC4_HDMI_OUTPUT_YUV422; 1542 if (vc4_hdmi_sink_supports_format_bpc(vc4_hdmi, info, mode, format, bpc)) { 1543 int ret; 1544 1545 ret = vc4_hdmi_encoder_compute_clock(vc4_hdmi, vc4_state, 1546 mode, bpc, format); 1547 if (!ret) { 1548 vc4_state->output_format = format; 1549 return 0; 1550 } 1551 } 1552 1553 drm_dbg(dev, "Failed. No Format Supported for that bpc count.\n"); 1554 1555 return -EINVAL; 1556 } 1557 1558 static int 1559 vc4_hdmi_encoder_compute_config(const struct vc4_hdmi *vc4_hdmi, 1560 struct vc4_hdmi_connector_state *vc4_state, 1561 const struct drm_display_mode *mode) 1562 { 1563 struct drm_device *dev = vc4_hdmi->connector.dev; 1564 struct drm_connector_state *conn_state = &vc4_state->base; 1565 unsigned int max_bpc = clamp_t(unsigned int, conn_state->max_bpc, 8, 12); 1566 unsigned int bpc; 1567 int ret; 1568 1569 for (bpc = max_bpc; bpc >= 8; bpc -= 2) { 1570 drm_dbg(dev, "Trying with a %d bpc output\n", bpc); 1571 1572 ret = vc4_hdmi_encoder_compute_format(vc4_hdmi, vc4_state, 1573 mode, bpc); 1574 if (ret) 1575 continue; 1576 1577 vc4_state->output_bpc = bpc; 1578 1579 drm_dbg(dev, 1580 "Mode %ux%u @ %uHz: Found configuration: bpc: %u, fmt: %s, clock: %llu\n", 1581 mode->hdisplay, mode->vdisplay, drm_mode_vrefresh(mode), 1582 vc4_state->output_bpc, 1583 vc4_hdmi_output_fmt_str(vc4_state->output_format), 1584 vc4_state->tmds_char_rate); 1585 1586 break; 1587 } 1588 1589 return ret; 1590 } 1591 1592 #define WIFI_2_4GHz_CH1_MIN_FREQ 2400000000ULL 1593 #define WIFI_2_4GHz_CH1_MAX_FREQ 2422000000ULL 1594 1595 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder, 1596 struct drm_crtc_state *crtc_state, 1597 struct drm_connector_state *conn_state) 1598 { 1599 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state); 1600 struct drm_display_mode *mode = &crtc_state->adjusted_mode; 1601 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1602 unsigned long long tmds_char_rate = mode->clock * 1000; 1603 unsigned long long tmds_bit_rate; 1604 int ret; 1605 1606 if (vc4_hdmi->variant->unsupported_odd_h_timings && 1607 !(mode->flags & DRM_MODE_FLAG_DBLCLK) && 1608 ((mode->hdisplay % 2) || (mode->hsync_start % 2) || 1609 (mode->hsync_end % 2) || (mode->htotal % 2))) 1610 return -EINVAL; 1611 1612 /* 1613 * The 1440p@60 pixel rate is in the same range than the first 1614 * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz 1615 * bandwidth). Slightly lower the frequency to bring it out of 1616 * the WiFi range. 1617 */ 1618 tmds_bit_rate = tmds_char_rate * 10; 1619 if (vc4_hdmi->disable_wifi_frequencies && 1620 (tmds_bit_rate >= WIFI_2_4GHz_CH1_MIN_FREQ && 1621 tmds_bit_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) { 1622 mode->clock = 238560; 1623 tmds_char_rate = mode->clock * 1000; 1624 } 1625 1626 ret = vc4_hdmi_encoder_compute_config(vc4_hdmi, vc4_state, mode); 1627 if (ret) 1628 return ret; 1629 1630 return 0; 1631 } 1632 1633 static enum drm_mode_status 1634 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder, 1635 const struct drm_display_mode *mode) 1636 { 1637 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1638 1639 if (vc4_hdmi->variant->unsupported_odd_h_timings && 1640 !(mode->flags & DRM_MODE_FLAG_DBLCLK) && 1641 ((mode->hdisplay % 2) || (mode->hsync_start % 2) || 1642 (mode->hsync_end % 2) || (mode->htotal % 2))) 1643 return MODE_H_ILLEGAL; 1644 1645 return vc4_hdmi_encoder_clock_valid(vc4_hdmi, mode->clock * 1000); 1646 } 1647 1648 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = { 1649 .atomic_check = vc4_hdmi_encoder_atomic_check, 1650 .atomic_mode_set = vc4_hdmi_encoder_atomic_mode_set, 1651 .mode_valid = vc4_hdmi_encoder_mode_valid, 1652 .disable = vc4_hdmi_encoder_disable, 1653 .enable = vc4_hdmi_encoder_enable, 1654 }; 1655 1656 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask) 1657 { 1658 int i; 1659 u32 channel_map = 0; 1660 1661 for (i = 0; i < 8; i++) { 1662 if (channel_mask & BIT(i)) 1663 channel_map |= i << (3 * i); 1664 } 1665 return channel_map; 1666 } 1667 1668 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask) 1669 { 1670 int i; 1671 u32 channel_map = 0; 1672 1673 for (i = 0; i < 8; i++) { 1674 if (channel_mask & BIT(i)) 1675 channel_map |= i << (4 * i); 1676 } 1677 return channel_map; 1678 } 1679 1680 static bool vc5_hdmi_hp_detect(struct vc4_hdmi *vc4_hdmi) 1681 { 1682 unsigned long flags; 1683 u32 hotplug; 1684 1685 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1686 hotplug = HDMI_READ(HDMI_HOTPLUG); 1687 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1688 1689 return !!(hotplug & VC4_HDMI_HOTPLUG_CONNECTED); 1690 } 1691 1692 /* HDMI audio codec callbacks */ 1693 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi, 1694 unsigned int samplerate) 1695 { 1696 u32 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock); 1697 unsigned long flags; 1698 unsigned long n, m; 1699 1700 rational_best_approximation(hsm_clock, samplerate, 1701 VC4_HD_MAI_SMP_N_MASK >> 1702 VC4_HD_MAI_SMP_N_SHIFT, 1703 (VC4_HD_MAI_SMP_M_MASK >> 1704 VC4_HD_MAI_SMP_M_SHIFT) + 1, 1705 &n, &m); 1706 1707 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1708 HDMI_WRITE(HDMI_MAI_SMP, 1709 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) | 1710 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M)); 1711 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1712 } 1713 1714 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi, unsigned int samplerate) 1715 { 1716 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1717 u32 n, cts; 1718 u64 tmp; 1719 1720 lockdep_assert_held(&vc4_hdmi->mutex); 1721 lockdep_assert_held(&vc4_hdmi->hw_lock); 1722 1723 n = 128 * samplerate / 1000; 1724 tmp = (u64)(mode->clock * 1000) * n; 1725 do_div(tmp, 128 * samplerate); 1726 cts = tmp; 1727 1728 HDMI_WRITE(HDMI_CRP_CFG, 1729 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN | 1730 VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N)); 1731 1732 /* 1733 * We could get slightly more accurate clocks in some cases by 1734 * providing a CTS_1 value. The two CTS values are alternated 1735 * between based on the period fields 1736 */ 1737 HDMI_WRITE(HDMI_CTS_0, cts); 1738 HDMI_WRITE(HDMI_CTS_1, cts); 1739 } 1740 1741 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai) 1742 { 1743 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai); 1744 1745 return snd_soc_card_get_drvdata(card); 1746 } 1747 1748 static bool vc4_hdmi_audio_can_stream(struct vc4_hdmi *vc4_hdmi) 1749 { 1750 lockdep_assert_held(&vc4_hdmi->mutex); 1751 1752 /* 1753 * If the controller is disabled, prevent any ALSA output. 1754 */ 1755 if (!vc4_hdmi->output_enabled) 1756 return false; 1757 1758 /* 1759 * If the encoder is currently in DVI mode, treat the codec DAI 1760 * as missing. 1761 */ 1762 if (!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) & VC4_HDMI_RAM_PACKET_ENABLE)) 1763 return false; 1764 1765 return true; 1766 } 1767 1768 static int vc4_hdmi_audio_startup(struct device *dev, void *data) 1769 { 1770 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 1771 unsigned long flags; 1772 1773 mutex_lock(&vc4_hdmi->mutex); 1774 1775 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) { 1776 mutex_unlock(&vc4_hdmi->mutex); 1777 return -ENODEV; 1778 } 1779 1780 vc4_hdmi->audio.streaming = true; 1781 1782 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1783 HDMI_WRITE(HDMI_MAI_CTL, 1784 VC4_HD_MAI_CTL_RESET | 1785 VC4_HD_MAI_CTL_FLUSH | 1786 VC4_HD_MAI_CTL_DLATE | 1787 VC4_HD_MAI_CTL_ERRORE | 1788 VC4_HD_MAI_CTL_ERRORF); 1789 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1790 1791 if (vc4_hdmi->variant->phy_rng_enable) 1792 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi); 1793 1794 mutex_unlock(&vc4_hdmi->mutex); 1795 1796 return 0; 1797 } 1798 1799 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi) 1800 { 1801 struct drm_encoder *encoder = &vc4_hdmi->encoder.base; 1802 struct device *dev = &vc4_hdmi->pdev->dev; 1803 unsigned long flags; 1804 int ret; 1805 1806 lockdep_assert_held(&vc4_hdmi->mutex); 1807 1808 vc4_hdmi->audio.streaming = false; 1809 ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO, false); 1810 if (ret) 1811 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret); 1812 1813 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1814 1815 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET); 1816 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF); 1817 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH); 1818 1819 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1820 } 1821 1822 static void vc4_hdmi_audio_shutdown(struct device *dev, void *data) 1823 { 1824 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 1825 unsigned long flags; 1826 1827 mutex_lock(&vc4_hdmi->mutex); 1828 1829 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1830 1831 HDMI_WRITE(HDMI_MAI_CTL, 1832 VC4_HD_MAI_CTL_DLATE | 1833 VC4_HD_MAI_CTL_ERRORE | 1834 VC4_HD_MAI_CTL_ERRORF); 1835 1836 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1837 1838 if (vc4_hdmi->variant->phy_rng_disable) 1839 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi); 1840 1841 vc4_hdmi->audio.streaming = false; 1842 vc4_hdmi_audio_reset(vc4_hdmi); 1843 1844 mutex_unlock(&vc4_hdmi->mutex); 1845 } 1846 1847 static int sample_rate_to_mai_fmt(int samplerate) 1848 { 1849 switch (samplerate) { 1850 case 8000: 1851 return VC4_HDMI_MAI_SAMPLE_RATE_8000; 1852 case 11025: 1853 return VC4_HDMI_MAI_SAMPLE_RATE_11025; 1854 case 12000: 1855 return VC4_HDMI_MAI_SAMPLE_RATE_12000; 1856 case 16000: 1857 return VC4_HDMI_MAI_SAMPLE_RATE_16000; 1858 case 22050: 1859 return VC4_HDMI_MAI_SAMPLE_RATE_22050; 1860 case 24000: 1861 return VC4_HDMI_MAI_SAMPLE_RATE_24000; 1862 case 32000: 1863 return VC4_HDMI_MAI_SAMPLE_RATE_32000; 1864 case 44100: 1865 return VC4_HDMI_MAI_SAMPLE_RATE_44100; 1866 case 48000: 1867 return VC4_HDMI_MAI_SAMPLE_RATE_48000; 1868 case 64000: 1869 return VC4_HDMI_MAI_SAMPLE_RATE_64000; 1870 case 88200: 1871 return VC4_HDMI_MAI_SAMPLE_RATE_88200; 1872 case 96000: 1873 return VC4_HDMI_MAI_SAMPLE_RATE_96000; 1874 case 128000: 1875 return VC4_HDMI_MAI_SAMPLE_RATE_128000; 1876 case 176400: 1877 return VC4_HDMI_MAI_SAMPLE_RATE_176400; 1878 case 192000: 1879 return VC4_HDMI_MAI_SAMPLE_RATE_192000; 1880 default: 1881 return VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED; 1882 } 1883 } 1884 1885 /* HDMI audio codec callbacks */ 1886 static int vc4_hdmi_audio_prepare(struct device *dev, void *data, 1887 struct hdmi_codec_daifmt *daifmt, 1888 struct hdmi_codec_params *params) 1889 { 1890 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 1891 struct drm_encoder *encoder = &vc4_hdmi->encoder.base; 1892 unsigned int sample_rate = params->sample_rate; 1893 unsigned int channels = params->channels; 1894 unsigned long flags; 1895 u32 audio_packet_config, channel_mask; 1896 u32 channel_map; 1897 u32 mai_audio_format; 1898 u32 mai_sample_rate; 1899 1900 dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__, 1901 sample_rate, params->sample_width, channels); 1902 1903 mutex_lock(&vc4_hdmi->mutex); 1904 1905 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) { 1906 mutex_unlock(&vc4_hdmi->mutex); 1907 return -EINVAL; 1908 } 1909 1910 vc4_hdmi_audio_set_mai_clock(vc4_hdmi, sample_rate); 1911 1912 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1913 HDMI_WRITE(HDMI_MAI_CTL, 1914 VC4_SET_FIELD(channels, VC4_HD_MAI_CTL_CHNUM) | 1915 VC4_HD_MAI_CTL_WHOLSMP | 1916 VC4_HD_MAI_CTL_CHALIGN | 1917 VC4_HD_MAI_CTL_ENABLE); 1918 1919 mai_sample_rate = sample_rate_to_mai_fmt(sample_rate); 1920 if (params->iec.status[0] & IEC958_AES0_NONAUDIO && 1921 params->channels == 8) 1922 mai_audio_format = VC4_HDMI_MAI_FORMAT_HBR; 1923 else 1924 mai_audio_format = VC4_HDMI_MAI_FORMAT_PCM; 1925 HDMI_WRITE(HDMI_MAI_FMT, 1926 VC4_SET_FIELD(mai_sample_rate, 1927 VC4_HDMI_MAI_FORMAT_SAMPLE_RATE) | 1928 VC4_SET_FIELD(mai_audio_format, 1929 VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT)); 1930 1931 /* The B frame identifier should match the value used by alsa-lib (8) */ 1932 audio_packet_config = 1933 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT | 1934 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS | 1935 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER); 1936 1937 channel_mask = GENMASK(channels - 1, 0); 1938 audio_packet_config |= VC4_SET_FIELD(channel_mask, 1939 VC4_HDMI_AUDIO_PACKET_CEA_MASK); 1940 1941 /* Set the MAI threshold */ 1942 HDMI_WRITE(HDMI_MAI_THR, 1943 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) | 1944 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) | 1945 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQHIGH) | 1946 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQLOW)); 1947 1948 HDMI_WRITE(HDMI_MAI_CONFIG, 1949 VC4_HDMI_MAI_CONFIG_BIT_REVERSE | 1950 VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE | 1951 VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK)); 1952 1953 channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask); 1954 HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map); 1955 HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config); 1956 1957 vc4_hdmi_set_n_cts(vc4_hdmi, sample_rate); 1958 1959 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1960 1961 memcpy(&vc4_hdmi->audio.infoframe, ¶ms->cea, sizeof(params->cea)); 1962 vc4_hdmi_set_audio_infoframe(encoder); 1963 1964 mutex_unlock(&vc4_hdmi->mutex); 1965 1966 return 0; 1967 } 1968 1969 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = { 1970 .name = "vc4-hdmi-cpu-dai-component", 1971 }; 1972 1973 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai) 1974 { 1975 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai); 1976 1977 snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL); 1978 1979 return 0; 1980 } 1981 1982 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = { 1983 .name = "vc4-hdmi-cpu-dai", 1984 .probe = vc4_hdmi_audio_cpu_dai_probe, 1985 .playback = { 1986 .stream_name = "Playback", 1987 .channels_min = 1, 1988 .channels_max = 8, 1989 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 1990 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 1991 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 1992 SNDRV_PCM_RATE_192000, 1993 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 1994 }, 1995 }; 1996 1997 static const struct snd_dmaengine_pcm_config pcm_conf = { 1998 .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx", 1999 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 2000 }; 2001 2002 static int vc4_hdmi_audio_get_eld(struct device *dev, void *data, 2003 uint8_t *buf, size_t len) 2004 { 2005 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 2006 struct drm_connector *connector = &vc4_hdmi->connector; 2007 2008 mutex_lock(&vc4_hdmi->mutex); 2009 memcpy(buf, connector->eld, min(sizeof(connector->eld), len)); 2010 mutex_unlock(&vc4_hdmi->mutex); 2011 2012 return 0; 2013 } 2014 2015 static const struct hdmi_codec_ops vc4_hdmi_codec_ops = { 2016 .get_eld = vc4_hdmi_audio_get_eld, 2017 .prepare = vc4_hdmi_audio_prepare, 2018 .audio_shutdown = vc4_hdmi_audio_shutdown, 2019 .audio_startup = vc4_hdmi_audio_startup, 2020 }; 2021 2022 static struct hdmi_codec_pdata vc4_hdmi_codec_pdata = { 2023 .ops = &vc4_hdmi_codec_ops, 2024 .max_i2s_channels = 8, 2025 .i2s = 1, 2026 }; 2027 2028 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi) 2029 { 2030 const struct vc4_hdmi_register *mai_data = 2031 &vc4_hdmi->variant->registers[HDMI_MAI_DATA]; 2032 struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link; 2033 struct snd_soc_card *card = &vc4_hdmi->audio.card; 2034 struct device *dev = &vc4_hdmi->pdev->dev; 2035 struct platform_device *codec_pdev; 2036 const __be32 *addr; 2037 int index; 2038 int ret; 2039 2040 if (!of_find_property(dev->of_node, "dmas", NULL)) { 2041 dev_warn(dev, 2042 "'dmas' DT property is missing, no HDMI audio\n"); 2043 return 0; 2044 } 2045 2046 if (mai_data->reg != VC4_HD) { 2047 WARN_ONCE(true, "MAI isn't in the HD block\n"); 2048 return -EINVAL; 2049 } 2050 2051 /* 2052 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve 2053 * the bus address specified in the DT, because the physical address 2054 * (the one returned by platform_get_resource()) is not appropriate 2055 * for DMA transfers. 2056 * This VC/MMU should probably be exposed to avoid this kind of hacks. 2057 */ 2058 index = of_property_match_string(dev->of_node, "reg-names", "hd"); 2059 /* Before BCM2711, we don't have a named register range */ 2060 if (index < 0) 2061 index = 1; 2062 2063 addr = of_get_address(dev->of_node, index, NULL, NULL); 2064 2065 vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset; 2066 vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 2067 vc4_hdmi->audio.dma_data.maxburst = 2; 2068 2069 ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0); 2070 if (ret) { 2071 dev_err(dev, "Could not register PCM component: %d\n", ret); 2072 return ret; 2073 } 2074 2075 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp, 2076 &vc4_hdmi_audio_cpu_dai_drv, 1); 2077 if (ret) { 2078 dev_err(dev, "Could not register CPU DAI: %d\n", ret); 2079 return ret; 2080 } 2081 2082 codec_pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME, 2083 PLATFORM_DEVID_AUTO, 2084 &vc4_hdmi_codec_pdata, 2085 sizeof(vc4_hdmi_codec_pdata)); 2086 if (IS_ERR(codec_pdev)) { 2087 dev_err(dev, "Couldn't register the HDMI codec: %ld\n", PTR_ERR(codec_pdev)); 2088 return PTR_ERR(codec_pdev); 2089 } 2090 vc4_hdmi->audio.codec_pdev = codec_pdev; 2091 2092 dai_link->cpus = &vc4_hdmi->audio.cpu; 2093 dai_link->codecs = &vc4_hdmi->audio.codec; 2094 dai_link->platforms = &vc4_hdmi->audio.platform; 2095 2096 dai_link->num_cpus = 1; 2097 dai_link->num_codecs = 1; 2098 dai_link->num_platforms = 1; 2099 2100 dai_link->name = "MAI"; 2101 dai_link->stream_name = "MAI PCM"; 2102 dai_link->codecs->dai_name = "i2s-hifi"; 2103 dai_link->cpus->dai_name = dev_name(dev); 2104 dai_link->codecs->name = dev_name(&codec_pdev->dev); 2105 dai_link->platforms->name = dev_name(dev); 2106 2107 card->dai_link = dai_link; 2108 card->num_links = 1; 2109 card->name = vc4_hdmi->variant->card_name; 2110 card->driver_name = "vc4-hdmi"; 2111 card->dev = dev; 2112 card->owner = THIS_MODULE; 2113 2114 /* 2115 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and 2116 * stores a pointer to the snd card object in dev->driver_data. This 2117 * means we cannot use it for something else. The hdmi back-pointer is 2118 * now stored in card->drvdata and should be retrieved with 2119 * snd_soc_card_get_drvdata() if needed. 2120 */ 2121 snd_soc_card_set_drvdata(card, vc4_hdmi); 2122 ret = devm_snd_soc_register_card(dev, card); 2123 if (ret) 2124 dev_err_probe(dev, ret, "Could not register sound card\n"); 2125 2126 return ret; 2127 2128 } 2129 2130 static void vc4_hdmi_audio_exit(struct vc4_hdmi *vc4_hdmi) 2131 { 2132 platform_device_unregister(vc4_hdmi->audio.codec_pdev); 2133 vc4_hdmi->audio.codec_pdev = NULL; 2134 } 2135 2136 static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv) 2137 { 2138 struct vc4_hdmi *vc4_hdmi = priv; 2139 struct drm_connector *connector = &vc4_hdmi->connector; 2140 struct drm_device *dev = connector->dev; 2141 2142 if (dev && dev->registered) 2143 drm_connector_helper_hpd_irq_event(connector); 2144 2145 return IRQ_HANDLED; 2146 } 2147 2148 static int vc4_hdmi_hotplug_init(struct vc4_hdmi *vc4_hdmi) 2149 { 2150 struct drm_connector *connector = &vc4_hdmi->connector; 2151 struct platform_device *pdev = vc4_hdmi->pdev; 2152 int ret; 2153 2154 if (vc4_hdmi->variant->external_irq_controller) { 2155 unsigned int hpd_con = platform_get_irq_byname(pdev, "hpd-connected"); 2156 unsigned int hpd_rm = platform_get_irq_byname(pdev, "hpd-removed"); 2157 2158 ret = request_threaded_irq(hpd_con, 2159 NULL, 2160 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT, 2161 "vc4 hdmi hpd connected", vc4_hdmi); 2162 if (ret) 2163 return ret; 2164 2165 ret = request_threaded_irq(hpd_rm, 2166 NULL, 2167 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT, 2168 "vc4 hdmi hpd disconnected", vc4_hdmi); 2169 if (ret) { 2170 free_irq(hpd_con, vc4_hdmi); 2171 return ret; 2172 } 2173 2174 connector->polled = DRM_CONNECTOR_POLL_HPD; 2175 } 2176 2177 return 0; 2178 } 2179 2180 static void vc4_hdmi_hotplug_exit(struct vc4_hdmi *vc4_hdmi) 2181 { 2182 struct platform_device *pdev = vc4_hdmi->pdev; 2183 2184 if (vc4_hdmi->variant->external_irq_controller) { 2185 free_irq(platform_get_irq_byname(pdev, "hpd-connected"), vc4_hdmi); 2186 free_irq(platform_get_irq_byname(pdev, "hpd-removed"), vc4_hdmi); 2187 } 2188 } 2189 2190 #ifdef CONFIG_DRM_VC4_HDMI_CEC 2191 static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv) 2192 { 2193 struct vc4_hdmi *vc4_hdmi = priv; 2194 2195 if (vc4_hdmi->cec_rx_msg.len) 2196 cec_received_msg(vc4_hdmi->cec_adap, 2197 &vc4_hdmi->cec_rx_msg); 2198 2199 return IRQ_HANDLED; 2200 } 2201 2202 static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv) 2203 { 2204 struct vc4_hdmi *vc4_hdmi = priv; 2205 2206 if (vc4_hdmi->cec_tx_ok) { 2207 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK, 2208 0, 0, 0, 0); 2209 } else { 2210 /* 2211 * This CEC implementation makes 1 retry, so if we 2212 * get a NACK, then that means it made 2 attempts. 2213 */ 2214 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK, 2215 0, 2, 0, 0); 2216 } 2217 return IRQ_HANDLED; 2218 } 2219 2220 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv) 2221 { 2222 struct vc4_hdmi *vc4_hdmi = priv; 2223 irqreturn_t ret; 2224 2225 if (vc4_hdmi->cec_irq_was_rx) 2226 ret = vc4_cec_irq_handler_rx_thread(irq, priv); 2227 else 2228 ret = vc4_cec_irq_handler_tx_thread(irq, priv); 2229 2230 return ret; 2231 } 2232 2233 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1) 2234 { 2235 struct drm_device *dev = vc4_hdmi->connector.dev; 2236 struct cec_msg *msg = &vc4_hdmi->cec_rx_msg; 2237 unsigned int i; 2238 2239 lockdep_assert_held(&vc4_hdmi->hw_lock); 2240 2241 msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >> 2242 VC4_HDMI_CEC_REC_WRD_CNT_SHIFT); 2243 2244 if (msg->len > 16) { 2245 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len); 2246 return; 2247 } 2248 2249 for (i = 0; i < msg->len; i += 4) { 2250 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2)); 2251 2252 msg->msg[i] = val & 0xff; 2253 msg->msg[i + 1] = (val >> 8) & 0xff; 2254 msg->msg[i + 2] = (val >> 16) & 0xff; 2255 msg->msg[i + 3] = (val >> 24) & 0xff; 2256 } 2257 } 2258 2259 static irqreturn_t vc4_cec_irq_handler_tx_bare_locked(struct vc4_hdmi *vc4_hdmi) 2260 { 2261 u32 cntrl1; 2262 2263 lockdep_assert_held(&vc4_hdmi->hw_lock); 2264 2265 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1); 2266 vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD; 2267 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 2268 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 2269 2270 return IRQ_WAKE_THREAD; 2271 } 2272 2273 static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv) 2274 { 2275 struct vc4_hdmi *vc4_hdmi = priv; 2276 irqreturn_t ret; 2277 2278 spin_lock(&vc4_hdmi->hw_lock); 2279 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi); 2280 spin_unlock(&vc4_hdmi->hw_lock); 2281 2282 return ret; 2283 } 2284 2285 static irqreturn_t vc4_cec_irq_handler_rx_bare_locked(struct vc4_hdmi *vc4_hdmi) 2286 { 2287 u32 cntrl1; 2288 2289 lockdep_assert_held(&vc4_hdmi->hw_lock); 2290 2291 vc4_hdmi->cec_rx_msg.len = 0; 2292 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1); 2293 vc4_cec_read_msg(vc4_hdmi, cntrl1); 2294 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 2295 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 2296 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 2297 2298 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 2299 2300 return IRQ_WAKE_THREAD; 2301 } 2302 2303 static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv) 2304 { 2305 struct vc4_hdmi *vc4_hdmi = priv; 2306 irqreturn_t ret; 2307 2308 spin_lock(&vc4_hdmi->hw_lock); 2309 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi); 2310 spin_unlock(&vc4_hdmi->hw_lock); 2311 2312 return ret; 2313 } 2314 2315 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv) 2316 { 2317 struct vc4_hdmi *vc4_hdmi = priv; 2318 u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS); 2319 irqreturn_t ret; 2320 u32 cntrl5; 2321 2322 if (!(stat & VC4_HDMI_CPU_CEC)) 2323 return IRQ_NONE; 2324 2325 spin_lock(&vc4_hdmi->hw_lock); 2326 cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5); 2327 vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT; 2328 if (vc4_hdmi->cec_irq_was_rx) 2329 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi); 2330 else 2331 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi); 2332 2333 HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC); 2334 spin_unlock(&vc4_hdmi->hw_lock); 2335 2336 return ret; 2337 } 2338 2339 static int vc4_hdmi_cec_enable(struct cec_adapter *adap) 2340 { 2341 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 2342 /* clock period in microseconds */ 2343 const u32 usecs = 1000000 / CEC_CLOCK_FREQ; 2344 unsigned long flags; 2345 u32 val; 2346 int ret; 2347 2348 /* 2349 * NOTE: This function should really take vc4_hdmi->mutex, but doing so 2350 * results in a reentrancy since cec_s_phys_addr_from_edid() called in 2351 * .detect or .get_modes might call .adap_enable, which leads to this 2352 * function being called with that mutex held. 2353 * 2354 * Concurrency is not an issue for the moment since we don't share any 2355 * state with KMS, so we can ignore the lock for now, but we need to 2356 * keep it in mind if we were to change that assumption. 2357 */ 2358 2359 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev); 2360 if (ret) 2361 return ret; 2362 2363 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2364 2365 val = HDMI_READ(HDMI_CEC_CNTRL_5); 2366 val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET | 2367 VC4_HDMI_CEC_CNT_TO_4700_US_MASK | 2368 VC4_HDMI_CEC_CNT_TO_4500_US_MASK); 2369 val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) | 2370 ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT); 2371 2372 HDMI_WRITE(HDMI_CEC_CNTRL_5, val | 2373 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 2374 HDMI_WRITE(HDMI_CEC_CNTRL_5, val); 2375 HDMI_WRITE(HDMI_CEC_CNTRL_2, 2376 ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) | 2377 ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) | 2378 ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) | 2379 ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) | 2380 ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT)); 2381 HDMI_WRITE(HDMI_CEC_CNTRL_3, 2382 ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) | 2383 ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) | 2384 ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) | 2385 ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT)); 2386 HDMI_WRITE(HDMI_CEC_CNTRL_4, 2387 ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) | 2388 ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) | 2389 ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) | 2390 ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT)); 2391 2392 if (!vc4_hdmi->variant->external_irq_controller) 2393 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC); 2394 2395 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2396 2397 return 0; 2398 } 2399 2400 static int vc4_hdmi_cec_disable(struct cec_adapter *adap) 2401 { 2402 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 2403 unsigned long flags; 2404 2405 /* 2406 * NOTE: This function should really take vc4_hdmi->mutex, but doing so 2407 * results in a reentrancy since cec_s_phys_addr_from_edid() called in 2408 * .detect or .get_modes might call .adap_enable, which leads to this 2409 * function being called with that mutex held. 2410 * 2411 * Concurrency is not an issue for the moment since we don't share any 2412 * state with KMS, so we can ignore the lock for now, but we need to 2413 * keep it in mind if we were to change that assumption. 2414 */ 2415 2416 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2417 2418 if (!vc4_hdmi->variant->external_irq_controller) 2419 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC); 2420 2421 HDMI_WRITE(HDMI_CEC_CNTRL_5, HDMI_READ(HDMI_CEC_CNTRL_5) | 2422 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 2423 2424 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2425 2426 pm_runtime_put(&vc4_hdmi->pdev->dev); 2427 2428 return 0; 2429 } 2430 2431 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable) 2432 { 2433 if (enable) 2434 return vc4_hdmi_cec_enable(adap); 2435 else 2436 return vc4_hdmi_cec_disable(adap); 2437 } 2438 2439 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr) 2440 { 2441 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 2442 unsigned long flags; 2443 2444 /* 2445 * NOTE: This function should really take vc4_hdmi->mutex, but doing so 2446 * results in a reentrancy since cec_s_phys_addr_from_edid() called in 2447 * .detect or .get_modes might call .adap_enable, which leads to this 2448 * function being called with that mutex held. 2449 * 2450 * Concurrency is not an issue for the moment since we don't share any 2451 * state with KMS, so we can ignore the lock for now, but we need to 2452 * keep it in mind if we were to change that assumption. 2453 */ 2454 2455 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2456 HDMI_WRITE(HDMI_CEC_CNTRL_1, 2457 (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) | 2458 (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT); 2459 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2460 2461 return 0; 2462 } 2463 2464 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts, 2465 u32 signal_free_time, struct cec_msg *msg) 2466 { 2467 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 2468 struct drm_device *dev = vc4_hdmi->connector.dev; 2469 unsigned long flags; 2470 u32 val; 2471 unsigned int i; 2472 2473 /* 2474 * NOTE: This function should really take vc4_hdmi->mutex, but doing so 2475 * results in a reentrancy since cec_s_phys_addr_from_edid() called in 2476 * .detect or .get_modes might call .adap_enable, which leads to this 2477 * function being called with that mutex held. 2478 * 2479 * Concurrency is not an issue for the moment since we don't share any 2480 * state with KMS, so we can ignore the lock for now, but we need to 2481 * keep it in mind if we were to change that assumption. 2482 */ 2483 2484 if (msg->len > 16) { 2485 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len); 2486 return -ENOMEM; 2487 } 2488 2489 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2490 2491 for (i = 0; i < msg->len; i += 4) 2492 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2), 2493 (msg->msg[i]) | 2494 (msg->msg[i + 1] << 8) | 2495 (msg->msg[i + 2] << 16) | 2496 (msg->msg[i + 3] << 24)); 2497 2498 val = HDMI_READ(HDMI_CEC_CNTRL_1); 2499 val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 2500 HDMI_WRITE(HDMI_CEC_CNTRL_1, val); 2501 val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK; 2502 val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT; 2503 val |= VC4_HDMI_CEC_START_XMIT_BEGIN; 2504 2505 HDMI_WRITE(HDMI_CEC_CNTRL_1, val); 2506 2507 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2508 2509 return 0; 2510 } 2511 2512 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = { 2513 .adap_enable = vc4_hdmi_cec_adap_enable, 2514 .adap_log_addr = vc4_hdmi_cec_adap_log_addr, 2515 .adap_transmit = vc4_hdmi_cec_adap_transmit, 2516 }; 2517 2518 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi) 2519 { 2520 struct cec_connector_info conn_info; 2521 struct platform_device *pdev = vc4_hdmi->pdev; 2522 struct device *dev = &pdev->dev; 2523 unsigned long flags; 2524 u32 value; 2525 int ret; 2526 2527 if (!of_find_property(dev->of_node, "interrupts", NULL)) { 2528 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n"); 2529 return 0; 2530 } 2531 2532 vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops, 2533 vc4_hdmi, "vc4", 2534 CEC_CAP_DEFAULTS | 2535 CEC_CAP_CONNECTOR_INFO, 1); 2536 ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap); 2537 if (ret < 0) 2538 return ret; 2539 2540 cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector); 2541 cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info); 2542 2543 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2544 value = HDMI_READ(HDMI_CEC_CNTRL_1); 2545 /* Set the logical address to Unregistered */ 2546 value |= VC4_HDMI_CEC_ADDR_MASK; 2547 HDMI_WRITE(HDMI_CEC_CNTRL_1, value); 2548 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2549 2550 vc4_hdmi_cec_update_clk_div(vc4_hdmi); 2551 2552 if (vc4_hdmi->variant->external_irq_controller) { 2553 ret = request_threaded_irq(platform_get_irq_byname(pdev, "cec-rx"), 2554 vc4_cec_irq_handler_rx_bare, 2555 vc4_cec_irq_handler_rx_thread, 0, 2556 "vc4 hdmi cec rx", vc4_hdmi); 2557 if (ret) 2558 goto err_delete_cec_adap; 2559 2560 ret = request_threaded_irq(platform_get_irq_byname(pdev, "cec-tx"), 2561 vc4_cec_irq_handler_tx_bare, 2562 vc4_cec_irq_handler_tx_thread, 0, 2563 "vc4 hdmi cec tx", vc4_hdmi); 2564 if (ret) 2565 goto err_remove_cec_rx_handler; 2566 } else { 2567 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2568 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff); 2569 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2570 2571 ret = request_threaded_irq(platform_get_irq(pdev, 0), 2572 vc4_cec_irq_handler, 2573 vc4_cec_irq_handler_thread, 0, 2574 "vc4 hdmi cec", vc4_hdmi); 2575 if (ret) 2576 goto err_delete_cec_adap; 2577 } 2578 2579 ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev); 2580 if (ret < 0) 2581 goto err_remove_handlers; 2582 2583 return 0; 2584 2585 err_remove_handlers: 2586 if (vc4_hdmi->variant->external_irq_controller) 2587 free_irq(platform_get_irq_byname(pdev, "cec-tx"), vc4_hdmi); 2588 else 2589 free_irq(platform_get_irq(pdev, 0), vc4_hdmi); 2590 2591 err_remove_cec_rx_handler: 2592 if (vc4_hdmi->variant->external_irq_controller) 2593 free_irq(platform_get_irq_byname(pdev, "cec-rx"), vc4_hdmi); 2594 2595 err_delete_cec_adap: 2596 cec_delete_adapter(vc4_hdmi->cec_adap); 2597 2598 return ret; 2599 } 2600 2601 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi) 2602 { 2603 struct platform_device *pdev = vc4_hdmi->pdev; 2604 2605 if (vc4_hdmi->variant->external_irq_controller) { 2606 free_irq(platform_get_irq_byname(pdev, "cec-rx"), vc4_hdmi); 2607 free_irq(platform_get_irq_byname(pdev, "cec-tx"), vc4_hdmi); 2608 } else { 2609 free_irq(platform_get_irq(pdev, 0), vc4_hdmi); 2610 } 2611 2612 cec_unregister_adapter(vc4_hdmi->cec_adap); 2613 } 2614 #else 2615 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi) 2616 { 2617 return 0; 2618 } 2619 2620 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi) {}; 2621 2622 #endif 2623 2624 static int vc4_hdmi_build_regset(struct vc4_hdmi *vc4_hdmi, 2625 struct debugfs_regset32 *regset, 2626 enum vc4_hdmi_regs reg) 2627 { 2628 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant; 2629 struct debugfs_reg32 *regs, *new_regs; 2630 unsigned int count = 0; 2631 unsigned int i; 2632 2633 regs = kcalloc(variant->num_registers, sizeof(*regs), 2634 GFP_KERNEL); 2635 if (!regs) 2636 return -ENOMEM; 2637 2638 for (i = 0; i < variant->num_registers; i++) { 2639 const struct vc4_hdmi_register *field = &variant->registers[i]; 2640 2641 if (field->reg != reg) 2642 continue; 2643 2644 regs[count].name = field->name; 2645 regs[count].offset = field->offset; 2646 count++; 2647 } 2648 2649 new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL); 2650 if (!new_regs) 2651 return -ENOMEM; 2652 2653 regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg); 2654 regset->regs = new_regs; 2655 regset->nregs = count; 2656 2657 return 0; 2658 } 2659 2660 static int vc4_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi) 2661 { 2662 struct platform_device *pdev = vc4_hdmi->pdev; 2663 struct device *dev = &pdev->dev; 2664 int ret; 2665 2666 vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0); 2667 if (IS_ERR(vc4_hdmi->hdmicore_regs)) 2668 return PTR_ERR(vc4_hdmi->hdmicore_regs); 2669 2670 vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1); 2671 if (IS_ERR(vc4_hdmi->hd_regs)) 2672 return PTR_ERR(vc4_hdmi->hd_regs); 2673 2674 ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD); 2675 if (ret) 2676 return ret; 2677 2678 ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI); 2679 if (ret) 2680 return ret; 2681 2682 vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel"); 2683 if (IS_ERR(vc4_hdmi->pixel_clock)) { 2684 ret = PTR_ERR(vc4_hdmi->pixel_clock); 2685 if (ret != -EPROBE_DEFER) 2686 DRM_ERROR("Failed to get pixel clock\n"); 2687 return ret; 2688 } 2689 2690 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); 2691 if (IS_ERR(vc4_hdmi->hsm_clock)) { 2692 DRM_ERROR("Failed to get HDMI state machine clock\n"); 2693 return PTR_ERR(vc4_hdmi->hsm_clock); 2694 } 2695 vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock; 2696 vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock; 2697 2698 return 0; 2699 } 2700 2701 static int vc5_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi) 2702 { 2703 struct platform_device *pdev = vc4_hdmi->pdev; 2704 struct device *dev = &pdev->dev; 2705 struct resource *res; 2706 2707 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi"); 2708 if (!res) 2709 return -ENODEV; 2710 2711 vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start, 2712 resource_size(res)); 2713 if (!vc4_hdmi->hdmicore_regs) 2714 return -ENOMEM; 2715 2716 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd"); 2717 if (!res) 2718 return -ENODEV; 2719 2720 vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res)); 2721 if (!vc4_hdmi->hd_regs) 2722 return -ENOMEM; 2723 2724 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec"); 2725 if (!res) 2726 return -ENODEV; 2727 2728 vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res)); 2729 if (!vc4_hdmi->cec_regs) 2730 return -ENOMEM; 2731 2732 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc"); 2733 if (!res) 2734 return -ENODEV; 2735 2736 vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res)); 2737 if (!vc4_hdmi->csc_regs) 2738 return -ENOMEM; 2739 2740 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp"); 2741 if (!res) 2742 return -ENODEV; 2743 2744 vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res)); 2745 if (!vc4_hdmi->dvp_regs) 2746 return -ENOMEM; 2747 2748 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy"); 2749 if (!res) 2750 return -ENODEV; 2751 2752 vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res)); 2753 if (!vc4_hdmi->phy_regs) 2754 return -ENOMEM; 2755 2756 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet"); 2757 if (!res) 2758 return -ENODEV; 2759 2760 vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res)); 2761 if (!vc4_hdmi->ram_regs) 2762 return -ENOMEM; 2763 2764 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm"); 2765 if (!res) 2766 return -ENODEV; 2767 2768 vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res)); 2769 if (!vc4_hdmi->rm_regs) 2770 return -ENOMEM; 2771 2772 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); 2773 if (IS_ERR(vc4_hdmi->hsm_clock)) { 2774 DRM_ERROR("Failed to get HDMI state machine clock\n"); 2775 return PTR_ERR(vc4_hdmi->hsm_clock); 2776 } 2777 2778 vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb"); 2779 if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) { 2780 DRM_ERROR("Failed to get pixel bvb clock\n"); 2781 return PTR_ERR(vc4_hdmi->pixel_bvb_clock); 2782 } 2783 2784 vc4_hdmi->audio_clock = devm_clk_get(dev, "audio"); 2785 if (IS_ERR(vc4_hdmi->audio_clock)) { 2786 DRM_ERROR("Failed to get audio clock\n"); 2787 return PTR_ERR(vc4_hdmi->audio_clock); 2788 } 2789 2790 vc4_hdmi->cec_clock = devm_clk_get(dev, "cec"); 2791 if (IS_ERR(vc4_hdmi->cec_clock)) { 2792 DRM_ERROR("Failed to get CEC clock\n"); 2793 return PTR_ERR(vc4_hdmi->cec_clock); 2794 } 2795 2796 vc4_hdmi->reset = devm_reset_control_get(dev, NULL); 2797 if (IS_ERR(vc4_hdmi->reset)) { 2798 DRM_ERROR("Failed to get HDMI reset line\n"); 2799 return PTR_ERR(vc4_hdmi->reset); 2800 } 2801 2802 return 0; 2803 } 2804 2805 static int __maybe_unused vc4_hdmi_runtime_suspend(struct device *dev) 2806 { 2807 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 2808 2809 clk_disable_unprepare(vc4_hdmi->hsm_clock); 2810 2811 return 0; 2812 } 2813 2814 static int vc4_hdmi_runtime_resume(struct device *dev) 2815 { 2816 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 2817 int ret; 2818 2819 ret = clk_prepare_enable(vc4_hdmi->hsm_clock); 2820 if (ret) 2821 return ret; 2822 2823 return 0; 2824 } 2825 2826 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data) 2827 { 2828 const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev); 2829 struct platform_device *pdev = to_platform_device(dev); 2830 struct drm_device *drm = dev_get_drvdata(master); 2831 struct vc4_hdmi *vc4_hdmi; 2832 struct drm_encoder *encoder; 2833 struct device_node *ddc_node; 2834 int ret; 2835 2836 vc4_hdmi = devm_kzalloc(dev, sizeof(*vc4_hdmi), GFP_KERNEL); 2837 if (!vc4_hdmi) 2838 return -ENOMEM; 2839 mutex_init(&vc4_hdmi->mutex); 2840 spin_lock_init(&vc4_hdmi->hw_lock); 2841 INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq); 2842 2843 dev_set_drvdata(dev, vc4_hdmi); 2844 encoder = &vc4_hdmi->encoder.base; 2845 vc4_hdmi->encoder.type = variant->encoder_type; 2846 vc4_hdmi->encoder.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure; 2847 vc4_hdmi->encoder.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable; 2848 vc4_hdmi->encoder.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable; 2849 vc4_hdmi->encoder.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable; 2850 vc4_hdmi->encoder.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown; 2851 vc4_hdmi->pdev = pdev; 2852 vc4_hdmi->variant = variant; 2853 2854 /* 2855 * Since we don't know the state of the controller and its 2856 * display (if any), let's assume it's always enabled. 2857 * vc4_hdmi_disable_scrambling() will thus run at boot, make 2858 * sure it's disabled, and avoid any inconsistency. 2859 */ 2860 if (variant->max_pixel_clock > HDMI_14_MAX_TMDS_CLK) 2861 vc4_hdmi->scdc_enabled = true; 2862 2863 ret = variant->init_resources(vc4_hdmi); 2864 if (ret) 2865 return ret; 2866 2867 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0); 2868 if (!ddc_node) { 2869 DRM_ERROR("Failed to find ddc node in device tree\n"); 2870 return -ENODEV; 2871 } 2872 2873 vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node); 2874 of_node_put(ddc_node); 2875 if (!vc4_hdmi->ddc) { 2876 DRM_DEBUG("Failed to get ddc i2c adapter by node\n"); 2877 return -EPROBE_DEFER; 2878 } 2879 2880 /* Only use the GPIO HPD pin if present in the DT, otherwise 2881 * we'll use the HDMI core's register. 2882 */ 2883 vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN); 2884 if (IS_ERR(vc4_hdmi->hpd_gpio)) { 2885 ret = PTR_ERR(vc4_hdmi->hpd_gpio); 2886 goto err_put_ddc; 2887 } 2888 2889 vc4_hdmi->disable_wifi_frequencies = 2890 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence"); 2891 2892 if (variant->max_pixel_clock == 600000000) { 2893 struct vc4_dev *vc4 = to_vc4_dev(drm); 2894 long max_rate = clk_round_rate(vc4->hvs->core_clk, 550000000); 2895 2896 if (max_rate < 550000000) 2897 vc4_hdmi->disable_4kp60 = true; 2898 } 2899 2900 /* 2901 * We need to have the device powered up at this point to call 2902 * our reset hook and for the CEC init. 2903 */ 2904 ret = vc4_hdmi_runtime_resume(dev); 2905 if (ret) 2906 goto err_put_ddc; 2907 2908 pm_runtime_get_noresume(dev); 2909 pm_runtime_set_active(dev); 2910 pm_runtime_enable(dev); 2911 2912 if (vc4_hdmi->variant->reset) 2913 vc4_hdmi->variant->reset(vc4_hdmi); 2914 2915 if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") || 2916 of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1")) && 2917 HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) { 2918 clk_prepare_enable(vc4_hdmi->pixel_clock); 2919 clk_prepare_enable(vc4_hdmi->hsm_clock); 2920 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock); 2921 } 2922 2923 drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS); 2924 drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs); 2925 2926 ret = vc4_hdmi_connector_init(drm, vc4_hdmi); 2927 if (ret) 2928 goto err_destroy_encoder; 2929 2930 ret = vc4_hdmi_hotplug_init(vc4_hdmi); 2931 if (ret) 2932 goto err_destroy_conn; 2933 2934 ret = vc4_hdmi_cec_init(vc4_hdmi); 2935 if (ret) 2936 goto err_free_hotplug; 2937 2938 ret = vc4_hdmi_audio_init(vc4_hdmi); 2939 if (ret) 2940 goto err_free_cec; 2941 2942 vc4_debugfs_add_file(drm, variant->debugfs_name, 2943 vc4_hdmi_debugfs_regs, 2944 vc4_hdmi); 2945 2946 pm_runtime_put_sync(dev); 2947 2948 return 0; 2949 2950 err_free_cec: 2951 vc4_hdmi_cec_exit(vc4_hdmi); 2952 err_free_hotplug: 2953 vc4_hdmi_hotplug_exit(vc4_hdmi); 2954 err_destroy_conn: 2955 vc4_hdmi_connector_destroy(&vc4_hdmi->connector); 2956 err_destroy_encoder: 2957 drm_encoder_cleanup(encoder); 2958 pm_runtime_put_sync(dev); 2959 pm_runtime_disable(dev); 2960 err_put_ddc: 2961 put_device(&vc4_hdmi->ddc->dev); 2962 2963 return ret; 2964 } 2965 2966 static void vc4_hdmi_unbind(struct device *dev, struct device *master, 2967 void *data) 2968 { 2969 struct vc4_hdmi *vc4_hdmi; 2970 2971 /* 2972 * ASoC makes it a bit hard to retrieve a pointer to the 2973 * vc4_hdmi structure. Registering the card will overwrite our 2974 * device drvdata with a pointer to the snd_soc_card structure, 2975 * which can then be used to retrieve whatever drvdata we want 2976 * to associate. 2977 * 2978 * However, that doesn't fly in the case where we wouldn't 2979 * register an ASoC card (because of an old DT that is missing 2980 * the dmas properties for example), then the card isn't 2981 * registered and the device drvdata wouldn't be set. 2982 * 2983 * We can deal with both cases by making sure a snd_soc_card 2984 * pointer and a vc4_hdmi structure are pointing to the same 2985 * memory address, so we can treat them indistinctly without any 2986 * issue. 2987 */ 2988 BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0); 2989 BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0); 2990 vc4_hdmi = dev_get_drvdata(dev); 2991 2992 kfree(vc4_hdmi->hdmi_regset.regs); 2993 kfree(vc4_hdmi->hd_regset.regs); 2994 2995 vc4_hdmi_audio_exit(vc4_hdmi); 2996 vc4_hdmi_cec_exit(vc4_hdmi); 2997 vc4_hdmi_hotplug_exit(vc4_hdmi); 2998 vc4_hdmi_connector_destroy(&vc4_hdmi->connector); 2999 drm_encoder_cleanup(&vc4_hdmi->encoder.base); 3000 3001 pm_runtime_disable(dev); 3002 3003 put_device(&vc4_hdmi->ddc->dev); 3004 } 3005 3006 static const struct component_ops vc4_hdmi_ops = { 3007 .bind = vc4_hdmi_bind, 3008 .unbind = vc4_hdmi_unbind, 3009 }; 3010 3011 static int vc4_hdmi_dev_probe(struct platform_device *pdev) 3012 { 3013 return component_add(&pdev->dev, &vc4_hdmi_ops); 3014 } 3015 3016 static int vc4_hdmi_dev_remove(struct platform_device *pdev) 3017 { 3018 component_del(&pdev->dev, &vc4_hdmi_ops); 3019 return 0; 3020 } 3021 3022 static const struct vc4_hdmi_variant bcm2835_variant = { 3023 .encoder_type = VC4_ENCODER_TYPE_HDMI0, 3024 .debugfs_name = "hdmi_regs", 3025 .card_name = "vc4-hdmi", 3026 .max_pixel_clock = 162000000, 3027 .registers = vc4_hdmi_fields, 3028 .num_registers = ARRAY_SIZE(vc4_hdmi_fields), 3029 3030 .init_resources = vc4_hdmi_init_resources, 3031 .csc_setup = vc4_hdmi_csc_setup, 3032 .reset = vc4_hdmi_reset, 3033 .set_timings = vc4_hdmi_set_timings, 3034 .phy_init = vc4_hdmi_phy_init, 3035 .phy_disable = vc4_hdmi_phy_disable, 3036 .phy_rng_enable = vc4_hdmi_phy_rng_enable, 3037 .phy_rng_disable = vc4_hdmi_phy_rng_disable, 3038 .channel_map = vc4_hdmi_channel_map, 3039 .supports_hdr = false, 3040 }; 3041 3042 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = { 3043 .encoder_type = VC4_ENCODER_TYPE_HDMI0, 3044 .debugfs_name = "hdmi0_regs", 3045 .card_name = "vc4-hdmi-0", 3046 .max_pixel_clock = 600000000, 3047 .registers = vc5_hdmi_hdmi0_fields, 3048 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi0_fields), 3049 .phy_lane_mapping = { 3050 PHY_LANE_0, 3051 PHY_LANE_1, 3052 PHY_LANE_2, 3053 PHY_LANE_CK, 3054 }, 3055 .unsupported_odd_h_timings = true, 3056 .external_irq_controller = true, 3057 3058 .init_resources = vc5_hdmi_init_resources, 3059 .csc_setup = vc5_hdmi_csc_setup, 3060 .reset = vc5_hdmi_reset, 3061 .set_timings = vc5_hdmi_set_timings, 3062 .phy_init = vc5_hdmi_phy_init, 3063 .phy_disable = vc5_hdmi_phy_disable, 3064 .phy_rng_enable = vc5_hdmi_phy_rng_enable, 3065 .phy_rng_disable = vc5_hdmi_phy_rng_disable, 3066 .channel_map = vc5_hdmi_channel_map, 3067 .supports_hdr = true, 3068 .hp_detect = vc5_hdmi_hp_detect, 3069 }; 3070 3071 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = { 3072 .encoder_type = VC4_ENCODER_TYPE_HDMI1, 3073 .debugfs_name = "hdmi1_regs", 3074 .card_name = "vc4-hdmi-1", 3075 .max_pixel_clock = HDMI_14_MAX_TMDS_CLK, 3076 .registers = vc5_hdmi_hdmi1_fields, 3077 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi1_fields), 3078 .phy_lane_mapping = { 3079 PHY_LANE_1, 3080 PHY_LANE_0, 3081 PHY_LANE_CK, 3082 PHY_LANE_2, 3083 }, 3084 .unsupported_odd_h_timings = true, 3085 .external_irq_controller = true, 3086 3087 .init_resources = vc5_hdmi_init_resources, 3088 .csc_setup = vc5_hdmi_csc_setup, 3089 .reset = vc5_hdmi_reset, 3090 .set_timings = vc5_hdmi_set_timings, 3091 .phy_init = vc5_hdmi_phy_init, 3092 .phy_disable = vc5_hdmi_phy_disable, 3093 .phy_rng_enable = vc5_hdmi_phy_rng_enable, 3094 .phy_rng_disable = vc5_hdmi_phy_rng_disable, 3095 .channel_map = vc5_hdmi_channel_map, 3096 .supports_hdr = true, 3097 .hp_detect = vc5_hdmi_hp_detect, 3098 }; 3099 3100 static const struct of_device_id vc4_hdmi_dt_match[] = { 3101 { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant }, 3102 { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant }, 3103 { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant }, 3104 {} 3105 }; 3106 3107 static const struct dev_pm_ops vc4_hdmi_pm_ops = { 3108 SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend, 3109 vc4_hdmi_runtime_resume, 3110 NULL) 3111 }; 3112 3113 struct platform_driver vc4_hdmi_driver = { 3114 .probe = vc4_hdmi_dev_probe, 3115 .remove = vc4_hdmi_dev_remove, 3116 .driver = { 3117 .name = "vc4_hdmi", 3118 .of_match_table = vc4_hdmi_dt_match, 3119 .pm = &vc4_hdmi_pm_ops, 3120 }, 3121 }; 3122