1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 Broadcom 4 * Copyright (c) 2014 The Linux Foundation. All rights reserved. 5 * Copyright (C) 2013 Red Hat 6 * Author: Rob Clark <robdclark@gmail.com> 7 */ 8 9 /** 10 * DOC: VC4 Falcon HDMI module 11 * 12 * The HDMI core has a state machine and a PHY. On BCM2835, most of 13 * the unit operates off of the HSM clock from CPRMAN. It also 14 * internally uses the PLLH_PIX clock for the PHY. 15 * 16 * HDMI infoframes are kept within a small packet ram, where each 17 * packet can be individually enabled for including in a frame. 18 * 19 * HDMI audio is implemented entirely within the HDMI IP block. A 20 * register in the HDMI encoder takes SPDIF frames from the DMA engine 21 * and transfers them over an internal MAI (multi-channel audio 22 * interconnect) bus to the encoder side for insertion into the video 23 * blank regions. 24 * 25 * The driver's HDMI encoder does not yet support power management. 26 * The HDMI encoder's power domain and the HSM/pixel clocks are kept 27 * continuously running, and only the HDMI logic and packet ram are 28 * powered off/on at disable/enable time. 29 * 30 * The driver does not yet support CEC control, though the HDMI 31 * encoder block has CEC support. 32 */ 33 34 #include <drm/display/drm_hdmi_helper.h> 35 #include <drm/display/drm_scdc_helper.h> 36 #include <drm/drm_atomic_helper.h> 37 #include <drm/drm_drv.h> 38 #include <drm/drm_probe_helper.h> 39 #include <drm/drm_simple_kms_helper.h> 40 #include <linux/clk.h> 41 #include <linux/component.h> 42 #include <linux/gpio/consumer.h> 43 #include <linux/i2c.h> 44 #include <linux/of_address.h> 45 #include <linux/of_platform.h> 46 #include <linux/pm_runtime.h> 47 #include <linux/rational.h> 48 #include <linux/reset.h> 49 #include <sound/dmaengine_pcm.h> 50 #include <sound/hdmi-codec.h> 51 #include <sound/pcm_drm_eld.h> 52 #include <sound/pcm_params.h> 53 #include <sound/soc.h> 54 #include "media/cec.h" 55 #include "vc4_drv.h" 56 #include "vc4_hdmi.h" 57 #include "vc4_hdmi_regs.h" 58 #include "vc4_regs.h" 59 60 #define VC5_HDMI_HORZA_HFP_SHIFT 16 61 #define VC5_HDMI_HORZA_HFP_MASK VC4_MASK(28, 16) 62 #define VC5_HDMI_HORZA_VPOS BIT(15) 63 #define VC5_HDMI_HORZA_HPOS BIT(14) 64 #define VC5_HDMI_HORZA_HAP_SHIFT 0 65 #define VC5_HDMI_HORZA_HAP_MASK VC4_MASK(13, 0) 66 67 #define VC5_HDMI_HORZB_HBP_SHIFT 16 68 #define VC5_HDMI_HORZB_HBP_MASK VC4_MASK(26, 16) 69 #define VC5_HDMI_HORZB_HSP_SHIFT 0 70 #define VC5_HDMI_HORZB_HSP_MASK VC4_MASK(10, 0) 71 72 #define VC5_HDMI_VERTA_VSP_SHIFT 24 73 #define VC5_HDMI_VERTA_VSP_MASK VC4_MASK(28, 24) 74 #define VC5_HDMI_VERTA_VFP_SHIFT 16 75 #define VC5_HDMI_VERTA_VFP_MASK VC4_MASK(22, 16) 76 #define VC5_HDMI_VERTA_VAL_SHIFT 0 77 #define VC5_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0) 78 79 #define VC5_HDMI_VERTB_VSPO_SHIFT 16 80 #define VC5_HDMI_VERTB_VSPO_MASK VC4_MASK(29, 16) 81 82 #define VC4_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT 0 83 #define VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK VC4_MASK(3, 0) 84 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT 0 85 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK VC4_MASK(3, 0) 86 87 #define VC5_HDMI_SCRAMBLER_CTL_ENABLE BIT(0) 88 89 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT 8 90 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK VC4_MASK(10, 8) 91 92 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT 0 93 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK VC4_MASK(3, 0) 94 95 #define VC5_HDMI_GCP_CONFIG_GCP_ENABLE BIT(31) 96 97 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT 8 98 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK VC4_MASK(15, 8) 99 100 # define VC4_HD_M_SW_RST BIT(2) 101 # define VC4_HD_M_ENABLE BIT(0) 102 103 #define HSM_MIN_CLOCK_FREQ 120000000 104 #define CEC_CLOCK_FREQ 40000 105 106 #define HDMI_14_MAX_TMDS_CLK (340 * 1000 * 1000) 107 108 static const char * const output_format_str[] = { 109 [VC4_HDMI_OUTPUT_RGB] = "RGB", 110 [VC4_HDMI_OUTPUT_YUV420] = "YUV 4:2:0", 111 [VC4_HDMI_OUTPUT_YUV422] = "YUV 4:2:2", 112 [VC4_HDMI_OUTPUT_YUV444] = "YUV 4:4:4", 113 }; 114 115 static const char *vc4_hdmi_output_fmt_str(enum vc4_hdmi_output_format fmt) 116 { 117 if (fmt >= ARRAY_SIZE(output_format_str)) 118 return "invalid"; 119 120 return output_format_str[fmt]; 121 } 122 123 static unsigned long long 124 vc4_hdmi_encoder_compute_mode_clock(const struct drm_display_mode *mode, 125 unsigned int bpc, enum vc4_hdmi_output_format fmt); 126 127 static bool vc4_hdmi_supports_scrambling(struct drm_encoder *encoder) 128 { 129 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 130 struct drm_display_info *display = &vc4_hdmi->connector.display_info; 131 132 lockdep_assert_held(&vc4_hdmi->mutex); 133 134 if (!display->is_hdmi) 135 return false; 136 137 if (!display->hdmi.scdc.supported || 138 !display->hdmi.scdc.scrambling.supported) 139 return false; 140 141 return true; 142 } 143 144 static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode, 145 unsigned int bpc, 146 enum vc4_hdmi_output_format fmt) 147 { 148 unsigned long long clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc, fmt); 149 150 return clock > HDMI_14_MAX_TMDS_CLK; 151 } 152 153 static bool vc4_hdmi_is_full_range_rgb(struct vc4_hdmi *vc4_hdmi, 154 const struct drm_display_mode *mode) 155 { 156 struct drm_display_info *display = &vc4_hdmi->connector.display_info; 157 158 return !display->is_hdmi || 159 drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_FULL; 160 } 161 162 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused) 163 { 164 struct drm_info_node *node = (struct drm_info_node *)m->private; 165 struct vc4_hdmi *vc4_hdmi = node->info_ent->data; 166 struct drm_device *drm = vc4_hdmi->connector.dev; 167 struct drm_printer p = drm_seq_file_printer(m); 168 int idx; 169 170 if (!drm_dev_enter(drm, &idx)) 171 return -ENODEV; 172 173 drm_print_regset32(&p, &vc4_hdmi->hdmi_regset); 174 drm_print_regset32(&p, &vc4_hdmi->hd_regset); 175 drm_print_regset32(&p, &vc4_hdmi->cec_regset); 176 drm_print_regset32(&p, &vc4_hdmi->csc_regset); 177 drm_print_regset32(&p, &vc4_hdmi->dvp_regset); 178 drm_print_regset32(&p, &vc4_hdmi->phy_regset); 179 drm_print_regset32(&p, &vc4_hdmi->ram_regset); 180 drm_print_regset32(&p, &vc4_hdmi->rm_regset); 181 182 drm_dev_exit(idx); 183 184 return 0; 185 } 186 187 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi) 188 { 189 struct drm_device *drm = vc4_hdmi->connector.dev; 190 unsigned long flags; 191 int idx; 192 193 /* 194 * We can be called by our bind callback, when the 195 * connector->dev pointer might not be initialised yet. 196 */ 197 if (drm && !drm_dev_enter(drm, &idx)) 198 return; 199 200 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 201 202 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST); 203 udelay(1); 204 HDMI_WRITE(HDMI_M_CTL, 0); 205 206 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE); 207 208 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 209 VC4_HDMI_SW_RESET_HDMI | 210 VC4_HDMI_SW_RESET_FORMAT_DETECT); 211 212 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0); 213 214 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 215 216 if (drm) 217 drm_dev_exit(idx); 218 } 219 220 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi) 221 { 222 struct drm_device *drm = vc4_hdmi->connector.dev; 223 unsigned long flags; 224 int idx; 225 226 /* 227 * We can be called by our bind callback, when the 228 * connector->dev pointer might not be initialised yet. 229 */ 230 if (drm && !drm_dev_enter(drm, &idx)) 231 return; 232 233 reset_control_reset(vc4_hdmi->reset); 234 235 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 236 237 HDMI_WRITE(HDMI_DVP_CTL, 0); 238 239 HDMI_WRITE(HDMI_CLOCK_STOP, 240 HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL); 241 242 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 243 244 if (drm) 245 drm_dev_exit(idx); 246 } 247 248 #ifdef CONFIG_DRM_VC4_HDMI_CEC 249 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) 250 { 251 struct drm_device *drm = vc4_hdmi->connector.dev; 252 unsigned long cec_rate; 253 unsigned long flags; 254 u16 clk_cnt; 255 u32 value; 256 int idx; 257 258 /* 259 * This function is called by our runtime_resume implementation 260 * and thus at bind time, when we haven't registered our 261 * connector yet and thus don't have a pointer to the DRM 262 * device. 263 */ 264 if (drm && !drm_dev_enter(drm, &idx)) 265 return; 266 267 cec_rate = clk_get_rate(vc4_hdmi->cec_clock); 268 269 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 270 271 value = HDMI_READ(HDMI_CEC_CNTRL_1); 272 value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK; 273 274 /* 275 * Set the clock divider: the hsm_clock rate and this divider 276 * setting will give a 40 kHz CEC clock. 277 */ 278 clk_cnt = cec_rate / CEC_CLOCK_FREQ; 279 value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT; 280 HDMI_WRITE(HDMI_CEC_CNTRL_1, value); 281 282 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 283 284 if (drm) 285 drm_dev_exit(idx); 286 } 287 #else 288 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {} 289 #endif 290 291 static int reset_pipe(struct drm_crtc *crtc, 292 struct drm_modeset_acquire_ctx *ctx) 293 { 294 struct drm_atomic_state *state; 295 struct drm_crtc_state *crtc_state; 296 int ret; 297 298 state = drm_atomic_state_alloc(crtc->dev); 299 if (!state) 300 return -ENOMEM; 301 302 state->acquire_ctx = ctx; 303 304 crtc_state = drm_atomic_get_crtc_state(state, crtc); 305 if (IS_ERR(crtc_state)) { 306 ret = PTR_ERR(crtc_state); 307 goto out; 308 } 309 310 crtc_state->connectors_changed = true; 311 312 ret = drm_atomic_commit(state); 313 out: 314 drm_atomic_state_put(state); 315 316 return ret; 317 } 318 319 static int vc4_hdmi_reset_link(struct drm_connector *connector, 320 struct drm_modeset_acquire_ctx *ctx) 321 { 322 struct drm_device *drm = connector->dev; 323 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 324 struct drm_encoder *encoder = &vc4_hdmi->encoder.base; 325 struct drm_connector_state *conn_state; 326 struct drm_crtc_state *crtc_state; 327 struct drm_crtc *crtc; 328 bool scrambling_needed; 329 u8 config; 330 int ret; 331 332 if (!connector) 333 return 0; 334 335 ret = drm_modeset_lock(&drm->mode_config.connection_mutex, ctx); 336 if (ret) 337 return ret; 338 339 conn_state = connector->state; 340 crtc = conn_state->crtc; 341 if (!crtc) 342 return 0; 343 344 ret = drm_modeset_lock(&crtc->mutex, ctx); 345 if (ret) 346 return ret; 347 348 crtc_state = crtc->state; 349 if (!crtc_state->active) 350 return 0; 351 352 mutex_lock(&vc4_hdmi->mutex); 353 354 if (!vc4_hdmi_supports_scrambling(encoder)) { 355 mutex_unlock(&vc4_hdmi->mutex); 356 return 0; 357 } 358 359 scrambling_needed = vc4_hdmi_mode_needs_scrambling(&vc4_hdmi->saved_adjusted_mode, 360 vc4_hdmi->output_bpc, 361 vc4_hdmi->output_format); 362 if (!scrambling_needed) { 363 mutex_unlock(&vc4_hdmi->mutex); 364 return 0; 365 } 366 367 if (conn_state->commit && 368 !try_wait_for_completion(&conn_state->commit->hw_done)) { 369 mutex_unlock(&vc4_hdmi->mutex); 370 return 0; 371 } 372 373 ret = drm_scdc_readb(connector->ddc, SCDC_TMDS_CONFIG, &config); 374 if (ret < 0) { 375 drm_err(drm, "Failed to read TMDS config: %d\n", ret); 376 mutex_unlock(&vc4_hdmi->mutex); 377 return 0; 378 } 379 380 if (!!(config & SCDC_SCRAMBLING_ENABLE) == scrambling_needed) { 381 mutex_unlock(&vc4_hdmi->mutex); 382 return 0; 383 } 384 385 mutex_unlock(&vc4_hdmi->mutex); 386 387 /* 388 * HDMI 2.0 says that one should not send scrambled data 389 * prior to configuring the sink scrambling, and that 390 * TMDS clock/data transmission should be suspended when 391 * changing the TMDS clock rate in the sink. So let's 392 * just do a full modeset here, even though some sinks 393 * would be perfectly happy if were to just reconfigure 394 * the SCDC settings on the fly. 395 */ 396 return reset_pipe(crtc, ctx); 397 } 398 399 static void vc4_hdmi_handle_hotplug(struct vc4_hdmi *vc4_hdmi, 400 struct drm_modeset_acquire_ctx *ctx, 401 enum drm_connector_status status) 402 { 403 struct drm_connector *connector = &vc4_hdmi->connector; 404 struct edid *edid; 405 406 /* 407 * NOTE: This function should really be called with 408 * vc4_hdmi->mutex held, but doing so results in reentrancy 409 * issues since cec_s_phys_addr_from_edid might call 410 * .adap_enable, which leads to that funtion being called with 411 * our mutex held. 412 * 413 * A similar situation occurs with vc4_hdmi_reset_link() that 414 * will call into our KMS hooks if the scrambling was enabled. 415 * 416 * Concurrency isn't an issue at the moment since we don't share 417 * any state with any of the other frameworks so we can ignore 418 * the lock for now. 419 */ 420 421 if (status == connector_status_disconnected) { 422 cec_phys_addr_invalidate(vc4_hdmi->cec_adap); 423 return; 424 } 425 426 edid = drm_get_edid(connector, vc4_hdmi->ddc); 427 if (!edid) 428 return; 429 430 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid); 431 kfree(edid); 432 433 vc4_hdmi_reset_link(connector, ctx); 434 } 435 436 static int vc4_hdmi_connector_detect_ctx(struct drm_connector *connector, 437 struct drm_modeset_acquire_ctx *ctx, 438 bool force) 439 { 440 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 441 enum drm_connector_status status = connector_status_disconnected; 442 443 /* 444 * NOTE: This function should really take vc4_hdmi->mutex, but 445 * doing so results in reentrancy issues since 446 * vc4_hdmi_handle_hotplug() can call into other functions that 447 * would take the mutex while it's held here. 448 * 449 * Concurrency isn't an issue at the moment since we don't share 450 * any state with any of the other frameworks so we can ignore 451 * the lock for now. 452 */ 453 454 WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev)); 455 456 if (vc4_hdmi->hpd_gpio) { 457 if (gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio)) 458 status = connector_status_connected; 459 } else { 460 if (vc4_hdmi->variant->hp_detect && 461 vc4_hdmi->variant->hp_detect(vc4_hdmi)) 462 status = connector_status_connected; 463 } 464 465 vc4_hdmi_handle_hotplug(vc4_hdmi, ctx, status); 466 pm_runtime_put(&vc4_hdmi->pdev->dev); 467 468 return status; 469 } 470 471 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector) 472 { 473 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 474 int ret = 0; 475 struct edid *edid; 476 477 /* 478 * NOTE: This function should really take vc4_hdmi->mutex, but 479 * doing so results in reentrancy issues since 480 * cec_s_phys_addr_from_edid might call .adap_enable, which 481 * leads to that funtion being called with our mutex held. 482 * 483 * Concurrency isn't an issue at the moment since we don't share 484 * any state with any of the other frameworks so we can ignore 485 * the lock for now. 486 */ 487 488 edid = drm_get_edid(connector, vc4_hdmi->ddc); 489 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid); 490 if (!edid) 491 return -ENODEV; 492 493 drm_connector_update_edid_property(connector, edid); 494 ret = drm_add_edid_modes(connector, edid); 495 kfree(edid); 496 497 if (vc4_hdmi->disable_4kp60) { 498 struct drm_device *drm = connector->dev; 499 const struct drm_display_mode *mode; 500 501 list_for_each_entry(mode, &connector->probed_modes, head) { 502 if (vc4_hdmi_mode_needs_scrambling(mode, 8, VC4_HDMI_OUTPUT_RGB)) { 503 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz."); 504 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60."); 505 } 506 } 507 } 508 509 return ret; 510 } 511 512 static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector, 513 struct drm_atomic_state *state) 514 { 515 struct drm_connector_state *old_state = 516 drm_atomic_get_old_connector_state(state, connector); 517 struct drm_connector_state *new_state = 518 drm_atomic_get_new_connector_state(state, connector); 519 struct drm_crtc *crtc = new_state->crtc; 520 521 if (!crtc) 522 return 0; 523 524 if (old_state->colorspace != new_state->colorspace || 525 !drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) { 526 struct drm_crtc_state *crtc_state; 527 528 crtc_state = drm_atomic_get_crtc_state(state, crtc); 529 if (IS_ERR(crtc_state)) 530 return PTR_ERR(crtc_state); 531 532 crtc_state->mode_changed = true; 533 } 534 535 return 0; 536 } 537 538 static void vc4_hdmi_connector_reset(struct drm_connector *connector) 539 { 540 struct vc4_hdmi_connector_state *old_state = 541 conn_state_to_vc4_hdmi_conn_state(connector->state); 542 struct vc4_hdmi_connector_state *new_state = 543 kzalloc(sizeof(*new_state), GFP_KERNEL); 544 545 if (connector->state) 546 __drm_atomic_helper_connector_destroy_state(connector->state); 547 548 kfree(old_state); 549 __drm_atomic_helper_connector_reset(connector, &new_state->base); 550 551 if (!new_state) 552 return; 553 554 new_state->base.max_bpc = 8; 555 new_state->base.max_requested_bpc = 8; 556 new_state->output_format = VC4_HDMI_OUTPUT_RGB; 557 drm_atomic_helper_connector_tv_reset(connector); 558 } 559 560 static struct drm_connector_state * 561 vc4_hdmi_connector_duplicate_state(struct drm_connector *connector) 562 { 563 struct drm_connector_state *conn_state = connector->state; 564 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state); 565 struct vc4_hdmi_connector_state *new_state; 566 567 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL); 568 if (!new_state) 569 return NULL; 570 571 new_state->tmds_char_rate = vc4_state->tmds_char_rate; 572 new_state->output_bpc = vc4_state->output_bpc; 573 new_state->output_format = vc4_state->output_format; 574 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base); 575 576 return &new_state->base; 577 } 578 579 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = { 580 .fill_modes = drm_helper_probe_single_connector_modes, 581 .reset = vc4_hdmi_connector_reset, 582 .atomic_duplicate_state = vc4_hdmi_connector_duplicate_state, 583 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 584 }; 585 586 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = { 587 .detect_ctx = vc4_hdmi_connector_detect_ctx, 588 .get_modes = vc4_hdmi_connector_get_modes, 589 .atomic_check = vc4_hdmi_connector_atomic_check, 590 }; 591 592 static int vc4_hdmi_connector_init(struct drm_device *dev, 593 struct vc4_hdmi *vc4_hdmi) 594 { 595 struct drm_connector *connector = &vc4_hdmi->connector; 596 struct drm_encoder *encoder = &vc4_hdmi->encoder.base; 597 int ret; 598 599 ret = drmm_connector_init(dev, connector, 600 &vc4_hdmi_connector_funcs, 601 DRM_MODE_CONNECTOR_HDMIA, 602 vc4_hdmi->ddc); 603 if (ret) 604 return ret; 605 606 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs); 607 608 /* 609 * Some of the properties below require access to state, like bpc. 610 * Allocate some default initial connector state with our reset helper. 611 */ 612 if (connector->funcs->reset) 613 connector->funcs->reset(connector); 614 615 /* Create and attach TV margin props to this connector. */ 616 ret = drm_mode_create_tv_margin_properties(dev); 617 if (ret) 618 return ret; 619 620 ret = drm_mode_create_hdmi_colorspace_property(connector); 621 if (ret) 622 return ret; 623 624 drm_connector_attach_colorspace_property(connector); 625 drm_connector_attach_tv_margin_properties(connector); 626 drm_connector_attach_max_bpc_property(connector, 8, 12); 627 628 connector->polled = (DRM_CONNECTOR_POLL_CONNECT | 629 DRM_CONNECTOR_POLL_DISCONNECT); 630 631 connector->interlace_allowed = 1; 632 connector->doublescan_allowed = 0; 633 connector->stereo_allowed = 1; 634 635 if (vc4_hdmi->variant->supports_hdr) 636 drm_connector_attach_hdr_output_metadata_property(connector); 637 638 drm_connector_attach_encoder(connector, encoder); 639 640 return 0; 641 } 642 643 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder, 644 enum hdmi_infoframe_type type, 645 bool poll) 646 { 647 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 648 struct drm_device *drm = vc4_hdmi->connector.dev; 649 u32 packet_id = type - 0x80; 650 unsigned long flags; 651 int ret = 0; 652 int idx; 653 654 if (!drm_dev_enter(drm, &idx)) 655 return -ENODEV; 656 657 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 658 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 659 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id)); 660 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 661 662 if (poll) { 663 ret = wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) & 664 BIT(packet_id)), 100); 665 } 666 667 drm_dev_exit(idx); 668 return ret; 669 } 670 671 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder, 672 union hdmi_infoframe *frame) 673 { 674 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 675 struct drm_device *drm = vc4_hdmi->connector.dev; 676 u32 packet_id = frame->any.type - 0x80; 677 const struct vc4_hdmi_register *ram_packet_start = 678 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START]; 679 u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id; 680 u32 packet_reg_next = ram_packet_start->offset + 681 VC4_HDMI_PACKET_STRIDE * (packet_id + 1); 682 void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi, 683 ram_packet_start->reg); 684 uint8_t buffer[VC4_HDMI_PACKET_STRIDE] = {}; 685 unsigned long flags; 686 ssize_t len, i; 687 int ret; 688 int idx; 689 690 if (!drm_dev_enter(drm, &idx)) 691 return; 692 693 WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) & 694 VC4_HDMI_RAM_PACKET_ENABLE), 695 "Packet RAM has to be on to store the packet."); 696 697 len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer)); 698 if (len < 0) 699 goto out; 700 701 ret = vc4_hdmi_stop_packet(encoder, frame->any.type, true); 702 if (ret) { 703 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret); 704 goto out; 705 } 706 707 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 708 709 for (i = 0; i < len; i += 7) { 710 writel(buffer[i + 0] << 0 | 711 buffer[i + 1] << 8 | 712 buffer[i + 2] << 16, 713 base + packet_reg); 714 packet_reg += 4; 715 716 writel(buffer[i + 3] << 0 | 717 buffer[i + 4] << 8 | 718 buffer[i + 5] << 16 | 719 buffer[i + 6] << 24, 720 base + packet_reg); 721 packet_reg += 4; 722 } 723 724 /* 725 * clear remainder of packet ram as it's included in the 726 * infoframe and triggers a checksum error on hdmi analyser 727 */ 728 for (; packet_reg < packet_reg_next; packet_reg += 4) 729 writel(0, base + packet_reg); 730 731 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 732 HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id)); 733 734 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 735 736 ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) & 737 BIT(packet_id)), 100); 738 if (ret) 739 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret); 740 741 out: 742 drm_dev_exit(idx); 743 } 744 745 static void vc4_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame, 746 enum vc4_hdmi_output_format fmt) 747 { 748 switch (fmt) { 749 case VC4_HDMI_OUTPUT_RGB: 750 frame->colorspace = HDMI_COLORSPACE_RGB; 751 break; 752 753 case VC4_HDMI_OUTPUT_YUV420: 754 frame->colorspace = HDMI_COLORSPACE_YUV420; 755 break; 756 757 case VC4_HDMI_OUTPUT_YUV422: 758 frame->colorspace = HDMI_COLORSPACE_YUV422; 759 break; 760 761 case VC4_HDMI_OUTPUT_YUV444: 762 frame->colorspace = HDMI_COLORSPACE_YUV444; 763 break; 764 765 default: 766 break; 767 } 768 } 769 770 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder) 771 { 772 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 773 struct drm_connector *connector = &vc4_hdmi->connector; 774 struct drm_connector_state *cstate = connector->state; 775 struct vc4_hdmi_connector_state *vc4_state = 776 conn_state_to_vc4_hdmi_conn_state(cstate); 777 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 778 union hdmi_infoframe frame; 779 int ret; 780 781 lockdep_assert_held(&vc4_hdmi->mutex); 782 783 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, 784 connector, mode); 785 if (ret < 0) { 786 DRM_ERROR("couldn't fill AVI infoframe\n"); 787 return; 788 } 789 790 drm_hdmi_avi_infoframe_quant_range(&frame.avi, 791 connector, mode, 792 vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode) ? 793 HDMI_QUANTIZATION_RANGE_FULL : 794 HDMI_QUANTIZATION_RANGE_LIMITED); 795 drm_hdmi_avi_infoframe_colorimetry(&frame.avi, cstate); 796 vc4_hdmi_avi_infoframe_colorspace(&frame.avi, vc4_state->output_format); 797 drm_hdmi_avi_infoframe_bars(&frame.avi, cstate); 798 799 vc4_hdmi_write_infoframe(encoder, &frame); 800 } 801 802 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder) 803 { 804 union hdmi_infoframe frame; 805 int ret; 806 807 ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore"); 808 if (ret < 0) { 809 DRM_ERROR("couldn't fill SPD infoframe\n"); 810 return; 811 } 812 813 frame.spd.sdi = HDMI_SPD_SDI_PC; 814 815 vc4_hdmi_write_infoframe(encoder, &frame); 816 } 817 818 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder) 819 { 820 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 821 struct hdmi_audio_infoframe *audio = &vc4_hdmi->audio.infoframe; 822 union hdmi_infoframe frame; 823 824 memcpy(&frame.audio, audio, sizeof(*audio)); 825 826 if (vc4_hdmi->packet_ram_enabled) 827 vc4_hdmi_write_infoframe(encoder, &frame); 828 } 829 830 static void vc4_hdmi_set_hdr_infoframe(struct drm_encoder *encoder) 831 { 832 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 833 struct drm_connector *connector = &vc4_hdmi->connector; 834 struct drm_connector_state *conn_state = connector->state; 835 union hdmi_infoframe frame; 836 837 lockdep_assert_held(&vc4_hdmi->mutex); 838 839 if (!vc4_hdmi->variant->supports_hdr) 840 return; 841 842 if (!conn_state->hdr_output_metadata) 843 return; 844 845 if (drm_hdmi_infoframe_set_hdr_metadata(&frame.drm, conn_state)) 846 return; 847 848 vc4_hdmi_write_infoframe(encoder, &frame); 849 } 850 851 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder) 852 { 853 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 854 855 lockdep_assert_held(&vc4_hdmi->mutex); 856 857 vc4_hdmi_set_avi_infoframe(encoder); 858 vc4_hdmi_set_spd_infoframe(encoder); 859 /* 860 * If audio was streaming, then we need to reenabled the audio 861 * infoframe here during encoder_enable. 862 */ 863 if (vc4_hdmi->audio.streaming) 864 vc4_hdmi_set_audio_infoframe(encoder); 865 866 vc4_hdmi_set_hdr_infoframe(encoder); 867 } 868 869 #define SCRAMBLING_POLLING_DELAY_MS 1000 870 871 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder) 872 { 873 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 874 struct drm_device *drm = vc4_hdmi->connector.dev; 875 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 876 unsigned long flags; 877 int idx; 878 879 lockdep_assert_held(&vc4_hdmi->mutex); 880 881 if (!vc4_hdmi_supports_scrambling(encoder)) 882 return; 883 884 if (!vc4_hdmi_mode_needs_scrambling(mode, 885 vc4_hdmi->output_bpc, 886 vc4_hdmi->output_format)) 887 return; 888 889 if (!drm_dev_enter(drm, &idx)) 890 return; 891 892 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true); 893 drm_scdc_set_scrambling(vc4_hdmi->ddc, true); 894 895 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 896 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) | 897 VC5_HDMI_SCRAMBLER_CTL_ENABLE); 898 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 899 900 drm_dev_exit(idx); 901 902 vc4_hdmi->scdc_enabled = true; 903 904 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work, 905 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS)); 906 } 907 908 static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder) 909 { 910 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 911 struct drm_device *drm = vc4_hdmi->connector.dev; 912 unsigned long flags; 913 int idx; 914 915 lockdep_assert_held(&vc4_hdmi->mutex); 916 917 if (!vc4_hdmi->scdc_enabled) 918 return; 919 920 vc4_hdmi->scdc_enabled = false; 921 922 if (delayed_work_pending(&vc4_hdmi->scrambling_work)) 923 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work); 924 925 if (!drm_dev_enter(drm, &idx)) 926 return; 927 928 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 929 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) & 930 ~VC5_HDMI_SCRAMBLER_CTL_ENABLE); 931 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 932 933 drm_scdc_set_scrambling(vc4_hdmi->ddc, false); 934 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, false); 935 936 drm_dev_exit(idx); 937 } 938 939 static void vc4_hdmi_scrambling_wq(struct work_struct *work) 940 { 941 struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work), 942 struct vc4_hdmi, 943 scrambling_work); 944 945 if (drm_scdc_get_scrambling_status(vc4_hdmi->ddc)) 946 return; 947 948 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true); 949 drm_scdc_set_scrambling(vc4_hdmi->ddc, true); 950 951 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work, 952 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS)); 953 } 954 955 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder, 956 struct drm_atomic_state *state) 957 { 958 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 959 struct drm_device *drm = vc4_hdmi->connector.dev; 960 unsigned long flags; 961 int idx; 962 963 mutex_lock(&vc4_hdmi->mutex); 964 965 vc4_hdmi->packet_ram_enabled = false; 966 967 if (!drm_dev_enter(drm, &idx)) 968 goto out; 969 970 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 971 972 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0); 973 974 HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB); 975 976 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 977 978 mdelay(1); 979 980 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 981 HDMI_WRITE(HDMI_VID_CTL, 982 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE); 983 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 984 985 vc4_hdmi_disable_scrambling(encoder); 986 987 drm_dev_exit(idx); 988 989 out: 990 mutex_unlock(&vc4_hdmi->mutex); 991 } 992 993 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder, 994 struct drm_atomic_state *state) 995 { 996 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 997 struct drm_device *drm = vc4_hdmi->connector.dev; 998 unsigned long flags; 999 int ret; 1000 int idx; 1001 1002 mutex_lock(&vc4_hdmi->mutex); 1003 1004 if (!drm_dev_enter(drm, &idx)) 1005 goto out; 1006 1007 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1008 HDMI_WRITE(HDMI_VID_CTL, 1009 HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX); 1010 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1011 1012 if (vc4_hdmi->variant->phy_disable) 1013 vc4_hdmi->variant->phy_disable(vc4_hdmi); 1014 1015 clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock); 1016 clk_disable_unprepare(vc4_hdmi->pixel_clock); 1017 1018 ret = pm_runtime_put(&vc4_hdmi->pdev->dev); 1019 if (ret < 0) 1020 DRM_ERROR("Failed to release power domain: %d\n", ret); 1021 1022 drm_dev_exit(idx); 1023 1024 out: 1025 mutex_unlock(&vc4_hdmi->mutex); 1026 } 1027 1028 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, 1029 struct drm_connector_state *state, 1030 const struct drm_display_mode *mode) 1031 { 1032 struct drm_device *drm = vc4_hdmi->connector.dev; 1033 unsigned long flags; 1034 u32 csc_ctl; 1035 int idx; 1036 1037 if (!drm_dev_enter(drm, &idx)) 1038 return; 1039 1040 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1041 1042 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR, 1043 VC4_HD_CSC_CTL_ORDER); 1044 1045 if (!vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode)) { 1046 /* CEA VICs other than #1 requre limited range RGB 1047 * output unless overridden by an AVI infoframe. 1048 * Apply a colorspace conversion to squash 0-255 down 1049 * to 16-235. The matrix here is: 1050 * 1051 * [ 0 0 0.8594 16] 1052 * [ 0 0.8594 0 16] 1053 * [ 0.8594 0 0 16] 1054 * [ 0 0 0 1] 1055 */ 1056 csc_ctl |= VC4_HD_CSC_CTL_ENABLE; 1057 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC; 1058 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM, 1059 VC4_HD_CSC_CTL_MODE); 1060 1061 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000); 1062 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0); 1063 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000); 1064 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000); 1065 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0); 1066 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000); 1067 } 1068 1069 /* The RGB order applies even when CSC is disabled. */ 1070 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl); 1071 1072 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1073 1074 drm_dev_exit(idx); 1075 } 1076 1077 /* 1078 * If we need to output Full Range RGB, then use the unity matrix 1079 * 1080 * [ 1 0 0 0] 1081 * [ 0 1 0 0] 1082 * [ 0 0 1 0] 1083 * 1084 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets 1085 */ 1086 static const u16 vc5_hdmi_csc_full_rgb_unity[3][4] = { 1087 { 0x2000, 0x0000, 0x0000, 0x0000 }, 1088 { 0x0000, 0x2000, 0x0000, 0x0000 }, 1089 { 0x0000, 0x0000, 0x2000, 0x0000 }, 1090 }; 1091 1092 /* 1093 * CEA VICs other than #1 require limited range RGB output unless 1094 * overridden by an AVI infoframe. Apply a colorspace conversion to 1095 * squash 0-255 down to 16-235. The matrix here is: 1096 * 1097 * [ 0.8594 0 0 16] 1098 * [ 0 0.8594 0 16] 1099 * [ 0 0 0.8594 16] 1100 * 1101 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets 1102 */ 1103 static const u16 vc5_hdmi_csc_full_rgb_to_limited_rgb[3][4] = { 1104 { 0x1b80, 0x0000, 0x0000, 0x0400 }, 1105 { 0x0000, 0x1b80, 0x0000, 0x0400 }, 1106 { 0x0000, 0x0000, 0x1b80, 0x0400 }, 1107 }; 1108 1109 /* 1110 * Conversion between Full Range RGB and Full Range YUV422 using the 1111 * BT.709 Colorspace 1112 * 1113 * 1114 * [ 0.181906 0.611804 0.061758 16 ] 1115 * [ -0.100268 -0.337232 0.437500 128 ] 1116 * [ 0.437500 -0.397386 -0.040114 128 ] 1117 * 1118 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets 1119 */ 1120 static const u16 vc5_hdmi_csc_full_rgb_to_limited_yuv422_bt709[3][4] = { 1121 { 0x05d2, 0x1394, 0x01fa, 0x0400 }, 1122 { 0xfccc, 0xf536, 0x0e00, 0x2000 }, 1123 { 0x0e00, 0xf34a, 0xfeb8, 0x2000 }, 1124 }; 1125 1126 /* 1127 * Conversion between Full Range RGB and Full Range YUV444 using the 1128 * BT.709 Colorspace 1129 * 1130 * [ -0.100268 -0.337232 0.437500 128 ] 1131 * [ 0.437500 -0.397386 -0.040114 128 ] 1132 * [ 0.181906 0.611804 0.061758 16 ] 1133 * 1134 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets 1135 */ 1136 static const u16 vc5_hdmi_csc_full_rgb_to_limited_yuv444_bt709[3][4] = { 1137 { 0xfccc, 0xf536, 0x0e00, 0x2000 }, 1138 { 0x0e00, 0xf34a, 0xfeb8, 0x2000 }, 1139 { 0x05d2, 0x1394, 0x01fa, 0x0400 }, 1140 }; 1141 1142 static void vc5_hdmi_set_csc_coeffs(struct vc4_hdmi *vc4_hdmi, 1143 const u16 coeffs[3][4]) 1144 { 1145 lockdep_assert_held(&vc4_hdmi->hw_lock); 1146 1147 HDMI_WRITE(HDMI_CSC_12_11, (coeffs[0][1] << 16) | coeffs[0][0]); 1148 HDMI_WRITE(HDMI_CSC_14_13, (coeffs[0][3] << 16) | coeffs[0][2]); 1149 HDMI_WRITE(HDMI_CSC_22_21, (coeffs[1][1] << 16) | coeffs[1][0]); 1150 HDMI_WRITE(HDMI_CSC_24_23, (coeffs[1][3] << 16) | coeffs[1][2]); 1151 HDMI_WRITE(HDMI_CSC_32_31, (coeffs[2][1] << 16) | coeffs[2][0]); 1152 HDMI_WRITE(HDMI_CSC_34_33, (coeffs[2][3] << 16) | coeffs[2][2]); 1153 } 1154 1155 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, 1156 struct drm_connector_state *state, 1157 const struct drm_display_mode *mode) 1158 { 1159 struct drm_device *drm = vc4_hdmi->connector.dev; 1160 struct vc4_hdmi_connector_state *vc4_state = 1161 conn_state_to_vc4_hdmi_conn_state(state); 1162 unsigned long flags; 1163 u32 if_cfg = 0; 1164 u32 if_xbar = 0x543210; 1165 u32 csc_chan_ctl = 0; 1166 u32 csc_ctl = VC5_MT_CP_CSC_CTL_ENABLE | VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM, 1167 VC5_MT_CP_CSC_CTL_MODE); 1168 int idx; 1169 1170 if (!drm_dev_enter(drm, &idx)) 1171 return; 1172 1173 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1174 1175 switch (vc4_state->output_format) { 1176 case VC4_HDMI_OUTPUT_YUV444: 1177 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_limited_yuv444_bt709); 1178 break; 1179 1180 case VC4_HDMI_OUTPUT_YUV422: 1181 csc_ctl |= VC4_SET_FIELD(VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422_STANDARD, 1182 VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422) | 1183 VC5_MT_CP_CSC_CTL_USE_444_TO_422 | 1184 VC5_MT_CP_CSC_CTL_USE_RNG_SUPPRESSION; 1185 1186 csc_chan_ctl |= VC4_SET_FIELD(VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP_LEGACY_STYLE, 1187 VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP); 1188 1189 if_cfg |= VC4_SET_FIELD(VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422_FORMAT_422_LEGACY, 1190 VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422); 1191 1192 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_limited_yuv422_bt709); 1193 break; 1194 1195 case VC4_HDMI_OUTPUT_RGB: 1196 if_xbar = 0x354021; 1197 1198 if (!vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode)) 1199 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_limited_rgb); 1200 else 1201 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_unity); 1202 break; 1203 1204 default: 1205 break; 1206 } 1207 1208 HDMI_WRITE(HDMI_VEC_INTERFACE_CFG, if_cfg); 1209 HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, if_xbar); 1210 HDMI_WRITE(HDMI_CSC_CHANNEL_CTL, csc_chan_ctl); 1211 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl); 1212 1213 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1214 1215 drm_dev_exit(idx); 1216 } 1217 1218 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi, 1219 struct drm_connector_state *state, 1220 const struct drm_display_mode *mode) 1221 { 1222 struct drm_device *drm = vc4_hdmi->connector.dev; 1223 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 1224 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 1225 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 1226 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 1227 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 1228 VC4_HDMI_VERTA_VSP) | 1229 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 1230 VC4_HDMI_VERTA_VFP) | 1231 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL)); 1232 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 1233 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end + 1234 interlaced, 1235 VC4_HDMI_VERTB_VBP)); 1236 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 1237 VC4_SET_FIELD(mode->crtc_vtotal - 1238 mode->crtc_vsync_end, 1239 VC4_HDMI_VERTB_VBP)); 1240 unsigned long flags; 1241 u32 reg; 1242 int idx; 1243 1244 if (!drm_dev_enter(drm, &idx)) 1245 return; 1246 1247 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1248 1249 HDMI_WRITE(HDMI_HORZA, 1250 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) | 1251 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) | 1252 VC4_SET_FIELD(mode->hdisplay * pixel_rep, 1253 VC4_HDMI_HORZA_HAP)); 1254 1255 HDMI_WRITE(HDMI_HORZB, 1256 VC4_SET_FIELD((mode->htotal - 1257 mode->hsync_end) * pixel_rep, 1258 VC4_HDMI_HORZB_HBP) | 1259 VC4_SET_FIELD((mode->hsync_end - 1260 mode->hsync_start) * pixel_rep, 1261 VC4_HDMI_HORZB_HSP) | 1262 VC4_SET_FIELD((mode->hsync_start - 1263 mode->hdisplay) * pixel_rep, 1264 VC4_HDMI_HORZB_HFP)); 1265 1266 HDMI_WRITE(HDMI_VERTA0, verta); 1267 HDMI_WRITE(HDMI_VERTA1, verta); 1268 1269 HDMI_WRITE(HDMI_VERTB0, vertb_even); 1270 HDMI_WRITE(HDMI_VERTB1, vertb); 1271 1272 reg = HDMI_READ(HDMI_MISC_CONTROL); 1273 reg &= ~VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK; 1274 reg |= VC4_SET_FIELD(pixel_rep - 1, VC4_HDMI_MISC_CONTROL_PIXEL_REP); 1275 HDMI_WRITE(HDMI_MISC_CONTROL, reg); 1276 1277 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1278 1279 drm_dev_exit(idx); 1280 } 1281 1282 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi, 1283 struct drm_connector_state *state, 1284 const struct drm_display_mode *mode) 1285 { 1286 struct drm_device *drm = vc4_hdmi->connector.dev; 1287 const struct vc4_hdmi_connector_state *vc4_state = 1288 conn_state_to_vc4_hdmi_conn_state(state); 1289 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 1290 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 1291 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 1292 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 1293 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 1294 VC5_HDMI_VERTA_VSP) | 1295 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 1296 VC5_HDMI_VERTA_VFP) | 1297 VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL)); 1298 u32 vertb = (VC4_SET_FIELD(mode->htotal >> (2 - pixel_rep), 1299 VC5_HDMI_VERTB_VSPO) | 1300 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end, 1301 VC4_HDMI_VERTB_VBP)); 1302 u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) | 1303 VC4_SET_FIELD(mode->crtc_vtotal - 1304 mode->crtc_vsync_end - interlaced, 1305 VC4_HDMI_VERTB_VBP)); 1306 unsigned long flags; 1307 unsigned char gcp; 1308 bool gcp_en; 1309 u32 reg; 1310 int idx; 1311 1312 if (!drm_dev_enter(drm, &idx)) 1313 return; 1314 1315 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1316 1317 HDMI_WRITE(HDMI_HORZA, 1318 (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) | 1319 (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) | 1320 VC4_SET_FIELD(mode->hdisplay * pixel_rep, 1321 VC5_HDMI_HORZA_HAP) | 1322 VC4_SET_FIELD((mode->hsync_start - 1323 mode->hdisplay) * pixel_rep, 1324 VC5_HDMI_HORZA_HFP)); 1325 1326 HDMI_WRITE(HDMI_HORZB, 1327 VC4_SET_FIELD((mode->htotal - 1328 mode->hsync_end) * pixel_rep, 1329 VC5_HDMI_HORZB_HBP) | 1330 VC4_SET_FIELD((mode->hsync_end - 1331 mode->hsync_start) * pixel_rep, 1332 VC5_HDMI_HORZB_HSP)); 1333 1334 HDMI_WRITE(HDMI_VERTA0, verta); 1335 HDMI_WRITE(HDMI_VERTA1, verta); 1336 1337 HDMI_WRITE(HDMI_VERTB0, vertb_even); 1338 HDMI_WRITE(HDMI_VERTB1, vertb); 1339 1340 switch (vc4_state->output_bpc) { 1341 case 12: 1342 gcp = 6; 1343 gcp_en = true; 1344 break; 1345 case 10: 1346 gcp = 5; 1347 gcp_en = true; 1348 break; 1349 case 8: 1350 default: 1351 gcp = 4; 1352 gcp_en = false; 1353 break; 1354 } 1355 1356 /* 1357 * YCC422 is always 36-bit and not considered deep colour so 1358 * doesn't signal in GCP. 1359 */ 1360 if (vc4_state->output_format == VC4_HDMI_OUTPUT_YUV422) { 1361 gcp = 4; 1362 gcp_en = false; 1363 } 1364 1365 reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1); 1366 reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK | 1367 VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK); 1368 reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) | 1369 VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH); 1370 HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg); 1371 1372 reg = HDMI_READ(HDMI_GCP_WORD_1); 1373 reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK; 1374 reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1); 1375 HDMI_WRITE(HDMI_GCP_WORD_1, reg); 1376 1377 reg = HDMI_READ(HDMI_GCP_CONFIG); 1378 reg &= ~VC5_HDMI_GCP_CONFIG_GCP_ENABLE; 1379 reg |= gcp_en ? VC5_HDMI_GCP_CONFIG_GCP_ENABLE : 0; 1380 HDMI_WRITE(HDMI_GCP_CONFIG, reg); 1381 1382 reg = HDMI_READ(HDMI_MISC_CONTROL); 1383 reg &= ~VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK; 1384 reg |= VC4_SET_FIELD(pixel_rep - 1, VC5_HDMI_MISC_CONTROL_PIXEL_REP); 1385 HDMI_WRITE(HDMI_MISC_CONTROL, reg); 1386 1387 HDMI_WRITE(HDMI_CLOCK_STOP, 0); 1388 1389 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1390 1391 drm_dev_exit(idx); 1392 } 1393 1394 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi) 1395 { 1396 struct drm_device *drm = vc4_hdmi->connector.dev; 1397 unsigned long flags; 1398 u32 drift; 1399 int ret; 1400 int idx; 1401 1402 if (!drm_dev_enter(drm, &idx)) 1403 return; 1404 1405 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1406 1407 drift = HDMI_READ(HDMI_FIFO_CTL); 1408 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK; 1409 1410 HDMI_WRITE(HDMI_FIFO_CTL, 1411 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 1412 HDMI_WRITE(HDMI_FIFO_CTL, 1413 drift | VC4_HDMI_FIFO_CTL_RECENTER); 1414 1415 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1416 1417 usleep_range(1000, 1100); 1418 1419 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1420 1421 HDMI_WRITE(HDMI_FIFO_CTL, 1422 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 1423 HDMI_WRITE(HDMI_FIFO_CTL, 1424 drift | VC4_HDMI_FIFO_CTL_RECENTER); 1425 1426 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1427 1428 ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) & 1429 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1); 1430 WARN_ONCE(ret, "Timeout waiting for " 1431 "VC4_HDMI_FIFO_CTL_RECENTER_DONE"); 1432 1433 drm_dev_exit(idx); 1434 } 1435 1436 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder, 1437 struct drm_atomic_state *state) 1438 { 1439 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1440 struct drm_device *drm = vc4_hdmi->connector.dev; 1441 struct drm_connector *connector = &vc4_hdmi->connector; 1442 struct drm_connector_state *conn_state = 1443 drm_atomic_get_new_connector_state(state, connector); 1444 struct vc4_hdmi_connector_state *vc4_conn_state = 1445 conn_state_to_vc4_hdmi_conn_state(conn_state); 1446 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1447 unsigned long tmds_char_rate = vc4_conn_state->tmds_char_rate; 1448 unsigned long bvb_rate, hsm_rate; 1449 unsigned long flags; 1450 int ret; 1451 int idx; 1452 1453 mutex_lock(&vc4_hdmi->mutex); 1454 1455 if (!drm_dev_enter(drm, &idx)) 1456 goto out; 1457 1458 /* 1459 * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must 1460 * be faster than pixel clock, infinitesimally faster, tested in 1461 * simulation. Otherwise, exact value is unimportant for HDMI 1462 * operation." This conflicts with bcm2835's vc4 documentation, which 1463 * states HSM's clock has to be at least 108% of the pixel clock. 1464 * 1465 * Real life tests reveal that vc4's firmware statement holds up, and 1466 * users are able to use pixel clocks closer to HSM's, namely for 1467 * 1920x1200@60Hz. So it was decided to have leave a 1% margin between 1468 * both clocks. Which, for RPi0-3 implies a maximum pixel clock of 1469 * 162MHz. 1470 * 1471 * Additionally, the AXI clock needs to be at least 25% of 1472 * pixel clock, but HSM ends up being the limiting factor. 1473 */ 1474 hsm_rate = max_t(unsigned long, 120000000, (tmds_char_rate / 100) * 101); 1475 ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate); 1476 if (ret) { 1477 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret); 1478 goto err_dev_exit; 1479 } 1480 1481 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev); 1482 if (ret < 0) { 1483 DRM_ERROR("Failed to retain power domain: %d\n", ret); 1484 goto err_dev_exit; 1485 } 1486 1487 ret = clk_set_rate(vc4_hdmi->pixel_clock, tmds_char_rate); 1488 if (ret) { 1489 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret); 1490 goto err_put_runtime_pm; 1491 } 1492 1493 ret = clk_prepare_enable(vc4_hdmi->pixel_clock); 1494 if (ret) { 1495 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret); 1496 goto err_put_runtime_pm; 1497 } 1498 1499 1500 vc4_hdmi_cec_update_clk_div(vc4_hdmi); 1501 1502 if (tmds_char_rate > 297000000) 1503 bvb_rate = 300000000; 1504 else if (tmds_char_rate > 148500000) 1505 bvb_rate = 150000000; 1506 else 1507 bvb_rate = 75000000; 1508 1509 ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate); 1510 if (ret) { 1511 DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret); 1512 goto err_disable_pixel_clock; 1513 } 1514 1515 ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock); 1516 if (ret) { 1517 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret); 1518 goto err_disable_pixel_clock; 1519 } 1520 1521 if (vc4_hdmi->variant->phy_init) 1522 vc4_hdmi->variant->phy_init(vc4_hdmi, vc4_conn_state); 1523 1524 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1525 1526 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1527 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 1528 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT | 1529 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS); 1530 1531 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1532 1533 if (vc4_hdmi->variant->set_timings) 1534 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode); 1535 1536 drm_dev_exit(idx); 1537 1538 mutex_unlock(&vc4_hdmi->mutex); 1539 1540 return; 1541 1542 err_disable_pixel_clock: 1543 clk_disable_unprepare(vc4_hdmi->pixel_clock); 1544 err_put_runtime_pm: 1545 pm_runtime_put(&vc4_hdmi->pdev->dev); 1546 err_dev_exit: 1547 drm_dev_exit(idx); 1548 out: 1549 mutex_unlock(&vc4_hdmi->mutex); 1550 return; 1551 } 1552 1553 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder, 1554 struct drm_atomic_state *state) 1555 { 1556 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1557 struct drm_device *drm = vc4_hdmi->connector.dev; 1558 struct drm_connector *connector = &vc4_hdmi->connector; 1559 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1560 struct drm_connector_state *conn_state = 1561 drm_atomic_get_new_connector_state(state, connector); 1562 unsigned long flags; 1563 int idx; 1564 1565 mutex_lock(&vc4_hdmi->mutex); 1566 1567 if (!drm_dev_enter(drm, &idx)) 1568 goto out; 1569 1570 if (vc4_hdmi->variant->csc_setup) 1571 vc4_hdmi->variant->csc_setup(vc4_hdmi, conn_state, mode); 1572 1573 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1574 HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N); 1575 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1576 1577 drm_dev_exit(idx); 1578 1579 out: 1580 mutex_unlock(&vc4_hdmi->mutex); 1581 } 1582 1583 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder, 1584 struct drm_atomic_state *state) 1585 { 1586 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1587 struct drm_device *drm = vc4_hdmi->connector.dev; 1588 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1589 struct drm_display_info *display = &vc4_hdmi->connector.display_info; 1590 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 1591 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 1592 unsigned long flags; 1593 int ret; 1594 int idx; 1595 1596 mutex_lock(&vc4_hdmi->mutex); 1597 1598 if (!drm_dev_enter(drm, &idx)) 1599 goto out; 1600 1601 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1602 1603 HDMI_WRITE(HDMI_VID_CTL, 1604 VC4_HD_VID_CTL_ENABLE | 1605 VC4_HD_VID_CTL_CLRRGB | 1606 VC4_HD_VID_CTL_UNDERFLOW_ENABLE | 1607 VC4_HD_VID_CTL_FRAME_COUNTER_RESET | 1608 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) | 1609 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW)); 1610 1611 HDMI_WRITE(HDMI_VID_CTL, 1612 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX); 1613 1614 if (display->is_hdmi) { 1615 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1616 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 1617 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 1618 1619 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1620 1621 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1622 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000); 1623 WARN_ONCE(ret, "Timeout waiting for " 1624 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 1625 } else { 1626 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 1627 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & 1628 ~(VC4_HDMI_RAM_PACKET_ENABLE)); 1629 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1630 HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1631 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 1632 1633 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1634 1635 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1636 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000); 1637 WARN_ONCE(ret, "Timeout waiting for " 1638 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 1639 } 1640 1641 if (display->is_hdmi) { 1642 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1643 1644 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1645 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE)); 1646 1647 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 1648 VC4_HDMI_RAM_PACKET_ENABLE); 1649 1650 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1651 vc4_hdmi->packet_ram_enabled = true; 1652 1653 vc4_hdmi_set_infoframes(encoder); 1654 } 1655 1656 vc4_hdmi_recenter_fifo(vc4_hdmi); 1657 vc4_hdmi_enable_scrambling(encoder); 1658 1659 drm_dev_exit(idx); 1660 1661 out: 1662 mutex_unlock(&vc4_hdmi->mutex); 1663 } 1664 1665 static void vc4_hdmi_encoder_atomic_mode_set(struct drm_encoder *encoder, 1666 struct drm_crtc_state *crtc_state, 1667 struct drm_connector_state *conn_state) 1668 { 1669 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1670 struct vc4_hdmi_connector_state *vc4_state = 1671 conn_state_to_vc4_hdmi_conn_state(conn_state); 1672 1673 mutex_lock(&vc4_hdmi->mutex); 1674 drm_mode_copy(&vc4_hdmi->saved_adjusted_mode, 1675 &crtc_state->adjusted_mode); 1676 vc4_hdmi->output_bpc = vc4_state->output_bpc; 1677 vc4_hdmi->output_format = vc4_state->output_format; 1678 mutex_unlock(&vc4_hdmi->mutex); 1679 } 1680 1681 static bool 1682 vc4_hdmi_sink_supports_format_bpc(const struct vc4_hdmi *vc4_hdmi, 1683 const struct drm_display_info *info, 1684 const struct drm_display_mode *mode, 1685 unsigned int format, unsigned int bpc) 1686 { 1687 struct drm_device *dev = vc4_hdmi->connector.dev; 1688 u8 vic = drm_match_cea_mode(mode); 1689 1690 if (vic == 1 && bpc != 8) { 1691 drm_dbg(dev, "VIC1 requires a bpc of 8, got %u\n", bpc); 1692 return false; 1693 } 1694 1695 if (!info->is_hdmi && 1696 (format != VC4_HDMI_OUTPUT_RGB || bpc != 8)) { 1697 drm_dbg(dev, "DVI Monitors require an RGB output at 8 bpc\n"); 1698 return false; 1699 } 1700 1701 switch (format) { 1702 case VC4_HDMI_OUTPUT_RGB: 1703 drm_dbg(dev, "RGB Format, checking the constraints.\n"); 1704 1705 if (!(info->color_formats & DRM_COLOR_FORMAT_RGB444)) 1706 return false; 1707 1708 if (bpc == 10 && !(info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30)) { 1709 drm_dbg(dev, "10 BPC but sink doesn't support Deep Color 30.\n"); 1710 return false; 1711 } 1712 1713 if (bpc == 12 && !(info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36)) { 1714 drm_dbg(dev, "12 BPC but sink doesn't support Deep Color 36.\n"); 1715 return false; 1716 } 1717 1718 drm_dbg(dev, "RGB format supported in that configuration.\n"); 1719 1720 return true; 1721 1722 case VC4_HDMI_OUTPUT_YUV422: 1723 drm_dbg(dev, "YUV422 format, checking the constraints.\n"); 1724 1725 if (!(info->color_formats & DRM_COLOR_FORMAT_YCBCR422)) { 1726 drm_dbg(dev, "Sink doesn't support YUV422.\n"); 1727 return false; 1728 } 1729 1730 if (bpc != 12) { 1731 drm_dbg(dev, "YUV422 only supports 12 bpc.\n"); 1732 return false; 1733 } 1734 1735 drm_dbg(dev, "YUV422 format supported in that configuration.\n"); 1736 1737 return true; 1738 1739 case VC4_HDMI_OUTPUT_YUV444: 1740 drm_dbg(dev, "YUV444 format, checking the constraints.\n"); 1741 1742 if (!(info->color_formats & DRM_COLOR_FORMAT_YCBCR444)) { 1743 drm_dbg(dev, "Sink doesn't support YUV444.\n"); 1744 return false; 1745 } 1746 1747 if (bpc == 10 && !(info->edid_hdmi_ycbcr444_dc_modes & DRM_EDID_HDMI_DC_30)) { 1748 drm_dbg(dev, "10 BPC but sink doesn't support Deep Color 30.\n"); 1749 return false; 1750 } 1751 1752 if (bpc == 12 && !(info->edid_hdmi_ycbcr444_dc_modes & DRM_EDID_HDMI_DC_36)) { 1753 drm_dbg(dev, "12 BPC but sink doesn't support Deep Color 36.\n"); 1754 return false; 1755 } 1756 1757 drm_dbg(dev, "YUV444 format supported in that configuration.\n"); 1758 1759 return true; 1760 } 1761 1762 return false; 1763 } 1764 1765 static enum drm_mode_status 1766 vc4_hdmi_encoder_clock_valid(const struct vc4_hdmi *vc4_hdmi, 1767 unsigned long long clock) 1768 { 1769 const struct drm_connector *connector = &vc4_hdmi->connector; 1770 const struct drm_display_info *info = &connector->display_info; 1771 1772 if (clock > vc4_hdmi->variant->max_pixel_clock) 1773 return MODE_CLOCK_HIGH; 1774 1775 if (vc4_hdmi->disable_4kp60 && clock > HDMI_14_MAX_TMDS_CLK) 1776 return MODE_CLOCK_HIGH; 1777 1778 if (info->max_tmds_clock && clock > (info->max_tmds_clock * 1000)) 1779 return MODE_CLOCK_HIGH; 1780 1781 return MODE_OK; 1782 } 1783 1784 static unsigned long long 1785 vc4_hdmi_encoder_compute_mode_clock(const struct drm_display_mode *mode, 1786 unsigned int bpc, 1787 enum vc4_hdmi_output_format fmt) 1788 { 1789 unsigned long long clock = mode->clock * 1000ULL; 1790 1791 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 1792 clock = clock * 2; 1793 1794 if (fmt == VC4_HDMI_OUTPUT_YUV422) 1795 bpc = 8; 1796 1797 clock = clock * bpc; 1798 do_div(clock, 8); 1799 1800 return clock; 1801 } 1802 1803 static int 1804 vc4_hdmi_encoder_compute_clock(const struct vc4_hdmi *vc4_hdmi, 1805 struct vc4_hdmi_connector_state *vc4_state, 1806 const struct drm_display_mode *mode, 1807 unsigned int bpc, unsigned int fmt) 1808 { 1809 unsigned long long clock; 1810 1811 clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc, fmt); 1812 if (vc4_hdmi_encoder_clock_valid(vc4_hdmi, clock) != MODE_OK) 1813 return -EINVAL; 1814 1815 vc4_state->tmds_char_rate = clock; 1816 1817 return 0; 1818 } 1819 1820 static int 1821 vc4_hdmi_encoder_compute_format(const struct vc4_hdmi *vc4_hdmi, 1822 struct vc4_hdmi_connector_state *vc4_state, 1823 const struct drm_display_mode *mode, 1824 unsigned int bpc) 1825 { 1826 struct drm_device *dev = vc4_hdmi->connector.dev; 1827 const struct drm_connector *connector = &vc4_hdmi->connector; 1828 const struct drm_display_info *info = &connector->display_info; 1829 unsigned int format; 1830 1831 drm_dbg(dev, "Trying with an RGB output\n"); 1832 1833 format = VC4_HDMI_OUTPUT_RGB; 1834 if (vc4_hdmi_sink_supports_format_bpc(vc4_hdmi, info, mode, format, bpc)) { 1835 int ret; 1836 1837 ret = vc4_hdmi_encoder_compute_clock(vc4_hdmi, vc4_state, 1838 mode, bpc, format); 1839 if (!ret) { 1840 vc4_state->output_format = format; 1841 return 0; 1842 } 1843 } 1844 1845 drm_dbg(dev, "Failed, Trying with an YUV422 output\n"); 1846 1847 format = VC4_HDMI_OUTPUT_YUV422; 1848 if (vc4_hdmi_sink_supports_format_bpc(vc4_hdmi, info, mode, format, bpc)) { 1849 int ret; 1850 1851 ret = vc4_hdmi_encoder_compute_clock(vc4_hdmi, vc4_state, 1852 mode, bpc, format); 1853 if (!ret) { 1854 vc4_state->output_format = format; 1855 return 0; 1856 } 1857 } 1858 1859 drm_dbg(dev, "Failed. No Format Supported for that bpc count.\n"); 1860 1861 return -EINVAL; 1862 } 1863 1864 static int 1865 vc4_hdmi_encoder_compute_config(const struct vc4_hdmi *vc4_hdmi, 1866 struct vc4_hdmi_connector_state *vc4_state, 1867 const struct drm_display_mode *mode) 1868 { 1869 struct drm_device *dev = vc4_hdmi->connector.dev; 1870 struct drm_connector_state *conn_state = &vc4_state->base; 1871 unsigned int max_bpc = clamp_t(unsigned int, conn_state->max_bpc, 8, 12); 1872 unsigned int bpc; 1873 int ret; 1874 1875 for (bpc = max_bpc; bpc >= 8; bpc -= 2) { 1876 drm_dbg(dev, "Trying with a %d bpc output\n", bpc); 1877 1878 ret = vc4_hdmi_encoder_compute_format(vc4_hdmi, vc4_state, 1879 mode, bpc); 1880 if (ret) 1881 continue; 1882 1883 vc4_state->output_bpc = bpc; 1884 1885 drm_dbg(dev, 1886 "Mode %ux%u @ %uHz: Found configuration: bpc: %u, fmt: %s, clock: %llu\n", 1887 mode->hdisplay, mode->vdisplay, drm_mode_vrefresh(mode), 1888 vc4_state->output_bpc, 1889 vc4_hdmi_output_fmt_str(vc4_state->output_format), 1890 vc4_state->tmds_char_rate); 1891 1892 break; 1893 } 1894 1895 return ret; 1896 } 1897 1898 #define WIFI_2_4GHz_CH1_MIN_FREQ 2400000000ULL 1899 #define WIFI_2_4GHz_CH1_MAX_FREQ 2422000000ULL 1900 1901 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder, 1902 struct drm_crtc_state *crtc_state, 1903 struct drm_connector_state *conn_state) 1904 { 1905 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1906 struct drm_connector *connector = &vc4_hdmi->connector; 1907 struct drm_connector_state *old_conn_state = 1908 drm_atomic_get_old_connector_state(conn_state->state, connector); 1909 struct vc4_hdmi_connector_state *old_vc4_state = 1910 conn_state_to_vc4_hdmi_conn_state(old_conn_state); 1911 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state); 1912 struct drm_display_mode *mode = &crtc_state->adjusted_mode; 1913 unsigned long long tmds_char_rate = mode->clock * 1000; 1914 unsigned long long tmds_bit_rate; 1915 int ret; 1916 1917 if (vc4_hdmi->variant->unsupported_odd_h_timings) { 1918 if (mode->flags & DRM_MODE_FLAG_DBLCLK) { 1919 /* Only try to fixup DBLCLK modes to get 480i and 576i 1920 * working. 1921 * A generic solution for all modes with odd horizontal 1922 * timing values seems impossible based on trying to 1923 * solve it for 1366x768 monitors. 1924 */ 1925 if ((mode->hsync_start - mode->hdisplay) & 1) 1926 mode->hsync_start--; 1927 if ((mode->hsync_end - mode->hsync_start) & 1) 1928 mode->hsync_end--; 1929 } 1930 1931 /* Now check whether we still have odd values remaining */ 1932 if ((mode->hdisplay % 2) || (mode->hsync_start % 2) || 1933 (mode->hsync_end % 2) || (mode->htotal % 2)) 1934 return -EINVAL; 1935 } 1936 1937 /* 1938 * The 1440p@60 pixel rate is in the same range than the first 1939 * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz 1940 * bandwidth). Slightly lower the frequency to bring it out of 1941 * the WiFi range. 1942 */ 1943 tmds_bit_rate = tmds_char_rate * 10; 1944 if (vc4_hdmi->disable_wifi_frequencies && 1945 (tmds_bit_rate >= WIFI_2_4GHz_CH1_MIN_FREQ && 1946 tmds_bit_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) { 1947 mode->clock = 238560; 1948 tmds_char_rate = mode->clock * 1000; 1949 } 1950 1951 ret = vc4_hdmi_encoder_compute_config(vc4_hdmi, vc4_state, mode); 1952 if (ret) 1953 return ret; 1954 1955 /* vc4_hdmi_encoder_compute_config may have changed output_bpc and/or output_format */ 1956 if (vc4_state->output_bpc != old_vc4_state->output_bpc || 1957 vc4_state->output_format != old_vc4_state->output_format) 1958 crtc_state->mode_changed = true; 1959 1960 return 0; 1961 } 1962 1963 static enum drm_mode_status 1964 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder, 1965 const struct drm_display_mode *mode) 1966 { 1967 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1968 1969 if (vc4_hdmi->variant->unsupported_odd_h_timings && 1970 !(mode->flags & DRM_MODE_FLAG_DBLCLK) && 1971 ((mode->hdisplay % 2) || (mode->hsync_start % 2) || 1972 (mode->hsync_end % 2) || (mode->htotal % 2))) 1973 return MODE_H_ILLEGAL; 1974 1975 return vc4_hdmi_encoder_clock_valid(vc4_hdmi, mode->clock * 1000); 1976 } 1977 1978 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = { 1979 .atomic_check = vc4_hdmi_encoder_atomic_check, 1980 .atomic_mode_set = vc4_hdmi_encoder_atomic_mode_set, 1981 .mode_valid = vc4_hdmi_encoder_mode_valid, 1982 }; 1983 1984 static int vc4_hdmi_late_register(struct drm_encoder *encoder) 1985 { 1986 struct drm_device *drm = encoder->dev; 1987 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1988 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant; 1989 int ret; 1990 1991 ret = vc4_debugfs_add_file(drm->primary, variant->debugfs_name, 1992 vc4_hdmi_debugfs_regs, 1993 vc4_hdmi); 1994 if (ret) 1995 return ret; 1996 1997 return 0; 1998 } 1999 2000 static const struct drm_encoder_funcs vc4_hdmi_encoder_funcs = { 2001 .late_register = vc4_hdmi_late_register, 2002 }; 2003 2004 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask) 2005 { 2006 int i; 2007 u32 channel_map = 0; 2008 2009 for (i = 0; i < 8; i++) { 2010 if (channel_mask & BIT(i)) 2011 channel_map |= i << (3 * i); 2012 } 2013 return channel_map; 2014 } 2015 2016 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask) 2017 { 2018 int i; 2019 u32 channel_map = 0; 2020 2021 for (i = 0; i < 8; i++) { 2022 if (channel_mask & BIT(i)) 2023 channel_map |= i << (4 * i); 2024 } 2025 return channel_map; 2026 } 2027 2028 static bool vc5_hdmi_hp_detect(struct vc4_hdmi *vc4_hdmi) 2029 { 2030 struct drm_device *drm = vc4_hdmi->connector.dev; 2031 unsigned long flags; 2032 u32 hotplug; 2033 int idx; 2034 2035 if (!drm_dev_enter(drm, &idx)) 2036 return false; 2037 2038 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2039 hotplug = HDMI_READ(HDMI_HOTPLUG); 2040 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2041 2042 drm_dev_exit(idx); 2043 2044 return !!(hotplug & VC4_HDMI_HOTPLUG_CONNECTED); 2045 } 2046 2047 /* HDMI audio codec callbacks */ 2048 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi, 2049 unsigned int samplerate) 2050 { 2051 struct drm_device *drm = vc4_hdmi->connector.dev; 2052 u32 hsm_clock; 2053 unsigned long flags; 2054 unsigned long n, m; 2055 int idx; 2056 2057 if (!drm_dev_enter(drm, &idx)) 2058 return; 2059 2060 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock); 2061 rational_best_approximation(hsm_clock, samplerate, 2062 VC4_HD_MAI_SMP_N_MASK >> 2063 VC4_HD_MAI_SMP_N_SHIFT, 2064 (VC4_HD_MAI_SMP_M_MASK >> 2065 VC4_HD_MAI_SMP_M_SHIFT) + 1, 2066 &n, &m); 2067 2068 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2069 HDMI_WRITE(HDMI_MAI_SMP, 2070 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) | 2071 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M)); 2072 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2073 2074 drm_dev_exit(idx); 2075 } 2076 2077 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi, unsigned int samplerate) 2078 { 2079 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 2080 u32 n, cts; 2081 u64 tmp; 2082 2083 lockdep_assert_held(&vc4_hdmi->mutex); 2084 lockdep_assert_held(&vc4_hdmi->hw_lock); 2085 2086 n = 128 * samplerate / 1000; 2087 tmp = (u64)(mode->clock * 1000) * n; 2088 do_div(tmp, 128 * samplerate); 2089 cts = tmp; 2090 2091 HDMI_WRITE(HDMI_CRP_CFG, 2092 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN | 2093 VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N)); 2094 2095 /* 2096 * We could get slightly more accurate clocks in some cases by 2097 * providing a CTS_1 value. The two CTS values are alternated 2098 * between based on the period fields 2099 */ 2100 HDMI_WRITE(HDMI_CTS_0, cts); 2101 HDMI_WRITE(HDMI_CTS_1, cts); 2102 } 2103 2104 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai) 2105 { 2106 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai); 2107 2108 return snd_soc_card_get_drvdata(card); 2109 } 2110 2111 static bool vc4_hdmi_audio_can_stream(struct vc4_hdmi *vc4_hdmi) 2112 { 2113 struct drm_display_info *display = &vc4_hdmi->connector.display_info; 2114 2115 lockdep_assert_held(&vc4_hdmi->mutex); 2116 2117 /* 2118 * If the encoder is currently in DVI mode, treat the codec DAI 2119 * as missing. 2120 */ 2121 if (!display->is_hdmi) 2122 return false; 2123 2124 return true; 2125 } 2126 2127 static int vc4_hdmi_audio_startup(struct device *dev, void *data) 2128 { 2129 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 2130 struct drm_device *drm = vc4_hdmi->connector.dev; 2131 unsigned long flags; 2132 int ret = 0; 2133 int idx; 2134 2135 mutex_lock(&vc4_hdmi->mutex); 2136 2137 if (!drm_dev_enter(drm, &idx)) { 2138 ret = -ENODEV; 2139 goto out; 2140 } 2141 2142 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) { 2143 ret = -ENODEV; 2144 goto out_dev_exit; 2145 } 2146 2147 vc4_hdmi->audio.streaming = true; 2148 2149 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2150 HDMI_WRITE(HDMI_MAI_CTL, 2151 VC4_HD_MAI_CTL_RESET | 2152 VC4_HD_MAI_CTL_FLUSH | 2153 VC4_HD_MAI_CTL_DLATE | 2154 VC4_HD_MAI_CTL_ERRORE | 2155 VC4_HD_MAI_CTL_ERRORF); 2156 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2157 2158 if (vc4_hdmi->variant->phy_rng_enable) 2159 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi); 2160 2161 out_dev_exit: 2162 drm_dev_exit(idx); 2163 out: 2164 mutex_unlock(&vc4_hdmi->mutex); 2165 2166 return ret; 2167 } 2168 2169 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi) 2170 { 2171 struct drm_encoder *encoder = &vc4_hdmi->encoder.base; 2172 struct device *dev = &vc4_hdmi->pdev->dev; 2173 unsigned long flags; 2174 int ret; 2175 2176 lockdep_assert_held(&vc4_hdmi->mutex); 2177 2178 vc4_hdmi->audio.streaming = false; 2179 ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO, false); 2180 if (ret) 2181 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret); 2182 2183 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2184 2185 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET); 2186 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF); 2187 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH); 2188 2189 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2190 } 2191 2192 static void vc4_hdmi_audio_shutdown(struct device *dev, void *data) 2193 { 2194 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 2195 struct drm_device *drm = vc4_hdmi->connector.dev; 2196 unsigned long flags; 2197 int idx; 2198 2199 mutex_lock(&vc4_hdmi->mutex); 2200 2201 if (!drm_dev_enter(drm, &idx)) 2202 goto out; 2203 2204 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2205 2206 HDMI_WRITE(HDMI_MAI_CTL, 2207 VC4_HD_MAI_CTL_DLATE | 2208 VC4_HD_MAI_CTL_ERRORE | 2209 VC4_HD_MAI_CTL_ERRORF); 2210 2211 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2212 2213 if (vc4_hdmi->variant->phy_rng_disable) 2214 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi); 2215 2216 vc4_hdmi->audio.streaming = false; 2217 vc4_hdmi_audio_reset(vc4_hdmi); 2218 2219 drm_dev_exit(idx); 2220 2221 out: 2222 mutex_unlock(&vc4_hdmi->mutex); 2223 } 2224 2225 static int sample_rate_to_mai_fmt(int samplerate) 2226 { 2227 switch (samplerate) { 2228 case 8000: 2229 return VC4_HDMI_MAI_SAMPLE_RATE_8000; 2230 case 11025: 2231 return VC4_HDMI_MAI_SAMPLE_RATE_11025; 2232 case 12000: 2233 return VC4_HDMI_MAI_SAMPLE_RATE_12000; 2234 case 16000: 2235 return VC4_HDMI_MAI_SAMPLE_RATE_16000; 2236 case 22050: 2237 return VC4_HDMI_MAI_SAMPLE_RATE_22050; 2238 case 24000: 2239 return VC4_HDMI_MAI_SAMPLE_RATE_24000; 2240 case 32000: 2241 return VC4_HDMI_MAI_SAMPLE_RATE_32000; 2242 case 44100: 2243 return VC4_HDMI_MAI_SAMPLE_RATE_44100; 2244 case 48000: 2245 return VC4_HDMI_MAI_SAMPLE_RATE_48000; 2246 case 64000: 2247 return VC4_HDMI_MAI_SAMPLE_RATE_64000; 2248 case 88200: 2249 return VC4_HDMI_MAI_SAMPLE_RATE_88200; 2250 case 96000: 2251 return VC4_HDMI_MAI_SAMPLE_RATE_96000; 2252 case 128000: 2253 return VC4_HDMI_MAI_SAMPLE_RATE_128000; 2254 case 176400: 2255 return VC4_HDMI_MAI_SAMPLE_RATE_176400; 2256 case 192000: 2257 return VC4_HDMI_MAI_SAMPLE_RATE_192000; 2258 default: 2259 return VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED; 2260 } 2261 } 2262 2263 /* HDMI audio codec callbacks */ 2264 static int vc4_hdmi_audio_prepare(struct device *dev, void *data, 2265 struct hdmi_codec_daifmt *daifmt, 2266 struct hdmi_codec_params *params) 2267 { 2268 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 2269 struct drm_device *drm = vc4_hdmi->connector.dev; 2270 struct drm_encoder *encoder = &vc4_hdmi->encoder.base; 2271 unsigned int sample_rate = params->sample_rate; 2272 unsigned int channels = params->channels; 2273 unsigned long flags; 2274 u32 audio_packet_config, channel_mask; 2275 u32 channel_map; 2276 u32 mai_audio_format; 2277 u32 mai_sample_rate; 2278 int ret = 0; 2279 int idx; 2280 2281 dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__, 2282 sample_rate, params->sample_width, channels); 2283 2284 mutex_lock(&vc4_hdmi->mutex); 2285 2286 if (!drm_dev_enter(drm, &idx)) { 2287 ret = -ENODEV; 2288 goto out; 2289 } 2290 2291 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) { 2292 ret = -EINVAL; 2293 goto out_dev_exit; 2294 } 2295 2296 vc4_hdmi_audio_set_mai_clock(vc4_hdmi, sample_rate); 2297 2298 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2299 HDMI_WRITE(HDMI_MAI_CTL, 2300 VC4_SET_FIELD(channels, VC4_HD_MAI_CTL_CHNUM) | 2301 VC4_HD_MAI_CTL_WHOLSMP | 2302 VC4_HD_MAI_CTL_CHALIGN | 2303 VC4_HD_MAI_CTL_ENABLE); 2304 2305 mai_sample_rate = sample_rate_to_mai_fmt(sample_rate); 2306 if (params->iec.status[0] & IEC958_AES0_NONAUDIO && 2307 params->channels == 8) 2308 mai_audio_format = VC4_HDMI_MAI_FORMAT_HBR; 2309 else 2310 mai_audio_format = VC4_HDMI_MAI_FORMAT_PCM; 2311 HDMI_WRITE(HDMI_MAI_FMT, 2312 VC4_SET_FIELD(mai_sample_rate, 2313 VC4_HDMI_MAI_FORMAT_SAMPLE_RATE) | 2314 VC4_SET_FIELD(mai_audio_format, 2315 VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT)); 2316 2317 /* The B frame identifier should match the value used by alsa-lib (8) */ 2318 audio_packet_config = 2319 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT | 2320 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS | 2321 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER); 2322 2323 channel_mask = GENMASK(channels - 1, 0); 2324 audio_packet_config |= VC4_SET_FIELD(channel_mask, 2325 VC4_HDMI_AUDIO_PACKET_CEA_MASK); 2326 2327 /* Set the MAI threshold */ 2328 HDMI_WRITE(HDMI_MAI_THR, 2329 VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICHIGH) | 2330 VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICLOW) | 2331 VC4_SET_FIELD(0x06, VC4_HD_MAI_THR_DREQHIGH) | 2332 VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_DREQLOW)); 2333 2334 HDMI_WRITE(HDMI_MAI_CONFIG, 2335 VC4_HDMI_MAI_CONFIG_BIT_REVERSE | 2336 VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE | 2337 VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK)); 2338 2339 channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask); 2340 HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map); 2341 HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config); 2342 2343 vc4_hdmi_set_n_cts(vc4_hdmi, sample_rate); 2344 2345 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2346 2347 memcpy(&vc4_hdmi->audio.infoframe, ¶ms->cea, sizeof(params->cea)); 2348 vc4_hdmi_set_audio_infoframe(encoder); 2349 2350 out_dev_exit: 2351 drm_dev_exit(idx); 2352 out: 2353 mutex_unlock(&vc4_hdmi->mutex); 2354 2355 return ret; 2356 } 2357 2358 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = { 2359 .name = "vc4-hdmi-cpu-dai-component", 2360 .legacy_dai_naming = 1, 2361 }; 2362 2363 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai) 2364 { 2365 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai); 2366 2367 snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL); 2368 2369 return 0; 2370 } 2371 2372 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = { 2373 .name = "vc4-hdmi-cpu-dai", 2374 .probe = vc4_hdmi_audio_cpu_dai_probe, 2375 .playback = { 2376 .stream_name = "Playback", 2377 .channels_min = 1, 2378 .channels_max = 8, 2379 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 2380 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 2381 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 2382 SNDRV_PCM_RATE_192000, 2383 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 2384 }, 2385 }; 2386 2387 static const struct snd_dmaengine_pcm_config pcm_conf = { 2388 .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx", 2389 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 2390 }; 2391 2392 static int vc4_hdmi_audio_get_eld(struct device *dev, void *data, 2393 uint8_t *buf, size_t len) 2394 { 2395 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 2396 struct drm_connector *connector = &vc4_hdmi->connector; 2397 2398 mutex_lock(&vc4_hdmi->mutex); 2399 memcpy(buf, connector->eld, min(sizeof(connector->eld), len)); 2400 mutex_unlock(&vc4_hdmi->mutex); 2401 2402 return 0; 2403 } 2404 2405 static const struct hdmi_codec_ops vc4_hdmi_codec_ops = { 2406 .get_eld = vc4_hdmi_audio_get_eld, 2407 .prepare = vc4_hdmi_audio_prepare, 2408 .audio_shutdown = vc4_hdmi_audio_shutdown, 2409 .audio_startup = vc4_hdmi_audio_startup, 2410 }; 2411 2412 static struct hdmi_codec_pdata vc4_hdmi_codec_pdata = { 2413 .ops = &vc4_hdmi_codec_ops, 2414 .max_i2s_channels = 8, 2415 .i2s = 1, 2416 }; 2417 2418 static void vc4_hdmi_audio_codec_release(void *ptr) 2419 { 2420 struct vc4_hdmi *vc4_hdmi = ptr; 2421 2422 platform_device_unregister(vc4_hdmi->audio.codec_pdev); 2423 vc4_hdmi->audio.codec_pdev = NULL; 2424 } 2425 2426 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi) 2427 { 2428 const struct vc4_hdmi_register *mai_data = 2429 &vc4_hdmi->variant->registers[HDMI_MAI_DATA]; 2430 struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link; 2431 struct snd_soc_card *card = &vc4_hdmi->audio.card; 2432 struct device *dev = &vc4_hdmi->pdev->dev; 2433 struct platform_device *codec_pdev; 2434 const __be32 *addr; 2435 int index, len; 2436 int ret; 2437 2438 /* 2439 * ASoC makes it a bit hard to retrieve a pointer to the 2440 * vc4_hdmi structure. Registering the card will overwrite our 2441 * device drvdata with a pointer to the snd_soc_card structure, 2442 * which can then be used to retrieve whatever drvdata we want 2443 * to associate. 2444 * 2445 * However, that doesn't fly in the case where we wouldn't 2446 * register an ASoC card (because of an old DT that is missing 2447 * the dmas properties for example), then the card isn't 2448 * registered and the device drvdata wouldn't be set. 2449 * 2450 * We can deal with both cases by making sure a snd_soc_card 2451 * pointer and a vc4_hdmi structure are pointing to the same 2452 * memory address, so we can treat them indistinctly without any 2453 * issue. 2454 */ 2455 BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0); 2456 BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0); 2457 2458 if (!of_find_property(dev->of_node, "dmas", &len) || !len) { 2459 dev_warn(dev, 2460 "'dmas' DT property is missing or empty, no HDMI audio\n"); 2461 return 0; 2462 } 2463 2464 if (mai_data->reg != VC4_HD) { 2465 WARN_ONCE(true, "MAI isn't in the HD block\n"); 2466 return -EINVAL; 2467 } 2468 2469 /* 2470 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve 2471 * the bus address specified in the DT, because the physical address 2472 * (the one returned by platform_get_resource()) is not appropriate 2473 * for DMA transfers. 2474 * This VC/MMU should probably be exposed to avoid this kind of hacks. 2475 */ 2476 index = of_property_match_string(dev->of_node, "reg-names", "hd"); 2477 /* Before BCM2711, we don't have a named register range */ 2478 if (index < 0) 2479 index = 1; 2480 2481 addr = of_get_address(dev->of_node, index, NULL, NULL); 2482 2483 vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset; 2484 vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 2485 vc4_hdmi->audio.dma_data.maxburst = 2; 2486 2487 /* 2488 * NOTE: Strictly speaking, we should probably use a DRM-managed 2489 * registration there to avoid removing all the audio components 2490 * by the time the driver doesn't have any user anymore. 2491 * 2492 * However, the ASoC core uses a number of devm_kzalloc calls 2493 * when registering, even when using non-device-managed 2494 * functions (such as in snd_soc_register_component()). 2495 * 2496 * If we call snd_soc_unregister_component() in a DRM-managed 2497 * action, the device-managed actions have already been executed 2498 * and thus we would access memory that has been freed. 2499 * 2500 * Using device-managed hooks here probably leaves us open to a 2501 * bunch of issues if userspace still has a handle on the ALSA 2502 * device when the device is removed. However, this is mitigated 2503 * by the use of drm_dev_enter()/drm_dev_exit() in the audio 2504 * path to prevent the access to the device resources if it 2505 * isn't there anymore. 2506 * 2507 * Then, the vc4_hdmi structure is DRM-managed and thus only 2508 * freed whenever the last user has closed the DRM device file. 2509 * It should thus outlive ALSA in most situations. 2510 */ 2511 ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0); 2512 if (ret) { 2513 dev_err(dev, "Could not register PCM component: %d\n", ret); 2514 return ret; 2515 } 2516 2517 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp, 2518 &vc4_hdmi_audio_cpu_dai_drv, 1); 2519 if (ret) { 2520 dev_err(dev, "Could not register CPU DAI: %d\n", ret); 2521 return ret; 2522 } 2523 2524 codec_pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME, 2525 PLATFORM_DEVID_AUTO, 2526 &vc4_hdmi_codec_pdata, 2527 sizeof(vc4_hdmi_codec_pdata)); 2528 if (IS_ERR(codec_pdev)) { 2529 dev_err(dev, "Couldn't register the HDMI codec: %ld\n", PTR_ERR(codec_pdev)); 2530 return PTR_ERR(codec_pdev); 2531 } 2532 vc4_hdmi->audio.codec_pdev = codec_pdev; 2533 2534 ret = devm_add_action_or_reset(dev, vc4_hdmi_audio_codec_release, vc4_hdmi); 2535 if (ret) 2536 return ret; 2537 2538 dai_link->cpus = &vc4_hdmi->audio.cpu; 2539 dai_link->codecs = &vc4_hdmi->audio.codec; 2540 dai_link->platforms = &vc4_hdmi->audio.platform; 2541 2542 dai_link->num_cpus = 1; 2543 dai_link->num_codecs = 1; 2544 dai_link->num_platforms = 1; 2545 2546 dai_link->name = "MAI"; 2547 dai_link->stream_name = "MAI PCM"; 2548 dai_link->codecs->dai_name = "i2s-hifi"; 2549 dai_link->cpus->dai_name = dev_name(dev); 2550 dai_link->codecs->name = dev_name(&codec_pdev->dev); 2551 dai_link->platforms->name = dev_name(dev); 2552 2553 card->dai_link = dai_link; 2554 card->num_links = 1; 2555 card->name = vc4_hdmi->variant->card_name; 2556 card->driver_name = "vc4-hdmi"; 2557 card->dev = dev; 2558 card->owner = THIS_MODULE; 2559 2560 /* 2561 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and 2562 * stores a pointer to the snd card object in dev->driver_data. This 2563 * means we cannot use it for something else. The hdmi back-pointer is 2564 * now stored in card->drvdata and should be retrieved with 2565 * snd_soc_card_get_drvdata() if needed. 2566 */ 2567 snd_soc_card_set_drvdata(card, vc4_hdmi); 2568 ret = devm_snd_soc_register_card(dev, card); 2569 if (ret) 2570 dev_err_probe(dev, ret, "Could not register sound card\n"); 2571 2572 return ret; 2573 2574 } 2575 2576 static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv) 2577 { 2578 struct vc4_hdmi *vc4_hdmi = priv; 2579 struct drm_connector *connector = &vc4_hdmi->connector; 2580 struct drm_device *dev = connector->dev; 2581 2582 if (dev && dev->registered) 2583 drm_connector_helper_hpd_irq_event(connector); 2584 2585 return IRQ_HANDLED; 2586 } 2587 2588 static int vc4_hdmi_hotplug_init(struct vc4_hdmi *vc4_hdmi) 2589 { 2590 struct drm_connector *connector = &vc4_hdmi->connector; 2591 struct platform_device *pdev = vc4_hdmi->pdev; 2592 int ret; 2593 2594 if (vc4_hdmi->variant->external_irq_controller) { 2595 unsigned int hpd_con = platform_get_irq_byname(pdev, "hpd-connected"); 2596 unsigned int hpd_rm = platform_get_irq_byname(pdev, "hpd-removed"); 2597 2598 ret = devm_request_threaded_irq(&pdev->dev, hpd_con, 2599 NULL, 2600 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT, 2601 "vc4 hdmi hpd connected", vc4_hdmi); 2602 if (ret) 2603 return ret; 2604 2605 ret = devm_request_threaded_irq(&pdev->dev, hpd_rm, 2606 NULL, 2607 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT, 2608 "vc4 hdmi hpd disconnected", vc4_hdmi); 2609 if (ret) 2610 return ret; 2611 2612 connector->polled = DRM_CONNECTOR_POLL_HPD; 2613 } 2614 2615 return 0; 2616 } 2617 2618 #ifdef CONFIG_DRM_VC4_HDMI_CEC 2619 static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv) 2620 { 2621 struct vc4_hdmi *vc4_hdmi = priv; 2622 2623 if (vc4_hdmi->cec_rx_msg.len) 2624 cec_received_msg(vc4_hdmi->cec_adap, 2625 &vc4_hdmi->cec_rx_msg); 2626 2627 return IRQ_HANDLED; 2628 } 2629 2630 static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv) 2631 { 2632 struct vc4_hdmi *vc4_hdmi = priv; 2633 2634 if (vc4_hdmi->cec_tx_ok) { 2635 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK, 2636 0, 0, 0, 0); 2637 } else { 2638 /* 2639 * This CEC implementation makes 1 retry, so if we 2640 * get a NACK, then that means it made 2 attempts. 2641 */ 2642 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK, 2643 0, 2, 0, 0); 2644 } 2645 return IRQ_HANDLED; 2646 } 2647 2648 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv) 2649 { 2650 struct vc4_hdmi *vc4_hdmi = priv; 2651 irqreturn_t ret; 2652 2653 if (vc4_hdmi->cec_irq_was_rx) 2654 ret = vc4_cec_irq_handler_rx_thread(irq, priv); 2655 else 2656 ret = vc4_cec_irq_handler_tx_thread(irq, priv); 2657 2658 return ret; 2659 } 2660 2661 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1) 2662 { 2663 struct drm_device *dev = vc4_hdmi->connector.dev; 2664 struct cec_msg *msg = &vc4_hdmi->cec_rx_msg; 2665 unsigned int i; 2666 2667 lockdep_assert_held(&vc4_hdmi->hw_lock); 2668 2669 msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >> 2670 VC4_HDMI_CEC_REC_WRD_CNT_SHIFT); 2671 2672 if (msg->len > 16) { 2673 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len); 2674 return; 2675 } 2676 2677 for (i = 0; i < msg->len; i += 4) { 2678 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2)); 2679 2680 msg->msg[i] = val & 0xff; 2681 msg->msg[i + 1] = (val >> 8) & 0xff; 2682 msg->msg[i + 2] = (val >> 16) & 0xff; 2683 msg->msg[i + 3] = (val >> 24) & 0xff; 2684 } 2685 } 2686 2687 static irqreturn_t vc4_cec_irq_handler_tx_bare_locked(struct vc4_hdmi *vc4_hdmi) 2688 { 2689 u32 cntrl1; 2690 2691 /* 2692 * We don't need to protect the register access using 2693 * drm_dev_enter() there because the interrupt handler lifetime 2694 * is tied to the device itself, and not to the DRM device. 2695 * 2696 * So when the device will be gone, one of the first thing we 2697 * will be doing will be to unregister the interrupt handler, 2698 * and then unregister the DRM device. drm_dev_enter() would 2699 * thus always succeed if we are here. 2700 */ 2701 2702 lockdep_assert_held(&vc4_hdmi->hw_lock); 2703 2704 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1); 2705 vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD; 2706 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 2707 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 2708 2709 return IRQ_WAKE_THREAD; 2710 } 2711 2712 static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv) 2713 { 2714 struct vc4_hdmi *vc4_hdmi = priv; 2715 irqreturn_t ret; 2716 2717 spin_lock(&vc4_hdmi->hw_lock); 2718 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi); 2719 spin_unlock(&vc4_hdmi->hw_lock); 2720 2721 return ret; 2722 } 2723 2724 static irqreturn_t vc4_cec_irq_handler_rx_bare_locked(struct vc4_hdmi *vc4_hdmi) 2725 { 2726 u32 cntrl1; 2727 2728 lockdep_assert_held(&vc4_hdmi->hw_lock); 2729 2730 /* 2731 * We don't need to protect the register access using 2732 * drm_dev_enter() there because the interrupt handler lifetime 2733 * is tied to the device itself, and not to the DRM device. 2734 * 2735 * So when the device will be gone, one of the first thing we 2736 * will be doing will be to unregister the interrupt handler, 2737 * and then unregister the DRM device. drm_dev_enter() would 2738 * thus always succeed if we are here. 2739 */ 2740 2741 vc4_hdmi->cec_rx_msg.len = 0; 2742 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1); 2743 vc4_cec_read_msg(vc4_hdmi, cntrl1); 2744 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 2745 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 2746 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 2747 2748 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 2749 2750 return IRQ_WAKE_THREAD; 2751 } 2752 2753 static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv) 2754 { 2755 struct vc4_hdmi *vc4_hdmi = priv; 2756 irqreturn_t ret; 2757 2758 spin_lock(&vc4_hdmi->hw_lock); 2759 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi); 2760 spin_unlock(&vc4_hdmi->hw_lock); 2761 2762 return ret; 2763 } 2764 2765 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv) 2766 { 2767 struct vc4_hdmi *vc4_hdmi = priv; 2768 u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS); 2769 irqreturn_t ret; 2770 u32 cntrl5; 2771 2772 /* 2773 * We don't need to protect the register access using 2774 * drm_dev_enter() there because the interrupt handler lifetime 2775 * is tied to the device itself, and not to the DRM device. 2776 * 2777 * So when the device will be gone, one of the first thing we 2778 * will be doing will be to unregister the interrupt handler, 2779 * and then unregister the DRM device. drm_dev_enter() would 2780 * thus always succeed if we are here. 2781 */ 2782 2783 if (!(stat & VC4_HDMI_CPU_CEC)) 2784 return IRQ_NONE; 2785 2786 spin_lock(&vc4_hdmi->hw_lock); 2787 cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5); 2788 vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT; 2789 if (vc4_hdmi->cec_irq_was_rx) 2790 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi); 2791 else 2792 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi); 2793 2794 HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC); 2795 spin_unlock(&vc4_hdmi->hw_lock); 2796 2797 return ret; 2798 } 2799 2800 static int vc4_hdmi_cec_enable(struct cec_adapter *adap) 2801 { 2802 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 2803 struct drm_device *drm = vc4_hdmi->connector.dev; 2804 /* clock period in microseconds */ 2805 const u32 usecs = 1000000 / CEC_CLOCK_FREQ; 2806 unsigned long flags; 2807 u32 val; 2808 int ret; 2809 int idx; 2810 2811 if (!drm_dev_enter(drm, &idx)) 2812 /* 2813 * We can't return an error code, because the CEC 2814 * framework will emit WARN_ON messages at unbind 2815 * otherwise. 2816 */ 2817 return 0; 2818 2819 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev); 2820 if (ret) { 2821 drm_dev_exit(idx); 2822 return ret; 2823 } 2824 2825 mutex_lock(&vc4_hdmi->mutex); 2826 2827 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2828 2829 val = HDMI_READ(HDMI_CEC_CNTRL_5); 2830 val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET | 2831 VC4_HDMI_CEC_CNT_TO_4700_US_MASK | 2832 VC4_HDMI_CEC_CNT_TO_4500_US_MASK); 2833 val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) | 2834 ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT); 2835 2836 HDMI_WRITE(HDMI_CEC_CNTRL_5, val | 2837 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 2838 HDMI_WRITE(HDMI_CEC_CNTRL_5, val); 2839 HDMI_WRITE(HDMI_CEC_CNTRL_2, 2840 ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) | 2841 ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) | 2842 ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) | 2843 ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) | 2844 ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT)); 2845 HDMI_WRITE(HDMI_CEC_CNTRL_3, 2846 ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) | 2847 ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) | 2848 ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) | 2849 ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT)); 2850 HDMI_WRITE(HDMI_CEC_CNTRL_4, 2851 ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) | 2852 ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) | 2853 ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) | 2854 ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT)); 2855 2856 if (!vc4_hdmi->variant->external_irq_controller) 2857 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC); 2858 2859 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2860 2861 mutex_unlock(&vc4_hdmi->mutex); 2862 drm_dev_exit(idx); 2863 2864 return 0; 2865 } 2866 2867 static int vc4_hdmi_cec_disable(struct cec_adapter *adap) 2868 { 2869 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 2870 struct drm_device *drm = vc4_hdmi->connector.dev; 2871 unsigned long flags; 2872 int idx; 2873 2874 if (!drm_dev_enter(drm, &idx)) 2875 /* 2876 * We can't return an error code, because the CEC 2877 * framework will emit WARN_ON messages at unbind 2878 * otherwise. 2879 */ 2880 return 0; 2881 2882 mutex_lock(&vc4_hdmi->mutex); 2883 2884 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2885 2886 if (!vc4_hdmi->variant->external_irq_controller) 2887 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC); 2888 2889 HDMI_WRITE(HDMI_CEC_CNTRL_5, HDMI_READ(HDMI_CEC_CNTRL_5) | 2890 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 2891 2892 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2893 2894 mutex_unlock(&vc4_hdmi->mutex); 2895 2896 pm_runtime_put(&vc4_hdmi->pdev->dev); 2897 2898 drm_dev_exit(idx); 2899 2900 return 0; 2901 } 2902 2903 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable) 2904 { 2905 if (enable) 2906 return vc4_hdmi_cec_enable(adap); 2907 else 2908 return vc4_hdmi_cec_disable(adap); 2909 } 2910 2911 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr) 2912 { 2913 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 2914 struct drm_device *drm = vc4_hdmi->connector.dev; 2915 unsigned long flags; 2916 int idx; 2917 2918 if (!drm_dev_enter(drm, &idx)) 2919 /* 2920 * We can't return an error code, because the CEC 2921 * framework will emit WARN_ON messages at unbind 2922 * otherwise. 2923 */ 2924 return 0; 2925 2926 mutex_lock(&vc4_hdmi->mutex); 2927 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2928 HDMI_WRITE(HDMI_CEC_CNTRL_1, 2929 (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) | 2930 (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT); 2931 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2932 mutex_unlock(&vc4_hdmi->mutex); 2933 2934 drm_dev_exit(idx); 2935 2936 return 0; 2937 } 2938 2939 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts, 2940 u32 signal_free_time, struct cec_msg *msg) 2941 { 2942 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 2943 struct drm_device *dev = vc4_hdmi->connector.dev; 2944 unsigned long flags; 2945 u32 val; 2946 unsigned int i; 2947 int idx; 2948 2949 if (!drm_dev_enter(dev, &idx)) 2950 return -ENODEV; 2951 2952 if (msg->len > 16) { 2953 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len); 2954 drm_dev_exit(idx); 2955 return -ENOMEM; 2956 } 2957 2958 mutex_lock(&vc4_hdmi->mutex); 2959 2960 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2961 2962 for (i = 0; i < msg->len; i += 4) 2963 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2), 2964 (msg->msg[i]) | 2965 (msg->msg[i + 1] << 8) | 2966 (msg->msg[i + 2] << 16) | 2967 (msg->msg[i + 3] << 24)); 2968 2969 val = HDMI_READ(HDMI_CEC_CNTRL_1); 2970 val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 2971 HDMI_WRITE(HDMI_CEC_CNTRL_1, val); 2972 val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK; 2973 val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT; 2974 val |= VC4_HDMI_CEC_START_XMIT_BEGIN; 2975 2976 HDMI_WRITE(HDMI_CEC_CNTRL_1, val); 2977 2978 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2979 mutex_unlock(&vc4_hdmi->mutex); 2980 drm_dev_exit(idx); 2981 2982 return 0; 2983 } 2984 2985 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = { 2986 .adap_enable = vc4_hdmi_cec_adap_enable, 2987 .adap_log_addr = vc4_hdmi_cec_adap_log_addr, 2988 .adap_transmit = vc4_hdmi_cec_adap_transmit, 2989 }; 2990 2991 static void vc4_hdmi_cec_release(void *ptr) 2992 { 2993 struct vc4_hdmi *vc4_hdmi = ptr; 2994 2995 cec_unregister_adapter(vc4_hdmi->cec_adap); 2996 vc4_hdmi->cec_adap = NULL; 2997 } 2998 2999 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi) 3000 { 3001 struct cec_connector_info conn_info; 3002 struct platform_device *pdev = vc4_hdmi->pdev; 3003 struct device *dev = &pdev->dev; 3004 int ret; 3005 3006 if (!of_find_property(dev->of_node, "interrupts", NULL)) { 3007 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n"); 3008 return 0; 3009 } 3010 3011 vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops, 3012 vc4_hdmi, "vc4", 3013 CEC_CAP_DEFAULTS | 3014 CEC_CAP_CONNECTOR_INFO, 1); 3015 ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap); 3016 if (ret < 0) 3017 return ret; 3018 3019 cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector); 3020 cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info); 3021 3022 if (vc4_hdmi->variant->external_irq_controller) { 3023 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-rx"), 3024 vc4_cec_irq_handler_rx_bare, 3025 vc4_cec_irq_handler_rx_thread, 0, 3026 "vc4 hdmi cec rx", vc4_hdmi); 3027 if (ret) 3028 goto err_delete_cec_adap; 3029 3030 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-tx"), 3031 vc4_cec_irq_handler_tx_bare, 3032 vc4_cec_irq_handler_tx_thread, 0, 3033 "vc4 hdmi cec tx", vc4_hdmi); 3034 if (ret) 3035 goto err_delete_cec_adap; 3036 } else { 3037 ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0), 3038 vc4_cec_irq_handler, 3039 vc4_cec_irq_handler_thread, 0, 3040 "vc4 hdmi cec", vc4_hdmi); 3041 if (ret) 3042 goto err_delete_cec_adap; 3043 } 3044 3045 ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev); 3046 if (ret < 0) 3047 goto err_delete_cec_adap; 3048 3049 /* 3050 * NOTE: Strictly speaking, we should probably use a DRM-managed 3051 * registration there to avoid removing the CEC adapter by the 3052 * time the DRM driver doesn't have any user anymore. 3053 * 3054 * However, the CEC framework already cleans up the CEC adapter 3055 * only when the last user has closed its file descriptor, so we 3056 * don't need to handle it in DRM. 3057 * 3058 * By the time the device-managed hook is executed, we will give 3059 * up our reference to the CEC adapter and therefore don't 3060 * really care when it's actually freed. 3061 * 3062 * There's still a problematic sequence: if we unregister our 3063 * CEC adapter, but the userspace keeps a handle on the CEC 3064 * adapter but not the DRM device for some reason. In such a 3065 * case, our vc4_hdmi structure will be freed, but the 3066 * cec_adapter structure will have a dangling pointer to what 3067 * used to be our HDMI controller. If we get a CEC call at that 3068 * moment, we could end up with a use-after-free. Fortunately, 3069 * the CEC framework already handles this too, by calling 3070 * cec_is_registered() in cec_ioctl() and cec_poll(). 3071 */ 3072 ret = devm_add_action_or_reset(dev, vc4_hdmi_cec_release, vc4_hdmi); 3073 if (ret) 3074 return ret; 3075 3076 return 0; 3077 3078 err_delete_cec_adap: 3079 cec_delete_adapter(vc4_hdmi->cec_adap); 3080 3081 return ret; 3082 } 3083 #else 3084 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi) 3085 { 3086 return 0; 3087 } 3088 #endif 3089 3090 static void vc4_hdmi_free_regset(struct drm_device *drm, void *ptr) 3091 { 3092 struct debugfs_reg32 *regs = ptr; 3093 3094 kfree(regs); 3095 } 3096 3097 static int vc4_hdmi_build_regset(struct drm_device *drm, 3098 struct vc4_hdmi *vc4_hdmi, 3099 struct debugfs_regset32 *regset, 3100 enum vc4_hdmi_regs reg) 3101 { 3102 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant; 3103 struct debugfs_reg32 *regs, *new_regs; 3104 unsigned int count = 0; 3105 unsigned int i; 3106 int ret; 3107 3108 regs = kcalloc(variant->num_registers, sizeof(*regs), 3109 GFP_KERNEL); 3110 if (!regs) 3111 return -ENOMEM; 3112 3113 for (i = 0; i < variant->num_registers; i++) { 3114 const struct vc4_hdmi_register *field = &variant->registers[i]; 3115 3116 if (field->reg != reg) 3117 continue; 3118 3119 regs[count].name = field->name; 3120 regs[count].offset = field->offset; 3121 count++; 3122 } 3123 3124 new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL); 3125 if (!new_regs) 3126 return -ENOMEM; 3127 3128 regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg); 3129 regset->regs = new_regs; 3130 regset->nregs = count; 3131 3132 ret = drmm_add_action_or_reset(drm, vc4_hdmi_free_regset, new_regs); 3133 if (ret) 3134 return ret; 3135 3136 return 0; 3137 } 3138 3139 static int vc4_hdmi_init_resources(struct drm_device *drm, 3140 struct vc4_hdmi *vc4_hdmi) 3141 { 3142 struct platform_device *pdev = vc4_hdmi->pdev; 3143 struct device *dev = &pdev->dev; 3144 int ret; 3145 3146 vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0); 3147 if (IS_ERR(vc4_hdmi->hdmicore_regs)) 3148 return PTR_ERR(vc4_hdmi->hdmicore_regs); 3149 3150 vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1); 3151 if (IS_ERR(vc4_hdmi->hd_regs)) 3152 return PTR_ERR(vc4_hdmi->hd_regs); 3153 3154 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD); 3155 if (ret) 3156 return ret; 3157 3158 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI); 3159 if (ret) 3160 return ret; 3161 3162 vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel"); 3163 if (IS_ERR(vc4_hdmi->pixel_clock)) { 3164 ret = PTR_ERR(vc4_hdmi->pixel_clock); 3165 if (ret != -EPROBE_DEFER) 3166 DRM_ERROR("Failed to get pixel clock\n"); 3167 return ret; 3168 } 3169 3170 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); 3171 if (IS_ERR(vc4_hdmi->hsm_clock)) { 3172 DRM_ERROR("Failed to get HDMI state machine clock\n"); 3173 return PTR_ERR(vc4_hdmi->hsm_clock); 3174 } 3175 3176 vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock; 3177 vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock; 3178 3179 vc4_hdmi->hsm_rpm_clock = devm_clk_get(dev, "hdmi"); 3180 if (IS_ERR(vc4_hdmi->hsm_rpm_clock)) { 3181 DRM_ERROR("Failed to get HDMI state machine clock\n"); 3182 return PTR_ERR(vc4_hdmi->hsm_rpm_clock); 3183 } 3184 3185 return 0; 3186 } 3187 3188 static int vc5_hdmi_init_resources(struct drm_device *drm, 3189 struct vc4_hdmi *vc4_hdmi) 3190 { 3191 struct platform_device *pdev = vc4_hdmi->pdev; 3192 struct device *dev = &pdev->dev; 3193 struct resource *res; 3194 int ret; 3195 3196 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi"); 3197 if (!res) 3198 return -ENODEV; 3199 3200 vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start, 3201 resource_size(res)); 3202 if (!vc4_hdmi->hdmicore_regs) 3203 return -ENOMEM; 3204 3205 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd"); 3206 if (!res) 3207 return -ENODEV; 3208 3209 vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res)); 3210 if (!vc4_hdmi->hd_regs) 3211 return -ENOMEM; 3212 3213 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec"); 3214 if (!res) 3215 return -ENODEV; 3216 3217 vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res)); 3218 if (!vc4_hdmi->cec_regs) 3219 return -ENOMEM; 3220 3221 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc"); 3222 if (!res) 3223 return -ENODEV; 3224 3225 vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res)); 3226 if (!vc4_hdmi->csc_regs) 3227 return -ENOMEM; 3228 3229 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp"); 3230 if (!res) 3231 return -ENODEV; 3232 3233 vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res)); 3234 if (!vc4_hdmi->dvp_regs) 3235 return -ENOMEM; 3236 3237 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy"); 3238 if (!res) 3239 return -ENODEV; 3240 3241 vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res)); 3242 if (!vc4_hdmi->phy_regs) 3243 return -ENOMEM; 3244 3245 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet"); 3246 if (!res) 3247 return -ENODEV; 3248 3249 vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res)); 3250 if (!vc4_hdmi->ram_regs) 3251 return -ENOMEM; 3252 3253 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm"); 3254 if (!res) 3255 return -ENODEV; 3256 3257 vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res)); 3258 if (!vc4_hdmi->rm_regs) 3259 return -ENOMEM; 3260 3261 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); 3262 if (IS_ERR(vc4_hdmi->hsm_clock)) { 3263 DRM_ERROR("Failed to get HDMI state machine clock\n"); 3264 return PTR_ERR(vc4_hdmi->hsm_clock); 3265 } 3266 3267 vc4_hdmi->hsm_rpm_clock = devm_clk_get(dev, "hdmi"); 3268 if (IS_ERR(vc4_hdmi->hsm_rpm_clock)) { 3269 DRM_ERROR("Failed to get HDMI state machine clock\n"); 3270 return PTR_ERR(vc4_hdmi->hsm_rpm_clock); 3271 } 3272 3273 vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb"); 3274 if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) { 3275 DRM_ERROR("Failed to get pixel bvb clock\n"); 3276 return PTR_ERR(vc4_hdmi->pixel_bvb_clock); 3277 } 3278 3279 vc4_hdmi->audio_clock = devm_clk_get(dev, "audio"); 3280 if (IS_ERR(vc4_hdmi->audio_clock)) { 3281 DRM_ERROR("Failed to get audio clock\n"); 3282 return PTR_ERR(vc4_hdmi->audio_clock); 3283 } 3284 3285 vc4_hdmi->cec_clock = devm_clk_get(dev, "cec"); 3286 if (IS_ERR(vc4_hdmi->cec_clock)) { 3287 DRM_ERROR("Failed to get CEC clock\n"); 3288 return PTR_ERR(vc4_hdmi->cec_clock); 3289 } 3290 3291 vc4_hdmi->reset = devm_reset_control_get(dev, NULL); 3292 if (IS_ERR(vc4_hdmi->reset)) { 3293 DRM_ERROR("Failed to get HDMI reset line\n"); 3294 return PTR_ERR(vc4_hdmi->reset); 3295 } 3296 3297 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI); 3298 if (ret) 3299 return ret; 3300 3301 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD); 3302 if (ret) 3303 return ret; 3304 3305 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->cec_regset, VC5_CEC); 3306 if (ret) 3307 return ret; 3308 3309 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->csc_regset, VC5_CSC); 3310 if (ret) 3311 return ret; 3312 3313 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->dvp_regset, VC5_DVP); 3314 if (ret) 3315 return ret; 3316 3317 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->phy_regset, VC5_PHY); 3318 if (ret) 3319 return ret; 3320 3321 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->ram_regset, VC5_RAM); 3322 if (ret) 3323 return ret; 3324 3325 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->rm_regset, VC5_RM); 3326 if (ret) 3327 return ret; 3328 3329 return 0; 3330 } 3331 3332 static int vc4_hdmi_runtime_suspend(struct device *dev) 3333 { 3334 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 3335 3336 clk_disable_unprepare(vc4_hdmi->hsm_rpm_clock); 3337 3338 return 0; 3339 } 3340 3341 static int vc4_hdmi_runtime_resume(struct device *dev) 3342 { 3343 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 3344 unsigned long __maybe_unused flags; 3345 u32 __maybe_unused value; 3346 unsigned long rate; 3347 int ret; 3348 3349 /* 3350 * The HSM clock is in the HDMI power domain, so we need to set 3351 * its frequency while the power domain is active so that it 3352 * keeps its rate. 3353 */ 3354 ret = clk_set_min_rate(vc4_hdmi->hsm_rpm_clock, HSM_MIN_CLOCK_FREQ); 3355 if (ret) 3356 return ret; 3357 3358 ret = clk_prepare_enable(vc4_hdmi->hsm_rpm_clock); 3359 if (ret) 3360 return ret; 3361 3362 /* 3363 * Whenever the RaspberryPi boots without an HDMI monitor 3364 * plugged in, the firmware won't have initialized the HSM clock 3365 * rate and it will be reported as 0. 3366 * 3367 * If we try to access a register of the controller in such a 3368 * case, it will lead to a silent CPU stall. Let's make sure we 3369 * prevent such a case. 3370 */ 3371 rate = clk_get_rate(vc4_hdmi->hsm_rpm_clock); 3372 if (!rate) { 3373 ret = -EINVAL; 3374 goto err_disable_clk; 3375 } 3376 3377 if (vc4_hdmi->variant->reset) 3378 vc4_hdmi->variant->reset(vc4_hdmi); 3379 3380 #ifdef CONFIG_DRM_VC4_HDMI_CEC 3381 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 3382 value = HDMI_READ(HDMI_CEC_CNTRL_1); 3383 /* Set the logical address to Unregistered */ 3384 value |= VC4_HDMI_CEC_ADDR_MASK; 3385 HDMI_WRITE(HDMI_CEC_CNTRL_1, value); 3386 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 3387 3388 vc4_hdmi_cec_update_clk_div(vc4_hdmi); 3389 3390 if (!vc4_hdmi->variant->external_irq_controller) { 3391 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 3392 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff); 3393 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 3394 } 3395 #endif 3396 3397 return 0; 3398 3399 err_disable_clk: 3400 clk_disable_unprepare(vc4_hdmi->hsm_clock); 3401 return ret; 3402 } 3403 3404 static void vc4_hdmi_put_ddc_device(void *ptr) 3405 { 3406 struct vc4_hdmi *vc4_hdmi = ptr; 3407 3408 put_device(&vc4_hdmi->ddc->dev); 3409 } 3410 3411 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data) 3412 { 3413 const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev); 3414 struct platform_device *pdev = to_platform_device(dev); 3415 struct drm_device *drm = dev_get_drvdata(master); 3416 struct vc4_hdmi *vc4_hdmi; 3417 struct drm_encoder *encoder; 3418 struct device_node *ddc_node; 3419 int ret; 3420 3421 vc4_hdmi = drmm_kzalloc(drm, sizeof(*vc4_hdmi), GFP_KERNEL); 3422 if (!vc4_hdmi) 3423 return -ENOMEM; 3424 3425 ret = drmm_mutex_init(drm, &vc4_hdmi->mutex); 3426 if (ret) 3427 return ret; 3428 3429 spin_lock_init(&vc4_hdmi->hw_lock); 3430 INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq); 3431 3432 dev_set_drvdata(dev, vc4_hdmi); 3433 encoder = &vc4_hdmi->encoder.base; 3434 vc4_hdmi->encoder.type = variant->encoder_type; 3435 vc4_hdmi->encoder.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure; 3436 vc4_hdmi->encoder.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable; 3437 vc4_hdmi->encoder.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable; 3438 vc4_hdmi->encoder.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable; 3439 vc4_hdmi->encoder.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown; 3440 vc4_hdmi->pdev = pdev; 3441 vc4_hdmi->variant = variant; 3442 3443 /* 3444 * Since we don't know the state of the controller and its 3445 * display (if any), let's assume it's always enabled. 3446 * vc4_hdmi_disable_scrambling() will thus run at boot, make 3447 * sure it's disabled, and avoid any inconsistency. 3448 */ 3449 if (variant->max_pixel_clock > HDMI_14_MAX_TMDS_CLK) 3450 vc4_hdmi->scdc_enabled = true; 3451 3452 ret = variant->init_resources(drm, vc4_hdmi); 3453 if (ret) 3454 return ret; 3455 3456 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0); 3457 if (!ddc_node) { 3458 DRM_ERROR("Failed to find ddc node in device tree\n"); 3459 return -ENODEV; 3460 } 3461 3462 vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node); 3463 of_node_put(ddc_node); 3464 if (!vc4_hdmi->ddc) { 3465 DRM_DEBUG("Failed to get ddc i2c adapter by node\n"); 3466 return -EPROBE_DEFER; 3467 } 3468 3469 ret = devm_add_action_or_reset(dev, vc4_hdmi_put_ddc_device, vc4_hdmi); 3470 if (ret) 3471 return ret; 3472 3473 /* Only use the GPIO HPD pin if present in the DT, otherwise 3474 * we'll use the HDMI core's register. 3475 */ 3476 vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN); 3477 if (IS_ERR(vc4_hdmi->hpd_gpio)) { 3478 return PTR_ERR(vc4_hdmi->hpd_gpio); 3479 } 3480 3481 vc4_hdmi->disable_wifi_frequencies = 3482 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence"); 3483 3484 if (variant->max_pixel_clock == 600000000) { 3485 struct vc4_dev *vc4 = to_vc4_dev(drm); 3486 long max_rate = clk_round_rate(vc4->hvs->core_clk, 550000000); 3487 3488 if (max_rate < 550000000) 3489 vc4_hdmi->disable_4kp60 = true; 3490 } 3491 3492 ret = devm_pm_runtime_enable(dev); 3493 if (ret) 3494 return ret; 3495 3496 /* 3497 * We need to have the device powered up at this point to call 3498 * our reset hook and for the CEC init. 3499 */ 3500 ret = pm_runtime_resume_and_get(dev); 3501 if (ret) 3502 return ret; 3503 3504 if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") || 3505 of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1")) && 3506 HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) { 3507 clk_prepare_enable(vc4_hdmi->pixel_clock); 3508 clk_prepare_enable(vc4_hdmi->hsm_clock); 3509 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock); 3510 } 3511 3512 ret = drmm_encoder_init(drm, encoder, 3513 &vc4_hdmi_encoder_funcs, 3514 DRM_MODE_ENCODER_TMDS, 3515 NULL); 3516 if (ret) 3517 goto err_put_runtime_pm; 3518 3519 drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs); 3520 3521 ret = vc4_hdmi_connector_init(drm, vc4_hdmi); 3522 if (ret) 3523 goto err_put_runtime_pm; 3524 3525 ret = vc4_hdmi_hotplug_init(vc4_hdmi); 3526 if (ret) 3527 goto err_put_runtime_pm; 3528 3529 ret = vc4_hdmi_cec_init(vc4_hdmi); 3530 if (ret) 3531 goto err_put_runtime_pm; 3532 3533 ret = vc4_hdmi_audio_init(vc4_hdmi); 3534 if (ret) 3535 goto err_put_runtime_pm; 3536 3537 pm_runtime_put_sync(dev); 3538 3539 return 0; 3540 3541 err_put_runtime_pm: 3542 pm_runtime_put_sync(dev); 3543 3544 return ret; 3545 } 3546 3547 static const struct component_ops vc4_hdmi_ops = { 3548 .bind = vc4_hdmi_bind, 3549 }; 3550 3551 static int vc4_hdmi_dev_probe(struct platform_device *pdev) 3552 { 3553 return component_add(&pdev->dev, &vc4_hdmi_ops); 3554 } 3555 3556 static int vc4_hdmi_dev_remove(struct platform_device *pdev) 3557 { 3558 component_del(&pdev->dev, &vc4_hdmi_ops); 3559 return 0; 3560 } 3561 3562 static const struct vc4_hdmi_variant bcm2835_variant = { 3563 .encoder_type = VC4_ENCODER_TYPE_HDMI0, 3564 .debugfs_name = "hdmi_regs", 3565 .card_name = "vc4-hdmi", 3566 .max_pixel_clock = 162000000, 3567 .registers = vc4_hdmi_fields, 3568 .num_registers = ARRAY_SIZE(vc4_hdmi_fields), 3569 3570 .init_resources = vc4_hdmi_init_resources, 3571 .csc_setup = vc4_hdmi_csc_setup, 3572 .reset = vc4_hdmi_reset, 3573 .set_timings = vc4_hdmi_set_timings, 3574 .phy_init = vc4_hdmi_phy_init, 3575 .phy_disable = vc4_hdmi_phy_disable, 3576 .phy_rng_enable = vc4_hdmi_phy_rng_enable, 3577 .phy_rng_disable = vc4_hdmi_phy_rng_disable, 3578 .channel_map = vc4_hdmi_channel_map, 3579 .supports_hdr = false, 3580 }; 3581 3582 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = { 3583 .encoder_type = VC4_ENCODER_TYPE_HDMI0, 3584 .debugfs_name = "hdmi0_regs", 3585 .card_name = "vc4-hdmi-0", 3586 .max_pixel_clock = 600000000, 3587 .registers = vc5_hdmi_hdmi0_fields, 3588 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi0_fields), 3589 .phy_lane_mapping = { 3590 PHY_LANE_0, 3591 PHY_LANE_1, 3592 PHY_LANE_2, 3593 PHY_LANE_CK, 3594 }, 3595 .unsupported_odd_h_timings = true, 3596 .external_irq_controller = true, 3597 3598 .init_resources = vc5_hdmi_init_resources, 3599 .csc_setup = vc5_hdmi_csc_setup, 3600 .reset = vc5_hdmi_reset, 3601 .set_timings = vc5_hdmi_set_timings, 3602 .phy_init = vc5_hdmi_phy_init, 3603 .phy_disable = vc5_hdmi_phy_disable, 3604 .phy_rng_enable = vc5_hdmi_phy_rng_enable, 3605 .phy_rng_disable = vc5_hdmi_phy_rng_disable, 3606 .channel_map = vc5_hdmi_channel_map, 3607 .supports_hdr = true, 3608 .hp_detect = vc5_hdmi_hp_detect, 3609 }; 3610 3611 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = { 3612 .encoder_type = VC4_ENCODER_TYPE_HDMI1, 3613 .debugfs_name = "hdmi1_regs", 3614 .card_name = "vc4-hdmi-1", 3615 .max_pixel_clock = HDMI_14_MAX_TMDS_CLK, 3616 .registers = vc5_hdmi_hdmi1_fields, 3617 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi1_fields), 3618 .phy_lane_mapping = { 3619 PHY_LANE_1, 3620 PHY_LANE_0, 3621 PHY_LANE_CK, 3622 PHY_LANE_2, 3623 }, 3624 .unsupported_odd_h_timings = true, 3625 .external_irq_controller = true, 3626 3627 .init_resources = vc5_hdmi_init_resources, 3628 .csc_setup = vc5_hdmi_csc_setup, 3629 .reset = vc5_hdmi_reset, 3630 .set_timings = vc5_hdmi_set_timings, 3631 .phy_init = vc5_hdmi_phy_init, 3632 .phy_disable = vc5_hdmi_phy_disable, 3633 .phy_rng_enable = vc5_hdmi_phy_rng_enable, 3634 .phy_rng_disable = vc5_hdmi_phy_rng_disable, 3635 .channel_map = vc5_hdmi_channel_map, 3636 .supports_hdr = true, 3637 .hp_detect = vc5_hdmi_hp_detect, 3638 }; 3639 3640 static const struct of_device_id vc4_hdmi_dt_match[] = { 3641 { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant }, 3642 { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant }, 3643 { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant }, 3644 {} 3645 }; 3646 3647 static const struct dev_pm_ops vc4_hdmi_pm_ops = { 3648 SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend, 3649 vc4_hdmi_runtime_resume, 3650 NULL) 3651 }; 3652 3653 struct platform_driver vc4_hdmi_driver = { 3654 .probe = vc4_hdmi_dev_probe, 3655 .remove = vc4_hdmi_dev_remove, 3656 .driver = { 3657 .name = "vc4_hdmi", 3658 .of_match_table = vc4_hdmi_dt_match, 3659 .pm = &vc4_hdmi_pm_ops, 3660 }, 3661 }; 3662