1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 Broadcom 4 * Copyright (c) 2014 The Linux Foundation. All rights reserved. 5 * Copyright (C) 2013 Red Hat 6 * Author: Rob Clark <robdclark@gmail.com> 7 */ 8 9 /** 10 * DOC: VC4 Falcon HDMI module 11 * 12 * The HDMI core has a state machine and a PHY. On BCM2835, most of 13 * the unit operates off of the HSM clock from CPRMAN. It also 14 * internally uses the PLLH_PIX clock for the PHY. 15 * 16 * HDMI infoframes are kept within a small packet ram, where each 17 * packet can be individually enabled for including in a frame. 18 * 19 * HDMI audio is implemented entirely within the HDMI IP block. A 20 * register in the HDMI encoder takes SPDIF frames from the DMA engine 21 * and transfers them over an internal MAI (multi-channel audio 22 * interconnect) bus to the encoder side for insertion into the video 23 * blank regions. 24 * 25 * The driver's HDMI encoder does not yet support power management. 26 * The HDMI encoder's power domain and the HSM/pixel clocks are kept 27 * continuously running, and only the HDMI logic and packet ram are 28 * powered off/on at disable/enable time. 29 * 30 * The driver does not yet support CEC control, though the HDMI 31 * encoder block has CEC support. 32 */ 33 34 #include <drm/drm_atomic_helper.h> 35 #include <drm/drm_edid.h> 36 #include <drm/drm_probe_helper.h> 37 #include <drm/drm_simple_kms_helper.h> 38 #include <drm/drm_scdc_helper.h> 39 #include <linux/clk.h> 40 #include <linux/component.h> 41 #include <linux/i2c.h> 42 #include <linux/of_address.h> 43 #include <linux/of_gpio.h> 44 #include <linux/of_platform.h> 45 #include <linux/pm_runtime.h> 46 #include <linux/rational.h> 47 #include <linux/reset.h> 48 #include <sound/dmaengine_pcm.h> 49 #include <sound/hdmi-codec.h> 50 #include <sound/pcm_drm_eld.h> 51 #include <sound/pcm_params.h> 52 #include <sound/soc.h> 53 #include "media/cec.h" 54 #include "vc4_drv.h" 55 #include "vc4_hdmi.h" 56 #include "vc4_hdmi_regs.h" 57 #include "vc4_regs.h" 58 59 #define VC5_HDMI_HORZA_HFP_SHIFT 16 60 #define VC5_HDMI_HORZA_HFP_MASK VC4_MASK(28, 16) 61 #define VC5_HDMI_HORZA_VPOS BIT(15) 62 #define VC5_HDMI_HORZA_HPOS BIT(14) 63 #define VC5_HDMI_HORZA_HAP_SHIFT 0 64 #define VC5_HDMI_HORZA_HAP_MASK VC4_MASK(13, 0) 65 66 #define VC5_HDMI_HORZB_HBP_SHIFT 16 67 #define VC5_HDMI_HORZB_HBP_MASK VC4_MASK(26, 16) 68 #define VC5_HDMI_HORZB_HSP_SHIFT 0 69 #define VC5_HDMI_HORZB_HSP_MASK VC4_MASK(10, 0) 70 71 #define VC5_HDMI_VERTA_VSP_SHIFT 24 72 #define VC5_HDMI_VERTA_VSP_MASK VC4_MASK(28, 24) 73 #define VC5_HDMI_VERTA_VFP_SHIFT 16 74 #define VC5_HDMI_VERTA_VFP_MASK VC4_MASK(22, 16) 75 #define VC5_HDMI_VERTA_VAL_SHIFT 0 76 #define VC5_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0) 77 78 #define VC5_HDMI_VERTB_VSPO_SHIFT 16 79 #define VC5_HDMI_VERTB_VSPO_MASK VC4_MASK(29, 16) 80 81 #define VC5_HDMI_SCRAMBLER_CTL_ENABLE BIT(0) 82 83 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT 8 84 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK VC4_MASK(10, 8) 85 86 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT 0 87 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK VC4_MASK(3, 0) 88 89 #define VC5_HDMI_GCP_CONFIG_GCP_ENABLE BIT(31) 90 91 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT 8 92 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK VC4_MASK(15, 8) 93 94 # define VC4_HD_M_SW_RST BIT(2) 95 # define VC4_HD_M_ENABLE BIT(0) 96 97 #define HSM_MIN_CLOCK_FREQ 120000000 98 #define CEC_CLOCK_FREQ 40000 99 100 #define HDMI_14_MAX_TMDS_CLK (340 * 1000 * 1000) 101 102 static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode) 103 { 104 return (mode->clock * 1000) > HDMI_14_MAX_TMDS_CLK; 105 } 106 107 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused) 108 { 109 struct drm_info_node *node = (struct drm_info_node *)m->private; 110 struct vc4_hdmi *vc4_hdmi = node->info_ent->data; 111 struct drm_printer p = drm_seq_file_printer(m); 112 113 drm_print_regset32(&p, &vc4_hdmi->hdmi_regset); 114 drm_print_regset32(&p, &vc4_hdmi->hd_regset); 115 116 return 0; 117 } 118 119 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi) 120 { 121 unsigned long flags; 122 123 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 124 125 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST); 126 udelay(1); 127 HDMI_WRITE(HDMI_M_CTL, 0); 128 129 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE); 130 131 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 132 VC4_HDMI_SW_RESET_HDMI | 133 VC4_HDMI_SW_RESET_FORMAT_DETECT); 134 135 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0); 136 137 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 138 } 139 140 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi) 141 { 142 unsigned long flags; 143 144 reset_control_reset(vc4_hdmi->reset); 145 146 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 147 148 HDMI_WRITE(HDMI_DVP_CTL, 0); 149 150 HDMI_WRITE(HDMI_CLOCK_STOP, 151 HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL); 152 153 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 154 } 155 156 #ifdef CONFIG_DRM_VC4_HDMI_CEC 157 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) 158 { 159 unsigned long cec_rate = clk_get_rate(vc4_hdmi->cec_clock); 160 unsigned long flags; 161 u16 clk_cnt; 162 u32 value; 163 164 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 165 166 value = HDMI_READ(HDMI_CEC_CNTRL_1); 167 value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK; 168 169 /* 170 * Set the clock divider: the hsm_clock rate and this divider 171 * setting will give a 40 kHz CEC clock. 172 */ 173 clk_cnt = cec_rate / CEC_CLOCK_FREQ; 174 value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT; 175 HDMI_WRITE(HDMI_CEC_CNTRL_1, value); 176 177 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 178 } 179 #else 180 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {} 181 #endif 182 183 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder); 184 185 static enum drm_connector_status 186 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force) 187 { 188 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 189 bool connected = false; 190 191 mutex_lock(&vc4_hdmi->mutex); 192 193 WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev)); 194 195 if (vc4_hdmi->hpd_gpio) { 196 if (gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio)) 197 connected = true; 198 } else { 199 if (vc4_hdmi->variant->hp_detect && 200 vc4_hdmi->variant->hp_detect(vc4_hdmi)) 201 connected = true; 202 } 203 204 if (connected) { 205 if (connector->status != connector_status_connected) { 206 struct edid *edid = drm_get_edid(connector, vc4_hdmi->ddc); 207 208 if (edid) { 209 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid); 210 vc4_hdmi->encoder.hdmi_monitor = drm_detect_hdmi_monitor(edid); 211 kfree(edid); 212 } 213 } 214 215 vc4_hdmi_enable_scrambling(&vc4_hdmi->encoder.base.base); 216 pm_runtime_put(&vc4_hdmi->pdev->dev); 217 mutex_unlock(&vc4_hdmi->mutex); 218 return connector_status_connected; 219 } 220 221 cec_phys_addr_invalidate(vc4_hdmi->cec_adap); 222 pm_runtime_put(&vc4_hdmi->pdev->dev); 223 mutex_unlock(&vc4_hdmi->mutex); 224 return connector_status_disconnected; 225 } 226 227 static void vc4_hdmi_connector_destroy(struct drm_connector *connector) 228 { 229 drm_connector_unregister(connector); 230 drm_connector_cleanup(connector); 231 } 232 233 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector) 234 { 235 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 236 struct vc4_hdmi_encoder *vc4_encoder = &vc4_hdmi->encoder; 237 int ret = 0; 238 struct edid *edid; 239 240 mutex_lock(&vc4_hdmi->mutex); 241 242 edid = drm_get_edid(connector, vc4_hdmi->ddc); 243 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid); 244 if (!edid) { 245 ret = -ENODEV; 246 goto out; 247 } 248 249 vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid); 250 251 drm_connector_update_edid_property(connector, edid); 252 ret = drm_add_edid_modes(connector, edid); 253 kfree(edid); 254 255 if (vc4_hdmi->disable_4kp60) { 256 struct drm_device *drm = connector->dev; 257 struct drm_display_mode *mode; 258 259 list_for_each_entry(mode, &connector->probed_modes, head) { 260 if (vc4_hdmi_mode_needs_scrambling(mode)) { 261 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz."); 262 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60."); 263 } 264 } 265 } 266 267 out: 268 mutex_unlock(&vc4_hdmi->mutex); 269 270 return ret; 271 } 272 273 static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector, 274 struct drm_atomic_state *state) 275 { 276 struct drm_connector_state *old_state = 277 drm_atomic_get_old_connector_state(state, connector); 278 struct drm_connector_state *new_state = 279 drm_atomic_get_new_connector_state(state, connector); 280 struct drm_crtc *crtc = new_state->crtc; 281 282 if (!crtc) 283 return 0; 284 285 if (old_state->colorspace != new_state->colorspace || 286 !drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) { 287 struct drm_crtc_state *crtc_state; 288 289 crtc_state = drm_atomic_get_crtc_state(state, crtc); 290 if (IS_ERR(crtc_state)) 291 return PTR_ERR(crtc_state); 292 293 crtc_state->mode_changed = true; 294 } 295 296 return 0; 297 } 298 299 static void vc4_hdmi_connector_reset(struct drm_connector *connector) 300 { 301 struct vc4_hdmi_connector_state *old_state = 302 conn_state_to_vc4_hdmi_conn_state(connector->state); 303 struct vc4_hdmi_connector_state *new_state = 304 kzalloc(sizeof(*new_state), GFP_KERNEL); 305 306 if (connector->state) 307 __drm_atomic_helper_connector_destroy_state(connector->state); 308 309 kfree(old_state); 310 __drm_atomic_helper_connector_reset(connector, &new_state->base); 311 312 if (!new_state) 313 return; 314 315 new_state->base.max_bpc = 8; 316 new_state->base.max_requested_bpc = 8; 317 drm_atomic_helper_connector_tv_reset(connector); 318 } 319 320 static struct drm_connector_state * 321 vc4_hdmi_connector_duplicate_state(struct drm_connector *connector) 322 { 323 struct drm_connector_state *conn_state = connector->state; 324 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state); 325 struct vc4_hdmi_connector_state *new_state; 326 327 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL); 328 if (!new_state) 329 return NULL; 330 331 new_state->pixel_rate = vc4_state->pixel_rate; 332 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base); 333 334 return &new_state->base; 335 } 336 337 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = { 338 .detect = vc4_hdmi_connector_detect, 339 .fill_modes = drm_helper_probe_single_connector_modes, 340 .destroy = vc4_hdmi_connector_destroy, 341 .reset = vc4_hdmi_connector_reset, 342 .atomic_duplicate_state = vc4_hdmi_connector_duplicate_state, 343 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 344 }; 345 346 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = { 347 .get_modes = vc4_hdmi_connector_get_modes, 348 .atomic_check = vc4_hdmi_connector_atomic_check, 349 }; 350 351 static int vc4_hdmi_connector_init(struct drm_device *dev, 352 struct vc4_hdmi *vc4_hdmi) 353 { 354 struct drm_connector *connector = &vc4_hdmi->connector; 355 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base; 356 int ret; 357 358 drm_connector_init_with_ddc(dev, connector, 359 &vc4_hdmi_connector_funcs, 360 DRM_MODE_CONNECTOR_HDMIA, 361 vc4_hdmi->ddc); 362 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs); 363 364 /* 365 * Some of the properties below require access to state, like bpc. 366 * Allocate some default initial connector state with our reset helper. 367 */ 368 if (connector->funcs->reset) 369 connector->funcs->reset(connector); 370 371 /* Create and attach TV margin props to this connector. */ 372 ret = drm_mode_create_tv_margin_properties(dev); 373 if (ret) 374 return ret; 375 376 ret = drm_mode_create_hdmi_colorspace_property(connector); 377 if (ret) 378 return ret; 379 380 drm_connector_attach_colorspace_property(connector); 381 drm_connector_attach_tv_margin_properties(connector); 382 drm_connector_attach_max_bpc_property(connector, 8, 12); 383 384 connector->polled = (DRM_CONNECTOR_POLL_CONNECT | 385 DRM_CONNECTOR_POLL_DISCONNECT); 386 387 connector->interlace_allowed = 1; 388 connector->doublescan_allowed = 0; 389 390 if (vc4_hdmi->variant->supports_hdr) 391 drm_connector_attach_hdr_output_metadata_property(connector); 392 393 drm_connector_attach_encoder(connector, encoder); 394 395 return 0; 396 } 397 398 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder, 399 enum hdmi_infoframe_type type, 400 bool poll) 401 { 402 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 403 u32 packet_id = type - 0x80; 404 unsigned long flags; 405 406 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 407 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 408 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id)); 409 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 410 411 if (!poll) 412 return 0; 413 414 return wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) & 415 BIT(packet_id)), 100); 416 } 417 418 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder, 419 union hdmi_infoframe *frame) 420 { 421 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 422 u32 packet_id = frame->any.type - 0x80; 423 const struct vc4_hdmi_register *ram_packet_start = 424 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START]; 425 u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id; 426 void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi, 427 ram_packet_start->reg); 428 uint8_t buffer[VC4_HDMI_PACKET_STRIDE]; 429 unsigned long flags; 430 ssize_t len, i; 431 int ret; 432 433 WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) & 434 VC4_HDMI_RAM_PACKET_ENABLE), 435 "Packet RAM has to be on to store the packet."); 436 437 len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer)); 438 if (len < 0) 439 return; 440 441 ret = vc4_hdmi_stop_packet(encoder, frame->any.type, true); 442 if (ret) { 443 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret); 444 return; 445 } 446 447 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 448 449 for (i = 0; i < len; i += 7) { 450 writel(buffer[i + 0] << 0 | 451 buffer[i + 1] << 8 | 452 buffer[i + 2] << 16, 453 base + packet_reg); 454 packet_reg += 4; 455 456 writel(buffer[i + 3] << 0 | 457 buffer[i + 4] << 8 | 458 buffer[i + 5] << 16 | 459 buffer[i + 6] << 24, 460 base + packet_reg); 461 packet_reg += 4; 462 } 463 464 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 465 HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id)); 466 467 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 468 469 ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) & 470 BIT(packet_id)), 100); 471 if (ret) 472 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret); 473 } 474 475 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder) 476 { 477 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 478 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 479 struct drm_connector *connector = &vc4_hdmi->connector; 480 struct drm_connector_state *cstate = connector->state; 481 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 482 union hdmi_infoframe frame; 483 int ret; 484 485 lockdep_assert_held(&vc4_hdmi->mutex); 486 487 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, 488 connector, mode); 489 if (ret < 0) { 490 DRM_ERROR("couldn't fill AVI infoframe\n"); 491 return; 492 } 493 494 drm_hdmi_avi_infoframe_quant_range(&frame.avi, 495 connector, mode, 496 vc4_encoder->limited_rgb_range ? 497 HDMI_QUANTIZATION_RANGE_LIMITED : 498 HDMI_QUANTIZATION_RANGE_FULL); 499 drm_hdmi_avi_infoframe_colorspace(&frame.avi, cstate); 500 drm_hdmi_avi_infoframe_bars(&frame.avi, cstate); 501 502 vc4_hdmi_write_infoframe(encoder, &frame); 503 } 504 505 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder) 506 { 507 union hdmi_infoframe frame; 508 int ret; 509 510 ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore"); 511 if (ret < 0) { 512 DRM_ERROR("couldn't fill SPD infoframe\n"); 513 return; 514 } 515 516 frame.spd.sdi = HDMI_SPD_SDI_PC; 517 518 vc4_hdmi_write_infoframe(encoder, &frame); 519 } 520 521 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder) 522 { 523 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 524 struct hdmi_audio_infoframe *audio = &vc4_hdmi->audio.infoframe; 525 union hdmi_infoframe frame; 526 527 memcpy(&frame.audio, audio, sizeof(*audio)); 528 vc4_hdmi_write_infoframe(encoder, &frame); 529 } 530 531 static void vc4_hdmi_set_hdr_infoframe(struct drm_encoder *encoder) 532 { 533 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 534 struct drm_connector *connector = &vc4_hdmi->connector; 535 struct drm_connector_state *conn_state = connector->state; 536 union hdmi_infoframe frame; 537 538 lockdep_assert_held(&vc4_hdmi->mutex); 539 540 if (!vc4_hdmi->variant->supports_hdr) 541 return; 542 543 if (!conn_state->hdr_output_metadata) 544 return; 545 546 if (drm_hdmi_infoframe_set_hdr_metadata(&frame.drm, conn_state)) 547 return; 548 549 vc4_hdmi_write_infoframe(encoder, &frame); 550 } 551 552 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder) 553 { 554 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 555 556 lockdep_assert_held(&vc4_hdmi->mutex); 557 558 vc4_hdmi_set_avi_infoframe(encoder); 559 vc4_hdmi_set_spd_infoframe(encoder); 560 /* 561 * If audio was streaming, then we need to reenabled the audio 562 * infoframe here during encoder_enable. 563 */ 564 if (vc4_hdmi->audio.streaming) 565 vc4_hdmi_set_audio_infoframe(encoder); 566 567 vc4_hdmi_set_hdr_infoframe(encoder); 568 } 569 570 static bool vc4_hdmi_supports_scrambling(struct drm_encoder *encoder, 571 struct drm_display_mode *mode) 572 { 573 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 574 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 575 struct drm_display_info *display = &vc4_hdmi->connector.display_info; 576 577 lockdep_assert_held(&vc4_hdmi->mutex); 578 579 if (!vc4_encoder->hdmi_monitor) 580 return false; 581 582 if (!display->hdmi.scdc.supported || 583 !display->hdmi.scdc.scrambling.supported) 584 return false; 585 586 return true; 587 } 588 589 #define SCRAMBLING_POLLING_DELAY_MS 1000 590 591 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder) 592 { 593 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 594 struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 595 unsigned long flags; 596 597 lockdep_assert_held(&vc4_hdmi->mutex); 598 599 if (!vc4_hdmi_supports_scrambling(encoder, mode)) 600 return; 601 602 if (!vc4_hdmi_mode_needs_scrambling(mode)) 603 return; 604 605 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true); 606 drm_scdc_set_scrambling(vc4_hdmi->ddc, true); 607 608 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 609 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) | 610 VC5_HDMI_SCRAMBLER_CTL_ENABLE); 611 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 612 613 vc4_hdmi->scdc_enabled = true; 614 615 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work, 616 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS)); 617 } 618 619 static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder) 620 { 621 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 622 unsigned long flags; 623 624 lockdep_assert_held(&vc4_hdmi->mutex); 625 626 if (!vc4_hdmi->scdc_enabled) 627 return; 628 629 vc4_hdmi->scdc_enabled = false; 630 631 if (delayed_work_pending(&vc4_hdmi->scrambling_work)) 632 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work); 633 634 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 635 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) & 636 ~VC5_HDMI_SCRAMBLER_CTL_ENABLE); 637 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 638 639 drm_scdc_set_scrambling(vc4_hdmi->ddc, false); 640 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, false); 641 } 642 643 static void vc4_hdmi_scrambling_wq(struct work_struct *work) 644 { 645 struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work), 646 struct vc4_hdmi, 647 scrambling_work); 648 649 if (drm_scdc_get_scrambling_status(vc4_hdmi->ddc)) 650 return; 651 652 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true); 653 drm_scdc_set_scrambling(vc4_hdmi->ddc, true); 654 655 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work, 656 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS)); 657 } 658 659 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder, 660 struct drm_atomic_state *state) 661 { 662 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 663 unsigned long flags; 664 665 mutex_lock(&vc4_hdmi->mutex); 666 667 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 668 669 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0); 670 671 HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB); 672 673 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 674 675 mdelay(1); 676 677 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 678 HDMI_WRITE(HDMI_VID_CTL, 679 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE); 680 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 681 682 vc4_hdmi_disable_scrambling(encoder); 683 684 mutex_unlock(&vc4_hdmi->mutex); 685 } 686 687 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder, 688 struct drm_atomic_state *state) 689 { 690 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 691 unsigned long flags; 692 int ret; 693 694 mutex_lock(&vc4_hdmi->mutex); 695 696 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 697 HDMI_WRITE(HDMI_VID_CTL, 698 HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX); 699 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 700 701 if (vc4_hdmi->variant->phy_disable) 702 vc4_hdmi->variant->phy_disable(vc4_hdmi); 703 704 clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock); 705 clk_disable_unprepare(vc4_hdmi->pixel_clock); 706 707 ret = pm_runtime_put(&vc4_hdmi->pdev->dev); 708 if (ret < 0) 709 DRM_ERROR("Failed to release power domain: %d\n", ret); 710 711 mutex_unlock(&vc4_hdmi->mutex); 712 } 713 714 static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder) 715 { 716 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 717 718 mutex_lock(&vc4_hdmi->mutex); 719 vc4_hdmi->output_enabled = false; 720 mutex_unlock(&vc4_hdmi->mutex); 721 } 722 723 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable) 724 { 725 unsigned long flags; 726 u32 csc_ctl; 727 728 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 729 730 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR, 731 VC4_HD_CSC_CTL_ORDER); 732 733 if (enable) { 734 /* CEA VICs other than #1 requre limited range RGB 735 * output unless overridden by an AVI infoframe. 736 * Apply a colorspace conversion to squash 0-255 down 737 * to 16-235. The matrix here is: 738 * 739 * [ 0 0 0.8594 16] 740 * [ 0 0.8594 0 16] 741 * [ 0.8594 0 0 16] 742 * [ 0 0 0 1] 743 */ 744 csc_ctl |= VC4_HD_CSC_CTL_ENABLE; 745 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC; 746 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM, 747 VC4_HD_CSC_CTL_MODE); 748 749 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000); 750 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0); 751 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000); 752 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000); 753 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0); 754 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000); 755 } 756 757 /* The RGB order applies even when CSC is disabled. */ 758 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl); 759 760 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 761 } 762 763 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable) 764 { 765 unsigned long flags; 766 u32 csc_ctl; 767 768 csc_ctl = 0x07; /* RGB_CONVERT_MODE = custom matrix, || USE_RGB_TO_YCBCR */ 769 770 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 771 772 if (enable) { 773 /* CEA VICs other than #1 requre limited range RGB 774 * output unless overridden by an AVI infoframe. 775 * Apply a colorspace conversion to squash 0-255 down 776 * to 16-235. The matrix here is: 777 * 778 * [ 0.8594 0 0 16] 779 * [ 0 0.8594 0 16] 780 * [ 0 0 0.8594 16] 781 * [ 0 0 0 1] 782 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets 783 */ 784 HDMI_WRITE(HDMI_CSC_12_11, (0x0000 << 16) | 0x1b80); 785 HDMI_WRITE(HDMI_CSC_14_13, (0x0400 << 16) | 0x0000); 786 HDMI_WRITE(HDMI_CSC_22_21, (0x1b80 << 16) | 0x0000); 787 HDMI_WRITE(HDMI_CSC_24_23, (0x0400 << 16) | 0x0000); 788 HDMI_WRITE(HDMI_CSC_32_31, (0x0000 << 16) | 0x0000); 789 HDMI_WRITE(HDMI_CSC_34_33, (0x0400 << 16) | 0x1b80); 790 } else { 791 /* Still use the matrix for full range, but make it unity. 792 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets 793 */ 794 HDMI_WRITE(HDMI_CSC_12_11, (0x0000 << 16) | 0x2000); 795 HDMI_WRITE(HDMI_CSC_14_13, (0x0000 << 16) | 0x0000); 796 HDMI_WRITE(HDMI_CSC_22_21, (0x2000 << 16) | 0x0000); 797 HDMI_WRITE(HDMI_CSC_24_23, (0x0000 << 16) | 0x0000); 798 HDMI_WRITE(HDMI_CSC_32_31, (0x0000 << 16) | 0x0000); 799 HDMI_WRITE(HDMI_CSC_34_33, (0x0000 << 16) | 0x2000); 800 } 801 802 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl); 803 804 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 805 } 806 807 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi, 808 struct drm_connector_state *state, 809 struct drm_display_mode *mode) 810 { 811 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 812 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 813 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 814 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 815 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 816 VC4_HDMI_VERTA_VSP) | 817 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 818 VC4_HDMI_VERTA_VFP) | 819 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL)); 820 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 821 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end, 822 VC4_HDMI_VERTB_VBP)); 823 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 824 VC4_SET_FIELD(mode->crtc_vtotal - 825 mode->crtc_vsync_end - 826 interlaced, 827 VC4_HDMI_VERTB_VBP)); 828 unsigned long flags; 829 830 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 831 832 HDMI_WRITE(HDMI_HORZA, 833 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) | 834 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) | 835 VC4_SET_FIELD(mode->hdisplay * pixel_rep, 836 VC4_HDMI_HORZA_HAP)); 837 838 HDMI_WRITE(HDMI_HORZB, 839 VC4_SET_FIELD((mode->htotal - 840 mode->hsync_end) * pixel_rep, 841 VC4_HDMI_HORZB_HBP) | 842 VC4_SET_FIELD((mode->hsync_end - 843 mode->hsync_start) * pixel_rep, 844 VC4_HDMI_HORZB_HSP) | 845 VC4_SET_FIELD((mode->hsync_start - 846 mode->hdisplay) * pixel_rep, 847 VC4_HDMI_HORZB_HFP)); 848 849 HDMI_WRITE(HDMI_VERTA0, verta); 850 HDMI_WRITE(HDMI_VERTA1, verta); 851 852 HDMI_WRITE(HDMI_VERTB0, vertb_even); 853 HDMI_WRITE(HDMI_VERTB1, vertb); 854 855 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 856 } 857 858 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi, 859 struct drm_connector_state *state, 860 struct drm_display_mode *mode) 861 { 862 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 863 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 864 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 865 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 866 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 867 VC5_HDMI_VERTA_VSP) | 868 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 869 VC5_HDMI_VERTA_VFP) | 870 VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL)); 871 u32 vertb = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) | 872 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end, 873 VC4_HDMI_VERTB_VBP)); 874 u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) | 875 VC4_SET_FIELD(mode->crtc_vtotal - 876 mode->crtc_vsync_end - 877 interlaced, 878 VC4_HDMI_VERTB_VBP)); 879 unsigned long flags; 880 unsigned char gcp; 881 bool gcp_en; 882 u32 reg; 883 884 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 885 886 HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, 0x354021); 887 HDMI_WRITE(HDMI_HORZA, 888 (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) | 889 (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) | 890 VC4_SET_FIELD(mode->hdisplay * pixel_rep, 891 VC5_HDMI_HORZA_HAP) | 892 VC4_SET_FIELD((mode->hsync_start - 893 mode->hdisplay) * pixel_rep, 894 VC5_HDMI_HORZA_HFP)); 895 896 HDMI_WRITE(HDMI_HORZB, 897 VC4_SET_FIELD((mode->htotal - 898 mode->hsync_end) * pixel_rep, 899 VC5_HDMI_HORZB_HBP) | 900 VC4_SET_FIELD((mode->hsync_end - 901 mode->hsync_start) * pixel_rep, 902 VC5_HDMI_HORZB_HSP)); 903 904 HDMI_WRITE(HDMI_VERTA0, verta); 905 HDMI_WRITE(HDMI_VERTA1, verta); 906 907 HDMI_WRITE(HDMI_VERTB0, vertb_even); 908 HDMI_WRITE(HDMI_VERTB1, vertb); 909 910 switch (state->max_bpc) { 911 case 12: 912 gcp = 6; 913 gcp_en = true; 914 break; 915 case 10: 916 gcp = 5; 917 gcp_en = true; 918 break; 919 case 8: 920 default: 921 gcp = 4; 922 gcp_en = false; 923 break; 924 } 925 926 reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1); 927 reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK | 928 VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK); 929 reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) | 930 VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH); 931 HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg); 932 933 reg = HDMI_READ(HDMI_GCP_WORD_1); 934 reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK; 935 reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1); 936 HDMI_WRITE(HDMI_GCP_WORD_1, reg); 937 938 reg = HDMI_READ(HDMI_GCP_CONFIG); 939 reg &= ~VC5_HDMI_GCP_CONFIG_GCP_ENABLE; 940 reg |= gcp_en ? VC5_HDMI_GCP_CONFIG_GCP_ENABLE : 0; 941 HDMI_WRITE(HDMI_GCP_CONFIG, reg); 942 943 HDMI_WRITE(HDMI_CLOCK_STOP, 0); 944 945 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 946 } 947 948 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi) 949 { 950 unsigned long flags; 951 u32 drift; 952 int ret; 953 954 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 955 956 drift = HDMI_READ(HDMI_FIFO_CTL); 957 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK; 958 959 HDMI_WRITE(HDMI_FIFO_CTL, 960 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 961 HDMI_WRITE(HDMI_FIFO_CTL, 962 drift | VC4_HDMI_FIFO_CTL_RECENTER); 963 964 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 965 966 usleep_range(1000, 1100); 967 968 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 969 970 HDMI_WRITE(HDMI_FIFO_CTL, 971 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 972 HDMI_WRITE(HDMI_FIFO_CTL, 973 drift | VC4_HDMI_FIFO_CTL_RECENTER); 974 975 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 976 977 ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) & 978 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1); 979 WARN_ONCE(ret, "Timeout waiting for " 980 "VC4_HDMI_FIFO_CTL_RECENTER_DONE"); 981 } 982 983 static struct drm_connector_state * 984 vc4_hdmi_encoder_get_connector_state(struct drm_encoder *encoder, 985 struct drm_atomic_state *state) 986 { 987 struct drm_connector_state *conn_state; 988 struct drm_connector *connector; 989 unsigned int i; 990 991 for_each_new_connector_in_state(state, connector, conn_state, i) { 992 if (conn_state->best_encoder == encoder) 993 return conn_state; 994 } 995 996 return NULL; 997 } 998 999 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder, 1000 struct drm_atomic_state *state) 1001 { 1002 struct drm_connector_state *conn_state = 1003 vc4_hdmi_encoder_get_connector_state(encoder, state); 1004 struct vc4_hdmi_connector_state *vc4_conn_state = 1005 conn_state_to_vc4_hdmi_conn_state(conn_state); 1006 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1007 struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1008 unsigned long pixel_rate = vc4_conn_state->pixel_rate; 1009 unsigned long bvb_rate, hsm_rate; 1010 unsigned long flags; 1011 int ret; 1012 1013 mutex_lock(&vc4_hdmi->mutex); 1014 1015 /* 1016 * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must 1017 * be faster than pixel clock, infinitesimally faster, tested in 1018 * simulation. Otherwise, exact value is unimportant for HDMI 1019 * operation." This conflicts with bcm2835's vc4 documentation, which 1020 * states HSM's clock has to be at least 108% of the pixel clock. 1021 * 1022 * Real life tests reveal that vc4's firmware statement holds up, and 1023 * users are able to use pixel clocks closer to HSM's, namely for 1024 * 1920x1200@60Hz. So it was decided to have leave a 1% margin between 1025 * both clocks. Which, for RPi0-3 implies a maximum pixel clock of 1026 * 162MHz. 1027 * 1028 * Additionally, the AXI clock needs to be at least 25% of 1029 * pixel clock, but HSM ends up being the limiting factor. 1030 */ 1031 hsm_rate = max_t(unsigned long, 120000000, (pixel_rate / 100) * 101); 1032 ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate); 1033 if (ret) { 1034 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret); 1035 goto out; 1036 } 1037 1038 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev); 1039 if (ret < 0) { 1040 DRM_ERROR("Failed to retain power domain: %d\n", ret); 1041 goto out; 1042 } 1043 1044 ret = clk_set_rate(vc4_hdmi->pixel_clock, pixel_rate); 1045 if (ret) { 1046 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret); 1047 goto err_put_runtime_pm; 1048 } 1049 1050 ret = clk_prepare_enable(vc4_hdmi->pixel_clock); 1051 if (ret) { 1052 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret); 1053 goto err_put_runtime_pm; 1054 } 1055 1056 1057 vc4_hdmi_cec_update_clk_div(vc4_hdmi); 1058 1059 if (pixel_rate > 297000000) 1060 bvb_rate = 300000000; 1061 else if (pixel_rate > 148500000) 1062 bvb_rate = 150000000; 1063 else 1064 bvb_rate = 75000000; 1065 1066 ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate); 1067 if (ret) { 1068 DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret); 1069 goto err_disable_pixel_clock; 1070 } 1071 1072 ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock); 1073 if (ret) { 1074 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret); 1075 goto err_disable_pixel_clock; 1076 } 1077 1078 if (vc4_hdmi->variant->phy_init) 1079 vc4_hdmi->variant->phy_init(vc4_hdmi, vc4_conn_state); 1080 1081 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1082 1083 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1084 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 1085 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT | 1086 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS); 1087 1088 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1089 1090 if (vc4_hdmi->variant->set_timings) 1091 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode); 1092 1093 mutex_unlock(&vc4_hdmi->mutex); 1094 1095 return; 1096 1097 err_disable_pixel_clock: 1098 clk_disable_unprepare(vc4_hdmi->pixel_clock); 1099 err_put_runtime_pm: 1100 pm_runtime_put(&vc4_hdmi->pdev->dev); 1101 out: 1102 mutex_unlock(&vc4_hdmi->mutex); 1103 return; 1104 } 1105 1106 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder, 1107 struct drm_atomic_state *state) 1108 { 1109 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1110 struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1111 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 1112 unsigned long flags; 1113 1114 mutex_lock(&vc4_hdmi->mutex); 1115 1116 if (vc4_encoder->hdmi_monitor && 1117 drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_LIMITED) { 1118 if (vc4_hdmi->variant->csc_setup) 1119 vc4_hdmi->variant->csc_setup(vc4_hdmi, true); 1120 1121 vc4_encoder->limited_rgb_range = true; 1122 } else { 1123 if (vc4_hdmi->variant->csc_setup) 1124 vc4_hdmi->variant->csc_setup(vc4_hdmi, false); 1125 1126 vc4_encoder->limited_rgb_range = false; 1127 } 1128 1129 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1130 HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N); 1131 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1132 1133 mutex_unlock(&vc4_hdmi->mutex); 1134 } 1135 1136 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder, 1137 struct drm_atomic_state *state) 1138 { 1139 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1140 struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1141 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 1142 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 1143 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 1144 unsigned long flags; 1145 int ret; 1146 1147 mutex_lock(&vc4_hdmi->mutex); 1148 1149 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1150 1151 HDMI_WRITE(HDMI_VID_CTL, 1152 VC4_HD_VID_CTL_ENABLE | 1153 VC4_HD_VID_CTL_CLRRGB | 1154 VC4_HD_VID_CTL_UNDERFLOW_ENABLE | 1155 VC4_HD_VID_CTL_FRAME_COUNTER_RESET | 1156 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) | 1157 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW)); 1158 1159 HDMI_WRITE(HDMI_VID_CTL, 1160 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX); 1161 1162 if (vc4_encoder->hdmi_monitor) { 1163 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1164 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 1165 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 1166 1167 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1168 1169 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1170 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000); 1171 WARN_ONCE(ret, "Timeout waiting for " 1172 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 1173 } else { 1174 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 1175 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & 1176 ~(VC4_HDMI_RAM_PACKET_ENABLE)); 1177 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1178 HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1179 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 1180 1181 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1182 1183 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1184 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000); 1185 WARN_ONCE(ret, "Timeout waiting for " 1186 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 1187 } 1188 1189 if (vc4_encoder->hdmi_monitor) { 1190 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1191 1192 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1193 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE)); 1194 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1195 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 1196 VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT); 1197 1198 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 1199 VC4_HDMI_RAM_PACKET_ENABLE); 1200 1201 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1202 1203 vc4_hdmi_set_infoframes(encoder); 1204 } 1205 1206 vc4_hdmi_recenter_fifo(vc4_hdmi); 1207 vc4_hdmi_enable_scrambling(encoder); 1208 1209 mutex_unlock(&vc4_hdmi->mutex); 1210 } 1211 1212 static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder) 1213 { 1214 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1215 1216 mutex_lock(&vc4_hdmi->mutex); 1217 vc4_hdmi->output_enabled = true; 1218 mutex_unlock(&vc4_hdmi->mutex); 1219 } 1220 1221 static void vc4_hdmi_encoder_atomic_mode_set(struct drm_encoder *encoder, 1222 struct drm_crtc_state *crtc_state, 1223 struct drm_connector_state *conn_state) 1224 { 1225 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1226 1227 mutex_lock(&vc4_hdmi->mutex); 1228 memcpy(&vc4_hdmi->saved_adjusted_mode, 1229 &crtc_state->adjusted_mode, 1230 sizeof(vc4_hdmi->saved_adjusted_mode)); 1231 mutex_unlock(&vc4_hdmi->mutex); 1232 } 1233 1234 #define WIFI_2_4GHz_CH1_MIN_FREQ 2400000000ULL 1235 #define WIFI_2_4GHz_CH1_MAX_FREQ 2422000000ULL 1236 1237 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder, 1238 struct drm_crtc_state *crtc_state, 1239 struct drm_connector_state *conn_state) 1240 { 1241 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state); 1242 struct drm_display_mode *mode = &crtc_state->adjusted_mode; 1243 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1244 unsigned long long pixel_rate = mode->clock * 1000; 1245 unsigned long long tmds_rate; 1246 1247 if (vc4_hdmi->variant->unsupported_odd_h_timings && 1248 !(mode->flags & DRM_MODE_FLAG_DBLCLK) && 1249 ((mode->hdisplay % 2) || (mode->hsync_start % 2) || 1250 (mode->hsync_end % 2) || (mode->htotal % 2))) 1251 return -EINVAL; 1252 1253 /* 1254 * The 1440p@60 pixel rate is in the same range than the first 1255 * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz 1256 * bandwidth). Slightly lower the frequency to bring it out of 1257 * the WiFi range. 1258 */ 1259 tmds_rate = pixel_rate * 10; 1260 if (vc4_hdmi->disable_wifi_frequencies && 1261 (tmds_rate >= WIFI_2_4GHz_CH1_MIN_FREQ && 1262 tmds_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) { 1263 mode->clock = 238560; 1264 pixel_rate = mode->clock * 1000; 1265 } 1266 1267 if (conn_state->max_bpc == 12) { 1268 pixel_rate = pixel_rate * 150; 1269 do_div(pixel_rate, 100); 1270 } else if (conn_state->max_bpc == 10) { 1271 pixel_rate = pixel_rate * 125; 1272 do_div(pixel_rate, 100); 1273 } 1274 1275 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 1276 pixel_rate = pixel_rate * 2; 1277 1278 if (pixel_rate > vc4_hdmi->variant->max_pixel_clock) 1279 return -EINVAL; 1280 1281 if (vc4_hdmi->disable_4kp60 && (pixel_rate > HDMI_14_MAX_TMDS_CLK)) 1282 return -EINVAL; 1283 1284 vc4_state->pixel_rate = pixel_rate; 1285 1286 return 0; 1287 } 1288 1289 static enum drm_mode_status 1290 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder, 1291 const struct drm_display_mode *mode) 1292 { 1293 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1294 1295 if (vc4_hdmi->variant->unsupported_odd_h_timings && 1296 !(mode->flags & DRM_MODE_FLAG_DBLCLK) && 1297 ((mode->hdisplay % 2) || (mode->hsync_start % 2) || 1298 (mode->hsync_end % 2) || (mode->htotal % 2))) 1299 return MODE_H_ILLEGAL; 1300 1301 if ((mode->clock * 1000) > vc4_hdmi->variant->max_pixel_clock) 1302 return MODE_CLOCK_HIGH; 1303 1304 if (vc4_hdmi->disable_4kp60 && vc4_hdmi_mode_needs_scrambling(mode)) 1305 return MODE_CLOCK_HIGH; 1306 1307 return MODE_OK; 1308 } 1309 1310 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = { 1311 .atomic_check = vc4_hdmi_encoder_atomic_check, 1312 .atomic_mode_set = vc4_hdmi_encoder_atomic_mode_set, 1313 .mode_valid = vc4_hdmi_encoder_mode_valid, 1314 .disable = vc4_hdmi_encoder_disable, 1315 .enable = vc4_hdmi_encoder_enable, 1316 }; 1317 1318 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask) 1319 { 1320 int i; 1321 u32 channel_map = 0; 1322 1323 for (i = 0; i < 8; i++) { 1324 if (channel_mask & BIT(i)) 1325 channel_map |= i << (3 * i); 1326 } 1327 return channel_map; 1328 } 1329 1330 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask) 1331 { 1332 int i; 1333 u32 channel_map = 0; 1334 1335 for (i = 0; i < 8; i++) { 1336 if (channel_mask & BIT(i)) 1337 channel_map |= i << (4 * i); 1338 } 1339 return channel_map; 1340 } 1341 1342 static bool vc5_hdmi_hp_detect(struct vc4_hdmi *vc4_hdmi) 1343 { 1344 unsigned long flags; 1345 u32 hotplug; 1346 1347 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1348 hotplug = HDMI_READ(HDMI_HOTPLUG); 1349 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1350 1351 return !!(hotplug & VC4_HDMI_HOTPLUG_CONNECTED); 1352 } 1353 1354 /* HDMI audio codec callbacks */ 1355 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi, 1356 unsigned int samplerate) 1357 { 1358 u32 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock); 1359 unsigned long flags; 1360 unsigned long n, m; 1361 1362 rational_best_approximation(hsm_clock, samplerate, 1363 VC4_HD_MAI_SMP_N_MASK >> 1364 VC4_HD_MAI_SMP_N_SHIFT, 1365 (VC4_HD_MAI_SMP_M_MASK >> 1366 VC4_HD_MAI_SMP_M_SHIFT) + 1, 1367 &n, &m); 1368 1369 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1370 HDMI_WRITE(HDMI_MAI_SMP, 1371 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) | 1372 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M)); 1373 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1374 } 1375 1376 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi, unsigned int samplerate) 1377 { 1378 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1379 u32 n, cts; 1380 u64 tmp; 1381 1382 lockdep_assert_held(&vc4_hdmi->mutex); 1383 lockdep_assert_held(&vc4_hdmi->hw_lock); 1384 1385 n = 128 * samplerate / 1000; 1386 tmp = (u64)(mode->clock * 1000) * n; 1387 do_div(tmp, 128 * samplerate); 1388 cts = tmp; 1389 1390 HDMI_WRITE(HDMI_CRP_CFG, 1391 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN | 1392 VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N)); 1393 1394 /* 1395 * We could get slightly more accurate clocks in some cases by 1396 * providing a CTS_1 value. The two CTS values are alternated 1397 * between based on the period fields 1398 */ 1399 HDMI_WRITE(HDMI_CTS_0, cts); 1400 HDMI_WRITE(HDMI_CTS_1, cts); 1401 } 1402 1403 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai) 1404 { 1405 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai); 1406 1407 return snd_soc_card_get_drvdata(card); 1408 } 1409 1410 static bool vc4_hdmi_audio_can_stream(struct vc4_hdmi *vc4_hdmi) 1411 { 1412 lockdep_assert_held(&vc4_hdmi->mutex); 1413 1414 /* 1415 * If the controller is disabled, prevent any ALSA output. 1416 */ 1417 if (!vc4_hdmi->output_enabled) 1418 return false; 1419 1420 /* 1421 * If the encoder is currently in DVI mode, treat the codec DAI 1422 * as missing. 1423 */ 1424 if (!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) & VC4_HDMI_RAM_PACKET_ENABLE)) 1425 return false; 1426 1427 return true; 1428 } 1429 1430 static int vc4_hdmi_audio_startup(struct device *dev, void *data) 1431 { 1432 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 1433 unsigned long flags; 1434 1435 mutex_lock(&vc4_hdmi->mutex); 1436 1437 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) { 1438 mutex_unlock(&vc4_hdmi->mutex); 1439 return -ENODEV; 1440 } 1441 1442 vc4_hdmi->audio.streaming = true; 1443 1444 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1445 HDMI_WRITE(HDMI_MAI_CTL, 1446 VC4_HD_MAI_CTL_RESET | 1447 VC4_HD_MAI_CTL_FLUSH | 1448 VC4_HD_MAI_CTL_DLATE | 1449 VC4_HD_MAI_CTL_ERRORE | 1450 VC4_HD_MAI_CTL_ERRORF); 1451 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1452 1453 if (vc4_hdmi->variant->phy_rng_enable) 1454 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi); 1455 1456 mutex_unlock(&vc4_hdmi->mutex); 1457 1458 return 0; 1459 } 1460 1461 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi) 1462 { 1463 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base; 1464 struct device *dev = &vc4_hdmi->pdev->dev; 1465 unsigned long flags; 1466 int ret; 1467 1468 lockdep_assert_held(&vc4_hdmi->mutex); 1469 1470 vc4_hdmi->audio.streaming = false; 1471 ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO, false); 1472 if (ret) 1473 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret); 1474 1475 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1476 1477 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET); 1478 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF); 1479 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH); 1480 1481 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1482 } 1483 1484 static void vc4_hdmi_audio_shutdown(struct device *dev, void *data) 1485 { 1486 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 1487 unsigned long flags; 1488 1489 mutex_lock(&vc4_hdmi->mutex); 1490 1491 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1492 1493 HDMI_WRITE(HDMI_MAI_CTL, 1494 VC4_HD_MAI_CTL_DLATE | 1495 VC4_HD_MAI_CTL_ERRORE | 1496 VC4_HD_MAI_CTL_ERRORF); 1497 1498 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1499 1500 if (vc4_hdmi->variant->phy_rng_disable) 1501 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi); 1502 1503 vc4_hdmi->audio.streaming = false; 1504 vc4_hdmi_audio_reset(vc4_hdmi); 1505 1506 mutex_unlock(&vc4_hdmi->mutex); 1507 } 1508 1509 static int sample_rate_to_mai_fmt(int samplerate) 1510 { 1511 switch (samplerate) { 1512 case 8000: 1513 return VC4_HDMI_MAI_SAMPLE_RATE_8000; 1514 case 11025: 1515 return VC4_HDMI_MAI_SAMPLE_RATE_11025; 1516 case 12000: 1517 return VC4_HDMI_MAI_SAMPLE_RATE_12000; 1518 case 16000: 1519 return VC4_HDMI_MAI_SAMPLE_RATE_16000; 1520 case 22050: 1521 return VC4_HDMI_MAI_SAMPLE_RATE_22050; 1522 case 24000: 1523 return VC4_HDMI_MAI_SAMPLE_RATE_24000; 1524 case 32000: 1525 return VC4_HDMI_MAI_SAMPLE_RATE_32000; 1526 case 44100: 1527 return VC4_HDMI_MAI_SAMPLE_RATE_44100; 1528 case 48000: 1529 return VC4_HDMI_MAI_SAMPLE_RATE_48000; 1530 case 64000: 1531 return VC4_HDMI_MAI_SAMPLE_RATE_64000; 1532 case 88200: 1533 return VC4_HDMI_MAI_SAMPLE_RATE_88200; 1534 case 96000: 1535 return VC4_HDMI_MAI_SAMPLE_RATE_96000; 1536 case 128000: 1537 return VC4_HDMI_MAI_SAMPLE_RATE_128000; 1538 case 176400: 1539 return VC4_HDMI_MAI_SAMPLE_RATE_176400; 1540 case 192000: 1541 return VC4_HDMI_MAI_SAMPLE_RATE_192000; 1542 default: 1543 return VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED; 1544 } 1545 } 1546 1547 /* HDMI audio codec callbacks */ 1548 static int vc4_hdmi_audio_prepare(struct device *dev, void *data, 1549 struct hdmi_codec_daifmt *daifmt, 1550 struct hdmi_codec_params *params) 1551 { 1552 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 1553 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base; 1554 unsigned int sample_rate = params->sample_rate; 1555 unsigned int channels = params->channels; 1556 unsigned long flags; 1557 u32 audio_packet_config, channel_mask; 1558 u32 channel_map; 1559 u32 mai_audio_format; 1560 u32 mai_sample_rate; 1561 1562 dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__, 1563 sample_rate, params->sample_width, channels); 1564 1565 mutex_lock(&vc4_hdmi->mutex); 1566 1567 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) { 1568 mutex_unlock(&vc4_hdmi->mutex); 1569 return -EINVAL; 1570 } 1571 1572 vc4_hdmi_audio_set_mai_clock(vc4_hdmi, sample_rate); 1573 1574 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1575 HDMI_WRITE(HDMI_MAI_CTL, 1576 VC4_SET_FIELD(channels, VC4_HD_MAI_CTL_CHNUM) | 1577 VC4_HD_MAI_CTL_WHOLSMP | 1578 VC4_HD_MAI_CTL_CHALIGN | 1579 VC4_HD_MAI_CTL_ENABLE); 1580 1581 mai_sample_rate = sample_rate_to_mai_fmt(sample_rate); 1582 if (params->iec.status[0] & IEC958_AES0_NONAUDIO && 1583 params->channels == 8) 1584 mai_audio_format = VC4_HDMI_MAI_FORMAT_HBR; 1585 else 1586 mai_audio_format = VC4_HDMI_MAI_FORMAT_PCM; 1587 HDMI_WRITE(HDMI_MAI_FMT, 1588 VC4_SET_FIELD(mai_sample_rate, 1589 VC4_HDMI_MAI_FORMAT_SAMPLE_RATE) | 1590 VC4_SET_FIELD(mai_audio_format, 1591 VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT)); 1592 1593 /* The B frame identifier should match the value used by alsa-lib (8) */ 1594 audio_packet_config = 1595 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT | 1596 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS | 1597 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER); 1598 1599 channel_mask = GENMASK(channels - 1, 0); 1600 audio_packet_config |= VC4_SET_FIELD(channel_mask, 1601 VC4_HDMI_AUDIO_PACKET_CEA_MASK); 1602 1603 /* Set the MAI threshold */ 1604 HDMI_WRITE(HDMI_MAI_THR, 1605 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) | 1606 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) | 1607 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQHIGH) | 1608 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQLOW)); 1609 1610 HDMI_WRITE(HDMI_MAI_CONFIG, 1611 VC4_HDMI_MAI_CONFIG_BIT_REVERSE | 1612 VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE | 1613 VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK)); 1614 1615 channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask); 1616 HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map); 1617 HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config); 1618 1619 vc4_hdmi_set_n_cts(vc4_hdmi, sample_rate); 1620 1621 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1622 1623 memcpy(&vc4_hdmi->audio.infoframe, ¶ms->cea, sizeof(params->cea)); 1624 vc4_hdmi_set_audio_infoframe(encoder); 1625 1626 mutex_unlock(&vc4_hdmi->mutex); 1627 1628 return 0; 1629 } 1630 1631 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = { 1632 .name = "vc4-hdmi-cpu-dai-component", 1633 }; 1634 1635 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai) 1636 { 1637 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai); 1638 1639 snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL); 1640 1641 return 0; 1642 } 1643 1644 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = { 1645 .name = "vc4-hdmi-cpu-dai", 1646 .probe = vc4_hdmi_audio_cpu_dai_probe, 1647 .playback = { 1648 .stream_name = "Playback", 1649 .channels_min = 1, 1650 .channels_max = 8, 1651 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 1652 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 1653 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 1654 SNDRV_PCM_RATE_192000, 1655 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 1656 }, 1657 }; 1658 1659 static const struct snd_dmaengine_pcm_config pcm_conf = { 1660 .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx", 1661 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 1662 }; 1663 1664 static int vc4_hdmi_audio_get_eld(struct device *dev, void *data, 1665 uint8_t *buf, size_t len) 1666 { 1667 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 1668 struct drm_connector *connector = &vc4_hdmi->connector; 1669 1670 mutex_lock(&vc4_hdmi->mutex); 1671 memcpy(buf, connector->eld, min(sizeof(connector->eld), len)); 1672 mutex_unlock(&vc4_hdmi->mutex); 1673 1674 return 0; 1675 } 1676 1677 static const struct hdmi_codec_ops vc4_hdmi_codec_ops = { 1678 .get_eld = vc4_hdmi_audio_get_eld, 1679 .prepare = vc4_hdmi_audio_prepare, 1680 .audio_shutdown = vc4_hdmi_audio_shutdown, 1681 .audio_startup = vc4_hdmi_audio_startup, 1682 }; 1683 1684 static struct hdmi_codec_pdata vc4_hdmi_codec_pdata = { 1685 .ops = &vc4_hdmi_codec_ops, 1686 .max_i2s_channels = 8, 1687 .i2s = 1, 1688 }; 1689 1690 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi) 1691 { 1692 const struct vc4_hdmi_register *mai_data = 1693 &vc4_hdmi->variant->registers[HDMI_MAI_DATA]; 1694 struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link; 1695 struct snd_soc_card *card = &vc4_hdmi->audio.card; 1696 struct device *dev = &vc4_hdmi->pdev->dev; 1697 struct platform_device *codec_pdev; 1698 const __be32 *addr; 1699 int index; 1700 int ret; 1701 1702 if (!of_find_property(dev->of_node, "dmas", NULL)) { 1703 dev_warn(dev, 1704 "'dmas' DT property is missing, no HDMI audio\n"); 1705 return 0; 1706 } 1707 1708 if (mai_data->reg != VC4_HD) { 1709 WARN_ONCE(true, "MAI isn't in the HD block\n"); 1710 return -EINVAL; 1711 } 1712 1713 /* 1714 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve 1715 * the bus address specified in the DT, because the physical address 1716 * (the one returned by platform_get_resource()) is not appropriate 1717 * for DMA transfers. 1718 * This VC/MMU should probably be exposed to avoid this kind of hacks. 1719 */ 1720 index = of_property_match_string(dev->of_node, "reg-names", "hd"); 1721 /* Before BCM2711, we don't have a named register range */ 1722 if (index < 0) 1723 index = 1; 1724 1725 addr = of_get_address(dev->of_node, index, NULL, NULL); 1726 1727 vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset; 1728 vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1729 vc4_hdmi->audio.dma_data.maxburst = 2; 1730 1731 ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0); 1732 if (ret) { 1733 dev_err(dev, "Could not register PCM component: %d\n", ret); 1734 return ret; 1735 } 1736 1737 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp, 1738 &vc4_hdmi_audio_cpu_dai_drv, 1); 1739 if (ret) { 1740 dev_err(dev, "Could not register CPU DAI: %d\n", ret); 1741 return ret; 1742 } 1743 1744 codec_pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME, 1745 PLATFORM_DEVID_AUTO, 1746 &vc4_hdmi_codec_pdata, 1747 sizeof(vc4_hdmi_codec_pdata)); 1748 if (IS_ERR(codec_pdev)) { 1749 dev_err(dev, "Couldn't register the HDMI codec: %ld\n", PTR_ERR(codec_pdev)); 1750 return PTR_ERR(codec_pdev); 1751 } 1752 vc4_hdmi->audio.codec_pdev = codec_pdev; 1753 1754 dai_link->cpus = &vc4_hdmi->audio.cpu; 1755 dai_link->codecs = &vc4_hdmi->audio.codec; 1756 dai_link->platforms = &vc4_hdmi->audio.platform; 1757 1758 dai_link->num_cpus = 1; 1759 dai_link->num_codecs = 1; 1760 dai_link->num_platforms = 1; 1761 1762 dai_link->name = "MAI"; 1763 dai_link->stream_name = "MAI PCM"; 1764 dai_link->codecs->dai_name = "i2s-hifi"; 1765 dai_link->cpus->dai_name = dev_name(dev); 1766 dai_link->codecs->name = dev_name(&codec_pdev->dev); 1767 dai_link->platforms->name = dev_name(dev); 1768 1769 card->dai_link = dai_link; 1770 card->num_links = 1; 1771 card->name = vc4_hdmi->variant->card_name; 1772 card->driver_name = "vc4-hdmi"; 1773 card->dev = dev; 1774 card->owner = THIS_MODULE; 1775 1776 /* 1777 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and 1778 * stores a pointer to the snd card object in dev->driver_data. This 1779 * means we cannot use it for something else. The hdmi back-pointer is 1780 * now stored in card->drvdata and should be retrieved with 1781 * snd_soc_card_get_drvdata() if needed. 1782 */ 1783 snd_soc_card_set_drvdata(card, vc4_hdmi); 1784 ret = devm_snd_soc_register_card(dev, card); 1785 if (ret) 1786 dev_err_probe(dev, ret, "Could not register sound card\n"); 1787 1788 return ret; 1789 1790 } 1791 1792 static void vc4_hdmi_audio_exit(struct vc4_hdmi *vc4_hdmi) 1793 { 1794 platform_device_unregister(vc4_hdmi->audio.codec_pdev); 1795 vc4_hdmi->audio.codec_pdev = NULL; 1796 } 1797 1798 static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv) 1799 { 1800 struct vc4_hdmi *vc4_hdmi = priv; 1801 struct drm_connector *connector = &vc4_hdmi->connector; 1802 struct drm_device *dev = connector->dev; 1803 1804 if (dev && dev->registered) 1805 drm_connector_helper_hpd_irq_event(connector); 1806 1807 return IRQ_HANDLED; 1808 } 1809 1810 static int vc4_hdmi_hotplug_init(struct vc4_hdmi *vc4_hdmi) 1811 { 1812 struct drm_connector *connector = &vc4_hdmi->connector; 1813 struct platform_device *pdev = vc4_hdmi->pdev; 1814 int ret; 1815 1816 if (vc4_hdmi->variant->external_irq_controller) { 1817 unsigned int hpd_con = platform_get_irq_byname(pdev, "hpd-connected"); 1818 unsigned int hpd_rm = platform_get_irq_byname(pdev, "hpd-removed"); 1819 1820 ret = request_threaded_irq(hpd_con, 1821 NULL, 1822 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT, 1823 "vc4 hdmi hpd connected", vc4_hdmi); 1824 if (ret) 1825 return ret; 1826 1827 ret = request_threaded_irq(hpd_rm, 1828 NULL, 1829 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT, 1830 "vc4 hdmi hpd disconnected", vc4_hdmi); 1831 if (ret) { 1832 free_irq(hpd_con, vc4_hdmi); 1833 return ret; 1834 } 1835 1836 connector->polled = DRM_CONNECTOR_POLL_HPD; 1837 } 1838 1839 return 0; 1840 } 1841 1842 static void vc4_hdmi_hotplug_exit(struct vc4_hdmi *vc4_hdmi) 1843 { 1844 struct platform_device *pdev = vc4_hdmi->pdev; 1845 1846 if (vc4_hdmi->variant->external_irq_controller) { 1847 free_irq(platform_get_irq_byname(pdev, "hpd-connected"), vc4_hdmi); 1848 free_irq(platform_get_irq_byname(pdev, "hpd-removed"), vc4_hdmi); 1849 } 1850 } 1851 1852 #ifdef CONFIG_DRM_VC4_HDMI_CEC 1853 static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv) 1854 { 1855 struct vc4_hdmi *vc4_hdmi = priv; 1856 1857 if (vc4_hdmi->cec_rx_msg.len) 1858 cec_received_msg(vc4_hdmi->cec_adap, 1859 &vc4_hdmi->cec_rx_msg); 1860 1861 return IRQ_HANDLED; 1862 } 1863 1864 static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv) 1865 { 1866 struct vc4_hdmi *vc4_hdmi = priv; 1867 1868 if (vc4_hdmi->cec_tx_ok) { 1869 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK, 1870 0, 0, 0, 0); 1871 } else { 1872 /* 1873 * This CEC implementation makes 1 retry, so if we 1874 * get a NACK, then that means it made 2 attempts. 1875 */ 1876 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK, 1877 0, 2, 0, 0); 1878 } 1879 return IRQ_HANDLED; 1880 } 1881 1882 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv) 1883 { 1884 struct vc4_hdmi *vc4_hdmi = priv; 1885 irqreturn_t ret; 1886 1887 if (vc4_hdmi->cec_irq_was_rx) 1888 ret = vc4_cec_irq_handler_rx_thread(irq, priv); 1889 else 1890 ret = vc4_cec_irq_handler_tx_thread(irq, priv); 1891 1892 return ret; 1893 } 1894 1895 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1) 1896 { 1897 struct drm_device *dev = vc4_hdmi->connector.dev; 1898 struct cec_msg *msg = &vc4_hdmi->cec_rx_msg; 1899 unsigned int i; 1900 1901 lockdep_assert_held(&vc4_hdmi->hw_lock); 1902 1903 msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >> 1904 VC4_HDMI_CEC_REC_WRD_CNT_SHIFT); 1905 1906 if (msg->len > 16) { 1907 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len); 1908 return; 1909 } 1910 1911 for (i = 0; i < msg->len; i += 4) { 1912 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2)); 1913 1914 msg->msg[i] = val & 0xff; 1915 msg->msg[i + 1] = (val >> 8) & 0xff; 1916 msg->msg[i + 2] = (val >> 16) & 0xff; 1917 msg->msg[i + 3] = (val >> 24) & 0xff; 1918 } 1919 } 1920 1921 static irqreturn_t vc4_cec_irq_handler_tx_bare_locked(struct vc4_hdmi *vc4_hdmi) 1922 { 1923 u32 cntrl1; 1924 1925 lockdep_assert_held(&vc4_hdmi->hw_lock); 1926 1927 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1); 1928 vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD; 1929 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 1930 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 1931 1932 return IRQ_WAKE_THREAD; 1933 } 1934 1935 static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv) 1936 { 1937 struct vc4_hdmi *vc4_hdmi = priv; 1938 irqreturn_t ret; 1939 1940 spin_lock(&vc4_hdmi->hw_lock); 1941 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi); 1942 spin_unlock(&vc4_hdmi->hw_lock); 1943 1944 return ret; 1945 } 1946 1947 static irqreturn_t vc4_cec_irq_handler_rx_bare_locked(struct vc4_hdmi *vc4_hdmi) 1948 { 1949 u32 cntrl1; 1950 1951 lockdep_assert_held(&vc4_hdmi->hw_lock); 1952 1953 vc4_hdmi->cec_rx_msg.len = 0; 1954 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1); 1955 vc4_cec_read_msg(vc4_hdmi, cntrl1); 1956 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 1957 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 1958 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 1959 1960 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 1961 1962 return IRQ_WAKE_THREAD; 1963 } 1964 1965 static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv) 1966 { 1967 struct vc4_hdmi *vc4_hdmi = priv; 1968 irqreturn_t ret; 1969 1970 spin_lock(&vc4_hdmi->hw_lock); 1971 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi); 1972 spin_unlock(&vc4_hdmi->hw_lock); 1973 1974 return ret; 1975 } 1976 1977 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv) 1978 { 1979 struct vc4_hdmi *vc4_hdmi = priv; 1980 u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS); 1981 irqreturn_t ret; 1982 u32 cntrl5; 1983 1984 if (!(stat & VC4_HDMI_CPU_CEC)) 1985 return IRQ_NONE; 1986 1987 spin_lock(&vc4_hdmi->hw_lock); 1988 cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5); 1989 vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT; 1990 if (vc4_hdmi->cec_irq_was_rx) 1991 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi); 1992 else 1993 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi); 1994 1995 HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC); 1996 spin_unlock(&vc4_hdmi->hw_lock); 1997 1998 return ret; 1999 } 2000 2001 static int vc4_hdmi_cec_enable(struct cec_adapter *adap) 2002 { 2003 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 2004 /* clock period in microseconds */ 2005 const u32 usecs = 1000000 / CEC_CLOCK_FREQ; 2006 unsigned long flags; 2007 u32 val; 2008 int ret; 2009 2010 /* 2011 * NOTE: This function should really take vc4_hdmi->mutex, but doing so 2012 * results in a reentrancy since cec_s_phys_addr_from_edid() called in 2013 * .detect or .get_modes might call .adap_enable, which leads to this 2014 * function being called with that mutex held. 2015 * 2016 * Concurrency is not an issue for the moment since we don't share any 2017 * state with KMS, so we can ignore the lock for now, but we need to 2018 * keep it in mind if we were to change that assumption. 2019 */ 2020 2021 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev); 2022 if (ret) 2023 return ret; 2024 2025 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2026 2027 val = HDMI_READ(HDMI_CEC_CNTRL_5); 2028 val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET | 2029 VC4_HDMI_CEC_CNT_TO_4700_US_MASK | 2030 VC4_HDMI_CEC_CNT_TO_4500_US_MASK); 2031 val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) | 2032 ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT); 2033 2034 HDMI_WRITE(HDMI_CEC_CNTRL_5, val | 2035 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 2036 HDMI_WRITE(HDMI_CEC_CNTRL_5, val); 2037 HDMI_WRITE(HDMI_CEC_CNTRL_2, 2038 ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) | 2039 ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) | 2040 ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) | 2041 ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) | 2042 ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT)); 2043 HDMI_WRITE(HDMI_CEC_CNTRL_3, 2044 ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) | 2045 ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) | 2046 ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) | 2047 ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT)); 2048 HDMI_WRITE(HDMI_CEC_CNTRL_4, 2049 ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) | 2050 ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) | 2051 ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) | 2052 ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT)); 2053 2054 if (!vc4_hdmi->variant->external_irq_controller) 2055 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC); 2056 2057 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2058 2059 return 0; 2060 } 2061 2062 static int vc4_hdmi_cec_disable(struct cec_adapter *adap) 2063 { 2064 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 2065 unsigned long flags; 2066 2067 /* 2068 * NOTE: This function should really take vc4_hdmi->mutex, but doing so 2069 * results in a reentrancy since cec_s_phys_addr_from_edid() called in 2070 * .detect or .get_modes might call .adap_enable, which leads to this 2071 * function being called with that mutex held. 2072 * 2073 * Concurrency is not an issue for the moment since we don't share any 2074 * state with KMS, so we can ignore the lock for now, but we need to 2075 * keep it in mind if we were to change that assumption. 2076 */ 2077 2078 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2079 2080 if (!vc4_hdmi->variant->external_irq_controller) 2081 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC); 2082 2083 HDMI_WRITE(HDMI_CEC_CNTRL_5, HDMI_READ(HDMI_CEC_CNTRL_5) | 2084 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 2085 2086 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2087 2088 pm_runtime_put(&vc4_hdmi->pdev->dev); 2089 2090 return 0; 2091 } 2092 2093 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable) 2094 { 2095 if (enable) 2096 return vc4_hdmi_cec_enable(adap); 2097 else 2098 return vc4_hdmi_cec_disable(adap); 2099 } 2100 2101 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr) 2102 { 2103 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 2104 unsigned long flags; 2105 2106 /* 2107 * NOTE: This function should really take vc4_hdmi->mutex, but doing so 2108 * results in a reentrancy since cec_s_phys_addr_from_edid() called in 2109 * .detect or .get_modes might call .adap_enable, which leads to this 2110 * function being called with that mutex held. 2111 * 2112 * Concurrency is not an issue for the moment since we don't share any 2113 * state with KMS, so we can ignore the lock for now, but we need to 2114 * keep it in mind if we were to change that assumption. 2115 */ 2116 2117 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2118 HDMI_WRITE(HDMI_CEC_CNTRL_1, 2119 (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) | 2120 (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT); 2121 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2122 2123 return 0; 2124 } 2125 2126 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts, 2127 u32 signal_free_time, struct cec_msg *msg) 2128 { 2129 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 2130 struct drm_device *dev = vc4_hdmi->connector.dev; 2131 unsigned long flags; 2132 u32 val; 2133 unsigned int i; 2134 2135 /* 2136 * NOTE: This function should really take vc4_hdmi->mutex, but doing so 2137 * results in a reentrancy since cec_s_phys_addr_from_edid() called in 2138 * .detect or .get_modes might call .adap_enable, which leads to this 2139 * function being called with that mutex held. 2140 * 2141 * Concurrency is not an issue for the moment since we don't share any 2142 * state with KMS, so we can ignore the lock for now, but we need to 2143 * keep it in mind if we were to change that assumption. 2144 */ 2145 2146 if (msg->len > 16) { 2147 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len); 2148 return -ENOMEM; 2149 } 2150 2151 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2152 2153 for (i = 0; i < msg->len; i += 4) 2154 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2), 2155 (msg->msg[i]) | 2156 (msg->msg[i + 1] << 8) | 2157 (msg->msg[i + 2] << 16) | 2158 (msg->msg[i + 3] << 24)); 2159 2160 val = HDMI_READ(HDMI_CEC_CNTRL_1); 2161 val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 2162 HDMI_WRITE(HDMI_CEC_CNTRL_1, val); 2163 val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK; 2164 val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT; 2165 val |= VC4_HDMI_CEC_START_XMIT_BEGIN; 2166 2167 HDMI_WRITE(HDMI_CEC_CNTRL_1, val); 2168 2169 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2170 2171 return 0; 2172 } 2173 2174 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = { 2175 .adap_enable = vc4_hdmi_cec_adap_enable, 2176 .adap_log_addr = vc4_hdmi_cec_adap_log_addr, 2177 .adap_transmit = vc4_hdmi_cec_adap_transmit, 2178 }; 2179 2180 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi) 2181 { 2182 struct cec_connector_info conn_info; 2183 struct platform_device *pdev = vc4_hdmi->pdev; 2184 struct device *dev = &pdev->dev; 2185 unsigned long flags; 2186 u32 value; 2187 int ret; 2188 2189 if (!of_find_property(dev->of_node, "interrupts", NULL)) { 2190 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n"); 2191 return 0; 2192 } 2193 2194 vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops, 2195 vc4_hdmi, "vc4", 2196 CEC_CAP_DEFAULTS | 2197 CEC_CAP_CONNECTOR_INFO, 1); 2198 ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap); 2199 if (ret < 0) 2200 return ret; 2201 2202 cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector); 2203 cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info); 2204 2205 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2206 value = HDMI_READ(HDMI_CEC_CNTRL_1); 2207 /* Set the logical address to Unregistered */ 2208 value |= VC4_HDMI_CEC_ADDR_MASK; 2209 HDMI_WRITE(HDMI_CEC_CNTRL_1, value); 2210 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2211 2212 vc4_hdmi_cec_update_clk_div(vc4_hdmi); 2213 2214 if (vc4_hdmi->variant->external_irq_controller) { 2215 ret = request_threaded_irq(platform_get_irq_byname(pdev, "cec-rx"), 2216 vc4_cec_irq_handler_rx_bare, 2217 vc4_cec_irq_handler_rx_thread, 0, 2218 "vc4 hdmi cec rx", vc4_hdmi); 2219 if (ret) 2220 goto err_delete_cec_adap; 2221 2222 ret = request_threaded_irq(platform_get_irq_byname(pdev, "cec-tx"), 2223 vc4_cec_irq_handler_tx_bare, 2224 vc4_cec_irq_handler_tx_thread, 0, 2225 "vc4 hdmi cec tx", vc4_hdmi); 2226 if (ret) 2227 goto err_remove_cec_rx_handler; 2228 } else { 2229 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2230 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff); 2231 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2232 2233 ret = request_threaded_irq(platform_get_irq(pdev, 0), 2234 vc4_cec_irq_handler, 2235 vc4_cec_irq_handler_thread, 0, 2236 "vc4 hdmi cec", vc4_hdmi); 2237 if (ret) 2238 goto err_delete_cec_adap; 2239 } 2240 2241 ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev); 2242 if (ret < 0) 2243 goto err_remove_handlers; 2244 2245 return 0; 2246 2247 err_remove_handlers: 2248 if (vc4_hdmi->variant->external_irq_controller) 2249 free_irq(platform_get_irq_byname(pdev, "cec-tx"), vc4_hdmi); 2250 else 2251 free_irq(platform_get_irq(pdev, 0), vc4_hdmi); 2252 2253 err_remove_cec_rx_handler: 2254 if (vc4_hdmi->variant->external_irq_controller) 2255 free_irq(platform_get_irq_byname(pdev, "cec-rx"), vc4_hdmi); 2256 2257 err_delete_cec_adap: 2258 cec_delete_adapter(vc4_hdmi->cec_adap); 2259 2260 return ret; 2261 } 2262 2263 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi) 2264 { 2265 struct platform_device *pdev = vc4_hdmi->pdev; 2266 2267 if (vc4_hdmi->variant->external_irq_controller) { 2268 free_irq(platform_get_irq_byname(pdev, "cec-rx"), vc4_hdmi); 2269 free_irq(platform_get_irq_byname(pdev, "cec-tx"), vc4_hdmi); 2270 } else { 2271 free_irq(platform_get_irq(pdev, 0), vc4_hdmi); 2272 } 2273 2274 cec_unregister_adapter(vc4_hdmi->cec_adap); 2275 } 2276 #else 2277 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi) 2278 { 2279 return 0; 2280 } 2281 2282 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi) {}; 2283 2284 #endif 2285 2286 static int vc4_hdmi_build_regset(struct vc4_hdmi *vc4_hdmi, 2287 struct debugfs_regset32 *regset, 2288 enum vc4_hdmi_regs reg) 2289 { 2290 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant; 2291 struct debugfs_reg32 *regs, *new_regs; 2292 unsigned int count = 0; 2293 unsigned int i; 2294 2295 regs = kcalloc(variant->num_registers, sizeof(*regs), 2296 GFP_KERNEL); 2297 if (!regs) 2298 return -ENOMEM; 2299 2300 for (i = 0; i < variant->num_registers; i++) { 2301 const struct vc4_hdmi_register *field = &variant->registers[i]; 2302 2303 if (field->reg != reg) 2304 continue; 2305 2306 regs[count].name = field->name; 2307 regs[count].offset = field->offset; 2308 count++; 2309 } 2310 2311 new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL); 2312 if (!new_regs) 2313 return -ENOMEM; 2314 2315 regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg); 2316 regset->regs = new_regs; 2317 regset->nregs = count; 2318 2319 return 0; 2320 } 2321 2322 static int vc4_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi) 2323 { 2324 struct platform_device *pdev = vc4_hdmi->pdev; 2325 struct device *dev = &pdev->dev; 2326 int ret; 2327 2328 vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0); 2329 if (IS_ERR(vc4_hdmi->hdmicore_regs)) 2330 return PTR_ERR(vc4_hdmi->hdmicore_regs); 2331 2332 vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1); 2333 if (IS_ERR(vc4_hdmi->hd_regs)) 2334 return PTR_ERR(vc4_hdmi->hd_regs); 2335 2336 ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD); 2337 if (ret) 2338 return ret; 2339 2340 ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI); 2341 if (ret) 2342 return ret; 2343 2344 vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel"); 2345 if (IS_ERR(vc4_hdmi->pixel_clock)) { 2346 ret = PTR_ERR(vc4_hdmi->pixel_clock); 2347 if (ret != -EPROBE_DEFER) 2348 DRM_ERROR("Failed to get pixel clock\n"); 2349 return ret; 2350 } 2351 2352 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); 2353 if (IS_ERR(vc4_hdmi->hsm_clock)) { 2354 DRM_ERROR("Failed to get HDMI state machine clock\n"); 2355 return PTR_ERR(vc4_hdmi->hsm_clock); 2356 } 2357 vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock; 2358 vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock; 2359 2360 return 0; 2361 } 2362 2363 static int vc5_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi) 2364 { 2365 struct platform_device *pdev = vc4_hdmi->pdev; 2366 struct device *dev = &pdev->dev; 2367 struct resource *res; 2368 2369 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi"); 2370 if (!res) 2371 return -ENODEV; 2372 2373 vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start, 2374 resource_size(res)); 2375 if (!vc4_hdmi->hdmicore_regs) 2376 return -ENOMEM; 2377 2378 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd"); 2379 if (!res) 2380 return -ENODEV; 2381 2382 vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res)); 2383 if (!vc4_hdmi->hd_regs) 2384 return -ENOMEM; 2385 2386 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec"); 2387 if (!res) 2388 return -ENODEV; 2389 2390 vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res)); 2391 if (!vc4_hdmi->cec_regs) 2392 return -ENOMEM; 2393 2394 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc"); 2395 if (!res) 2396 return -ENODEV; 2397 2398 vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res)); 2399 if (!vc4_hdmi->csc_regs) 2400 return -ENOMEM; 2401 2402 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp"); 2403 if (!res) 2404 return -ENODEV; 2405 2406 vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res)); 2407 if (!vc4_hdmi->dvp_regs) 2408 return -ENOMEM; 2409 2410 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy"); 2411 if (!res) 2412 return -ENODEV; 2413 2414 vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res)); 2415 if (!vc4_hdmi->phy_regs) 2416 return -ENOMEM; 2417 2418 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet"); 2419 if (!res) 2420 return -ENODEV; 2421 2422 vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res)); 2423 if (!vc4_hdmi->ram_regs) 2424 return -ENOMEM; 2425 2426 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm"); 2427 if (!res) 2428 return -ENODEV; 2429 2430 vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res)); 2431 if (!vc4_hdmi->rm_regs) 2432 return -ENOMEM; 2433 2434 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); 2435 if (IS_ERR(vc4_hdmi->hsm_clock)) { 2436 DRM_ERROR("Failed to get HDMI state machine clock\n"); 2437 return PTR_ERR(vc4_hdmi->hsm_clock); 2438 } 2439 2440 vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb"); 2441 if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) { 2442 DRM_ERROR("Failed to get pixel bvb clock\n"); 2443 return PTR_ERR(vc4_hdmi->pixel_bvb_clock); 2444 } 2445 2446 vc4_hdmi->audio_clock = devm_clk_get(dev, "audio"); 2447 if (IS_ERR(vc4_hdmi->audio_clock)) { 2448 DRM_ERROR("Failed to get audio clock\n"); 2449 return PTR_ERR(vc4_hdmi->audio_clock); 2450 } 2451 2452 vc4_hdmi->cec_clock = devm_clk_get(dev, "cec"); 2453 if (IS_ERR(vc4_hdmi->cec_clock)) { 2454 DRM_ERROR("Failed to get CEC clock\n"); 2455 return PTR_ERR(vc4_hdmi->cec_clock); 2456 } 2457 2458 vc4_hdmi->reset = devm_reset_control_get(dev, NULL); 2459 if (IS_ERR(vc4_hdmi->reset)) { 2460 DRM_ERROR("Failed to get HDMI reset line\n"); 2461 return PTR_ERR(vc4_hdmi->reset); 2462 } 2463 2464 return 0; 2465 } 2466 2467 static int __maybe_unused vc4_hdmi_runtime_suspend(struct device *dev) 2468 { 2469 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 2470 2471 clk_disable_unprepare(vc4_hdmi->hsm_clock); 2472 2473 return 0; 2474 } 2475 2476 static int vc4_hdmi_runtime_resume(struct device *dev) 2477 { 2478 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 2479 int ret; 2480 2481 ret = clk_prepare_enable(vc4_hdmi->hsm_clock); 2482 if (ret) 2483 return ret; 2484 2485 return 0; 2486 } 2487 2488 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data) 2489 { 2490 const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev); 2491 struct platform_device *pdev = to_platform_device(dev); 2492 struct drm_device *drm = dev_get_drvdata(master); 2493 struct vc4_hdmi *vc4_hdmi; 2494 struct drm_encoder *encoder; 2495 struct device_node *ddc_node; 2496 int ret; 2497 2498 vc4_hdmi = devm_kzalloc(dev, sizeof(*vc4_hdmi), GFP_KERNEL); 2499 if (!vc4_hdmi) 2500 return -ENOMEM; 2501 mutex_init(&vc4_hdmi->mutex); 2502 spin_lock_init(&vc4_hdmi->hw_lock); 2503 INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq); 2504 2505 dev_set_drvdata(dev, vc4_hdmi); 2506 encoder = &vc4_hdmi->encoder.base.base; 2507 vc4_hdmi->encoder.base.type = variant->encoder_type; 2508 vc4_hdmi->encoder.base.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure; 2509 vc4_hdmi->encoder.base.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable; 2510 vc4_hdmi->encoder.base.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable; 2511 vc4_hdmi->encoder.base.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable; 2512 vc4_hdmi->encoder.base.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown; 2513 vc4_hdmi->pdev = pdev; 2514 vc4_hdmi->variant = variant; 2515 2516 /* 2517 * Since we don't know the state of the controller and its 2518 * display (if any), let's assume it's always enabled. 2519 * vc4_hdmi_disable_scrambling() will thus run at boot, make 2520 * sure it's disabled, and avoid any inconsistency. 2521 */ 2522 if (variant->max_pixel_clock > HDMI_14_MAX_TMDS_CLK) 2523 vc4_hdmi->scdc_enabled = true; 2524 2525 ret = variant->init_resources(vc4_hdmi); 2526 if (ret) 2527 return ret; 2528 2529 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0); 2530 if (!ddc_node) { 2531 DRM_ERROR("Failed to find ddc node in device tree\n"); 2532 return -ENODEV; 2533 } 2534 2535 vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node); 2536 of_node_put(ddc_node); 2537 if (!vc4_hdmi->ddc) { 2538 DRM_DEBUG("Failed to get ddc i2c adapter by node\n"); 2539 return -EPROBE_DEFER; 2540 } 2541 2542 /* Only use the GPIO HPD pin if present in the DT, otherwise 2543 * we'll use the HDMI core's register. 2544 */ 2545 vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN); 2546 if (IS_ERR(vc4_hdmi->hpd_gpio)) { 2547 ret = PTR_ERR(vc4_hdmi->hpd_gpio); 2548 goto err_put_ddc; 2549 } 2550 2551 vc4_hdmi->disable_wifi_frequencies = 2552 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence"); 2553 2554 if (variant->max_pixel_clock == 600000000) { 2555 struct vc4_dev *vc4 = to_vc4_dev(drm); 2556 long max_rate = clk_round_rate(vc4->hvs->core_clk, 550000000); 2557 2558 if (max_rate < 550000000) 2559 vc4_hdmi->disable_4kp60 = true; 2560 } 2561 2562 /* 2563 * If we boot without any cable connected to the HDMI connector, 2564 * the firmware will skip the HSM initialization and leave it 2565 * with a rate of 0, resulting in a bus lockup when we're 2566 * accessing the registers even if it's enabled. 2567 * 2568 * Let's put a sensible default at runtime_resume so that we 2569 * don't end up in this situation. 2570 */ 2571 ret = clk_set_min_rate(vc4_hdmi->hsm_clock, HSM_MIN_CLOCK_FREQ); 2572 if (ret) 2573 goto err_put_ddc; 2574 2575 /* 2576 * We need to have the device powered up at this point to call 2577 * our reset hook and for the CEC init. 2578 */ 2579 ret = vc4_hdmi_runtime_resume(dev); 2580 if (ret) 2581 goto err_put_ddc; 2582 2583 pm_runtime_get_noresume(dev); 2584 pm_runtime_set_active(dev); 2585 pm_runtime_enable(dev); 2586 2587 if (vc4_hdmi->variant->reset) 2588 vc4_hdmi->variant->reset(vc4_hdmi); 2589 2590 if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") || 2591 of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1")) && 2592 HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) { 2593 clk_prepare_enable(vc4_hdmi->pixel_clock); 2594 clk_prepare_enable(vc4_hdmi->hsm_clock); 2595 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock); 2596 } 2597 2598 drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS); 2599 drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs); 2600 2601 ret = vc4_hdmi_connector_init(drm, vc4_hdmi); 2602 if (ret) 2603 goto err_destroy_encoder; 2604 2605 ret = vc4_hdmi_hotplug_init(vc4_hdmi); 2606 if (ret) 2607 goto err_destroy_conn; 2608 2609 ret = vc4_hdmi_cec_init(vc4_hdmi); 2610 if (ret) 2611 goto err_free_hotplug; 2612 2613 ret = vc4_hdmi_audio_init(vc4_hdmi); 2614 if (ret) 2615 goto err_free_cec; 2616 2617 vc4_debugfs_add_file(drm, variant->debugfs_name, 2618 vc4_hdmi_debugfs_regs, 2619 vc4_hdmi); 2620 2621 pm_runtime_put_sync(dev); 2622 2623 return 0; 2624 2625 err_free_cec: 2626 vc4_hdmi_cec_exit(vc4_hdmi); 2627 err_free_hotplug: 2628 vc4_hdmi_hotplug_exit(vc4_hdmi); 2629 err_destroy_conn: 2630 vc4_hdmi_connector_destroy(&vc4_hdmi->connector); 2631 err_destroy_encoder: 2632 drm_encoder_cleanup(encoder); 2633 pm_runtime_put_sync(dev); 2634 pm_runtime_disable(dev); 2635 err_put_ddc: 2636 put_device(&vc4_hdmi->ddc->dev); 2637 2638 return ret; 2639 } 2640 2641 static void vc4_hdmi_unbind(struct device *dev, struct device *master, 2642 void *data) 2643 { 2644 struct vc4_hdmi *vc4_hdmi; 2645 2646 /* 2647 * ASoC makes it a bit hard to retrieve a pointer to the 2648 * vc4_hdmi structure. Registering the card will overwrite our 2649 * device drvdata with a pointer to the snd_soc_card structure, 2650 * which can then be used to retrieve whatever drvdata we want 2651 * to associate. 2652 * 2653 * However, that doesn't fly in the case where we wouldn't 2654 * register an ASoC card (because of an old DT that is missing 2655 * the dmas properties for example), then the card isn't 2656 * registered and the device drvdata wouldn't be set. 2657 * 2658 * We can deal with both cases by making sure a snd_soc_card 2659 * pointer and a vc4_hdmi structure are pointing to the same 2660 * memory address, so we can treat them indistinctly without any 2661 * issue. 2662 */ 2663 BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0); 2664 BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0); 2665 vc4_hdmi = dev_get_drvdata(dev); 2666 2667 kfree(vc4_hdmi->hdmi_regset.regs); 2668 kfree(vc4_hdmi->hd_regset.regs); 2669 2670 vc4_hdmi_audio_exit(vc4_hdmi); 2671 vc4_hdmi_cec_exit(vc4_hdmi); 2672 vc4_hdmi_hotplug_exit(vc4_hdmi); 2673 vc4_hdmi_connector_destroy(&vc4_hdmi->connector); 2674 drm_encoder_cleanup(&vc4_hdmi->encoder.base.base); 2675 2676 pm_runtime_disable(dev); 2677 2678 put_device(&vc4_hdmi->ddc->dev); 2679 } 2680 2681 static const struct component_ops vc4_hdmi_ops = { 2682 .bind = vc4_hdmi_bind, 2683 .unbind = vc4_hdmi_unbind, 2684 }; 2685 2686 static int vc4_hdmi_dev_probe(struct platform_device *pdev) 2687 { 2688 return component_add(&pdev->dev, &vc4_hdmi_ops); 2689 } 2690 2691 static int vc4_hdmi_dev_remove(struct platform_device *pdev) 2692 { 2693 component_del(&pdev->dev, &vc4_hdmi_ops); 2694 return 0; 2695 } 2696 2697 static const struct vc4_hdmi_variant bcm2835_variant = { 2698 .encoder_type = VC4_ENCODER_TYPE_HDMI0, 2699 .debugfs_name = "hdmi_regs", 2700 .card_name = "vc4-hdmi", 2701 .max_pixel_clock = 162000000, 2702 .registers = vc4_hdmi_fields, 2703 .num_registers = ARRAY_SIZE(vc4_hdmi_fields), 2704 2705 .init_resources = vc4_hdmi_init_resources, 2706 .csc_setup = vc4_hdmi_csc_setup, 2707 .reset = vc4_hdmi_reset, 2708 .set_timings = vc4_hdmi_set_timings, 2709 .phy_init = vc4_hdmi_phy_init, 2710 .phy_disable = vc4_hdmi_phy_disable, 2711 .phy_rng_enable = vc4_hdmi_phy_rng_enable, 2712 .phy_rng_disable = vc4_hdmi_phy_rng_disable, 2713 .channel_map = vc4_hdmi_channel_map, 2714 .supports_hdr = false, 2715 }; 2716 2717 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = { 2718 .encoder_type = VC4_ENCODER_TYPE_HDMI0, 2719 .debugfs_name = "hdmi0_regs", 2720 .card_name = "vc4-hdmi-0", 2721 .max_pixel_clock = 600000000, 2722 .registers = vc5_hdmi_hdmi0_fields, 2723 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi0_fields), 2724 .phy_lane_mapping = { 2725 PHY_LANE_0, 2726 PHY_LANE_1, 2727 PHY_LANE_2, 2728 PHY_LANE_CK, 2729 }, 2730 .unsupported_odd_h_timings = true, 2731 .external_irq_controller = true, 2732 2733 .init_resources = vc5_hdmi_init_resources, 2734 .csc_setup = vc5_hdmi_csc_setup, 2735 .reset = vc5_hdmi_reset, 2736 .set_timings = vc5_hdmi_set_timings, 2737 .phy_init = vc5_hdmi_phy_init, 2738 .phy_disable = vc5_hdmi_phy_disable, 2739 .phy_rng_enable = vc5_hdmi_phy_rng_enable, 2740 .phy_rng_disable = vc5_hdmi_phy_rng_disable, 2741 .channel_map = vc5_hdmi_channel_map, 2742 .supports_hdr = true, 2743 .hp_detect = vc5_hdmi_hp_detect, 2744 }; 2745 2746 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = { 2747 .encoder_type = VC4_ENCODER_TYPE_HDMI1, 2748 .debugfs_name = "hdmi1_regs", 2749 .card_name = "vc4-hdmi-1", 2750 .max_pixel_clock = HDMI_14_MAX_TMDS_CLK, 2751 .registers = vc5_hdmi_hdmi1_fields, 2752 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi1_fields), 2753 .phy_lane_mapping = { 2754 PHY_LANE_1, 2755 PHY_LANE_0, 2756 PHY_LANE_CK, 2757 PHY_LANE_2, 2758 }, 2759 .unsupported_odd_h_timings = true, 2760 .external_irq_controller = true, 2761 2762 .init_resources = vc5_hdmi_init_resources, 2763 .csc_setup = vc5_hdmi_csc_setup, 2764 .reset = vc5_hdmi_reset, 2765 .set_timings = vc5_hdmi_set_timings, 2766 .phy_init = vc5_hdmi_phy_init, 2767 .phy_disable = vc5_hdmi_phy_disable, 2768 .phy_rng_enable = vc5_hdmi_phy_rng_enable, 2769 .phy_rng_disable = vc5_hdmi_phy_rng_disable, 2770 .channel_map = vc5_hdmi_channel_map, 2771 .supports_hdr = true, 2772 .hp_detect = vc5_hdmi_hp_detect, 2773 }; 2774 2775 static const struct of_device_id vc4_hdmi_dt_match[] = { 2776 { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant }, 2777 { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant }, 2778 { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant }, 2779 {} 2780 }; 2781 2782 static const struct dev_pm_ops vc4_hdmi_pm_ops = { 2783 SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend, 2784 vc4_hdmi_runtime_resume, 2785 NULL) 2786 }; 2787 2788 struct platform_driver vc4_hdmi_driver = { 2789 .probe = vc4_hdmi_dev_probe, 2790 .remove = vc4_hdmi_dev_remove, 2791 .driver = { 2792 .name = "vc4_hdmi", 2793 .of_match_table = vc4_hdmi_dt_match, 2794 .pm = &vc4_hdmi_pm_ops, 2795 }, 2796 }; 2797