1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 Broadcom 4 * Copyright (c) 2014 The Linux Foundation. All rights reserved. 5 * Copyright (C) 2013 Red Hat 6 * Author: Rob Clark <robdclark@gmail.com> 7 */ 8 9 /** 10 * DOC: VC4 Falcon HDMI module 11 * 12 * The HDMI core has a state machine and a PHY. On BCM2835, most of 13 * the unit operates off of the HSM clock from CPRMAN. It also 14 * internally uses the PLLH_PIX clock for the PHY. 15 * 16 * HDMI infoframes are kept within a small packet ram, where each 17 * packet can be individually enabled for including in a frame. 18 * 19 * HDMI audio is implemented entirely within the HDMI IP block. A 20 * register in the HDMI encoder takes SPDIF frames from the DMA engine 21 * and transfers them over an internal MAI (multi-channel audio 22 * interconnect) bus to the encoder side for insertion into the video 23 * blank regions. 24 * 25 * The driver's HDMI encoder does not yet support power management. 26 * The HDMI encoder's power domain and the HSM/pixel clocks are kept 27 * continuously running, and only the HDMI logic and packet ram are 28 * powered off/on at disable/enable time. 29 * 30 * The driver does not yet support CEC control, though the HDMI 31 * encoder block has CEC support. 32 */ 33 34 #include <drm/drm_atomic_helper.h> 35 #include <drm/drm_edid.h> 36 #include <drm/drm_probe_helper.h> 37 #include <linux/clk.h> 38 #include <linux/component.h> 39 #include <linux/i2c.h> 40 #include <linux/of_address.h> 41 #include <linux/of_gpio.h> 42 #include <linux/of_platform.h> 43 #include <linux/pm_runtime.h> 44 #include <linux/rational.h> 45 #include <sound/dmaengine_pcm.h> 46 #include <sound/pcm_drm_eld.h> 47 #include <sound/pcm_params.h> 48 #include <sound/soc.h> 49 #include "media/cec.h" 50 #include "vc4_drv.h" 51 #include "vc4_regs.h" 52 53 #define HSM_CLOCK_FREQ 163682864 54 #define CEC_CLOCK_FREQ 40000 55 #define CEC_CLOCK_DIV (HSM_CLOCK_FREQ / CEC_CLOCK_FREQ) 56 57 /* HDMI audio information */ 58 struct vc4_hdmi_audio { 59 struct snd_soc_card card; 60 struct snd_soc_dai_link link; 61 struct snd_soc_dai_link_component cpu; 62 struct snd_soc_dai_link_component codec; 63 struct snd_soc_dai_link_component platform; 64 int samplerate; 65 int channels; 66 struct snd_dmaengine_dai_dma_data dma_data; 67 struct snd_pcm_substream *substream; 68 }; 69 70 /* General HDMI hardware state. */ 71 struct vc4_hdmi { 72 struct platform_device *pdev; 73 74 struct drm_encoder *encoder; 75 struct drm_connector *connector; 76 77 struct vc4_hdmi_audio audio; 78 79 struct i2c_adapter *ddc; 80 void __iomem *hdmicore_regs; 81 void __iomem *hd_regs; 82 int hpd_gpio; 83 bool hpd_active_low; 84 85 struct cec_adapter *cec_adap; 86 struct cec_msg cec_rx_msg; 87 bool cec_tx_ok; 88 bool cec_irq_was_rx; 89 90 struct clk *pixel_clock; 91 struct clk *hsm_clock; 92 93 struct debugfs_regset32 hdmi_regset; 94 struct debugfs_regset32 hd_regset; 95 }; 96 97 #define HDMI_READ(offset) readl(vc4->hdmi->hdmicore_regs + offset) 98 #define HDMI_WRITE(offset, val) writel(val, vc4->hdmi->hdmicore_regs + offset) 99 #define HD_READ(offset) readl(vc4->hdmi->hd_regs + offset) 100 #define HD_WRITE(offset, val) writel(val, vc4->hdmi->hd_regs + offset) 101 102 /* VC4 HDMI encoder KMS struct */ 103 struct vc4_hdmi_encoder { 104 struct vc4_encoder base; 105 bool hdmi_monitor; 106 bool limited_rgb_range; 107 }; 108 109 static inline struct vc4_hdmi_encoder * 110 to_vc4_hdmi_encoder(struct drm_encoder *encoder) 111 { 112 return container_of(encoder, struct vc4_hdmi_encoder, base.base); 113 } 114 115 /* VC4 HDMI connector KMS struct */ 116 struct vc4_hdmi_connector { 117 struct drm_connector base; 118 119 /* Since the connector is attached to just the one encoder, 120 * this is the reference to it so we can do the best_encoder() 121 * hook. 122 */ 123 struct drm_encoder *encoder; 124 }; 125 126 static inline struct vc4_hdmi_connector * 127 to_vc4_hdmi_connector(struct drm_connector *connector) 128 { 129 return container_of(connector, struct vc4_hdmi_connector, base); 130 } 131 132 static const struct debugfs_reg32 hdmi_regs[] = { 133 VC4_REG32(VC4_HDMI_CORE_REV), 134 VC4_REG32(VC4_HDMI_SW_RESET_CONTROL), 135 VC4_REG32(VC4_HDMI_HOTPLUG_INT), 136 VC4_REG32(VC4_HDMI_HOTPLUG), 137 VC4_REG32(VC4_HDMI_MAI_CHANNEL_MAP), 138 VC4_REG32(VC4_HDMI_MAI_CONFIG), 139 VC4_REG32(VC4_HDMI_MAI_FORMAT), 140 VC4_REG32(VC4_HDMI_AUDIO_PACKET_CONFIG), 141 VC4_REG32(VC4_HDMI_RAM_PACKET_CONFIG), 142 VC4_REG32(VC4_HDMI_HORZA), 143 VC4_REG32(VC4_HDMI_HORZB), 144 VC4_REG32(VC4_HDMI_FIFO_CTL), 145 VC4_REG32(VC4_HDMI_SCHEDULER_CONTROL), 146 VC4_REG32(VC4_HDMI_VERTA0), 147 VC4_REG32(VC4_HDMI_VERTA1), 148 VC4_REG32(VC4_HDMI_VERTB0), 149 VC4_REG32(VC4_HDMI_VERTB1), 150 VC4_REG32(VC4_HDMI_TX_PHY_RESET_CTL), 151 VC4_REG32(VC4_HDMI_TX_PHY_CTL0), 152 153 VC4_REG32(VC4_HDMI_CEC_CNTRL_1), 154 VC4_REG32(VC4_HDMI_CEC_CNTRL_2), 155 VC4_REG32(VC4_HDMI_CEC_CNTRL_3), 156 VC4_REG32(VC4_HDMI_CEC_CNTRL_4), 157 VC4_REG32(VC4_HDMI_CEC_CNTRL_5), 158 VC4_REG32(VC4_HDMI_CPU_STATUS), 159 VC4_REG32(VC4_HDMI_CPU_MASK_STATUS), 160 161 VC4_REG32(VC4_HDMI_CEC_RX_DATA_1), 162 VC4_REG32(VC4_HDMI_CEC_RX_DATA_2), 163 VC4_REG32(VC4_HDMI_CEC_RX_DATA_3), 164 VC4_REG32(VC4_HDMI_CEC_RX_DATA_4), 165 VC4_REG32(VC4_HDMI_CEC_TX_DATA_1), 166 VC4_REG32(VC4_HDMI_CEC_TX_DATA_2), 167 VC4_REG32(VC4_HDMI_CEC_TX_DATA_3), 168 VC4_REG32(VC4_HDMI_CEC_TX_DATA_4), 169 }; 170 171 static const struct debugfs_reg32 hd_regs[] = { 172 VC4_REG32(VC4_HD_M_CTL), 173 VC4_REG32(VC4_HD_MAI_CTL), 174 VC4_REG32(VC4_HD_MAI_THR), 175 VC4_REG32(VC4_HD_MAI_FMT), 176 VC4_REG32(VC4_HD_MAI_SMP), 177 VC4_REG32(VC4_HD_VID_CTL), 178 VC4_REG32(VC4_HD_CSC_CTL), 179 VC4_REG32(VC4_HD_FRAME_COUNT), 180 }; 181 182 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused) 183 { 184 struct drm_info_node *node = (struct drm_info_node *)m->private; 185 struct drm_device *dev = node->minor->dev; 186 struct vc4_dev *vc4 = to_vc4_dev(dev); 187 struct vc4_hdmi *hdmi = vc4->hdmi; 188 struct drm_printer p = drm_seq_file_printer(m); 189 190 drm_print_regset32(&p, &hdmi->hdmi_regset); 191 drm_print_regset32(&p, &hdmi->hd_regset); 192 193 return 0; 194 } 195 196 static enum drm_connector_status 197 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force) 198 { 199 struct drm_device *dev = connector->dev; 200 struct vc4_dev *vc4 = to_vc4_dev(dev); 201 202 if (vc4->hdmi->hpd_gpio) { 203 if (gpio_get_value_cansleep(vc4->hdmi->hpd_gpio) ^ 204 vc4->hdmi->hpd_active_low) 205 return connector_status_connected; 206 cec_phys_addr_invalidate(vc4->hdmi->cec_adap); 207 return connector_status_disconnected; 208 } 209 210 if (drm_probe_ddc(vc4->hdmi->ddc)) 211 return connector_status_connected; 212 213 if (HDMI_READ(VC4_HDMI_HOTPLUG) & VC4_HDMI_HOTPLUG_CONNECTED) 214 return connector_status_connected; 215 cec_phys_addr_invalidate(vc4->hdmi->cec_adap); 216 return connector_status_disconnected; 217 } 218 219 static void vc4_hdmi_connector_destroy(struct drm_connector *connector) 220 { 221 drm_connector_unregister(connector); 222 drm_connector_cleanup(connector); 223 } 224 225 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector) 226 { 227 struct vc4_hdmi_connector *vc4_connector = 228 to_vc4_hdmi_connector(connector); 229 struct drm_encoder *encoder = vc4_connector->encoder; 230 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 231 struct drm_device *dev = connector->dev; 232 struct vc4_dev *vc4 = to_vc4_dev(dev); 233 int ret = 0; 234 struct edid *edid; 235 236 edid = drm_get_edid(connector, vc4->hdmi->ddc); 237 cec_s_phys_addr_from_edid(vc4->hdmi->cec_adap, edid); 238 if (!edid) 239 return -ENODEV; 240 241 vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid); 242 243 drm_connector_update_edid_property(connector, edid); 244 ret = drm_add_edid_modes(connector, edid); 245 kfree(edid); 246 247 return ret; 248 } 249 250 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = { 251 .detect = vc4_hdmi_connector_detect, 252 .fill_modes = drm_helper_probe_single_connector_modes, 253 .destroy = vc4_hdmi_connector_destroy, 254 .reset = drm_atomic_helper_connector_reset, 255 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 256 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 257 }; 258 259 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = { 260 .get_modes = vc4_hdmi_connector_get_modes, 261 }; 262 263 static struct drm_connector *vc4_hdmi_connector_init(struct drm_device *dev, 264 struct drm_encoder *encoder) 265 { 266 struct drm_connector *connector; 267 struct vc4_hdmi_connector *hdmi_connector; 268 int ret; 269 270 hdmi_connector = devm_kzalloc(dev->dev, sizeof(*hdmi_connector), 271 GFP_KERNEL); 272 if (!hdmi_connector) 273 return ERR_PTR(-ENOMEM); 274 connector = &hdmi_connector->base; 275 276 hdmi_connector->encoder = encoder; 277 278 drm_connector_init(dev, connector, &vc4_hdmi_connector_funcs, 279 DRM_MODE_CONNECTOR_HDMIA); 280 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs); 281 282 /* Create and attach TV margin props to this connector. */ 283 ret = drm_mode_create_tv_margin_properties(dev); 284 if (ret) 285 return ERR_PTR(ret); 286 287 drm_connector_attach_tv_margin_properties(connector); 288 289 connector->polled = (DRM_CONNECTOR_POLL_CONNECT | 290 DRM_CONNECTOR_POLL_DISCONNECT); 291 292 connector->interlace_allowed = 1; 293 connector->doublescan_allowed = 0; 294 295 drm_connector_attach_encoder(connector, encoder); 296 297 return connector; 298 } 299 300 static void vc4_hdmi_encoder_destroy(struct drm_encoder *encoder) 301 { 302 drm_encoder_cleanup(encoder); 303 } 304 305 static const struct drm_encoder_funcs vc4_hdmi_encoder_funcs = { 306 .destroy = vc4_hdmi_encoder_destroy, 307 }; 308 309 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder, 310 enum hdmi_infoframe_type type) 311 { 312 struct drm_device *dev = encoder->dev; 313 struct vc4_dev *vc4 = to_vc4_dev(dev); 314 u32 packet_id = type - 0x80; 315 316 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, 317 HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id)); 318 319 return wait_for(!(HDMI_READ(VC4_HDMI_RAM_PACKET_STATUS) & 320 BIT(packet_id)), 100); 321 } 322 323 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder, 324 union hdmi_infoframe *frame) 325 { 326 struct drm_device *dev = encoder->dev; 327 struct vc4_dev *vc4 = to_vc4_dev(dev); 328 u32 packet_id = frame->any.type - 0x80; 329 u32 packet_reg = VC4_HDMI_RAM_PACKET(packet_id); 330 uint8_t buffer[VC4_HDMI_PACKET_STRIDE]; 331 ssize_t len, i; 332 int ret; 333 334 WARN_ONCE(!(HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) & 335 VC4_HDMI_RAM_PACKET_ENABLE), 336 "Packet RAM has to be on to store the packet."); 337 338 len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer)); 339 if (len < 0) 340 return; 341 342 ret = vc4_hdmi_stop_packet(encoder, frame->any.type); 343 if (ret) { 344 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret); 345 return; 346 } 347 348 for (i = 0; i < len; i += 7) { 349 HDMI_WRITE(packet_reg, 350 buffer[i + 0] << 0 | 351 buffer[i + 1] << 8 | 352 buffer[i + 2] << 16); 353 packet_reg += 4; 354 355 HDMI_WRITE(packet_reg, 356 buffer[i + 3] << 0 | 357 buffer[i + 4] << 8 | 358 buffer[i + 5] << 16 | 359 buffer[i + 6] << 24); 360 packet_reg += 4; 361 } 362 363 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, 364 HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) | BIT(packet_id)); 365 ret = wait_for((HDMI_READ(VC4_HDMI_RAM_PACKET_STATUS) & 366 BIT(packet_id)), 100); 367 if (ret) 368 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret); 369 } 370 371 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder) 372 { 373 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 374 struct vc4_dev *vc4 = encoder->dev->dev_private; 375 struct vc4_hdmi *hdmi = vc4->hdmi; 376 struct drm_connector_state *cstate = hdmi->connector->state; 377 struct drm_crtc *crtc = encoder->crtc; 378 const struct drm_display_mode *mode = &crtc->state->adjusted_mode; 379 union hdmi_infoframe frame; 380 int ret; 381 382 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, 383 hdmi->connector, mode); 384 if (ret < 0) { 385 DRM_ERROR("couldn't fill AVI infoframe\n"); 386 return; 387 } 388 389 drm_hdmi_avi_infoframe_quant_range(&frame.avi, 390 hdmi->connector, mode, 391 vc4_encoder->limited_rgb_range ? 392 HDMI_QUANTIZATION_RANGE_LIMITED : 393 HDMI_QUANTIZATION_RANGE_FULL); 394 395 frame.avi.right_bar = cstate->tv.margins.right; 396 frame.avi.left_bar = cstate->tv.margins.left; 397 frame.avi.top_bar = cstate->tv.margins.top; 398 frame.avi.bottom_bar = cstate->tv.margins.bottom; 399 400 vc4_hdmi_write_infoframe(encoder, &frame); 401 } 402 403 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder) 404 { 405 union hdmi_infoframe frame; 406 int ret; 407 408 ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore"); 409 if (ret < 0) { 410 DRM_ERROR("couldn't fill SPD infoframe\n"); 411 return; 412 } 413 414 frame.spd.sdi = HDMI_SPD_SDI_PC; 415 416 vc4_hdmi_write_infoframe(encoder, &frame); 417 } 418 419 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder) 420 { 421 struct drm_device *drm = encoder->dev; 422 struct vc4_dev *vc4 = drm->dev_private; 423 struct vc4_hdmi *hdmi = vc4->hdmi; 424 union hdmi_infoframe frame; 425 int ret; 426 427 ret = hdmi_audio_infoframe_init(&frame.audio); 428 429 frame.audio.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM; 430 frame.audio.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM; 431 frame.audio.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM; 432 frame.audio.channels = hdmi->audio.channels; 433 434 vc4_hdmi_write_infoframe(encoder, &frame); 435 } 436 437 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder) 438 { 439 vc4_hdmi_set_avi_infoframe(encoder); 440 vc4_hdmi_set_spd_infoframe(encoder); 441 } 442 443 static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder) 444 { 445 struct drm_device *dev = encoder->dev; 446 struct vc4_dev *vc4 = to_vc4_dev(dev); 447 struct vc4_hdmi *hdmi = vc4->hdmi; 448 int ret; 449 450 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, 0); 451 452 HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16); 453 HD_WRITE(VC4_HD_VID_CTL, 454 HD_READ(VC4_HD_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE); 455 456 clk_disable_unprepare(hdmi->pixel_clock); 457 458 ret = pm_runtime_put(&hdmi->pdev->dev); 459 if (ret < 0) 460 DRM_ERROR("Failed to release power domain: %d\n", ret); 461 } 462 463 static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder) 464 { 465 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; 466 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 467 struct drm_device *dev = encoder->dev; 468 struct vc4_dev *vc4 = to_vc4_dev(dev); 469 struct vc4_hdmi *hdmi = vc4->hdmi; 470 bool debug_dump_regs = false; 471 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 472 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 473 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 474 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 475 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 476 VC4_HDMI_VERTA_VSP) | 477 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 478 VC4_HDMI_VERTA_VFP) | 479 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL)); 480 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 481 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end, 482 VC4_HDMI_VERTB_VBP)); 483 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 484 VC4_SET_FIELD(mode->crtc_vtotal - 485 mode->crtc_vsync_end - 486 interlaced, 487 VC4_HDMI_VERTB_VBP)); 488 u32 csc_ctl; 489 int ret; 490 491 ret = pm_runtime_get_sync(&hdmi->pdev->dev); 492 if (ret < 0) { 493 DRM_ERROR("Failed to retain power domain: %d\n", ret); 494 return; 495 } 496 497 ret = clk_set_rate(hdmi->pixel_clock, 498 mode->clock * 1000 * 499 ((mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1)); 500 if (ret) { 501 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret); 502 return; 503 } 504 505 ret = clk_prepare_enable(hdmi->pixel_clock); 506 if (ret) { 507 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret); 508 return; 509 } 510 511 HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL, 512 VC4_HDMI_SW_RESET_HDMI | 513 VC4_HDMI_SW_RESET_FORMAT_DETECT); 514 515 HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL, 0); 516 517 /* PHY should be in reset, like 518 * vc4_hdmi_encoder_disable() does. 519 */ 520 HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16); 521 522 HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0); 523 524 if (debug_dump_regs) { 525 struct drm_printer p = drm_info_printer(&hdmi->pdev->dev); 526 527 dev_info(&hdmi->pdev->dev, "HDMI regs before:\n"); 528 drm_print_regset32(&p, &hdmi->hdmi_regset); 529 drm_print_regset32(&p, &hdmi->hd_regset); 530 } 531 532 HD_WRITE(VC4_HD_VID_CTL, 0); 533 534 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL, 535 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) | 536 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT | 537 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS); 538 539 HDMI_WRITE(VC4_HDMI_HORZA, 540 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) | 541 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) | 542 VC4_SET_FIELD(mode->hdisplay * pixel_rep, 543 VC4_HDMI_HORZA_HAP)); 544 545 HDMI_WRITE(VC4_HDMI_HORZB, 546 VC4_SET_FIELD((mode->htotal - 547 mode->hsync_end) * pixel_rep, 548 VC4_HDMI_HORZB_HBP) | 549 VC4_SET_FIELD((mode->hsync_end - 550 mode->hsync_start) * pixel_rep, 551 VC4_HDMI_HORZB_HSP) | 552 VC4_SET_FIELD((mode->hsync_start - 553 mode->hdisplay) * pixel_rep, 554 VC4_HDMI_HORZB_HFP)); 555 556 HDMI_WRITE(VC4_HDMI_VERTA0, verta); 557 HDMI_WRITE(VC4_HDMI_VERTA1, verta); 558 559 HDMI_WRITE(VC4_HDMI_VERTB0, vertb_even); 560 HDMI_WRITE(VC4_HDMI_VERTB1, vertb); 561 562 HD_WRITE(VC4_HD_VID_CTL, 563 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) | 564 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW)); 565 566 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR, 567 VC4_HD_CSC_CTL_ORDER); 568 569 if (vc4_encoder->hdmi_monitor && 570 drm_default_rgb_quant_range(mode) == 571 HDMI_QUANTIZATION_RANGE_LIMITED) { 572 /* CEA VICs other than #1 requre limited range RGB 573 * output unless overridden by an AVI infoframe. 574 * Apply a colorspace conversion to squash 0-255 down 575 * to 16-235. The matrix here is: 576 * 577 * [ 0 0 0.8594 16] 578 * [ 0 0.8594 0 16] 579 * [ 0.8594 0 0 16] 580 * [ 0 0 0 1] 581 */ 582 csc_ctl |= VC4_HD_CSC_CTL_ENABLE; 583 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC; 584 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM, 585 VC4_HD_CSC_CTL_MODE); 586 587 HD_WRITE(VC4_HD_CSC_12_11, (0x000 << 16) | 0x000); 588 HD_WRITE(VC4_HD_CSC_14_13, (0x100 << 16) | 0x6e0); 589 HD_WRITE(VC4_HD_CSC_22_21, (0x6e0 << 16) | 0x000); 590 HD_WRITE(VC4_HD_CSC_24_23, (0x100 << 16) | 0x000); 591 HD_WRITE(VC4_HD_CSC_32_31, (0x000 << 16) | 0x6e0); 592 HD_WRITE(VC4_HD_CSC_34_33, (0x100 << 16) | 0x000); 593 vc4_encoder->limited_rgb_range = true; 594 } else { 595 vc4_encoder->limited_rgb_range = false; 596 } 597 598 /* The RGB order applies even when CSC is disabled. */ 599 HD_WRITE(VC4_HD_CSC_CTL, csc_ctl); 600 601 HDMI_WRITE(VC4_HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N); 602 603 if (debug_dump_regs) { 604 struct drm_printer p = drm_info_printer(&hdmi->pdev->dev); 605 606 dev_info(&hdmi->pdev->dev, "HDMI regs after:\n"); 607 drm_print_regset32(&p, &hdmi->hdmi_regset); 608 drm_print_regset32(&p, &hdmi->hd_regset); 609 } 610 611 HD_WRITE(VC4_HD_VID_CTL, 612 HD_READ(VC4_HD_VID_CTL) | 613 VC4_HD_VID_CTL_ENABLE | 614 VC4_HD_VID_CTL_UNDERFLOW_ENABLE | 615 VC4_HD_VID_CTL_FRAME_COUNTER_RESET); 616 617 if (vc4_encoder->hdmi_monitor) { 618 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL, 619 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) | 620 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 621 622 ret = wait_for(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) & 623 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000); 624 WARN_ONCE(ret, "Timeout waiting for " 625 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 626 } else { 627 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, 628 HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) & 629 ~(VC4_HDMI_RAM_PACKET_ENABLE)); 630 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL, 631 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) & 632 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 633 634 ret = wait_for(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) & 635 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000); 636 WARN_ONCE(ret, "Timeout waiting for " 637 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 638 } 639 640 if (vc4_encoder->hdmi_monitor) { 641 u32 drift; 642 643 WARN_ON(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) & 644 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE)); 645 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL, 646 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) | 647 VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT); 648 649 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, 650 VC4_HDMI_RAM_PACKET_ENABLE); 651 652 vc4_hdmi_set_infoframes(encoder); 653 654 drift = HDMI_READ(VC4_HDMI_FIFO_CTL); 655 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK; 656 657 HDMI_WRITE(VC4_HDMI_FIFO_CTL, 658 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 659 HDMI_WRITE(VC4_HDMI_FIFO_CTL, 660 drift | VC4_HDMI_FIFO_CTL_RECENTER); 661 usleep_range(1000, 1100); 662 HDMI_WRITE(VC4_HDMI_FIFO_CTL, 663 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 664 HDMI_WRITE(VC4_HDMI_FIFO_CTL, 665 drift | VC4_HDMI_FIFO_CTL_RECENTER); 666 667 ret = wait_for(HDMI_READ(VC4_HDMI_FIFO_CTL) & 668 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1); 669 WARN_ONCE(ret, "Timeout waiting for " 670 "VC4_HDMI_FIFO_CTL_RECENTER_DONE"); 671 } 672 } 673 674 static enum drm_mode_status 675 vc4_hdmi_encoder_mode_valid(struct drm_encoder *crtc, 676 const struct drm_display_mode *mode) 677 { 678 /* HSM clock must be 108% of the pixel clock. Additionally, 679 * the AXI clock needs to be at least 25% of pixel clock, but 680 * HSM ends up being the limiting factor. 681 */ 682 if (mode->clock > HSM_CLOCK_FREQ / (1000 * 108 / 100)) 683 return MODE_CLOCK_HIGH; 684 685 return MODE_OK; 686 } 687 688 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = { 689 .mode_valid = vc4_hdmi_encoder_mode_valid, 690 .disable = vc4_hdmi_encoder_disable, 691 .enable = vc4_hdmi_encoder_enable, 692 }; 693 694 /* HDMI audio codec callbacks */ 695 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *hdmi) 696 { 697 struct drm_device *drm = hdmi->encoder->dev; 698 struct vc4_dev *vc4 = to_vc4_dev(drm); 699 u32 hsm_clock = clk_get_rate(hdmi->hsm_clock); 700 unsigned long n, m; 701 702 rational_best_approximation(hsm_clock, hdmi->audio.samplerate, 703 VC4_HD_MAI_SMP_N_MASK >> 704 VC4_HD_MAI_SMP_N_SHIFT, 705 (VC4_HD_MAI_SMP_M_MASK >> 706 VC4_HD_MAI_SMP_M_SHIFT) + 1, 707 &n, &m); 708 709 HD_WRITE(VC4_HD_MAI_SMP, 710 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) | 711 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M)); 712 } 713 714 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *hdmi) 715 { 716 struct drm_encoder *encoder = hdmi->encoder; 717 struct drm_crtc *crtc = encoder->crtc; 718 struct drm_device *drm = encoder->dev; 719 struct vc4_dev *vc4 = to_vc4_dev(drm); 720 const struct drm_display_mode *mode = &crtc->state->adjusted_mode; 721 u32 samplerate = hdmi->audio.samplerate; 722 u32 n, cts; 723 u64 tmp; 724 725 n = 128 * samplerate / 1000; 726 tmp = (u64)(mode->clock * 1000) * n; 727 do_div(tmp, 128 * samplerate); 728 cts = tmp; 729 730 HDMI_WRITE(VC4_HDMI_CRP_CFG, 731 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN | 732 VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N)); 733 734 /* 735 * We could get slightly more accurate clocks in some cases by 736 * providing a CTS_1 value. The two CTS values are alternated 737 * between based on the period fields 738 */ 739 HDMI_WRITE(VC4_HDMI_CTS_0, cts); 740 HDMI_WRITE(VC4_HDMI_CTS_1, cts); 741 } 742 743 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai) 744 { 745 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai); 746 747 return snd_soc_card_get_drvdata(card); 748 } 749 750 static int vc4_hdmi_audio_startup(struct snd_pcm_substream *substream, 751 struct snd_soc_dai *dai) 752 { 753 struct vc4_hdmi *hdmi = dai_to_hdmi(dai); 754 struct drm_encoder *encoder = hdmi->encoder; 755 struct vc4_dev *vc4 = to_vc4_dev(encoder->dev); 756 int ret; 757 758 if (hdmi->audio.substream && hdmi->audio.substream != substream) 759 return -EINVAL; 760 761 hdmi->audio.substream = substream; 762 763 /* 764 * If the HDMI encoder hasn't probed, or the encoder is 765 * currently in DVI mode, treat the codec dai as missing. 766 */ 767 if (!encoder->crtc || !(HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) & 768 VC4_HDMI_RAM_PACKET_ENABLE)) 769 return -ENODEV; 770 771 ret = snd_pcm_hw_constraint_eld(substream->runtime, 772 hdmi->connector->eld); 773 if (ret) 774 return ret; 775 776 return 0; 777 } 778 779 static int vc4_hdmi_audio_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 780 { 781 return 0; 782 } 783 784 static void vc4_hdmi_audio_reset(struct vc4_hdmi *hdmi) 785 { 786 struct drm_encoder *encoder = hdmi->encoder; 787 struct drm_device *drm = encoder->dev; 788 struct device *dev = &hdmi->pdev->dev; 789 struct vc4_dev *vc4 = to_vc4_dev(drm); 790 int ret; 791 792 ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO); 793 if (ret) 794 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret); 795 796 HD_WRITE(VC4_HD_MAI_CTL, VC4_HD_MAI_CTL_RESET); 797 HD_WRITE(VC4_HD_MAI_CTL, VC4_HD_MAI_CTL_ERRORF); 798 HD_WRITE(VC4_HD_MAI_CTL, VC4_HD_MAI_CTL_FLUSH); 799 } 800 801 static void vc4_hdmi_audio_shutdown(struct snd_pcm_substream *substream, 802 struct snd_soc_dai *dai) 803 { 804 struct vc4_hdmi *hdmi = dai_to_hdmi(dai); 805 806 if (substream != hdmi->audio.substream) 807 return; 808 809 vc4_hdmi_audio_reset(hdmi); 810 811 hdmi->audio.substream = NULL; 812 } 813 814 /* HDMI audio codec callbacks */ 815 static int vc4_hdmi_audio_hw_params(struct snd_pcm_substream *substream, 816 struct snd_pcm_hw_params *params, 817 struct snd_soc_dai *dai) 818 { 819 struct vc4_hdmi *hdmi = dai_to_hdmi(dai); 820 struct drm_encoder *encoder = hdmi->encoder; 821 struct drm_device *drm = encoder->dev; 822 struct device *dev = &hdmi->pdev->dev; 823 struct vc4_dev *vc4 = to_vc4_dev(drm); 824 u32 audio_packet_config, channel_mask; 825 u32 channel_map, i; 826 827 if (substream != hdmi->audio.substream) 828 return -EINVAL; 829 830 dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__, 831 params_rate(params), params_width(params), 832 params_channels(params)); 833 834 hdmi->audio.channels = params_channels(params); 835 hdmi->audio.samplerate = params_rate(params); 836 837 HD_WRITE(VC4_HD_MAI_CTL, 838 VC4_HD_MAI_CTL_RESET | 839 VC4_HD_MAI_CTL_FLUSH | 840 VC4_HD_MAI_CTL_DLATE | 841 VC4_HD_MAI_CTL_ERRORE | 842 VC4_HD_MAI_CTL_ERRORF); 843 844 vc4_hdmi_audio_set_mai_clock(hdmi); 845 846 audio_packet_config = 847 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT | 848 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS | 849 VC4_SET_FIELD(0xf, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER); 850 851 channel_mask = GENMASK(hdmi->audio.channels - 1, 0); 852 audio_packet_config |= VC4_SET_FIELD(channel_mask, 853 VC4_HDMI_AUDIO_PACKET_CEA_MASK); 854 855 /* Set the MAI threshold. This logic mimics the firmware's. */ 856 if (hdmi->audio.samplerate > 96000) { 857 HD_WRITE(VC4_HD_MAI_THR, 858 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQHIGH) | 859 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW)); 860 } else if (hdmi->audio.samplerate > 48000) { 861 HD_WRITE(VC4_HD_MAI_THR, 862 VC4_SET_FIELD(0x14, VC4_HD_MAI_THR_DREQHIGH) | 863 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW)); 864 } else { 865 HD_WRITE(VC4_HD_MAI_THR, 866 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) | 867 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) | 868 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQHIGH) | 869 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQLOW)); 870 } 871 872 HDMI_WRITE(VC4_HDMI_MAI_CONFIG, 873 VC4_HDMI_MAI_CONFIG_BIT_REVERSE | 874 VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK)); 875 876 channel_map = 0; 877 for (i = 0; i < 8; i++) { 878 if (channel_mask & BIT(i)) 879 channel_map |= i << (3 * i); 880 } 881 882 HDMI_WRITE(VC4_HDMI_MAI_CHANNEL_MAP, channel_map); 883 HDMI_WRITE(VC4_HDMI_AUDIO_PACKET_CONFIG, audio_packet_config); 884 vc4_hdmi_set_n_cts(hdmi); 885 886 return 0; 887 } 888 889 static int vc4_hdmi_audio_trigger(struct snd_pcm_substream *substream, int cmd, 890 struct snd_soc_dai *dai) 891 { 892 struct vc4_hdmi *hdmi = dai_to_hdmi(dai); 893 struct drm_encoder *encoder = hdmi->encoder; 894 struct drm_device *drm = encoder->dev; 895 struct vc4_dev *vc4 = to_vc4_dev(drm); 896 897 switch (cmd) { 898 case SNDRV_PCM_TRIGGER_START: 899 vc4_hdmi_set_audio_infoframe(encoder); 900 HDMI_WRITE(VC4_HDMI_TX_PHY_CTL0, 901 HDMI_READ(VC4_HDMI_TX_PHY_CTL0) & 902 ~VC4_HDMI_TX_PHY_RNG_PWRDN); 903 HD_WRITE(VC4_HD_MAI_CTL, 904 VC4_SET_FIELD(hdmi->audio.channels, 905 VC4_HD_MAI_CTL_CHNUM) | 906 VC4_HD_MAI_CTL_ENABLE); 907 break; 908 case SNDRV_PCM_TRIGGER_STOP: 909 HD_WRITE(VC4_HD_MAI_CTL, 910 VC4_HD_MAI_CTL_DLATE | 911 VC4_HD_MAI_CTL_ERRORE | 912 VC4_HD_MAI_CTL_ERRORF); 913 HDMI_WRITE(VC4_HDMI_TX_PHY_CTL0, 914 HDMI_READ(VC4_HDMI_TX_PHY_CTL0) | 915 VC4_HDMI_TX_PHY_RNG_PWRDN); 916 break; 917 default: 918 break; 919 } 920 921 return 0; 922 } 923 924 static inline struct vc4_hdmi * 925 snd_component_to_hdmi(struct snd_soc_component *component) 926 { 927 struct snd_soc_card *card = snd_soc_component_get_drvdata(component); 928 929 return snd_soc_card_get_drvdata(card); 930 } 931 932 static int vc4_hdmi_audio_eld_ctl_info(struct snd_kcontrol *kcontrol, 933 struct snd_ctl_elem_info *uinfo) 934 { 935 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 936 struct vc4_hdmi *hdmi = snd_component_to_hdmi(component); 937 938 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 939 uinfo->count = sizeof(hdmi->connector->eld); 940 941 return 0; 942 } 943 944 static int vc4_hdmi_audio_eld_ctl_get(struct snd_kcontrol *kcontrol, 945 struct snd_ctl_elem_value *ucontrol) 946 { 947 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 948 struct vc4_hdmi *hdmi = snd_component_to_hdmi(component); 949 950 memcpy(ucontrol->value.bytes.data, hdmi->connector->eld, 951 sizeof(hdmi->connector->eld)); 952 953 return 0; 954 } 955 956 static const struct snd_kcontrol_new vc4_hdmi_audio_controls[] = { 957 { 958 .access = SNDRV_CTL_ELEM_ACCESS_READ | 959 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 960 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 961 .name = "ELD", 962 .info = vc4_hdmi_audio_eld_ctl_info, 963 .get = vc4_hdmi_audio_eld_ctl_get, 964 }, 965 }; 966 967 static const struct snd_soc_dapm_widget vc4_hdmi_audio_widgets[] = { 968 SND_SOC_DAPM_OUTPUT("TX"), 969 }; 970 971 static const struct snd_soc_dapm_route vc4_hdmi_audio_routes[] = { 972 { "TX", NULL, "Playback" }, 973 }; 974 975 static const struct snd_soc_component_driver vc4_hdmi_audio_component_drv = { 976 .controls = vc4_hdmi_audio_controls, 977 .num_controls = ARRAY_SIZE(vc4_hdmi_audio_controls), 978 .dapm_widgets = vc4_hdmi_audio_widgets, 979 .num_dapm_widgets = ARRAY_SIZE(vc4_hdmi_audio_widgets), 980 .dapm_routes = vc4_hdmi_audio_routes, 981 .num_dapm_routes = ARRAY_SIZE(vc4_hdmi_audio_routes), 982 .idle_bias_on = 1, 983 .use_pmdown_time = 1, 984 .endianness = 1, 985 .non_legacy_dai_naming = 1, 986 }; 987 988 static const struct snd_soc_dai_ops vc4_hdmi_audio_dai_ops = { 989 .startup = vc4_hdmi_audio_startup, 990 .shutdown = vc4_hdmi_audio_shutdown, 991 .hw_params = vc4_hdmi_audio_hw_params, 992 .set_fmt = vc4_hdmi_audio_set_fmt, 993 .trigger = vc4_hdmi_audio_trigger, 994 }; 995 996 static struct snd_soc_dai_driver vc4_hdmi_audio_codec_dai_drv = { 997 .name = "vc4-hdmi-hifi", 998 .playback = { 999 .stream_name = "Playback", 1000 .channels_min = 2, 1001 .channels_max = 8, 1002 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 1003 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 1004 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 1005 SNDRV_PCM_RATE_192000, 1006 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 1007 }, 1008 }; 1009 1010 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = { 1011 .name = "vc4-hdmi-cpu-dai-component", 1012 }; 1013 1014 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai) 1015 { 1016 struct vc4_hdmi *hdmi = dai_to_hdmi(dai); 1017 1018 snd_soc_dai_init_dma_data(dai, &hdmi->audio.dma_data, NULL); 1019 1020 return 0; 1021 } 1022 1023 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = { 1024 .name = "vc4-hdmi-cpu-dai", 1025 .probe = vc4_hdmi_audio_cpu_dai_probe, 1026 .playback = { 1027 .stream_name = "Playback", 1028 .channels_min = 1, 1029 .channels_max = 8, 1030 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 1031 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 1032 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 1033 SNDRV_PCM_RATE_192000, 1034 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 1035 }, 1036 .ops = &vc4_hdmi_audio_dai_ops, 1037 }; 1038 1039 static const struct snd_dmaengine_pcm_config pcm_conf = { 1040 .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx", 1041 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 1042 }; 1043 1044 static int vc4_hdmi_audio_init(struct vc4_hdmi *hdmi) 1045 { 1046 struct snd_soc_dai_link *dai_link = &hdmi->audio.link; 1047 struct snd_soc_card *card = &hdmi->audio.card; 1048 struct device *dev = &hdmi->pdev->dev; 1049 const __be32 *addr; 1050 int ret; 1051 1052 if (!of_find_property(dev->of_node, "dmas", NULL)) { 1053 dev_warn(dev, 1054 "'dmas' DT property is missing, no HDMI audio\n"); 1055 return 0; 1056 } 1057 1058 /* 1059 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve 1060 * the bus address specified in the DT, because the physical address 1061 * (the one returned by platform_get_resource()) is not appropriate 1062 * for DMA transfers. 1063 * This VC/MMU should probably be exposed to avoid this kind of hacks. 1064 */ 1065 addr = of_get_address(dev->of_node, 1, NULL, NULL); 1066 hdmi->audio.dma_data.addr = be32_to_cpup(addr) + VC4_HD_MAI_DATA; 1067 hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1068 hdmi->audio.dma_data.maxburst = 2; 1069 1070 ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0); 1071 if (ret) { 1072 dev_err(dev, "Could not register PCM component: %d\n", ret); 1073 return ret; 1074 } 1075 1076 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp, 1077 &vc4_hdmi_audio_cpu_dai_drv, 1); 1078 if (ret) { 1079 dev_err(dev, "Could not register CPU DAI: %d\n", ret); 1080 return ret; 1081 } 1082 1083 /* register component and codec dai */ 1084 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_component_drv, 1085 &vc4_hdmi_audio_codec_dai_drv, 1); 1086 if (ret) { 1087 dev_err(dev, "Could not register component: %d\n", ret); 1088 return ret; 1089 } 1090 1091 dai_link->cpus = &hdmi->audio.cpu; 1092 dai_link->codecs = &hdmi->audio.codec; 1093 dai_link->platforms = &hdmi->audio.platform; 1094 1095 dai_link->num_cpus = 1; 1096 dai_link->num_codecs = 1; 1097 dai_link->num_platforms = 1; 1098 1099 dai_link->name = "MAI"; 1100 dai_link->stream_name = "MAI PCM"; 1101 dai_link->codecs->dai_name = vc4_hdmi_audio_codec_dai_drv.name; 1102 dai_link->cpus->dai_name = dev_name(dev); 1103 dai_link->codecs->name = dev_name(dev); 1104 dai_link->platforms->name = dev_name(dev); 1105 1106 card->dai_link = dai_link; 1107 card->num_links = 1; 1108 card->name = "vc4-hdmi"; 1109 card->dev = dev; 1110 1111 /* 1112 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and 1113 * stores a pointer to the snd card object in dev->driver_data. This 1114 * means we cannot use it for something else. The hdmi back-pointer is 1115 * now stored in card->drvdata and should be retrieved with 1116 * snd_soc_card_get_drvdata() if needed. 1117 */ 1118 snd_soc_card_set_drvdata(card, hdmi); 1119 ret = devm_snd_soc_register_card(dev, card); 1120 if (ret) 1121 dev_err(dev, "Could not register sound card: %d\n", ret); 1122 1123 return ret; 1124 1125 } 1126 1127 #ifdef CONFIG_DRM_VC4_HDMI_CEC 1128 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv) 1129 { 1130 struct vc4_dev *vc4 = priv; 1131 struct vc4_hdmi *hdmi = vc4->hdmi; 1132 1133 if (hdmi->cec_irq_was_rx) { 1134 if (hdmi->cec_rx_msg.len) 1135 cec_received_msg(hdmi->cec_adap, &hdmi->cec_rx_msg); 1136 } else if (hdmi->cec_tx_ok) { 1137 cec_transmit_done(hdmi->cec_adap, CEC_TX_STATUS_OK, 1138 0, 0, 0, 0); 1139 } else { 1140 /* 1141 * This CEC implementation makes 1 retry, so if we 1142 * get a NACK, then that means it made 2 attempts. 1143 */ 1144 cec_transmit_done(hdmi->cec_adap, CEC_TX_STATUS_NACK, 1145 0, 2, 0, 0); 1146 } 1147 return IRQ_HANDLED; 1148 } 1149 1150 static void vc4_cec_read_msg(struct vc4_dev *vc4, u32 cntrl1) 1151 { 1152 struct cec_msg *msg = &vc4->hdmi->cec_rx_msg; 1153 unsigned int i; 1154 1155 msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >> 1156 VC4_HDMI_CEC_REC_WRD_CNT_SHIFT); 1157 for (i = 0; i < msg->len; i += 4) { 1158 u32 val = HDMI_READ(VC4_HDMI_CEC_RX_DATA_1 + i); 1159 1160 msg->msg[i] = val & 0xff; 1161 msg->msg[i + 1] = (val >> 8) & 0xff; 1162 msg->msg[i + 2] = (val >> 16) & 0xff; 1163 msg->msg[i + 3] = (val >> 24) & 0xff; 1164 } 1165 } 1166 1167 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv) 1168 { 1169 struct vc4_dev *vc4 = priv; 1170 struct vc4_hdmi *hdmi = vc4->hdmi; 1171 u32 stat = HDMI_READ(VC4_HDMI_CPU_STATUS); 1172 u32 cntrl1, cntrl5; 1173 1174 if (!(stat & VC4_HDMI_CPU_CEC)) 1175 return IRQ_NONE; 1176 hdmi->cec_rx_msg.len = 0; 1177 cntrl1 = HDMI_READ(VC4_HDMI_CEC_CNTRL_1); 1178 cntrl5 = HDMI_READ(VC4_HDMI_CEC_CNTRL_5); 1179 hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT; 1180 if (hdmi->cec_irq_was_rx) { 1181 vc4_cec_read_msg(vc4, cntrl1); 1182 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 1183 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, cntrl1); 1184 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 1185 } else { 1186 hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD; 1187 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 1188 } 1189 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, cntrl1); 1190 HDMI_WRITE(VC4_HDMI_CPU_CLEAR, VC4_HDMI_CPU_CEC); 1191 1192 return IRQ_WAKE_THREAD; 1193 } 1194 1195 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable) 1196 { 1197 struct vc4_dev *vc4 = cec_get_drvdata(adap); 1198 /* clock period in microseconds */ 1199 const u32 usecs = 1000000 / CEC_CLOCK_FREQ; 1200 u32 val = HDMI_READ(VC4_HDMI_CEC_CNTRL_5); 1201 1202 val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET | 1203 VC4_HDMI_CEC_CNT_TO_4700_US_MASK | 1204 VC4_HDMI_CEC_CNT_TO_4500_US_MASK); 1205 val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) | 1206 ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT); 1207 1208 if (enable) { 1209 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_5, val | 1210 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 1211 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_5, val); 1212 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_2, 1213 ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) | 1214 ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) | 1215 ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) | 1216 ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) | 1217 ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT)); 1218 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_3, 1219 ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) | 1220 ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) | 1221 ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) | 1222 ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT)); 1223 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_4, 1224 ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) | 1225 ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) | 1226 ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) | 1227 ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT)); 1228 1229 HDMI_WRITE(VC4_HDMI_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC); 1230 } else { 1231 HDMI_WRITE(VC4_HDMI_CPU_MASK_SET, VC4_HDMI_CPU_CEC); 1232 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_5, val | 1233 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 1234 } 1235 return 0; 1236 } 1237 1238 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr) 1239 { 1240 struct vc4_dev *vc4 = cec_get_drvdata(adap); 1241 1242 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, 1243 (HDMI_READ(VC4_HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) | 1244 (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT); 1245 return 0; 1246 } 1247 1248 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts, 1249 u32 signal_free_time, struct cec_msg *msg) 1250 { 1251 struct vc4_dev *vc4 = cec_get_drvdata(adap); 1252 u32 val; 1253 unsigned int i; 1254 1255 for (i = 0; i < msg->len; i += 4) 1256 HDMI_WRITE(VC4_HDMI_CEC_TX_DATA_1 + i, 1257 (msg->msg[i]) | 1258 (msg->msg[i + 1] << 8) | 1259 (msg->msg[i + 2] << 16) | 1260 (msg->msg[i + 3] << 24)); 1261 1262 val = HDMI_READ(VC4_HDMI_CEC_CNTRL_1); 1263 val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 1264 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, val); 1265 val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK; 1266 val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT; 1267 val |= VC4_HDMI_CEC_START_XMIT_BEGIN; 1268 1269 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, val); 1270 return 0; 1271 } 1272 1273 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = { 1274 .adap_enable = vc4_hdmi_cec_adap_enable, 1275 .adap_log_addr = vc4_hdmi_cec_adap_log_addr, 1276 .adap_transmit = vc4_hdmi_cec_adap_transmit, 1277 }; 1278 #endif 1279 1280 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data) 1281 { 1282 struct platform_device *pdev = to_platform_device(dev); 1283 struct drm_device *drm = dev_get_drvdata(master); 1284 struct vc4_dev *vc4 = drm->dev_private; 1285 struct vc4_hdmi *hdmi; 1286 struct vc4_hdmi_encoder *vc4_hdmi_encoder; 1287 struct device_node *ddc_node; 1288 u32 value; 1289 int ret; 1290 1291 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); 1292 if (!hdmi) 1293 return -ENOMEM; 1294 1295 vc4_hdmi_encoder = devm_kzalloc(dev, sizeof(*vc4_hdmi_encoder), 1296 GFP_KERNEL); 1297 if (!vc4_hdmi_encoder) 1298 return -ENOMEM; 1299 vc4_hdmi_encoder->base.type = VC4_ENCODER_TYPE_HDMI; 1300 hdmi->encoder = &vc4_hdmi_encoder->base.base; 1301 1302 hdmi->pdev = pdev; 1303 hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0); 1304 if (IS_ERR(hdmi->hdmicore_regs)) 1305 return PTR_ERR(hdmi->hdmicore_regs); 1306 1307 hdmi->hd_regs = vc4_ioremap_regs(pdev, 1); 1308 if (IS_ERR(hdmi->hd_regs)) 1309 return PTR_ERR(hdmi->hd_regs); 1310 1311 hdmi->hdmi_regset.base = hdmi->hdmicore_regs; 1312 hdmi->hdmi_regset.regs = hdmi_regs; 1313 hdmi->hdmi_regset.nregs = ARRAY_SIZE(hdmi_regs); 1314 hdmi->hd_regset.base = hdmi->hd_regs; 1315 hdmi->hd_regset.regs = hd_regs; 1316 hdmi->hd_regset.nregs = ARRAY_SIZE(hd_regs); 1317 1318 hdmi->pixel_clock = devm_clk_get(dev, "pixel"); 1319 if (IS_ERR(hdmi->pixel_clock)) { 1320 DRM_ERROR("Failed to get pixel clock\n"); 1321 return PTR_ERR(hdmi->pixel_clock); 1322 } 1323 hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); 1324 if (IS_ERR(hdmi->hsm_clock)) { 1325 DRM_ERROR("Failed to get HDMI state machine clock\n"); 1326 return PTR_ERR(hdmi->hsm_clock); 1327 } 1328 1329 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0); 1330 if (!ddc_node) { 1331 DRM_ERROR("Failed to find ddc node in device tree\n"); 1332 return -ENODEV; 1333 } 1334 1335 hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node); 1336 of_node_put(ddc_node); 1337 if (!hdmi->ddc) { 1338 DRM_DEBUG("Failed to get ddc i2c adapter by node\n"); 1339 return -EPROBE_DEFER; 1340 } 1341 1342 /* This is the rate that is set by the firmware. The number 1343 * needs to be a bit higher than the pixel clock rate 1344 * (generally 148.5Mhz). 1345 */ 1346 ret = clk_set_rate(hdmi->hsm_clock, HSM_CLOCK_FREQ); 1347 if (ret) { 1348 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret); 1349 goto err_put_i2c; 1350 } 1351 1352 ret = clk_prepare_enable(hdmi->hsm_clock); 1353 if (ret) { 1354 DRM_ERROR("Failed to turn on HDMI state machine clock: %d\n", 1355 ret); 1356 goto err_put_i2c; 1357 } 1358 1359 /* Only use the GPIO HPD pin if present in the DT, otherwise 1360 * we'll use the HDMI core's register. 1361 */ 1362 if (of_find_property(dev->of_node, "hpd-gpios", &value)) { 1363 enum of_gpio_flags hpd_gpio_flags; 1364 1365 hdmi->hpd_gpio = of_get_named_gpio_flags(dev->of_node, 1366 "hpd-gpios", 0, 1367 &hpd_gpio_flags); 1368 if (hdmi->hpd_gpio < 0) { 1369 ret = hdmi->hpd_gpio; 1370 goto err_unprepare_hsm; 1371 } 1372 1373 hdmi->hpd_active_low = hpd_gpio_flags & OF_GPIO_ACTIVE_LOW; 1374 } 1375 1376 vc4->hdmi = hdmi; 1377 1378 /* HDMI core must be enabled. */ 1379 if (!(HD_READ(VC4_HD_M_CTL) & VC4_HD_M_ENABLE)) { 1380 HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_SW_RST); 1381 udelay(1); 1382 HD_WRITE(VC4_HD_M_CTL, 0); 1383 1384 HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_ENABLE); 1385 } 1386 pm_runtime_enable(dev); 1387 1388 drm_encoder_init(drm, hdmi->encoder, &vc4_hdmi_encoder_funcs, 1389 DRM_MODE_ENCODER_TMDS, NULL); 1390 drm_encoder_helper_add(hdmi->encoder, &vc4_hdmi_encoder_helper_funcs); 1391 1392 hdmi->connector = vc4_hdmi_connector_init(drm, hdmi->encoder); 1393 if (IS_ERR(hdmi->connector)) { 1394 ret = PTR_ERR(hdmi->connector); 1395 goto err_destroy_encoder; 1396 } 1397 #ifdef CONFIG_DRM_VC4_HDMI_CEC 1398 hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops, 1399 vc4, "vc4", 1400 CEC_CAP_TRANSMIT | 1401 CEC_CAP_LOG_ADDRS | 1402 CEC_CAP_PASSTHROUGH | 1403 CEC_CAP_RC, 1); 1404 ret = PTR_ERR_OR_ZERO(hdmi->cec_adap); 1405 if (ret < 0) 1406 goto err_destroy_conn; 1407 HDMI_WRITE(VC4_HDMI_CPU_MASK_SET, 0xffffffff); 1408 value = HDMI_READ(VC4_HDMI_CEC_CNTRL_1); 1409 value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK; 1410 /* 1411 * Set the logical address to Unregistered and set the clock 1412 * divider: the hsm_clock rate and this divider setting will 1413 * give a 40 kHz CEC clock. 1414 */ 1415 value |= VC4_HDMI_CEC_ADDR_MASK | 1416 (4091 << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT); 1417 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, value); 1418 ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0), 1419 vc4_cec_irq_handler, 1420 vc4_cec_irq_handler_thread, 0, 1421 "vc4 hdmi cec", vc4); 1422 if (ret) 1423 goto err_delete_cec_adap; 1424 ret = cec_register_adapter(hdmi->cec_adap, dev); 1425 if (ret < 0) 1426 goto err_delete_cec_adap; 1427 #endif 1428 1429 ret = vc4_hdmi_audio_init(hdmi); 1430 if (ret) 1431 goto err_destroy_encoder; 1432 1433 vc4_debugfs_add_file(drm, "hdmi_regs", vc4_hdmi_debugfs_regs, hdmi); 1434 1435 return 0; 1436 1437 #ifdef CONFIG_DRM_VC4_HDMI_CEC 1438 err_delete_cec_adap: 1439 cec_delete_adapter(hdmi->cec_adap); 1440 err_destroy_conn: 1441 vc4_hdmi_connector_destroy(hdmi->connector); 1442 #endif 1443 err_destroy_encoder: 1444 vc4_hdmi_encoder_destroy(hdmi->encoder); 1445 err_unprepare_hsm: 1446 clk_disable_unprepare(hdmi->hsm_clock); 1447 pm_runtime_disable(dev); 1448 err_put_i2c: 1449 put_device(&hdmi->ddc->dev); 1450 1451 return ret; 1452 } 1453 1454 static void vc4_hdmi_unbind(struct device *dev, struct device *master, 1455 void *data) 1456 { 1457 struct drm_device *drm = dev_get_drvdata(master); 1458 struct vc4_dev *vc4 = drm->dev_private; 1459 struct vc4_hdmi *hdmi = vc4->hdmi; 1460 1461 cec_unregister_adapter(hdmi->cec_adap); 1462 vc4_hdmi_connector_destroy(hdmi->connector); 1463 vc4_hdmi_encoder_destroy(hdmi->encoder); 1464 1465 clk_disable_unprepare(hdmi->hsm_clock); 1466 pm_runtime_disable(dev); 1467 1468 put_device(&hdmi->ddc->dev); 1469 1470 vc4->hdmi = NULL; 1471 } 1472 1473 static const struct component_ops vc4_hdmi_ops = { 1474 .bind = vc4_hdmi_bind, 1475 .unbind = vc4_hdmi_unbind, 1476 }; 1477 1478 static int vc4_hdmi_dev_probe(struct platform_device *pdev) 1479 { 1480 return component_add(&pdev->dev, &vc4_hdmi_ops); 1481 } 1482 1483 static int vc4_hdmi_dev_remove(struct platform_device *pdev) 1484 { 1485 component_del(&pdev->dev, &vc4_hdmi_ops); 1486 return 0; 1487 } 1488 1489 static const struct of_device_id vc4_hdmi_dt_match[] = { 1490 { .compatible = "brcm,bcm2835-hdmi" }, 1491 {} 1492 }; 1493 1494 struct platform_driver vc4_hdmi_driver = { 1495 .probe = vc4_hdmi_dev_probe, 1496 .remove = vc4_hdmi_dev_remove, 1497 .driver = { 1498 .name = "vc4_hdmi", 1499 .of_match_table = vc4_hdmi_dt_match, 1500 }, 1501 }; 1502