1 /* 2 * Copyright (C) 2015 Broadcom 3 * Copyright (c) 2014 The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License version 2 as published by 9 * the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 /** 21 * DOC: VC4 Falcon HDMI module 22 * 23 * The HDMI core has a state machine and a PHY. On BCM2835, most of 24 * the unit operates off of the HSM clock from CPRMAN. It also 25 * internally uses the PLLH_PIX clock for the PHY. 26 * 27 * HDMI infoframes are kept within a small packet ram, where each 28 * packet can be individually enabled for including in a frame. 29 * 30 * HDMI audio is implemented entirely within the HDMI IP block. A 31 * register in the HDMI encoder takes SPDIF frames from the DMA engine 32 * and transfers them over an internal MAI (multi-channel audio 33 * interconnect) bus to the encoder side for insertion into the video 34 * blank regions. 35 * 36 * The driver's HDMI encoder does not yet support power management. 37 * The HDMI encoder's power domain and the HSM/pixel clocks are kept 38 * continuously running, and only the HDMI logic and packet ram are 39 * powered off/on at disable/enable time. 40 * 41 * The driver does not yet support CEC control, though the HDMI 42 * encoder block has CEC support. 43 */ 44 45 #include <drm/drm_atomic_helper.h> 46 #include <drm/drm_edid.h> 47 #include <drm/drm_probe_helper.h> 48 #include <linux/clk.h> 49 #include <linux/component.h> 50 #include <linux/i2c.h> 51 #include <linux/of_address.h> 52 #include <linux/of_gpio.h> 53 #include <linux/of_platform.h> 54 #include <linux/pm_runtime.h> 55 #include <linux/rational.h> 56 #include <sound/dmaengine_pcm.h> 57 #include <sound/pcm_drm_eld.h> 58 #include <sound/pcm_params.h> 59 #include <sound/soc.h> 60 #include "media/cec.h" 61 #include "vc4_drv.h" 62 #include "vc4_regs.h" 63 64 #define HSM_CLOCK_FREQ 163682864 65 #define CEC_CLOCK_FREQ 40000 66 #define CEC_CLOCK_DIV (HSM_CLOCK_FREQ / CEC_CLOCK_FREQ) 67 68 /* HDMI audio information */ 69 struct vc4_hdmi_audio { 70 struct snd_soc_card card; 71 struct snd_soc_dai_link link; 72 int samplerate; 73 int channels; 74 struct snd_dmaengine_dai_dma_data dma_data; 75 struct snd_pcm_substream *substream; 76 }; 77 78 /* General HDMI hardware state. */ 79 struct vc4_hdmi { 80 struct platform_device *pdev; 81 82 struct drm_encoder *encoder; 83 struct drm_connector *connector; 84 85 struct vc4_hdmi_audio audio; 86 87 struct i2c_adapter *ddc; 88 void __iomem *hdmicore_regs; 89 void __iomem *hd_regs; 90 int hpd_gpio; 91 bool hpd_active_low; 92 93 struct cec_adapter *cec_adap; 94 struct cec_msg cec_rx_msg; 95 bool cec_tx_ok; 96 bool cec_irq_was_rx; 97 98 struct clk *pixel_clock; 99 struct clk *hsm_clock; 100 101 struct debugfs_regset32 hdmi_regset; 102 struct debugfs_regset32 hd_regset; 103 }; 104 105 #define HDMI_READ(offset) readl(vc4->hdmi->hdmicore_regs + offset) 106 #define HDMI_WRITE(offset, val) writel(val, vc4->hdmi->hdmicore_regs + offset) 107 #define HD_READ(offset) readl(vc4->hdmi->hd_regs + offset) 108 #define HD_WRITE(offset, val) writel(val, vc4->hdmi->hd_regs + offset) 109 110 /* VC4 HDMI encoder KMS struct */ 111 struct vc4_hdmi_encoder { 112 struct vc4_encoder base; 113 bool hdmi_monitor; 114 bool limited_rgb_range; 115 }; 116 117 static inline struct vc4_hdmi_encoder * 118 to_vc4_hdmi_encoder(struct drm_encoder *encoder) 119 { 120 return container_of(encoder, struct vc4_hdmi_encoder, base.base); 121 } 122 123 /* VC4 HDMI connector KMS struct */ 124 struct vc4_hdmi_connector { 125 struct drm_connector base; 126 127 /* Since the connector is attached to just the one encoder, 128 * this is the reference to it so we can do the best_encoder() 129 * hook. 130 */ 131 struct drm_encoder *encoder; 132 }; 133 134 static inline struct vc4_hdmi_connector * 135 to_vc4_hdmi_connector(struct drm_connector *connector) 136 { 137 return container_of(connector, struct vc4_hdmi_connector, base); 138 } 139 140 static const struct debugfs_reg32 hdmi_regs[] = { 141 VC4_REG32(VC4_HDMI_CORE_REV), 142 VC4_REG32(VC4_HDMI_SW_RESET_CONTROL), 143 VC4_REG32(VC4_HDMI_HOTPLUG_INT), 144 VC4_REG32(VC4_HDMI_HOTPLUG), 145 VC4_REG32(VC4_HDMI_MAI_CHANNEL_MAP), 146 VC4_REG32(VC4_HDMI_MAI_CONFIG), 147 VC4_REG32(VC4_HDMI_MAI_FORMAT), 148 VC4_REG32(VC4_HDMI_AUDIO_PACKET_CONFIG), 149 VC4_REG32(VC4_HDMI_RAM_PACKET_CONFIG), 150 VC4_REG32(VC4_HDMI_HORZA), 151 VC4_REG32(VC4_HDMI_HORZB), 152 VC4_REG32(VC4_HDMI_FIFO_CTL), 153 VC4_REG32(VC4_HDMI_SCHEDULER_CONTROL), 154 VC4_REG32(VC4_HDMI_VERTA0), 155 VC4_REG32(VC4_HDMI_VERTA1), 156 VC4_REG32(VC4_HDMI_VERTB0), 157 VC4_REG32(VC4_HDMI_VERTB1), 158 VC4_REG32(VC4_HDMI_TX_PHY_RESET_CTL), 159 VC4_REG32(VC4_HDMI_TX_PHY_CTL0), 160 161 VC4_REG32(VC4_HDMI_CEC_CNTRL_1), 162 VC4_REG32(VC4_HDMI_CEC_CNTRL_2), 163 VC4_REG32(VC4_HDMI_CEC_CNTRL_3), 164 VC4_REG32(VC4_HDMI_CEC_CNTRL_4), 165 VC4_REG32(VC4_HDMI_CEC_CNTRL_5), 166 VC4_REG32(VC4_HDMI_CPU_STATUS), 167 VC4_REG32(VC4_HDMI_CPU_MASK_STATUS), 168 169 VC4_REG32(VC4_HDMI_CEC_RX_DATA_1), 170 VC4_REG32(VC4_HDMI_CEC_RX_DATA_2), 171 VC4_REG32(VC4_HDMI_CEC_RX_DATA_3), 172 VC4_REG32(VC4_HDMI_CEC_RX_DATA_4), 173 VC4_REG32(VC4_HDMI_CEC_TX_DATA_1), 174 VC4_REG32(VC4_HDMI_CEC_TX_DATA_2), 175 VC4_REG32(VC4_HDMI_CEC_TX_DATA_3), 176 VC4_REG32(VC4_HDMI_CEC_TX_DATA_4), 177 }; 178 179 static const struct debugfs_reg32 hd_regs[] = { 180 VC4_REG32(VC4_HD_M_CTL), 181 VC4_REG32(VC4_HD_MAI_CTL), 182 VC4_REG32(VC4_HD_MAI_THR), 183 VC4_REG32(VC4_HD_MAI_FMT), 184 VC4_REG32(VC4_HD_MAI_SMP), 185 VC4_REG32(VC4_HD_VID_CTL), 186 VC4_REG32(VC4_HD_CSC_CTL), 187 VC4_REG32(VC4_HD_FRAME_COUNT), 188 }; 189 190 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused) 191 { 192 struct drm_info_node *node = (struct drm_info_node *)m->private; 193 struct drm_device *dev = node->minor->dev; 194 struct vc4_dev *vc4 = to_vc4_dev(dev); 195 struct vc4_hdmi *hdmi = vc4->hdmi; 196 struct drm_printer p = drm_seq_file_printer(m); 197 198 drm_print_regset32(&p, &hdmi->hdmi_regset); 199 drm_print_regset32(&p, &hdmi->hd_regset); 200 201 return 0; 202 } 203 204 static enum drm_connector_status 205 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force) 206 { 207 struct drm_device *dev = connector->dev; 208 struct vc4_dev *vc4 = to_vc4_dev(dev); 209 210 if (vc4->hdmi->hpd_gpio) { 211 if (gpio_get_value_cansleep(vc4->hdmi->hpd_gpio) ^ 212 vc4->hdmi->hpd_active_low) 213 return connector_status_connected; 214 cec_phys_addr_invalidate(vc4->hdmi->cec_adap); 215 return connector_status_disconnected; 216 } 217 218 if (drm_probe_ddc(vc4->hdmi->ddc)) 219 return connector_status_connected; 220 221 if (HDMI_READ(VC4_HDMI_HOTPLUG) & VC4_HDMI_HOTPLUG_CONNECTED) 222 return connector_status_connected; 223 cec_phys_addr_invalidate(vc4->hdmi->cec_adap); 224 return connector_status_disconnected; 225 } 226 227 static void vc4_hdmi_connector_destroy(struct drm_connector *connector) 228 { 229 drm_connector_unregister(connector); 230 drm_connector_cleanup(connector); 231 } 232 233 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector) 234 { 235 struct vc4_hdmi_connector *vc4_connector = 236 to_vc4_hdmi_connector(connector); 237 struct drm_encoder *encoder = vc4_connector->encoder; 238 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 239 struct drm_device *dev = connector->dev; 240 struct vc4_dev *vc4 = to_vc4_dev(dev); 241 int ret = 0; 242 struct edid *edid; 243 244 edid = drm_get_edid(connector, vc4->hdmi->ddc); 245 cec_s_phys_addr_from_edid(vc4->hdmi->cec_adap, edid); 246 if (!edid) 247 return -ENODEV; 248 249 vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid); 250 251 drm_connector_update_edid_property(connector, edid); 252 ret = drm_add_edid_modes(connector, edid); 253 kfree(edid); 254 255 return ret; 256 } 257 258 static void vc4_hdmi_connector_reset(struct drm_connector *connector) 259 { 260 drm_atomic_helper_connector_reset(connector); 261 drm_atomic_helper_connector_tv_reset(connector); 262 } 263 264 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = { 265 .detect = vc4_hdmi_connector_detect, 266 .fill_modes = drm_helper_probe_single_connector_modes, 267 .destroy = vc4_hdmi_connector_destroy, 268 .reset = vc4_hdmi_connector_reset, 269 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 270 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 271 }; 272 273 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = { 274 .get_modes = vc4_hdmi_connector_get_modes, 275 }; 276 277 static struct drm_connector *vc4_hdmi_connector_init(struct drm_device *dev, 278 struct drm_encoder *encoder) 279 { 280 struct drm_connector *connector; 281 struct vc4_hdmi_connector *hdmi_connector; 282 int ret; 283 284 hdmi_connector = devm_kzalloc(dev->dev, sizeof(*hdmi_connector), 285 GFP_KERNEL); 286 if (!hdmi_connector) 287 return ERR_PTR(-ENOMEM); 288 connector = &hdmi_connector->base; 289 290 hdmi_connector->encoder = encoder; 291 292 drm_connector_init(dev, connector, &vc4_hdmi_connector_funcs, 293 DRM_MODE_CONNECTOR_HDMIA); 294 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs); 295 296 /* Create and attach TV margin props to this connector. */ 297 ret = drm_mode_create_tv_margin_properties(dev); 298 if (ret) 299 return ERR_PTR(ret); 300 301 drm_connector_attach_tv_margin_properties(connector); 302 303 connector->polled = (DRM_CONNECTOR_POLL_CONNECT | 304 DRM_CONNECTOR_POLL_DISCONNECT); 305 306 connector->interlace_allowed = 1; 307 connector->doublescan_allowed = 0; 308 309 drm_connector_attach_encoder(connector, encoder); 310 311 return connector; 312 } 313 314 static void vc4_hdmi_encoder_destroy(struct drm_encoder *encoder) 315 { 316 drm_encoder_cleanup(encoder); 317 } 318 319 static const struct drm_encoder_funcs vc4_hdmi_encoder_funcs = { 320 .destroy = vc4_hdmi_encoder_destroy, 321 }; 322 323 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder, 324 enum hdmi_infoframe_type type) 325 { 326 struct drm_device *dev = encoder->dev; 327 struct vc4_dev *vc4 = to_vc4_dev(dev); 328 u32 packet_id = type - 0x80; 329 330 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, 331 HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id)); 332 333 return wait_for(!(HDMI_READ(VC4_HDMI_RAM_PACKET_STATUS) & 334 BIT(packet_id)), 100); 335 } 336 337 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder, 338 union hdmi_infoframe *frame) 339 { 340 struct drm_device *dev = encoder->dev; 341 struct vc4_dev *vc4 = to_vc4_dev(dev); 342 u32 packet_id = frame->any.type - 0x80; 343 u32 packet_reg = VC4_HDMI_RAM_PACKET(packet_id); 344 uint8_t buffer[VC4_HDMI_PACKET_STRIDE]; 345 ssize_t len, i; 346 int ret; 347 348 WARN_ONCE(!(HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) & 349 VC4_HDMI_RAM_PACKET_ENABLE), 350 "Packet RAM has to be on to store the packet."); 351 352 len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer)); 353 if (len < 0) 354 return; 355 356 ret = vc4_hdmi_stop_packet(encoder, frame->any.type); 357 if (ret) { 358 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret); 359 return; 360 } 361 362 for (i = 0; i < len; i += 7) { 363 HDMI_WRITE(packet_reg, 364 buffer[i + 0] << 0 | 365 buffer[i + 1] << 8 | 366 buffer[i + 2] << 16); 367 packet_reg += 4; 368 369 HDMI_WRITE(packet_reg, 370 buffer[i + 3] << 0 | 371 buffer[i + 4] << 8 | 372 buffer[i + 5] << 16 | 373 buffer[i + 6] << 24); 374 packet_reg += 4; 375 } 376 377 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, 378 HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) | BIT(packet_id)); 379 ret = wait_for((HDMI_READ(VC4_HDMI_RAM_PACKET_STATUS) & 380 BIT(packet_id)), 100); 381 if (ret) 382 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret); 383 } 384 385 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder) 386 { 387 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 388 struct vc4_dev *vc4 = encoder->dev->dev_private; 389 struct vc4_hdmi *hdmi = vc4->hdmi; 390 struct drm_connector_state *cstate = hdmi->connector->state; 391 struct drm_crtc *crtc = encoder->crtc; 392 const struct drm_display_mode *mode = &crtc->state->adjusted_mode; 393 union hdmi_infoframe frame; 394 int ret; 395 396 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, 397 hdmi->connector, mode); 398 if (ret < 0) { 399 DRM_ERROR("couldn't fill AVI infoframe\n"); 400 return; 401 } 402 403 drm_hdmi_avi_infoframe_quant_range(&frame.avi, 404 hdmi->connector, mode, 405 vc4_encoder->limited_rgb_range ? 406 HDMI_QUANTIZATION_RANGE_LIMITED : 407 HDMI_QUANTIZATION_RANGE_FULL); 408 409 frame.avi.right_bar = cstate->tv.margins.right; 410 frame.avi.left_bar = cstate->tv.margins.left; 411 frame.avi.top_bar = cstate->tv.margins.top; 412 frame.avi.bottom_bar = cstate->tv.margins.bottom; 413 414 vc4_hdmi_write_infoframe(encoder, &frame); 415 } 416 417 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder) 418 { 419 union hdmi_infoframe frame; 420 int ret; 421 422 ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore"); 423 if (ret < 0) { 424 DRM_ERROR("couldn't fill SPD infoframe\n"); 425 return; 426 } 427 428 frame.spd.sdi = HDMI_SPD_SDI_PC; 429 430 vc4_hdmi_write_infoframe(encoder, &frame); 431 } 432 433 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder) 434 { 435 struct drm_device *drm = encoder->dev; 436 struct vc4_dev *vc4 = drm->dev_private; 437 struct vc4_hdmi *hdmi = vc4->hdmi; 438 union hdmi_infoframe frame; 439 int ret; 440 441 ret = hdmi_audio_infoframe_init(&frame.audio); 442 443 frame.audio.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM; 444 frame.audio.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM; 445 frame.audio.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM; 446 frame.audio.channels = hdmi->audio.channels; 447 448 vc4_hdmi_write_infoframe(encoder, &frame); 449 } 450 451 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder) 452 { 453 vc4_hdmi_set_avi_infoframe(encoder); 454 vc4_hdmi_set_spd_infoframe(encoder); 455 } 456 457 static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder) 458 { 459 struct drm_device *dev = encoder->dev; 460 struct vc4_dev *vc4 = to_vc4_dev(dev); 461 struct vc4_hdmi *hdmi = vc4->hdmi; 462 int ret; 463 464 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, 0); 465 466 HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16); 467 HD_WRITE(VC4_HD_VID_CTL, 468 HD_READ(VC4_HD_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE); 469 470 clk_disable_unprepare(hdmi->pixel_clock); 471 472 ret = pm_runtime_put(&hdmi->pdev->dev); 473 if (ret < 0) 474 DRM_ERROR("Failed to release power domain: %d\n", ret); 475 } 476 477 static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder) 478 { 479 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; 480 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 481 struct drm_device *dev = encoder->dev; 482 struct vc4_dev *vc4 = to_vc4_dev(dev); 483 struct vc4_hdmi *hdmi = vc4->hdmi; 484 bool debug_dump_regs = false; 485 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 486 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 487 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 488 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 489 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 490 VC4_HDMI_VERTA_VSP) | 491 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 492 VC4_HDMI_VERTA_VFP) | 493 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL)); 494 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 495 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end, 496 VC4_HDMI_VERTB_VBP)); 497 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 498 VC4_SET_FIELD(mode->crtc_vtotal - 499 mode->crtc_vsync_end - 500 interlaced, 501 VC4_HDMI_VERTB_VBP)); 502 u32 csc_ctl; 503 int ret; 504 505 ret = pm_runtime_get_sync(&hdmi->pdev->dev); 506 if (ret < 0) { 507 DRM_ERROR("Failed to retain power domain: %d\n", ret); 508 return; 509 } 510 511 ret = clk_set_rate(hdmi->pixel_clock, 512 mode->clock * 1000 * 513 ((mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1)); 514 if (ret) { 515 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret); 516 return; 517 } 518 519 ret = clk_prepare_enable(hdmi->pixel_clock); 520 if (ret) { 521 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret); 522 return; 523 } 524 525 HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL, 526 VC4_HDMI_SW_RESET_HDMI | 527 VC4_HDMI_SW_RESET_FORMAT_DETECT); 528 529 HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL, 0); 530 531 /* PHY should be in reset, like 532 * vc4_hdmi_encoder_disable() does. 533 */ 534 HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16); 535 536 HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0); 537 538 if (debug_dump_regs) { 539 struct drm_printer p = drm_info_printer(&hdmi->pdev->dev); 540 541 dev_info(&hdmi->pdev->dev, "HDMI regs before:\n"); 542 drm_print_regset32(&p, &hdmi->hdmi_regset); 543 drm_print_regset32(&p, &hdmi->hd_regset); 544 } 545 546 HD_WRITE(VC4_HD_VID_CTL, 0); 547 548 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL, 549 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) | 550 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT | 551 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS); 552 553 HDMI_WRITE(VC4_HDMI_HORZA, 554 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) | 555 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) | 556 VC4_SET_FIELD(mode->hdisplay * pixel_rep, 557 VC4_HDMI_HORZA_HAP)); 558 559 HDMI_WRITE(VC4_HDMI_HORZB, 560 VC4_SET_FIELD((mode->htotal - 561 mode->hsync_end) * pixel_rep, 562 VC4_HDMI_HORZB_HBP) | 563 VC4_SET_FIELD((mode->hsync_end - 564 mode->hsync_start) * pixel_rep, 565 VC4_HDMI_HORZB_HSP) | 566 VC4_SET_FIELD((mode->hsync_start - 567 mode->hdisplay) * pixel_rep, 568 VC4_HDMI_HORZB_HFP)); 569 570 HDMI_WRITE(VC4_HDMI_VERTA0, verta); 571 HDMI_WRITE(VC4_HDMI_VERTA1, verta); 572 573 HDMI_WRITE(VC4_HDMI_VERTB0, vertb_even); 574 HDMI_WRITE(VC4_HDMI_VERTB1, vertb); 575 576 HD_WRITE(VC4_HD_VID_CTL, 577 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) | 578 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW)); 579 580 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR, 581 VC4_HD_CSC_CTL_ORDER); 582 583 if (vc4_encoder->hdmi_monitor && 584 drm_default_rgb_quant_range(mode) == 585 HDMI_QUANTIZATION_RANGE_LIMITED) { 586 /* CEA VICs other than #1 requre limited range RGB 587 * output unless overridden by an AVI infoframe. 588 * Apply a colorspace conversion to squash 0-255 down 589 * to 16-235. The matrix here is: 590 * 591 * [ 0 0 0.8594 16] 592 * [ 0 0.8594 0 16] 593 * [ 0.8594 0 0 16] 594 * [ 0 0 0 1] 595 */ 596 csc_ctl |= VC4_HD_CSC_CTL_ENABLE; 597 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC; 598 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM, 599 VC4_HD_CSC_CTL_MODE); 600 601 HD_WRITE(VC4_HD_CSC_12_11, (0x000 << 16) | 0x000); 602 HD_WRITE(VC4_HD_CSC_14_13, (0x100 << 16) | 0x6e0); 603 HD_WRITE(VC4_HD_CSC_22_21, (0x6e0 << 16) | 0x000); 604 HD_WRITE(VC4_HD_CSC_24_23, (0x100 << 16) | 0x000); 605 HD_WRITE(VC4_HD_CSC_32_31, (0x000 << 16) | 0x6e0); 606 HD_WRITE(VC4_HD_CSC_34_33, (0x100 << 16) | 0x000); 607 vc4_encoder->limited_rgb_range = true; 608 } else { 609 vc4_encoder->limited_rgb_range = false; 610 } 611 612 /* The RGB order applies even when CSC is disabled. */ 613 HD_WRITE(VC4_HD_CSC_CTL, csc_ctl); 614 615 HDMI_WRITE(VC4_HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N); 616 617 if (debug_dump_regs) { 618 struct drm_printer p = drm_info_printer(&hdmi->pdev->dev); 619 620 dev_info(&hdmi->pdev->dev, "HDMI regs after:\n"); 621 drm_print_regset32(&p, &hdmi->hdmi_regset); 622 drm_print_regset32(&p, &hdmi->hd_regset); 623 } 624 625 HD_WRITE(VC4_HD_VID_CTL, 626 HD_READ(VC4_HD_VID_CTL) | 627 VC4_HD_VID_CTL_ENABLE | 628 VC4_HD_VID_CTL_UNDERFLOW_ENABLE | 629 VC4_HD_VID_CTL_FRAME_COUNTER_RESET); 630 631 if (vc4_encoder->hdmi_monitor) { 632 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL, 633 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) | 634 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 635 636 ret = wait_for(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) & 637 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000); 638 WARN_ONCE(ret, "Timeout waiting for " 639 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 640 } else { 641 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, 642 HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) & 643 ~(VC4_HDMI_RAM_PACKET_ENABLE)); 644 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL, 645 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) & 646 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 647 648 ret = wait_for(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) & 649 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000); 650 WARN_ONCE(ret, "Timeout waiting for " 651 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 652 } 653 654 if (vc4_encoder->hdmi_monitor) { 655 u32 drift; 656 657 WARN_ON(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) & 658 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE)); 659 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL, 660 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) | 661 VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT); 662 663 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, 664 VC4_HDMI_RAM_PACKET_ENABLE); 665 666 vc4_hdmi_set_infoframes(encoder); 667 668 drift = HDMI_READ(VC4_HDMI_FIFO_CTL); 669 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK; 670 671 HDMI_WRITE(VC4_HDMI_FIFO_CTL, 672 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 673 HDMI_WRITE(VC4_HDMI_FIFO_CTL, 674 drift | VC4_HDMI_FIFO_CTL_RECENTER); 675 usleep_range(1000, 1100); 676 HDMI_WRITE(VC4_HDMI_FIFO_CTL, 677 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 678 HDMI_WRITE(VC4_HDMI_FIFO_CTL, 679 drift | VC4_HDMI_FIFO_CTL_RECENTER); 680 681 ret = wait_for(HDMI_READ(VC4_HDMI_FIFO_CTL) & 682 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1); 683 WARN_ONCE(ret, "Timeout waiting for " 684 "VC4_HDMI_FIFO_CTL_RECENTER_DONE"); 685 } 686 } 687 688 static enum drm_mode_status 689 vc4_hdmi_encoder_mode_valid(struct drm_encoder *crtc, 690 const struct drm_display_mode *mode) 691 { 692 /* HSM clock must be 108% of the pixel clock. Additionally, 693 * the AXI clock needs to be at least 25% of pixel clock, but 694 * HSM ends up being the limiting factor. 695 */ 696 if (mode->clock > HSM_CLOCK_FREQ / (1000 * 108 / 100)) 697 return MODE_CLOCK_HIGH; 698 699 return MODE_OK; 700 } 701 702 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = { 703 .mode_valid = vc4_hdmi_encoder_mode_valid, 704 .disable = vc4_hdmi_encoder_disable, 705 .enable = vc4_hdmi_encoder_enable, 706 }; 707 708 /* HDMI audio codec callbacks */ 709 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *hdmi) 710 { 711 struct drm_device *drm = hdmi->encoder->dev; 712 struct vc4_dev *vc4 = to_vc4_dev(drm); 713 u32 hsm_clock = clk_get_rate(hdmi->hsm_clock); 714 unsigned long n, m; 715 716 rational_best_approximation(hsm_clock, hdmi->audio.samplerate, 717 VC4_HD_MAI_SMP_N_MASK >> 718 VC4_HD_MAI_SMP_N_SHIFT, 719 (VC4_HD_MAI_SMP_M_MASK >> 720 VC4_HD_MAI_SMP_M_SHIFT) + 1, 721 &n, &m); 722 723 HD_WRITE(VC4_HD_MAI_SMP, 724 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) | 725 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M)); 726 } 727 728 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *hdmi) 729 { 730 struct drm_encoder *encoder = hdmi->encoder; 731 struct drm_crtc *crtc = encoder->crtc; 732 struct drm_device *drm = encoder->dev; 733 struct vc4_dev *vc4 = to_vc4_dev(drm); 734 const struct drm_display_mode *mode = &crtc->state->adjusted_mode; 735 u32 samplerate = hdmi->audio.samplerate; 736 u32 n, cts; 737 u64 tmp; 738 739 n = 128 * samplerate / 1000; 740 tmp = (u64)(mode->clock * 1000) * n; 741 do_div(tmp, 128 * samplerate); 742 cts = tmp; 743 744 HDMI_WRITE(VC4_HDMI_CRP_CFG, 745 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN | 746 VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N)); 747 748 /* 749 * We could get slightly more accurate clocks in some cases by 750 * providing a CTS_1 value. The two CTS values are alternated 751 * between based on the period fields 752 */ 753 HDMI_WRITE(VC4_HDMI_CTS_0, cts); 754 HDMI_WRITE(VC4_HDMI_CTS_1, cts); 755 } 756 757 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai) 758 { 759 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai); 760 761 return snd_soc_card_get_drvdata(card); 762 } 763 764 static int vc4_hdmi_audio_startup(struct snd_pcm_substream *substream, 765 struct snd_soc_dai *dai) 766 { 767 struct vc4_hdmi *hdmi = dai_to_hdmi(dai); 768 struct drm_encoder *encoder = hdmi->encoder; 769 struct vc4_dev *vc4 = to_vc4_dev(encoder->dev); 770 int ret; 771 772 if (hdmi->audio.substream && hdmi->audio.substream != substream) 773 return -EINVAL; 774 775 hdmi->audio.substream = substream; 776 777 /* 778 * If the HDMI encoder hasn't probed, or the encoder is 779 * currently in DVI mode, treat the codec dai as missing. 780 */ 781 if (!encoder->crtc || !(HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) & 782 VC4_HDMI_RAM_PACKET_ENABLE)) 783 return -ENODEV; 784 785 ret = snd_pcm_hw_constraint_eld(substream->runtime, 786 hdmi->connector->eld); 787 if (ret) 788 return ret; 789 790 return 0; 791 } 792 793 static int vc4_hdmi_audio_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 794 { 795 return 0; 796 } 797 798 static void vc4_hdmi_audio_reset(struct vc4_hdmi *hdmi) 799 { 800 struct drm_encoder *encoder = hdmi->encoder; 801 struct drm_device *drm = encoder->dev; 802 struct device *dev = &hdmi->pdev->dev; 803 struct vc4_dev *vc4 = to_vc4_dev(drm); 804 int ret; 805 806 ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO); 807 if (ret) 808 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret); 809 810 HD_WRITE(VC4_HD_MAI_CTL, VC4_HD_MAI_CTL_RESET); 811 HD_WRITE(VC4_HD_MAI_CTL, VC4_HD_MAI_CTL_ERRORF); 812 HD_WRITE(VC4_HD_MAI_CTL, VC4_HD_MAI_CTL_FLUSH); 813 } 814 815 static void vc4_hdmi_audio_shutdown(struct snd_pcm_substream *substream, 816 struct snd_soc_dai *dai) 817 { 818 struct vc4_hdmi *hdmi = dai_to_hdmi(dai); 819 820 if (substream != hdmi->audio.substream) 821 return; 822 823 vc4_hdmi_audio_reset(hdmi); 824 825 hdmi->audio.substream = NULL; 826 } 827 828 /* HDMI audio codec callbacks */ 829 static int vc4_hdmi_audio_hw_params(struct snd_pcm_substream *substream, 830 struct snd_pcm_hw_params *params, 831 struct snd_soc_dai *dai) 832 { 833 struct vc4_hdmi *hdmi = dai_to_hdmi(dai); 834 struct drm_encoder *encoder = hdmi->encoder; 835 struct drm_device *drm = encoder->dev; 836 struct device *dev = &hdmi->pdev->dev; 837 struct vc4_dev *vc4 = to_vc4_dev(drm); 838 u32 audio_packet_config, channel_mask; 839 u32 channel_map, i; 840 841 if (substream != hdmi->audio.substream) 842 return -EINVAL; 843 844 dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__, 845 params_rate(params), params_width(params), 846 params_channels(params)); 847 848 hdmi->audio.channels = params_channels(params); 849 hdmi->audio.samplerate = params_rate(params); 850 851 HD_WRITE(VC4_HD_MAI_CTL, 852 VC4_HD_MAI_CTL_RESET | 853 VC4_HD_MAI_CTL_FLUSH | 854 VC4_HD_MAI_CTL_DLATE | 855 VC4_HD_MAI_CTL_ERRORE | 856 VC4_HD_MAI_CTL_ERRORF); 857 858 vc4_hdmi_audio_set_mai_clock(hdmi); 859 860 audio_packet_config = 861 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT | 862 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS | 863 VC4_SET_FIELD(0xf, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER); 864 865 channel_mask = GENMASK(hdmi->audio.channels - 1, 0); 866 audio_packet_config |= VC4_SET_FIELD(channel_mask, 867 VC4_HDMI_AUDIO_PACKET_CEA_MASK); 868 869 /* Set the MAI threshold. This logic mimics the firmware's. */ 870 if (hdmi->audio.samplerate > 96000) { 871 HD_WRITE(VC4_HD_MAI_THR, 872 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQHIGH) | 873 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW)); 874 } else if (hdmi->audio.samplerate > 48000) { 875 HD_WRITE(VC4_HD_MAI_THR, 876 VC4_SET_FIELD(0x14, VC4_HD_MAI_THR_DREQHIGH) | 877 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW)); 878 } else { 879 HD_WRITE(VC4_HD_MAI_THR, 880 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) | 881 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) | 882 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQHIGH) | 883 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQLOW)); 884 } 885 886 HDMI_WRITE(VC4_HDMI_MAI_CONFIG, 887 VC4_HDMI_MAI_CONFIG_BIT_REVERSE | 888 VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK)); 889 890 channel_map = 0; 891 for (i = 0; i < 8; i++) { 892 if (channel_mask & BIT(i)) 893 channel_map |= i << (3 * i); 894 } 895 896 HDMI_WRITE(VC4_HDMI_MAI_CHANNEL_MAP, channel_map); 897 HDMI_WRITE(VC4_HDMI_AUDIO_PACKET_CONFIG, audio_packet_config); 898 vc4_hdmi_set_n_cts(hdmi); 899 900 return 0; 901 } 902 903 static int vc4_hdmi_audio_trigger(struct snd_pcm_substream *substream, int cmd, 904 struct snd_soc_dai *dai) 905 { 906 struct vc4_hdmi *hdmi = dai_to_hdmi(dai); 907 struct drm_encoder *encoder = hdmi->encoder; 908 struct drm_device *drm = encoder->dev; 909 struct vc4_dev *vc4 = to_vc4_dev(drm); 910 911 switch (cmd) { 912 case SNDRV_PCM_TRIGGER_START: 913 vc4_hdmi_set_audio_infoframe(encoder); 914 HDMI_WRITE(VC4_HDMI_TX_PHY_CTL0, 915 HDMI_READ(VC4_HDMI_TX_PHY_CTL0) & 916 ~VC4_HDMI_TX_PHY_RNG_PWRDN); 917 HD_WRITE(VC4_HD_MAI_CTL, 918 VC4_SET_FIELD(hdmi->audio.channels, 919 VC4_HD_MAI_CTL_CHNUM) | 920 VC4_HD_MAI_CTL_ENABLE); 921 break; 922 case SNDRV_PCM_TRIGGER_STOP: 923 HD_WRITE(VC4_HD_MAI_CTL, 924 VC4_HD_MAI_CTL_DLATE | 925 VC4_HD_MAI_CTL_ERRORE | 926 VC4_HD_MAI_CTL_ERRORF); 927 HDMI_WRITE(VC4_HDMI_TX_PHY_CTL0, 928 HDMI_READ(VC4_HDMI_TX_PHY_CTL0) | 929 VC4_HDMI_TX_PHY_RNG_PWRDN); 930 break; 931 default: 932 break; 933 } 934 935 return 0; 936 } 937 938 static inline struct vc4_hdmi * 939 snd_component_to_hdmi(struct snd_soc_component *component) 940 { 941 struct snd_soc_card *card = snd_soc_component_get_drvdata(component); 942 943 return snd_soc_card_get_drvdata(card); 944 } 945 946 static int vc4_hdmi_audio_eld_ctl_info(struct snd_kcontrol *kcontrol, 947 struct snd_ctl_elem_info *uinfo) 948 { 949 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 950 struct vc4_hdmi *hdmi = snd_component_to_hdmi(component); 951 952 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 953 uinfo->count = sizeof(hdmi->connector->eld); 954 955 return 0; 956 } 957 958 static int vc4_hdmi_audio_eld_ctl_get(struct snd_kcontrol *kcontrol, 959 struct snd_ctl_elem_value *ucontrol) 960 { 961 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 962 struct vc4_hdmi *hdmi = snd_component_to_hdmi(component); 963 964 memcpy(ucontrol->value.bytes.data, hdmi->connector->eld, 965 sizeof(hdmi->connector->eld)); 966 967 return 0; 968 } 969 970 static const struct snd_kcontrol_new vc4_hdmi_audio_controls[] = { 971 { 972 .access = SNDRV_CTL_ELEM_ACCESS_READ | 973 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 974 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 975 .name = "ELD", 976 .info = vc4_hdmi_audio_eld_ctl_info, 977 .get = vc4_hdmi_audio_eld_ctl_get, 978 }, 979 }; 980 981 static const struct snd_soc_dapm_widget vc4_hdmi_audio_widgets[] = { 982 SND_SOC_DAPM_OUTPUT("TX"), 983 }; 984 985 static const struct snd_soc_dapm_route vc4_hdmi_audio_routes[] = { 986 { "TX", NULL, "Playback" }, 987 }; 988 989 static const struct snd_soc_component_driver vc4_hdmi_audio_component_drv = { 990 .controls = vc4_hdmi_audio_controls, 991 .num_controls = ARRAY_SIZE(vc4_hdmi_audio_controls), 992 .dapm_widgets = vc4_hdmi_audio_widgets, 993 .num_dapm_widgets = ARRAY_SIZE(vc4_hdmi_audio_widgets), 994 .dapm_routes = vc4_hdmi_audio_routes, 995 .num_dapm_routes = ARRAY_SIZE(vc4_hdmi_audio_routes), 996 .idle_bias_on = 1, 997 .use_pmdown_time = 1, 998 .endianness = 1, 999 .non_legacy_dai_naming = 1, 1000 }; 1001 1002 static const struct snd_soc_dai_ops vc4_hdmi_audio_dai_ops = { 1003 .startup = vc4_hdmi_audio_startup, 1004 .shutdown = vc4_hdmi_audio_shutdown, 1005 .hw_params = vc4_hdmi_audio_hw_params, 1006 .set_fmt = vc4_hdmi_audio_set_fmt, 1007 .trigger = vc4_hdmi_audio_trigger, 1008 }; 1009 1010 static struct snd_soc_dai_driver vc4_hdmi_audio_codec_dai_drv = { 1011 .name = "vc4-hdmi-hifi", 1012 .playback = { 1013 .stream_name = "Playback", 1014 .channels_min = 2, 1015 .channels_max = 8, 1016 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 1017 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 1018 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 1019 SNDRV_PCM_RATE_192000, 1020 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 1021 }, 1022 }; 1023 1024 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = { 1025 .name = "vc4-hdmi-cpu-dai-component", 1026 }; 1027 1028 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai) 1029 { 1030 struct vc4_hdmi *hdmi = dai_to_hdmi(dai); 1031 1032 snd_soc_dai_init_dma_data(dai, &hdmi->audio.dma_data, NULL); 1033 1034 return 0; 1035 } 1036 1037 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = { 1038 .name = "vc4-hdmi-cpu-dai", 1039 .probe = vc4_hdmi_audio_cpu_dai_probe, 1040 .playback = { 1041 .stream_name = "Playback", 1042 .channels_min = 1, 1043 .channels_max = 8, 1044 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 1045 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 1046 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 1047 SNDRV_PCM_RATE_192000, 1048 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 1049 }, 1050 .ops = &vc4_hdmi_audio_dai_ops, 1051 }; 1052 1053 static const struct snd_dmaengine_pcm_config pcm_conf = { 1054 .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx", 1055 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 1056 }; 1057 1058 static int vc4_hdmi_audio_init(struct vc4_hdmi *hdmi) 1059 { 1060 struct snd_soc_dai_link *dai_link = &hdmi->audio.link; 1061 struct snd_soc_card *card = &hdmi->audio.card; 1062 struct device *dev = &hdmi->pdev->dev; 1063 const __be32 *addr; 1064 int ret; 1065 1066 if (!of_find_property(dev->of_node, "dmas", NULL)) { 1067 dev_warn(dev, 1068 "'dmas' DT property is missing, no HDMI audio\n"); 1069 return 0; 1070 } 1071 1072 /* 1073 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve 1074 * the bus address specified in the DT, because the physical address 1075 * (the one returned by platform_get_resource()) is not appropriate 1076 * for DMA transfers. 1077 * This VC/MMU should probably be exposed to avoid this kind of hacks. 1078 */ 1079 addr = of_get_address(dev->of_node, 1, NULL, NULL); 1080 hdmi->audio.dma_data.addr = be32_to_cpup(addr) + VC4_HD_MAI_DATA; 1081 hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1082 hdmi->audio.dma_data.maxburst = 2; 1083 1084 ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0); 1085 if (ret) { 1086 dev_err(dev, "Could not register PCM component: %d\n", ret); 1087 return ret; 1088 } 1089 1090 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp, 1091 &vc4_hdmi_audio_cpu_dai_drv, 1); 1092 if (ret) { 1093 dev_err(dev, "Could not register CPU DAI: %d\n", ret); 1094 return ret; 1095 } 1096 1097 /* register component and codec dai */ 1098 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_component_drv, 1099 &vc4_hdmi_audio_codec_dai_drv, 1); 1100 if (ret) { 1101 dev_err(dev, "Could not register component: %d\n", ret); 1102 return ret; 1103 } 1104 1105 dai_link->name = "MAI"; 1106 dai_link->stream_name = "MAI PCM"; 1107 dai_link->codec_dai_name = vc4_hdmi_audio_codec_dai_drv.name; 1108 dai_link->cpu_dai_name = dev_name(dev); 1109 dai_link->codec_name = dev_name(dev); 1110 dai_link->platform_name = dev_name(dev); 1111 1112 card->dai_link = dai_link; 1113 card->num_links = 1; 1114 card->name = "vc4-hdmi"; 1115 card->dev = dev; 1116 1117 /* 1118 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and 1119 * stores a pointer to the snd card object in dev->driver_data. This 1120 * means we cannot use it for something else. The hdmi back-pointer is 1121 * now stored in card->drvdata and should be retrieved with 1122 * snd_soc_card_get_drvdata() if needed. 1123 */ 1124 snd_soc_card_set_drvdata(card, hdmi); 1125 ret = devm_snd_soc_register_card(dev, card); 1126 if (ret) 1127 dev_err(dev, "Could not register sound card: %d\n", ret); 1128 1129 return ret; 1130 1131 } 1132 1133 #ifdef CONFIG_DRM_VC4_HDMI_CEC 1134 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv) 1135 { 1136 struct vc4_dev *vc4 = priv; 1137 struct vc4_hdmi *hdmi = vc4->hdmi; 1138 1139 if (hdmi->cec_irq_was_rx) { 1140 if (hdmi->cec_rx_msg.len) 1141 cec_received_msg(hdmi->cec_adap, &hdmi->cec_rx_msg); 1142 } else if (hdmi->cec_tx_ok) { 1143 cec_transmit_done(hdmi->cec_adap, CEC_TX_STATUS_OK, 1144 0, 0, 0, 0); 1145 } else { 1146 /* 1147 * This CEC implementation makes 1 retry, so if we 1148 * get a NACK, then that means it made 2 attempts. 1149 */ 1150 cec_transmit_done(hdmi->cec_adap, CEC_TX_STATUS_NACK, 1151 0, 2, 0, 0); 1152 } 1153 return IRQ_HANDLED; 1154 } 1155 1156 static void vc4_cec_read_msg(struct vc4_dev *vc4, u32 cntrl1) 1157 { 1158 struct cec_msg *msg = &vc4->hdmi->cec_rx_msg; 1159 unsigned int i; 1160 1161 msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >> 1162 VC4_HDMI_CEC_REC_WRD_CNT_SHIFT); 1163 for (i = 0; i < msg->len; i += 4) { 1164 u32 val = HDMI_READ(VC4_HDMI_CEC_RX_DATA_1 + i); 1165 1166 msg->msg[i] = val & 0xff; 1167 msg->msg[i + 1] = (val >> 8) & 0xff; 1168 msg->msg[i + 2] = (val >> 16) & 0xff; 1169 msg->msg[i + 3] = (val >> 24) & 0xff; 1170 } 1171 } 1172 1173 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv) 1174 { 1175 struct vc4_dev *vc4 = priv; 1176 struct vc4_hdmi *hdmi = vc4->hdmi; 1177 u32 stat = HDMI_READ(VC4_HDMI_CPU_STATUS); 1178 u32 cntrl1, cntrl5; 1179 1180 if (!(stat & VC4_HDMI_CPU_CEC)) 1181 return IRQ_NONE; 1182 hdmi->cec_rx_msg.len = 0; 1183 cntrl1 = HDMI_READ(VC4_HDMI_CEC_CNTRL_1); 1184 cntrl5 = HDMI_READ(VC4_HDMI_CEC_CNTRL_5); 1185 hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT; 1186 if (hdmi->cec_irq_was_rx) { 1187 vc4_cec_read_msg(vc4, cntrl1); 1188 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 1189 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, cntrl1); 1190 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 1191 } else { 1192 hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD; 1193 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 1194 } 1195 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, cntrl1); 1196 HDMI_WRITE(VC4_HDMI_CPU_CLEAR, VC4_HDMI_CPU_CEC); 1197 1198 return IRQ_WAKE_THREAD; 1199 } 1200 1201 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable) 1202 { 1203 struct vc4_dev *vc4 = cec_get_drvdata(adap); 1204 /* clock period in microseconds */ 1205 const u32 usecs = 1000000 / CEC_CLOCK_FREQ; 1206 u32 val = HDMI_READ(VC4_HDMI_CEC_CNTRL_5); 1207 1208 val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET | 1209 VC4_HDMI_CEC_CNT_TO_4700_US_MASK | 1210 VC4_HDMI_CEC_CNT_TO_4500_US_MASK); 1211 val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) | 1212 ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT); 1213 1214 if (enable) { 1215 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_5, val | 1216 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 1217 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_5, val); 1218 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_2, 1219 ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) | 1220 ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) | 1221 ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) | 1222 ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) | 1223 ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT)); 1224 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_3, 1225 ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) | 1226 ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) | 1227 ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) | 1228 ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT)); 1229 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_4, 1230 ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) | 1231 ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) | 1232 ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) | 1233 ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT)); 1234 1235 HDMI_WRITE(VC4_HDMI_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC); 1236 } else { 1237 HDMI_WRITE(VC4_HDMI_CPU_MASK_SET, VC4_HDMI_CPU_CEC); 1238 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_5, val | 1239 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 1240 } 1241 return 0; 1242 } 1243 1244 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr) 1245 { 1246 struct vc4_dev *vc4 = cec_get_drvdata(adap); 1247 1248 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, 1249 (HDMI_READ(VC4_HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) | 1250 (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT); 1251 return 0; 1252 } 1253 1254 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts, 1255 u32 signal_free_time, struct cec_msg *msg) 1256 { 1257 struct vc4_dev *vc4 = cec_get_drvdata(adap); 1258 u32 val; 1259 unsigned int i; 1260 1261 for (i = 0; i < msg->len; i += 4) 1262 HDMI_WRITE(VC4_HDMI_CEC_TX_DATA_1 + i, 1263 (msg->msg[i]) | 1264 (msg->msg[i + 1] << 8) | 1265 (msg->msg[i + 2] << 16) | 1266 (msg->msg[i + 3] << 24)); 1267 1268 val = HDMI_READ(VC4_HDMI_CEC_CNTRL_1); 1269 val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 1270 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, val); 1271 val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK; 1272 val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT; 1273 val |= VC4_HDMI_CEC_START_XMIT_BEGIN; 1274 1275 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, val); 1276 return 0; 1277 } 1278 1279 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = { 1280 .adap_enable = vc4_hdmi_cec_adap_enable, 1281 .adap_log_addr = vc4_hdmi_cec_adap_log_addr, 1282 .adap_transmit = vc4_hdmi_cec_adap_transmit, 1283 }; 1284 #endif 1285 1286 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data) 1287 { 1288 struct platform_device *pdev = to_platform_device(dev); 1289 struct drm_device *drm = dev_get_drvdata(master); 1290 struct vc4_dev *vc4 = drm->dev_private; 1291 struct vc4_hdmi *hdmi; 1292 struct vc4_hdmi_encoder *vc4_hdmi_encoder; 1293 struct device_node *ddc_node; 1294 u32 value; 1295 int ret; 1296 1297 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); 1298 if (!hdmi) 1299 return -ENOMEM; 1300 1301 vc4_hdmi_encoder = devm_kzalloc(dev, sizeof(*vc4_hdmi_encoder), 1302 GFP_KERNEL); 1303 if (!vc4_hdmi_encoder) 1304 return -ENOMEM; 1305 vc4_hdmi_encoder->base.type = VC4_ENCODER_TYPE_HDMI; 1306 hdmi->encoder = &vc4_hdmi_encoder->base.base; 1307 1308 hdmi->pdev = pdev; 1309 hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0); 1310 if (IS_ERR(hdmi->hdmicore_regs)) 1311 return PTR_ERR(hdmi->hdmicore_regs); 1312 1313 hdmi->hd_regs = vc4_ioremap_regs(pdev, 1); 1314 if (IS_ERR(hdmi->hd_regs)) 1315 return PTR_ERR(hdmi->hd_regs); 1316 1317 hdmi->hdmi_regset.base = hdmi->hdmicore_regs; 1318 hdmi->hdmi_regset.regs = hdmi_regs; 1319 hdmi->hdmi_regset.nregs = ARRAY_SIZE(hdmi_regs); 1320 hdmi->hd_regset.base = hdmi->hd_regs; 1321 hdmi->hd_regset.regs = hd_regs; 1322 hdmi->hd_regset.nregs = ARRAY_SIZE(hd_regs); 1323 1324 hdmi->pixel_clock = devm_clk_get(dev, "pixel"); 1325 if (IS_ERR(hdmi->pixel_clock)) { 1326 DRM_ERROR("Failed to get pixel clock\n"); 1327 return PTR_ERR(hdmi->pixel_clock); 1328 } 1329 hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); 1330 if (IS_ERR(hdmi->hsm_clock)) { 1331 DRM_ERROR("Failed to get HDMI state machine clock\n"); 1332 return PTR_ERR(hdmi->hsm_clock); 1333 } 1334 1335 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0); 1336 if (!ddc_node) { 1337 DRM_ERROR("Failed to find ddc node in device tree\n"); 1338 return -ENODEV; 1339 } 1340 1341 hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node); 1342 of_node_put(ddc_node); 1343 if (!hdmi->ddc) { 1344 DRM_DEBUG("Failed to get ddc i2c adapter by node\n"); 1345 return -EPROBE_DEFER; 1346 } 1347 1348 /* This is the rate that is set by the firmware. The number 1349 * needs to be a bit higher than the pixel clock rate 1350 * (generally 148.5Mhz). 1351 */ 1352 ret = clk_set_rate(hdmi->hsm_clock, HSM_CLOCK_FREQ); 1353 if (ret) { 1354 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret); 1355 goto err_put_i2c; 1356 } 1357 1358 ret = clk_prepare_enable(hdmi->hsm_clock); 1359 if (ret) { 1360 DRM_ERROR("Failed to turn on HDMI state machine clock: %d\n", 1361 ret); 1362 goto err_put_i2c; 1363 } 1364 1365 /* Only use the GPIO HPD pin if present in the DT, otherwise 1366 * we'll use the HDMI core's register. 1367 */ 1368 if (of_find_property(dev->of_node, "hpd-gpios", &value)) { 1369 enum of_gpio_flags hpd_gpio_flags; 1370 1371 hdmi->hpd_gpio = of_get_named_gpio_flags(dev->of_node, 1372 "hpd-gpios", 0, 1373 &hpd_gpio_flags); 1374 if (hdmi->hpd_gpio < 0) { 1375 ret = hdmi->hpd_gpio; 1376 goto err_unprepare_hsm; 1377 } 1378 1379 hdmi->hpd_active_low = hpd_gpio_flags & OF_GPIO_ACTIVE_LOW; 1380 } 1381 1382 vc4->hdmi = hdmi; 1383 1384 /* HDMI core must be enabled. */ 1385 if (!(HD_READ(VC4_HD_M_CTL) & VC4_HD_M_ENABLE)) { 1386 HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_SW_RST); 1387 udelay(1); 1388 HD_WRITE(VC4_HD_M_CTL, 0); 1389 1390 HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_ENABLE); 1391 } 1392 pm_runtime_enable(dev); 1393 1394 drm_encoder_init(drm, hdmi->encoder, &vc4_hdmi_encoder_funcs, 1395 DRM_MODE_ENCODER_TMDS, NULL); 1396 drm_encoder_helper_add(hdmi->encoder, &vc4_hdmi_encoder_helper_funcs); 1397 1398 hdmi->connector = vc4_hdmi_connector_init(drm, hdmi->encoder); 1399 if (IS_ERR(hdmi->connector)) { 1400 ret = PTR_ERR(hdmi->connector); 1401 goto err_destroy_encoder; 1402 } 1403 #ifdef CONFIG_DRM_VC4_HDMI_CEC 1404 hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops, 1405 vc4, "vc4", 1406 CEC_CAP_TRANSMIT | 1407 CEC_CAP_LOG_ADDRS | 1408 CEC_CAP_PASSTHROUGH | 1409 CEC_CAP_RC, 1); 1410 ret = PTR_ERR_OR_ZERO(hdmi->cec_adap); 1411 if (ret < 0) 1412 goto err_destroy_conn; 1413 HDMI_WRITE(VC4_HDMI_CPU_MASK_SET, 0xffffffff); 1414 value = HDMI_READ(VC4_HDMI_CEC_CNTRL_1); 1415 value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK; 1416 /* 1417 * Set the logical address to Unregistered and set the clock 1418 * divider: the hsm_clock rate and this divider setting will 1419 * give a 40 kHz CEC clock. 1420 */ 1421 value |= VC4_HDMI_CEC_ADDR_MASK | 1422 (4091 << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT); 1423 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, value); 1424 ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0), 1425 vc4_cec_irq_handler, 1426 vc4_cec_irq_handler_thread, 0, 1427 "vc4 hdmi cec", vc4); 1428 if (ret) 1429 goto err_delete_cec_adap; 1430 ret = cec_register_adapter(hdmi->cec_adap, dev); 1431 if (ret < 0) 1432 goto err_delete_cec_adap; 1433 #endif 1434 1435 ret = vc4_hdmi_audio_init(hdmi); 1436 if (ret) 1437 goto err_destroy_encoder; 1438 1439 vc4_debugfs_add_file(drm, "hdmi_regs", vc4_hdmi_debugfs_regs, hdmi); 1440 1441 return 0; 1442 1443 #ifdef CONFIG_DRM_VC4_HDMI_CEC 1444 err_delete_cec_adap: 1445 cec_delete_adapter(hdmi->cec_adap); 1446 err_destroy_conn: 1447 vc4_hdmi_connector_destroy(hdmi->connector); 1448 #endif 1449 err_destroy_encoder: 1450 vc4_hdmi_encoder_destroy(hdmi->encoder); 1451 err_unprepare_hsm: 1452 clk_disable_unprepare(hdmi->hsm_clock); 1453 pm_runtime_disable(dev); 1454 err_put_i2c: 1455 put_device(&hdmi->ddc->dev); 1456 1457 return ret; 1458 } 1459 1460 static void vc4_hdmi_unbind(struct device *dev, struct device *master, 1461 void *data) 1462 { 1463 struct drm_device *drm = dev_get_drvdata(master); 1464 struct vc4_dev *vc4 = drm->dev_private; 1465 struct vc4_hdmi *hdmi = vc4->hdmi; 1466 1467 cec_unregister_adapter(hdmi->cec_adap); 1468 vc4_hdmi_connector_destroy(hdmi->connector); 1469 vc4_hdmi_encoder_destroy(hdmi->encoder); 1470 1471 clk_disable_unprepare(hdmi->hsm_clock); 1472 pm_runtime_disable(dev); 1473 1474 put_device(&hdmi->ddc->dev); 1475 1476 vc4->hdmi = NULL; 1477 } 1478 1479 static const struct component_ops vc4_hdmi_ops = { 1480 .bind = vc4_hdmi_bind, 1481 .unbind = vc4_hdmi_unbind, 1482 }; 1483 1484 static int vc4_hdmi_dev_probe(struct platform_device *pdev) 1485 { 1486 return component_add(&pdev->dev, &vc4_hdmi_ops); 1487 } 1488 1489 static int vc4_hdmi_dev_remove(struct platform_device *pdev) 1490 { 1491 component_del(&pdev->dev, &vc4_hdmi_ops); 1492 return 0; 1493 } 1494 1495 static const struct of_device_id vc4_hdmi_dt_match[] = { 1496 { .compatible = "brcm,bcm2835-hdmi" }, 1497 {} 1498 }; 1499 1500 struct platform_driver vc4_hdmi_driver = { 1501 .probe = vc4_hdmi_dev_probe, 1502 .remove = vc4_hdmi_dev_remove, 1503 .driver = { 1504 .name = "vc4_hdmi", 1505 .of_match_table = vc4_hdmi_dt_match, 1506 }, 1507 }; 1508