1 /* 2 * Copyright (C) 2015 Broadcom 3 * Copyright (c) 2014 The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License version 2 as published by 9 * the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 /** 21 * DOC: VC4 Falcon HDMI module 22 * 23 * The HDMI core has a state machine and a PHY. Most of the unit 24 * operates off of the HSM clock from CPRMAN. It also internally uses 25 * the PLLH_PIX clock for the PHY. 26 */ 27 28 #include "drm_atomic_helper.h" 29 #include "drm_crtc_helper.h" 30 #include "drm_edid.h" 31 #include "linux/clk.h" 32 #include "linux/component.h" 33 #include "linux/i2c.h" 34 #include "linux/of_gpio.h" 35 #include "linux/of_platform.h" 36 #include "vc4_drv.h" 37 #include "vc4_regs.h" 38 39 /* General HDMI hardware state. */ 40 struct vc4_hdmi { 41 struct platform_device *pdev; 42 43 struct drm_encoder *encoder; 44 struct drm_connector *connector; 45 46 struct i2c_adapter *ddc; 47 void __iomem *hdmicore_regs; 48 void __iomem *hd_regs; 49 int hpd_gpio; 50 bool hpd_active_low; 51 52 struct clk *pixel_clock; 53 struct clk *hsm_clock; 54 }; 55 56 #define HDMI_READ(offset) readl(vc4->hdmi->hdmicore_regs + offset) 57 #define HDMI_WRITE(offset, val) writel(val, vc4->hdmi->hdmicore_regs + offset) 58 #define HD_READ(offset) readl(vc4->hdmi->hd_regs + offset) 59 #define HD_WRITE(offset, val) writel(val, vc4->hdmi->hd_regs + offset) 60 61 /* VC4 HDMI encoder KMS struct */ 62 struct vc4_hdmi_encoder { 63 struct vc4_encoder base; 64 bool hdmi_monitor; 65 }; 66 67 static inline struct vc4_hdmi_encoder * 68 to_vc4_hdmi_encoder(struct drm_encoder *encoder) 69 { 70 return container_of(encoder, struct vc4_hdmi_encoder, base.base); 71 } 72 73 /* VC4 HDMI connector KMS struct */ 74 struct vc4_hdmi_connector { 75 struct drm_connector base; 76 77 /* Since the connector is attached to just the one encoder, 78 * this is the reference to it so we can do the best_encoder() 79 * hook. 80 */ 81 struct drm_encoder *encoder; 82 }; 83 84 static inline struct vc4_hdmi_connector * 85 to_vc4_hdmi_connector(struct drm_connector *connector) 86 { 87 return container_of(connector, struct vc4_hdmi_connector, base); 88 } 89 90 #define HDMI_REG(reg) { reg, #reg } 91 static const struct { 92 u32 reg; 93 const char *name; 94 } hdmi_regs[] = { 95 HDMI_REG(VC4_HDMI_CORE_REV), 96 HDMI_REG(VC4_HDMI_SW_RESET_CONTROL), 97 HDMI_REG(VC4_HDMI_HOTPLUG_INT), 98 HDMI_REG(VC4_HDMI_HOTPLUG), 99 HDMI_REG(VC4_HDMI_RAM_PACKET_CONFIG), 100 HDMI_REG(VC4_HDMI_HORZA), 101 HDMI_REG(VC4_HDMI_HORZB), 102 HDMI_REG(VC4_HDMI_FIFO_CTL), 103 HDMI_REG(VC4_HDMI_SCHEDULER_CONTROL), 104 HDMI_REG(VC4_HDMI_VERTA0), 105 HDMI_REG(VC4_HDMI_VERTA1), 106 HDMI_REG(VC4_HDMI_VERTB0), 107 HDMI_REG(VC4_HDMI_VERTB1), 108 HDMI_REG(VC4_HDMI_TX_PHY_RESET_CTL), 109 }; 110 111 static const struct { 112 u32 reg; 113 const char *name; 114 } hd_regs[] = { 115 HDMI_REG(VC4_HD_M_CTL), 116 HDMI_REG(VC4_HD_MAI_CTL), 117 HDMI_REG(VC4_HD_VID_CTL), 118 HDMI_REG(VC4_HD_CSC_CTL), 119 HDMI_REG(VC4_HD_FRAME_COUNT), 120 }; 121 122 #ifdef CONFIG_DEBUG_FS 123 int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused) 124 { 125 struct drm_info_node *node = (struct drm_info_node *)m->private; 126 struct drm_device *dev = node->minor->dev; 127 struct vc4_dev *vc4 = to_vc4_dev(dev); 128 int i; 129 130 for (i = 0; i < ARRAY_SIZE(hdmi_regs); i++) { 131 seq_printf(m, "%s (0x%04x): 0x%08x\n", 132 hdmi_regs[i].name, hdmi_regs[i].reg, 133 HDMI_READ(hdmi_regs[i].reg)); 134 } 135 136 for (i = 0; i < ARRAY_SIZE(hd_regs); i++) { 137 seq_printf(m, "%s (0x%04x): 0x%08x\n", 138 hd_regs[i].name, hd_regs[i].reg, 139 HD_READ(hd_regs[i].reg)); 140 } 141 142 return 0; 143 } 144 #endif /* CONFIG_DEBUG_FS */ 145 146 static void vc4_hdmi_dump_regs(struct drm_device *dev) 147 { 148 struct vc4_dev *vc4 = to_vc4_dev(dev); 149 int i; 150 151 for (i = 0; i < ARRAY_SIZE(hdmi_regs); i++) { 152 DRM_INFO("0x%04x (%s): 0x%08x\n", 153 hdmi_regs[i].reg, hdmi_regs[i].name, 154 HDMI_READ(hdmi_regs[i].reg)); 155 } 156 for (i = 0; i < ARRAY_SIZE(hd_regs); i++) { 157 DRM_INFO("0x%04x (%s): 0x%08x\n", 158 hd_regs[i].reg, hd_regs[i].name, 159 HD_READ(hd_regs[i].reg)); 160 } 161 } 162 163 static enum drm_connector_status 164 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force) 165 { 166 struct drm_device *dev = connector->dev; 167 struct vc4_dev *vc4 = to_vc4_dev(dev); 168 169 if (vc4->hdmi->hpd_gpio) { 170 if (gpio_get_value_cansleep(vc4->hdmi->hpd_gpio) ^ 171 vc4->hdmi->hpd_active_low) 172 return connector_status_connected; 173 else 174 return connector_status_disconnected; 175 } 176 177 if (HDMI_READ(VC4_HDMI_HOTPLUG) & VC4_HDMI_HOTPLUG_CONNECTED) 178 return connector_status_connected; 179 else 180 return connector_status_disconnected; 181 } 182 183 static void vc4_hdmi_connector_destroy(struct drm_connector *connector) 184 { 185 drm_connector_unregister(connector); 186 drm_connector_cleanup(connector); 187 } 188 189 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector) 190 { 191 struct vc4_hdmi_connector *vc4_connector = 192 to_vc4_hdmi_connector(connector); 193 struct drm_encoder *encoder = vc4_connector->encoder; 194 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 195 struct drm_device *dev = connector->dev; 196 struct vc4_dev *vc4 = to_vc4_dev(dev); 197 int ret = 0; 198 struct edid *edid; 199 200 edid = drm_get_edid(connector, vc4->hdmi->ddc); 201 if (!edid) 202 return -ENODEV; 203 204 vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid); 205 drm_mode_connector_update_edid_property(connector, edid); 206 ret = drm_add_edid_modes(connector, edid); 207 208 return ret; 209 } 210 211 static struct drm_encoder * 212 vc4_hdmi_connector_best_encoder(struct drm_connector *connector) 213 { 214 struct vc4_hdmi_connector *hdmi_connector = 215 to_vc4_hdmi_connector(connector); 216 return hdmi_connector->encoder; 217 } 218 219 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = { 220 .dpms = drm_atomic_helper_connector_dpms, 221 .detect = vc4_hdmi_connector_detect, 222 .fill_modes = drm_helper_probe_single_connector_modes, 223 .destroy = vc4_hdmi_connector_destroy, 224 .reset = drm_atomic_helper_connector_reset, 225 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 226 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 227 }; 228 229 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = { 230 .get_modes = vc4_hdmi_connector_get_modes, 231 .best_encoder = vc4_hdmi_connector_best_encoder, 232 }; 233 234 static struct drm_connector *vc4_hdmi_connector_init(struct drm_device *dev, 235 struct drm_encoder *encoder) 236 { 237 struct drm_connector *connector = NULL; 238 struct vc4_hdmi_connector *hdmi_connector; 239 int ret = 0; 240 241 hdmi_connector = devm_kzalloc(dev->dev, sizeof(*hdmi_connector), 242 GFP_KERNEL); 243 if (!hdmi_connector) { 244 ret = -ENOMEM; 245 goto fail; 246 } 247 connector = &hdmi_connector->base; 248 249 hdmi_connector->encoder = encoder; 250 251 drm_connector_init(dev, connector, &vc4_hdmi_connector_funcs, 252 DRM_MODE_CONNECTOR_HDMIA); 253 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs); 254 255 connector->polled = (DRM_CONNECTOR_POLL_CONNECT | 256 DRM_CONNECTOR_POLL_DISCONNECT); 257 258 connector->interlace_allowed = 0; 259 connector->doublescan_allowed = 0; 260 261 drm_mode_connector_attach_encoder(connector, encoder); 262 263 return connector; 264 265 fail: 266 if (connector) 267 vc4_hdmi_connector_destroy(connector); 268 269 return ERR_PTR(ret); 270 } 271 272 static void vc4_hdmi_encoder_destroy(struct drm_encoder *encoder) 273 { 274 drm_encoder_cleanup(encoder); 275 } 276 277 static const struct drm_encoder_funcs vc4_hdmi_encoder_funcs = { 278 .destroy = vc4_hdmi_encoder_destroy, 279 }; 280 281 static void vc4_hdmi_encoder_mode_set(struct drm_encoder *encoder, 282 struct drm_display_mode *unadjusted_mode, 283 struct drm_display_mode *mode) 284 { 285 struct drm_device *dev = encoder->dev; 286 struct vc4_dev *vc4 = to_vc4_dev(dev); 287 bool debug_dump_regs = false; 288 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 289 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 290 u32 vactive = (mode->vdisplay >> 291 ((mode->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0)); 292 u32 verta = (VC4_SET_FIELD(mode->vsync_end - mode->vsync_start, 293 VC4_HDMI_VERTA_VSP) | 294 VC4_SET_FIELD(mode->vsync_start - mode->vdisplay, 295 VC4_HDMI_VERTA_VFP) | 296 VC4_SET_FIELD(vactive, VC4_HDMI_VERTA_VAL)); 297 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 298 VC4_SET_FIELD(mode->vtotal - mode->vsync_end, 299 VC4_HDMI_VERTB_VBP)); 300 301 if (debug_dump_regs) { 302 DRM_INFO("HDMI regs before:\n"); 303 vc4_hdmi_dump_regs(dev); 304 } 305 306 HD_WRITE(VC4_HD_VID_CTL, 0); 307 308 clk_set_rate(vc4->hdmi->pixel_clock, mode->clock * 1000); 309 310 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL, 311 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) | 312 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT | 313 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS); 314 315 HDMI_WRITE(VC4_HDMI_HORZA, 316 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) | 317 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) | 318 VC4_SET_FIELD(mode->hdisplay, VC4_HDMI_HORZA_HAP)); 319 320 HDMI_WRITE(VC4_HDMI_HORZB, 321 VC4_SET_FIELD(mode->htotal - mode->hsync_end, 322 VC4_HDMI_HORZB_HBP) | 323 VC4_SET_FIELD(mode->hsync_end - mode->hsync_start, 324 VC4_HDMI_HORZB_HSP) | 325 VC4_SET_FIELD(mode->hsync_start - mode->hdisplay, 326 VC4_HDMI_HORZB_HFP)); 327 328 HDMI_WRITE(VC4_HDMI_VERTA0, verta); 329 HDMI_WRITE(VC4_HDMI_VERTA1, verta); 330 331 HDMI_WRITE(VC4_HDMI_VERTB0, vertb); 332 HDMI_WRITE(VC4_HDMI_VERTB1, vertb); 333 334 HD_WRITE(VC4_HD_VID_CTL, 335 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) | 336 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW)); 337 338 /* The RGB order applies even when CSC is disabled. */ 339 HD_WRITE(VC4_HD_CSC_CTL, VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR, 340 VC4_HD_CSC_CTL_ORDER)); 341 342 HDMI_WRITE(VC4_HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N); 343 344 if (debug_dump_regs) { 345 DRM_INFO("HDMI regs after:\n"); 346 vc4_hdmi_dump_regs(dev); 347 } 348 } 349 350 static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder) 351 { 352 struct drm_device *dev = encoder->dev; 353 struct vc4_dev *vc4 = to_vc4_dev(dev); 354 355 HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16); 356 HD_WRITE(VC4_HD_VID_CTL, 357 HD_READ(VC4_HD_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE); 358 } 359 360 static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder) 361 { 362 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 363 struct drm_device *dev = encoder->dev; 364 struct vc4_dev *vc4 = to_vc4_dev(dev); 365 int ret; 366 367 HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0); 368 369 HD_WRITE(VC4_HD_VID_CTL, 370 HD_READ(VC4_HD_VID_CTL) | 371 VC4_HD_VID_CTL_ENABLE | 372 VC4_HD_VID_CTL_UNDERFLOW_ENABLE | 373 VC4_HD_VID_CTL_FRAME_COUNTER_RESET); 374 375 if (vc4_encoder->hdmi_monitor) { 376 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL, 377 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) | 378 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 379 380 ret = wait_for(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) & 381 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1); 382 WARN_ONCE(ret, "Timeout waiting for " 383 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 384 } else { 385 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, 386 HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) & 387 ~(VC4_HDMI_RAM_PACKET_ENABLE)); 388 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL, 389 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) & 390 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 391 392 ret = wait_for(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) & 393 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1); 394 WARN_ONCE(ret, "Timeout waiting for " 395 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 396 } 397 398 if (vc4_encoder->hdmi_monitor) { 399 u32 drift; 400 401 WARN_ON(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) & 402 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE)); 403 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL, 404 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) | 405 VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT); 406 407 /* XXX: Set HDMI_RAM_PACKET_CONFIG (1 << 16) and set 408 * up the infoframe. 409 */ 410 411 drift = HDMI_READ(VC4_HDMI_FIFO_CTL); 412 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK; 413 414 HDMI_WRITE(VC4_HDMI_FIFO_CTL, 415 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 416 HDMI_WRITE(VC4_HDMI_FIFO_CTL, 417 drift | VC4_HDMI_FIFO_CTL_RECENTER); 418 udelay(1000); 419 HDMI_WRITE(VC4_HDMI_FIFO_CTL, 420 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 421 HDMI_WRITE(VC4_HDMI_FIFO_CTL, 422 drift | VC4_HDMI_FIFO_CTL_RECENTER); 423 424 ret = wait_for(HDMI_READ(VC4_HDMI_FIFO_CTL) & 425 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1); 426 WARN_ONCE(ret, "Timeout waiting for " 427 "VC4_HDMI_FIFO_CTL_RECENTER_DONE"); 428 } 429 } 430 431 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = { 432 .mode_set = vc4_hdmi_encoder_mode_set, 433 .disable = vc4_hdmi_encoder_disable, 434 .enable = vc4_hdmi_encoder_enable, 435 }; 436 437 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data) 438 { 439 struct platform_device *pdev = to_platform_device(dev); 440 struct drm_device *drm = dev_get_drvdata(master); 441 struct vc4_dev *vc4 = drm->dev_private; 442 struct vc4_hdmi *hdmi; 443 struct vc4_hdmi_encoder *vc4_hdmi_encoder; 444 struct device_node *ddc_node; 445 u32 value; 446 int ret; 447 448 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); 449 if (!hdmi) 450 return -ENOMEM; 451 452 vc4_hdmi_encoder = devm_kzalloc(dev, sizeof(*vc4_hdmi_encoder), 453 GFP_KERNEL); 454 if (!vc4_hdmi_encoder) 455 return -ENOMEM; 456 vc4_hdmi_encoder->base.type = VC4_ENCODER_TYPE_HDMI; 457 hdmi->encoder = &vc4_hdmi_encoder->base.base; 458 459 hdmi->pdev = pdev; 460 hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0); 461 if (IS_ERR(hdmi->hdmicore_regs)) 462 return PTR_ERR(hdmi->hdmicore_regs); 463 464 hdmi->hd_regs = vc4_ioremap_regs(pdev, 1); 465 if (IS_ERR(hdmi->hd_regs)) 466 return PTR_ERR(hdmi->hd_regs); 467 468 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0); 469 if (!ddc_node) { 470 DRM_ERROR("Failed to find ddc node in device tree\n"); 471 return -ENODEV; 472 } 473 474 hdmi->pixel_clock = devm_clk_get(dev, "pixel"); 475 if (IS_ERR(hdmi->pixel_clock)) { 476 DRM_ERROR("Failed to get pixel clock\n"); 477 return PTR_ERR(hdmi->pixel_clock); 478 } 479 hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); 480 if (IS_ERR(hdmi->hsm_clock)) { 481 DRM_ERROR("Failed to get HDMI state machine clock\n"); 482 return PTR_ERR(hdmi->hsm_clock); 483 } 484 485 hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node); 486 if (!hdmi->ddc) { 487 DRM_DEBUG("Failed to get ddc i2c adapter by node\n"); 488 return -EPROBE_DEFER; 489 } 490 491 /* Enable the clocks at startup. We can't quite recover from 492 * turning off the pixel clock during disable/enables yet, so 493 * it's always running. 494 */ 495 ret = clk_prepare_enable(hdmi->pixel_clock); 496 if (ret) { 497 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret); 498 goto err_put_i2c; 499 } 500 501 /* This is the rate that is set by the firmware. The number 502 * needs to be a bit higher than the pixel clock rate 503 * (generally 148.5Mhz). 504 */ 505 ret = clk_set_rate(hdmi->hsm_clock, 163682864); 506 if (ret) { 507 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret); 508 goto err_unprepare_pix; 509 } 510 511 ret = clk_prepare_enable(hdmi->hsm_clock); 512 if (ret) { 513 DRM_ERROR("Failed to turn on HDMI state machine clock: %d\n", 514 ret); 515 goto err_unprepare_pix; 516 } 517 518 /* Only use the GPIO HPD pin if present in the DT, otherwise 519 * we'll use the HDMI core's register. 520 */ 521 if (of_find_property(dev->of_node, "hpd-gpios", &value)) { 522 enum of_gpio_flags hpd_gpio_flags; 523 524 hdmi->hpd_gpio = of_get_named_gpio_flags(dev->of_node, 525 "hpd-gpios", 0, 526 &hpd_gpio_flags); 527 if (hdmi->hpd_gpio < 0) { 528 ret = hdmi->hpd_gpio; 529 goto err_unprepare_hsm; 530 } 531 532 hdmi->hpd_active_low = hpd_gpio_flags & OF_GPIO_ACTIVE_LOW; 533 } 534 535 vc4->hdmi = hdmi; 536 537 /* HDMI core must be enabled. */ 538 if (!(HD_READ(VC4_HD_M_CTL) & VC4_HD_M_ENABLE)) { 539 HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_SW_RST); 540 udelay(1); 541 HD_WRITE(VC4_HD_M_CTL, 0); 542 543 HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_ENABLE); 544 545 HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL, 546 VC4_HDMI_SW_RESET_HDMI | 547 VC4_HDMI_SW_RESET_FORMAT_DETECT); 548 549 HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL, 0); 550 551 /* PHY should be in reset, like 552 * vc4_hdmi_encoder_disable() does. 553 */ 554 HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16); 555 } 556 557 drm_encoder_init(drm, hdmi->encoder, &vc4_hdmi_encoder_funcs, 558 DRM_MODE_ENCODER_TMDS, NULL); 559 drm_encoder_helper_add(hdmi->encoder, &vc4_hdmi_encoder_helper_funcs); 560 561 hdmi->connector = vc4_hdmi_connector_init(drm, hdmi->encoder); 562 if (IS_ERR(hdmi->connector)) { 563 ret = PTR_ERR(hdmi->connector); 564 goto err_destroy_encoder; 565 } 566 567 return 0; 568 569 err_destroy_encoder: 570 vc4_hdmi_encoder_destroy(hdmi->encoder); 571 err_unprepare_hsm: 572 clk_disable_unprepare(hdmi->hsm_clock); 573 err_unprepare_pix: 574 clk_disable_unprepare(hdmi->pixel_clock); 575 err_put_i2c: 576 put_device(&hdmi->ddc->dev); 577 578 return ret; 579 } 580 581 static void vc4_hdmi_unbind(struct device *dev, struct device *master, 582 void *data) 583 { 584 struct drm_device *drm = dev_get_drvdata(master); 585 struct vc4_dev *vc4 = drm->dev_private; 586 struct vc4_hdmi *hdmi = vc4->hdmi; 587 588 vc4_hdmi_connector_destroy(hdmi->connector); 589 vc4_hdmi_encoder_destroy(hdmi->encoder); 590 591 clk_disable_unprepare(hdmi->pixel_clock); 592 clk_disable_unprepare(hdmi->hsm_clock); 593 put_device(&hdmi->ddc->dev); 594 595 vc4->hdmi = NULL; 596 } 597 598 static const struct component_ops vc4_hdmi_ops = { 599 .bind = vc4_hdmi_bind, 600 .unbind = vc4_hdmi_unbind, 601 }; 602 603 static int vc4_hdmi_dev_probe(struct platform_device *pdev) 604 { 605 return component_add(&pdev->dev, &vc4_hdmi_ops); 606 } 607 608 static int vc4_hdmi_dev_remove(struct platform_device *pdev) 609 { 610 component_del(&pdev->dev, &vc4_hdmi_ops); 611 return 0; 612 } 613 614 static const struct of_device_id vc4_hdmi_dt_match[] = { 615 { .compatible = "brcm,bcm2835-hdmi" }, 616 {} 617 }; 618 619 struct platform_driver vc4_hdmi_driver = { 620 .probe = vc4_hdmi_dev_probe, 621 .remove = vc4_hdmi_dev_remove, 622 .driver = { 623 .name = "vc4_hdmi", 624 .of_match_table = vc4_hdmi_dt_match, 625 }, 626 }; 627