1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 Broadcom 4 * Copyright (c) 2014 The Linux Foundation. All rights reserved. 5 * Copyright (C) 2013 Red Hat 6 * Author: Rob Clark <robdclark@gmail.com> 7 */ 8 9 /** 10 * DOC: VC4 Falcon HDMI module 11 * 12 * The HDMI core has a state machine and a PHY. On BCM2835, most of 13 * the unit operates off of the HSM clock from CPRMAN. It also 14 * internally uses the PLLH_PIX clock for the PHY. 15 * 16 * HDMI infoframes are kept within a small packet ram, where each 17 * packet can be individually enabled for including in a frame. 18 * 19 * HDMI audio is implemented entirely within the HDMI IP block. A 20 * register in the HDMI encoder takes SPDIF frames from the DMA engine 21 * and transfers them over an internal MAI (multi-channel audio 22 * interconnect) bus to the encoder side for insertion into the video 23 * blank regions. 24 * 25 * The driver's HDMI encoder does not yet support power management. 26 * The HDMI encoder's power domain and the HSM/pixel clocks are kept 27 * continuously running, and only the HDMI logic and packet ram are 28 * powered off/on at disable/enable time. 29 * 30 * The driver does not yet support CEC control, though the HDMI 31 * encoder block has CEC support. 32 */ 33 34 #include <drm/display/drm_hdmi_helper.h> 35 #include <drm/display/drm_scdc_helper.h> 36 #include <drm/drm_atomic_helper.h> 37 #include <drm/drm_drv.h> 38 #include <drm/drm_probe_helper.h> 39 #include <drm/drm_simple_kms_helper.h> 40 #include <linux/clk.h> 41 #include <linux/component.h> 42 #include <linux/gpio/consumer.h> 43 #include <linux/i2c.h> 44 #include <linux/of_address.h> 45 #include <linux/of_platform.h> 46 #include <linux/pm_runtime.h> 47 #include <linux/rational.h> 48 #include <linux/reset.h> 49 #include <sound/dmaengine_pcm.h> 50 #include <sound/hdmi-codec.h> 51 #include <sound/pcm_drm_eld.h> 52 #include <sound/pcm_params.h> 53 #include <sound/soc.h> 54 #include "media/cec.h" 55 #include "vc4_drv.h" 56 #include "vc4_hdmi.h" 57 #include "vc4_hdmi_regs.h" 58 #include "vc4_regs.h" 59 60 #define VC5_HDMI_HORZA_HFP_SHIFT 16 61 #define VC5_HDMI_HORZA_HFP_MASK VC4_MASK(28, 16) 62 #define VC5_HDMI_HORZA_VPOS BIT(15) 63 #define VC5_HDMI_HORZA_HPOS BIT(14) 64 #define VC5_HDMI_HORZA_HAP_SHIFT 0 65 #define VC5_HDMI_HORZA_HAP_MASK VC4_MASK(13, 0) 66 67 #define VC5_HDMI_HORZB_HBP_SHIFT 16 68 #define VC5_HDMI_HORZB_HBP_MASK VC4_MASK(26, 16) 69 #define VC5_HDMI_HORZB_HSP_SHIFT 0 70 #define VC5_HDMI_HORZB_HSP_MASK VC4_MASK(10, 0) 71 72 #define VC5_HDMI_VERTA_VSP_SHIFT 24 73 #define VC5_HDMI_VERTA_VSP_MASK VC4_MASK(28, 24) 74 #define VC5_HDMI_VERTA_VFP_SHIFT 16 75 #define VC5_HDMI_VERTA_VFP_MASK VC4_MASK(22, 16) 76 #define VC5_HDMI_VERTA_VAL_SHIFT 0 77 #define VC5_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0) 78 79 #define VC5_HDMI_VERTB_VSPO_SHIFT 16 80 #define VC5_HDMI_VERTB_VSPO_MASK VC4_MASK(29, 16) 81 82 #define VC4_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT 0 83 #define VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK VC4_MASK(3, 0) 84 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT 0 85 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK VC4_MASK(3, 0) 86 87 #define VC5_HDMI_SCRAMBLER_CTL_ENABLE BIT(0) 88 89 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT 8 90 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK VC4_MASK(10, 8) 91 92 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT 0 93 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK VC4_MASK(3, 0) 94 95 #define VC5_HDMI_GCP_CONFIG_GCP_ENABLE BIT(31) 96 97 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT 8 98 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK VC4_MASK(15, 8) 99 100 # define VC4_HD_M_SW_RST BIT(2) 101 # define VC4_HD_M_ENABLE BIT(0) 102 103 #define HSM_MIN_CLOCK_FREQ 120000000 104 #define CEC_CLOCK_FREQ 40000 105 106 #define HDMI_14_MAX_TMDS_CLK (340 * 1000 * 1000) 107 108 static const char * const output_format_str[] = { 109 [VC4_HDMI_OUTPUT_RGB] = "RGB", 110 [VC4_HDMI_OUTPUT_YUV420] = "YUV 4:2:0", 111 [VC4_HDMI_OUTPUT_YUV422] = "YUV 4:2:2", 112 [VC4_HDMI_OUTPUT_YUV444] = "YUV 4:4:4", 113 }; 114 115 static const char *vc4_hdmi_output_fmt_str(enum vc4_hdmi_output_format fmt) 116 { 117 if (fmt >= ARRAY_SIZE(output_format_str)) 118 return "invalid"; 119 120 return output_format_str[fmt]; 121 } 122 123 static unsigned long long 124 vc4_hdmi_encoder_compute_mode_clock(const struct drm_display_mode *mode, 125 unsigned int bpc, enum vc4_hdmi_output_format fmt); 126 127 static bool vc4_hdmi_supports_scrambling(struct vc4_hdmi *vc4_hdmi) 128 { 129 struct drm_display_info *display = &vc4_hdmi->connector.display_info; 130 131 lockdep_assert_held(&vc4_hdmi->mutex); 132 133 if (!display->is_hdmi) 134 return false; 135 136 if (!display->hdmi.scdc.supported || 137 !display->hdmi.scdc.scrambling.supported) 138 return false; 139 140 return true; 141 } 142 143 static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode, 144 unsigned int bpc, 145 enum vc4_hdmi_output_format fmt) 146 { 147 unsigned long long clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc, fmt); 148 149 return clock > HDMI_14_MAX_TMDS_CLK; 150 } 151 152 static bool vc4_hdmi_is_full_range_rgb(struct vc4_hdmi *vc4_hdmi, 153 const struct drm_display_mode *mode) 154 { 155 struct drm_display_info *display = &vc4_hdmi->connector.display_info; 156 157 return !display->is_hdmi || 158 drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_FULL; 159 } 160 161 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused) 162 { 163 struct drm_debugfs_entry *entry = m->private; 164 struct vc4_hdmi *vc4_hdmi = entry->file.data; 165 struct drm_device *drm = vc4_hdmi->connector.dev; 166 struct drm_printer p = drm_seq_file_printer(m); 167 int idx; 168 169 if (!drm_dev_enter(drm, &idx)) 170 return -ENODEV; 171 172 drm_print_regset32(&p, &vc4_hdmi->hdmi_regset); 173 drm_print_regset32(&p, &vc4_hdmi->hd_regset); 174 drm_print_regset32(&p, &vc4_hdmi->cec_regset); 175 drm_print_regset32(&p, &vc4_hdmi->csc_regset); 176 drm_print_regset32(&p, &vc4_hdmi->dvp_regset); 177 drm_print_regset32(&p, &vc4_hdmi->phy_regset); 178 drm_print_regset32(&p, &vc4_hdmi->ram_regset); 179 drm_print_regset32(&p, &vc4_hdmi->rm_regset); 180 181 drm_dev_exit(idx); 182 183 return 0; 184 } 185 186 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi) 187 { 188 struct drm_device *drm = vc4_hdmi->connector.dev; 189 unsigned long flags; 190 int idx; 191 192 /* 193 * We can be called by our bind callback, when the 194 * connector->dev pointer might not be initialised yet. 195 */ 196 if (drm && !drm_dev_enter(drm, &idx)) 197 return; 198 199 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 200 201 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST); 202 udelay(1); 203 HDMI_WRITE(HDMI_M_CTL, 0); 204 205 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE); 206 207 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 208 VC4_HDMI_SW_RESET_HDMI | 209 VC4_HDMI_SW_RESET_FORMAT_DETECT); 210 211 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0); 212 213 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 214 215 if (drm) 216 drm_dev_exit(idx); 217 } 218 219 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi) 220 { 221 struct drm_device *drm = vc4_hdmi->connector.dev; 222 unsigned long flags; 223 int idx; 224 225 /* 226 * We can be called by our bind callback, when the 227 * connector->dev pointer might not be initialised yet. 228 */ 229 if (drm && !drm_dev_enter(drm, &idx)) 230 return; 231 232 reset_control_reset(vc4_hdmi->reset); 233 234 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 235 236 HDMI_WRITE(HDMI_DVP_CTL, 0); 237 238 HDMI_WRITE(HDMI_CLOCK_STOP, 239 HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL); 240 241 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 242 243 if (drm) 244 drm_dev_exit(idx); 245 } 246 247 #ifdef CONFIG_DRM_VC4_HDMI_CEC 248 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) 249 { 250 struct drm_device *drm = vc4_hdmi->connector.dev; 251 unsigned long cec_rate; 252 unsigned long flags; 253 u16 clk_cnt; 254 u32 value; 255 int idx; 256 257 /* 258 * This function is called by our runtime_resume implementation 259 * and thus at bind time, when we haven't registered our 260 * connector yet and thus don't have a pointer to the DRM 261 * device. 262 */ 263 if (drm && !drm_dev_enter(drm, &idx)) 264 return; 265 266 cec_rate = clk_get_rate(vc4_hdmi->cec_clock); 267 268 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 269 270 value = HDMI_READ(HDMI_CEC_CNTRL_1); 271 value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK; 272 273 /* 274 * Set the clock divider: the hsm_clock rate and this divider 275 * setting will give a 40 kHz CEC clock. 276 */ 277 clk_cnt = cec_rate / CEC_CLOCK_FREQ; 278 value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT; 279 HDMI_WRITE(HDMI_CEC_CNTRL_1, value); 280 281 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 282 283 if (drm) 284 drm_dev_exit(idx); 285 } 286 #else 287 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {} 288 #endif 289 290 static int reset_pipe(struct drm_crtc *crtc, 291 struct drm_modeset_acquire_ctx *ctx) 292 { 293 struct drm_atomic_state *state; 294 struct drm_crtc_state *crtc_state; 295 int ret; 296 297 state = drm_atomic_state_alloc(crtc->dev); 298 if (!state) 299 return -ENOMEM; 300 301 state->acquire_ctx = ctx; 302 303 crtc_state = drm_atomic_get_crtc_state(state, crtc); 304 if (IS_ERR(crtc_state)) { 305 ret = PTR_ERR(crtc_state); 306 goto out; 307 } 308 309 crtc_state->connectors_changed = true; 310 311 ret = drm_atomic_commit(state); 312 out: 313 drm_atomic_state_put(state); 314 315 return ret; 316 } 317 318 static int vc4_hdmi_reset_link(struct drm_connector *connector, 319 struct drm_modeset_acquire_ctx *ctx) 320 { 321 struct drm_device *drm; 322 struct vc4_hdmi *vc4_hdmi; 323 struct drm_connector_state *conn_state; 324 struct drm_crtc_state *crtc_state; 325 struct drm_crtc *crtc; 326 bool scrambling_needed; 327 u8 config; 328 int ret; 329 330 if (!connector) 331 return 0; 332 333 drm = connector->dev; 334 ret = drm_modeset_lock(&drm->mode_config.connection_mutex, ctx); 335 if (ret) 336 return ret; 337 338 conn_state = connector->state; 339 crtc = conn_state->crtc; 340 if (!crtc) 341 return 0; 342 343 ret = drm_modeset_lock(&crtc->mutex, ctx); 344 if (ret) 345 return ret; 346 347 crtc_state = crtc->state; 348 if (!crtc_state->active) 349 return 0; 350 351 vc4_hdmi = connector_to_vc4_hdmi(connector); 352 mutex_lock(&vc4_hdmi->mutex); 353 354 if (!vc4_hdmi_supports_scrambling(vc4_hdmi)) { 355 mutex_unlock(&vc4_hdmi->mutex); 356 return 0; 357 } 358 359 scrambling_needed = vc4_hdmi_mode_needs_scrambling(&vc4_hdmi->saved_adjusted_mode, 360 vc4_hdmi->output_bpc, 361 vc4_hdmi->output_format); 362 if (!scrambling_needed) { 363 mutex_unlock(&vc4_hdmi->mutex); 364 return 0; 365 } 366 367 if (conn_state->commit && 368 !try_wait_for_completion(&conn_state->commit->hw_done)) { 369 mutex_unlock(&vc4_hdmi->mutex); 370 return 0; 371 } 372 373 ret = drm_scdc_readb(connector->ddc, SCDC_TMDS_CONFIG, &config); 374 if (ret < 0) { 375 drm_err(drm, "Failed to read TMDS config: %d\n", ret); 376 mutex_unlock(&vc4_hdmi->mutex); 377 return 0; 378 } 379 380 if (!!(config & SCDC_SCRAMBLING_ENABLE) == scrambling_needed) { 381 mutex_unlock(&vc4_hdmi->mutex); 382 return 0; 383 } 384 385 mutex_unlock(&vc4_hdmi->mutex); 386 387 /* 388 * HDMI 2.0 says that one should not send scrambled data 389 * prior to configuring the sink scrambling, and that 390 * TMDS clock/data transmission should be suspended when 391 * changing the TMDS clock rate in the sink. So let's 392 * just do a full modeset here, even though some sinks 393 * would be perfectly happy if were to just reconfigure 394 * the SCDC settings on the fly. 395 */ 396 return reset_pipe(crtc, ctx); 397 } 398 399 static void vc4_hdmi_handle_hotplug(struct vc4_hdmi *vc4_hdmi, 400 struct drm_modeset_acquire_ctx *ctx, 401 enum drm_connector_status status) 402 { 403 struct drm_connector *connector = &vc4_hdmi->connector; 404 struct edid *edid; 405 int ret; 406 407 /* 408 * NOTE: This function should really be called with 409 * vc4_hdmi->mutex held, but doing so results in reentrancy 410 * issues since cec_s_phys_addr_from_edid might call 411 * .adap_enable, which leads to that funtion being called with 412 * our mutex held. 413 * 414 * A similar situation occurs with vc4_hdmi_reset_link() that 415 * will call into our KMS hooks if the scrambling was enabled. 416 * 417 * Concurrency isn't an issue at the moment since we don't share 418 * any state with any of the other frameworks so we can ignore 419 * the lock for now. 420 */ 421 422 if (status == connector_status_disconnected) { 423 cec_phys_addr_invalidate(vc4_hdmi->cec_adap); 424 return; 425 } 426 427 edid = drm_get_edid(connector, vc4_hdmi->ddc); 428 if (!edid) 429 return; 430 431 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid); 432 kfree(edid); 433 434 for (;;) { 435 ret = vc4_hdmi_reset_link(connector, ctx); 436 if (ret == -EDEADLK) { 437 drm_modeset_backoff(ctx); 438 continue; 439 } 440 441 break; 442 } 443 } 444 445 static int vc4_hdmi_connector_detect_ctx(struct drm_connector *connector, 446 struct drm_modeset_acquire_ctx *ctx, 447 bool force) 448 { 449 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 450 enum drm_connector_status status = connector_status_disconnected; 451 452 /* 453 * NOTE: This function should really take vc4_hdmi->mutex, but 454 * doing so results in reentrancy issues since 455 * vc4_hdmi_handle_hotplug() can call into other functions that 456 * would take the mutex while it's held here. 457 * 458 * Concurrency isn't an issue at the moment since we don't share 459 * any state with any of the other frameworks so we can ignore 460 * the lock for now. 461 */ 462 463 WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev)); 464 465 if (vc4_hdmi->hpd_gpio) { 466 if (gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio)) 467 status = connector_status_connected; 468 } else { 469 if (vc4_hdmi->variant->hp_detect && 470 vc4_hdmi->variant->hp_detect(vc4_hdmi)) 471 status = connector_status_connected; 472 } 473 474 vc4_hdmi_handle_hotplug(vc4_hdmi, ctx, status); 475 pm_runtime_put(&vc4_hdmi->pdev->dev); 476 477 return status; 478 } 479 480 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector) 481 { 482 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 483 struct vc4_dev *vc4 = to_vc4_dev(connector->dev); 484 int ret = 0; 485 struct edid *edid; 486 487 /* 488 * NOTE: This function should really take vc4_hdmi->mutex, but 489 * doing so results in reentrancy issues since 490 * cec_s_phys_addr_from_edid might call .adap_enable, which 491 * leads to that funtion being called with our mutex held. 492 * 493 * Concurrency isn't an issue at the moment since we don't share 494 * any state with any of the other frameworks so we can ignore 495 * the lock for now. 496 */ 497 498 edid = drm_get_edid(connector, vc4_hdmi->ddc); 499 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid); 500 if (!edid) 501 return -ENODEV; 502 503 drm_connector_update_edid_property(connector, edid); 504 ret = drm_add_edid_modes(connector, edid); 505 kfree(edid); 506 507 if (!vc4->hvs->vc5_hdmi_enable_hdmi_20) { 508 struct drm_device *drm = connector->dev; 509 const struct drm_display_mode *mode; 510 511 list_for_each_entry(mode, &connector->probed_modes, head) { 512 if (vc4_hdmi_mode_needs_scrambling(mode, 8, VC4_HDMI_OUTPUT_RGB)) { 513 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz."); 514 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60."); 515 } 516 } 517 } 518 519 return ret; 520 } 521 522 static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector, 523 struct drm_atomic_state *state) 524 { 525 struct drm_connector_state *old_state = 526 drm_atomic_get_old_connector_state(state, connector); 527 struct drm_connector_state *new_state = 528 drm_atomic_get_new_connector_state(state, connector); 529 struct drm_crtc *crtc = new_state->crtc; 530 531 if (!crtc) 532 return 0; 533 534 if (old_state->colorspace != new_state->colorspace || 535 !drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) { 536 struct drm_crtc_state *crtc_state; 537 538 crtc_state = drm_atomic_get_crtc_state(state, crtc); 539 if (IS_ERR(crtc_state)) 540 return PTR_ERR(crtc_state); 541 542 crtc_state->mode_changed = true; 543 } 544 545 return 0; 546 } 547 548 static void vc4_hdmi_connector_reset(struct drm_connector *connector) 549 { 550 struct vc4_hdmi_connector_state *old_state = 551 conn_state_to_vc4_hdmi_conn_state(connector->state); 552 struct vc4_hdmi_connector_state *new_state = 553 kzalloc(sizeof(*new_state), GFP_KERNEL); 554 555 if (connector->state) 556 __drm_atomic_helper_connector_destroy_state(connector->state); 557 558 kfree(old_state); 559 __drm_atomic_helper_connector_reset(connector, &new_state->base); 560 561 if (!new_state) 562 return; 563 564 new_state->base.max_bpc = 8; 565 new_state->base.max_requested_bpc = 8; 566 new_state->output_format = VC4_HDMI_OUTPUT_RGB; 567 drm_atomic_helper_connector_tv_margins_reset(connector); 568 } 569 570 static struct drm_connector_state * 571 vc4_hdmi_connector_duplicate_state(struct drm_connector *connector) 572 { 573 struct drm_connector_state *conn_state = connector->state; 574 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state); 575 struct vc4_hdmi_connector_state *new_state; 576 577 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL); 578 if (!new_state) 579 return NULL; 580 581 new_state->tmds_char_rate = vc4_state->tmds_char_rate; 582 new_state->output_bpc = vc4_state->output_bpc; 583 new_state->output_format = vc4_state->output_format; 584 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base); 585 586 return &new_state->base; 587 } 588 589 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = { 590 .fill_modes = drm_helper_probe_single_connector_modes, 591 .reset = vc4_hdmi_connector_reset, 592 .atomic_duplicate_state = vc4_hdmi_connector_duplicate_state, 593 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 594 }; 595 596 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = { 597 .detect_ctx = vc4_hdmi_connector_detect_ctx, 598 .get_modes = vc4_hdmi_connector_get_modes, 599 .atomic_check = vc4_hdmi_connector_atomic_check, 600 }; 601 602 static int vc4_hdmi_connector_init(struct drm_device *dev, 603 struct vc4_hdmi *vc4_hdmi) 604 { 605 struct drm_connector *connector = &vc4_hdmi->connector; 606 struct drm_encoder *encoder = &vc4_hdmi->encoder.base; 607 int ret; 608 609 ret = drmm_connector_init(dev, connector, 610 &vc4_hdmi_connector_funcs, 611 DRM_MODE_CONNECTOR_HDMIA, 612 vc4_hdmi->ddc); 613 if (ret) 614 return ret; 615 616 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs); 617 618 /* 619 * Some of the properties below require access to state, like bpc. 620 * Allocate some default initial connector state with our reset helper. 621 */ 622 if (connector->funcs->reset) 623 connector->funcs->reset(connector); 624 625 /* Create and attach TV margin props to this connector. */ 626 ret = drm_mode_create_tv_margin_properties(dev); 627 if (ret) 628 return ret; 629 630 ret = drm_mode_create_hdmi_colorspace_property(connector); 631 if (ret) 632 return ret; 633 634 drm_connector_attach_colorspace_property(connector); 635 drm_connector_attach_tv_margin_properties(connector); 636 drm_connector_attach_max_bpc_property(connector, 8, 12); 637 638 connector->polled = (DRM_CONNECTOR_POLL_CONNECT | 639 DRM_CONNECTOR_POLL_DISCONNECT); 640 641 connector->interlace_allowed = 1; 642 connector->doublescan_allowed = 0; 643 connector->stereo_allowed = 1; 644 645 if (vc4_hdmi->variant->supports_hdr) 646 drm_connector_attach_hdr_output_metadata_property(connector); 647 648 drm_connector_attach_encoder(connector, encoder); 649 650 return 0; 651 } 652 653 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder, 654 enum hdmi_infoframe_type type, 655 bool poll) 656 { 657 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 658 struct drm_device *drm = vc4_hdmi->connector.dev; 659 u32 packet_id = type - 0x80; 660 unsigned long flags; 661 int ret = 0; 662 int idx; 663 664 if (!drm_dev_enter(drm, &idx)) 665 return -ENODEV; 666 667 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 668 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 669 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id)); 670 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 671 672 if (poll) { 673 ret = wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) & 674 BIT(packet_id)), 100); 675 } 676 677 drm_dev_exit(idx); 678 return ret; 679 } 680 681 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder, 682 union hdmi_infoframe *frame) 683 { 684 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 685 struct drm_device *drm = vc4_hdmi->connector.dev; 686 u32 packet_id = frame->any.type - 0x80; 687 const struct vc4_hdmi_register *ram_packet_start = 688 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START]; 689 u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id; 690 u32 packet_reg_next = ram_packet_start->offset + 691 VC4_HDMI_PACKET_STRIDE * (packet_id + 1); 692 void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi, 693 ram_packet_start->reg); 694 uint8_t buffer[VC4_HDMI_PACKET_STRIDE] = {}; 695 unsigned long flags; 696 ssize_t len, i; 697 int ret; 698 int idx; 699 700 if (!drm_dev_enter(drm, &idx)) 701 return; 702 703 WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) & 704 VC4_HDMI_RAM_PACKET_ENABLE), 705 "Packet RAM has to be on to store the packet."); 706 707 len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer)); 708 if (len < 0) 709 goto out; 710 711 ret = vc4_hdmi_stop_packet(encoder, frame->any.type, true); 712 if (ret) { 713 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret); 714 goto out; 715 } 716 717 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 718 719 for (i = 0; i < len; i += 7) { 720 writel(buffer[i + 0] << 0 | 721 buffer[i + 1] << 8 | 722 buffer[i + 2] << 16, 723 base + packet_reg); 724 packet_reg += 4; 725 726 writel(buffer[i + 3] << 0 | 727 buffer[i + 4] << 8 | 728 buffer[i + 5] << 16 | 729 buffer[i + 6] << 24, 730 base + packet_reg); 731 packet_reg += 4; 732 } 733 734 /* 735 * clear remainder of packet ram as it's included in the 736 * infoframe and triggers a checksum error on hdmi analyser 737 */ 738 for (; packet_reg < packet_reg_next; packet_reg += 4) 739 writel(0, base + packet_reg); 740 741 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 742 HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id)); 743 744 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 745 746 ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) & 747 BIT(packet_id)), 100); 748 if (ret) 749 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret); 750 751 out: 752 drm_dev_exit(idx); 753 } 754 755 static void vc4_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame, 756 enum vc4_hdmi_output_format fmt) 757 { 758 switch (fmt) { 759 case VC4_HDMI_OUTPUT_RGB: 760 frame->colorspace = HDMI_COLORSPACE_RGB; 761 break; 762 763 case VC4_HDMI_OUTPUT_YUV420: 764 frame->colorspace = HDMI_COLORSPACE_YUV420; 765 break; 766 767 case VC4_HDMI_OUTPUT_YUV422: 768 frame->colorspace = HDMI_COLORSPACE_YUV422; 769 break; 770 771 case VC4_HDMI_OUTPUT_YUV444: 772 frame->colorspace = HDMI_COLORSPACE_YUV444; 773 break; 774 775 default: 776 break; 777 } 778 } 779 780 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder) 781 { 782 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 783 struct drm_connector *connector = &vc4_hdmi->connector; 784 struct drm_connector_state *cstate = connector->state; 785 struct vc4_hdmi_connector_state *vc4_state = 786 conn_state_to_vc4_hdmi_conn_state(cstate); 787 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 788 union hdmi_infoframe frame; 789 int ret; 790 791 lockdep_assert_held(&vc4_hdmi->mutex); 792 793 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, 794 connector, mode); 795 if (ret < 0) { 796 DRM_ERROR("couldn't fill AVI infoframe\n"); 797 return; 798 } 799 800 drm_hdmi_avi_infoframe_quant_range(&frame.avi, 801 connector, mode, 802 vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode) ? 803 HDMI_QUANTIZATION_RANGE_FULL : 804 HDMI_QUANTIZATION_RANGE_LIMITED); 805 drm_hdmi_avi_infoframe_colorimetry(&frame.avi, cstate); 806 vc4_hdmi_avi_infoframe_colorspace(&frame.avi, vc4_state->output_format); 807 drm_hdmi_avi_infoframe_bars(&frame.avi, cstate); 808 809 vc4_hdmi_write_infoframe(encoder, &frame); 810 } 811 812 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder) 813 { 814 union hdmi_infoframe frame; 815 int ret; 816 817 ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore"); 818 if (ret < 0) { 819 DRM_ERROR("couldn't fill SPD infoframe\n"); 820 return; 821 } 822 823 frame.spd.sdi = HDMI_SPD_SDI_PC; 824 825 vc4_hdmi_write_infoframe(encoder, &frame); 826 } 827 828 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder) 829 { 830 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 831 struct hdmi_audio_infoframe *audio = &vc4_hdmi->audio.infoframe; 832 union hdmi_infoframe frame; 833 834 memcpy(&frame.audio, audio, sizeof(*audio)); 835 836 if (vc4_hdmi->packet_ram_enabled) 837 vc4_hdmi_write_infoframe(encoder, &frame); 838 } 839 840 static void vc4_hdmi_set_hdr_infoframe(struct drm_encoder *encoder) 841 { 842 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 843 struct drm_connector *connector = &vc4_hdmi->connector; 844 struct drm_connector_state *conn_state = connector->state; 845 union hdmi_infoframe frame; 846 847 lockdep_assert_held(&vc4_hdmi->mutex); 848 849 if (!vc4_hdmi->variant->supports_hdr) 850 return; 851 852 if (!conn_state->hdr_output_metadata) 853 return; 854 855 if (drm_hdmi_infoframe_set_hdr_metadata(&frame.drm, conn_state)) 856 return; 857 858 vc4_hdmi_write_infoframe(encoder, &frame); 859 } 860 861 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder) 862 { 863 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 864 865 lockdep_assert_held(&vc4_hdmi->mutex); 866 867 vc4_hdmi_set_avi_infoframe(encoder); 868 vc4_hdmi_set_spd_infoframe(encoder); 869 /* 870 * If audio was streaming, then we need to reenabled the audio 871 * infoframe here during encoder_enable. 872 */ 873 if (vc4_hdmi->audio.streaming) 874 vc4_hdmi_set_audio_infoframe(encoder); 875 876 vc4_hdmi_set_hdr_infoframe(encoder); 877 } 878 879 #define SCRAMBLING_POLLING_DELAY_MS 1000 880 881 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder) 882 { 883 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 884 struct drm_device *drm = vc4_hdmi->connector.dev; 885 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 886 unsigned long flags; 887 int idx; 888 889 lockdep_assert_held(&vc4_hdmi->mutex); 890 891 if (!vc4_hdmi_supports_scrambling(vc4_hdmi)) 892 return; 893 894 if (!vc4_hdmi_mode_needs_scrambling(mode, 895 vc4_hdmi->output_bpc, 896 vc4_hdmi->output_format)) 897 return; 898 899 if (!drm_dev_enter(drm, &idx)) 900 return; 901 902 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true); 903 drm_scdc_set_scrambling(vc4_hdmi->ddc, true); 904 905 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 906 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) | 907 VC5_HDMI_SCRAMBLER_CTL_ENABLE); 908 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 909 910 drm_dev_exit(idx); 911 912 vc4_hdmi->scdc_enabled = true; 913 914 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work, 915 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS)); 916 } 917 918 static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder) 919 { 920 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 921 struct drm_device *drm = vc4_hdmi->connector.dev; 922 unsigned long flags; 923 int idx; 924 925 lockdep_assert_held(&vc4_hdmi->mutex); 926 927 if (!vc4_hdmi->scdc_enabled) 928 return; 929 930 vc4_hdmi->scdc_enabled = false; 931 932 if (delayed_work_pending(&vc4_hdmi->scrambling_work)) 933 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work); 934 935 if (!drm_dev_enter(drm, &idx)) 936 return; 937 938 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 939 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) & 940 ~VC5_HDMI_SCRAMBLER_CTL_ENABLE); 941 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 942 943 drm_scdc_set_scrambling(vc4_hdmi->ddc, false); 944 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, false); 945 946 drm_dev_exit(idx); 947 } 948 949 static void vc4_hdmi_scrambling_wq(struct work_struct *work) 950 { 951 struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work), 952 struct vc4_hdmi, 953 scrambling_work); 954 955 if (drm_scdc_get_scrambling_status(vc4_hdmi->ddc)) 956 return; 957 958 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true); 959 drm_scdc_set_scrambling(vc4_hdmi->ddc, true); 960 961 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work, 962 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS)); 963 } 964 965 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder, 966 struct drm_atomic_state *state) 967 { 968 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 969 struct drm_device *drm = vc4_hdmi->connector.dev; 970 unsigned long flags; 971 int idx; 972 973 mutex_lock(&vc4_hdmi->mutex); 974 975 vc4_hdmi->packet_ram_enabled = false; 976 977 if (!drm_dev_enter(drm, &idx)) 978 goto out; 979 980 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 981 982 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0); 983 984 HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB); 985 986 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 987 988 mdelay(1); 989 990 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 991 HDMI_WRITE(HDMI_VID_CTL, 992 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE); 993 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 994 995 vc4_hdmi_disable_scrambling(encoder); 996 997 drm_dev_exit(idx); 998 999 out: 1000 mutex_unlock(&vc4_hdmi->mutex); 1001 } 1002 1003 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder, 1004 struct drm_atomic_state *state) 1005 { 1006 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1007 struct drm_device *drm = vc4_hdmi->connector.dev; 1008 unsigned long flags; 1009 int ret; 1010 int idx; 1011 1012 mutex_lock(&vc4_hdmi->mutex); 1013 1014 if (!drm_dev_enter(drm, &idx)) 1015 goto out; 1016 1017 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1018 HDMI_WRITE(HDMI_VID_CTL, 1019 HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX); 1020 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1021 1022 if (vc4_hdmi->variant->phy_disable) 1023 vc4_hdmi->variant->phy_disable(vc4_hdmi); 1024 1025 clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock); 1026 clk_disable_unprepare(vc4_hdmi->pixel_clock); 1027 1028 ret = pm_runtime_put(&vc4_hdmi->pdev->dev); 1029 if (ret < 0) 1030 DRM_ERROR("Failed to release power domain: %d\n", ret); 1031 1032 drm_dev_exit(idx); 1033 1034 out: 1035 mutex_unlock(&vc4_hdmi->mutex); 1036 } 1037 1038 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, 1039 struct drm_connector_state *state, 1040 const struct drm_display_mode *mode) 1041 { 1042 struct drm_device *drm = vc4_hdmi->connector.dev; 1043 unsigned long flags; 1044 u32 csc_ctl; 1045 int idx; 1046 1047 if (!drm_dev_enter(drm, &idx)) 1048 return; 1049 1050 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1051 1052 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR, 1053 VC4_HD_CSC_CTL_ORDER); 1054 1055 if (!vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode)) { 1056 /* CEA VICs other than #1 requre limited range RGB 1057 * output unless overridden by an AVI infoframe. 1058 * Apply a colorspace conversion to squash 0-255 down 1059 * to 16-235. The matrix here is: 1060 * 1061 * [ 0 0 0.8594 16] 1062 * [ 0 0.8594 0 16] 1063 * [ 0.8594 0 0 16] 1064 * [ 0 0 0 1] 1065 */ 1066 csc_ctl |= VC4_HD_CSC_CTL_ENABLE; 1067 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC; 1068 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM, 1069 VC4_HD_CSC_CTL_MODE); 1070 1071 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000); 1072 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0); 1073 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000); 1074 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000); 1075 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0); 1076 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000); 1077 } 1078 1079 /* The RGB order applies even when CSC is disabled. */ 1080 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl); 1081 1082 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1083 1084 drm_dev_exit(idx); 1085 } 1086 1087 /* 1088 * If we need to output Full Range RGB, then use the unity matrix 1089 * 1090 * [ 1 0 0 0] 1091 * [ 0 1 0 0] 1092 * [ 0 0 1 0] 1093 * 1094 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets 1095 */ 1096 static const u16 vc5_hdmi_csc_full_rgb_unity[3][4] = { 1097 { 0x2000, 0x0000, 0x0000, 0x0000 }, 1098 { 0x0000, 0x2000, 0x0000, 0x0000 }, 1099 { 0x0000, 0x0000, 0x2000, 0x0000 }, 1100 }; 1101 1102 /* 1103 * CEA VICs other than #1 require limited range RGB output unless 1104 * overridden by an AVI infoframe. Apply a colorspace conversion to 1105 * squash 0-255 down to 16-235. The matrix here is: 1106 * 1107 * [ 0.8594 0 0 16] 1108 * [ 0 0.8594 0 16] 1109 * [ 0 0 0.8594 16] 1110 * 1111 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets 1112 */ 1113 static const u16 vc5_hdmi_csc_full_rgb_to_limited_rgb[3][4] = { 1114 { 0x1b80, 0x0000, 0x0000, 0x0400 }, 1115 { 0x0000, 0x1b80, 0x0000, 0x0400 }, 1116 { 0x0000, 0x0000, 0x1b80, 0x0400 }, 1117 }; 1118 1119 /* 1120 * Conversion between Full Range RGB and Full Range YUV422 using the 1121 * BT.709 Colorspace 1122 * 1123 * 1124 * [ 0.181906 0.611804 0.061758 16 ] 1125 * [ -0.100268 -0.337232 0.437500 128 ] 1126 * [ 0.437500 -0.397386 -0.040114 128 ] 1127 * 1128 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets 1129 */ 1130 static const u16 vc5_hdmi_csc_full_rgb_to_limited_yuv422_bt709[3][4] = { 1131 { 0x05d2, 0x1394, 0x01fa, 0x0400 }, 1132 { 0xfccc, 0xf536, 0x0e00, 0x2000 }, 1133 { 0x0e00, 0xf34a, 0xfeb8, 0x2000 }, 1134 }; 1135 1136 /* 1137 * Conversion between Full Range RGB and Full Range YUV444 using the 1138 * BT.709 Colorspace 1139 * 1140 * [ -0.100268 -0.337232 0.437500 128 ] 1141 * [ 0.437500 -0.397386 -0.040114 128 ] 1142 * [ 0.181906 0.611804 0.061758 16 ] 1143 * 1144 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets 1145 */ 1146 static const u16 vc5_hdmi_csc_full_rgb_to_limited_yuv444_bt709[3][4] = { 1147 { 0xfccc, 0xf536, 0x0e00, 0x2000 }, 1148 { 0x0e00, 0xf34a, 0xfeb8, 0x2000 }, 1149 { 0x05d2, 0x1394, 0x01fa, 0x0400 }, 1150 }; 1151 1152 static void vc5_hdmi_set_csc_coeffs(struct vc4_hdmi *vc4_hdmi, 1153 const u16 coeffs[3][4]) 1154 { 1155 lockdep_assert_held(&vc4_hdmi->hw_lock); 1156 1157 HDMI_WRITE(HDMI_CSC_12_11, (coeffs[0][1] << 16) | coeffs[0][0]); 1158 HDMI_WRITE(HDMI_CSC_14_13, (coeffs[0][3] << 16) | coeffs[0][2]); 1159 HDMI_WRITE(HDMI_CSC_22_21, (coeffs[1][1] << 16) | coeffs[1][0]); 1160 HDMI_WRITE(HDMI_CSC_24_23, (coeffs[1][3] << 16) | coeffs[1][2]); 1161 HDMI_WRITE(HDMI_CSC_32_31, (coeffs[2][1] << 16) | coeffs[2][0]); 1162 HDMI_WRITE(HDMI_CSC_34_33, (coeffs[2][3] << 16) | coeffs[2][2]); 1163 } 1164 1165 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, 1166 struct drm_connector_state *state, 1167 const struct drm_display_mode *mode) 1168 { 1169 struct drm_device *drm = vc4_hdmi->connector.dev; 1170 struct vc4_hdmi_connector_state *vc4_state = 1171 conn_state_to_vc4_hdmi_conn_state(state); 1172 unsigned long flags; 1173 u32 if_cfg = 0; 1174 u32 if_xbar = 0x543210; 1175 u32 csc_chan_ctl = 0; 1176 u32 csc_ctl = VC5_MT_CP_CSC_CTL_ENABLE | VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM, 1177 VC5_MT_CP_CSC_CTL_MODE); 1178 int idx; 1179 1180 if (!drm_dev_enter(drm, &idx)) 1181 return; 1182 1183 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1184 1185 switch (vc4_state->output_format) { 1186 case VC4_HDMI_OUTPUT_YUV444: 1187 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_limited_yuv444_bt709); 1188 break; 1189 1190 case VC4_HDMI_OUTPUT_YUV422: 1191 csc_ctl |= VC4_SET_FIELD(VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422_STANDARD, 1192 VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422) | 1193 VC5_MT_CP_CSC_CTL_USE_444_TO_422 | 1194 VC5_MT_CP_CSC_CTL_USE_RNG_SUPPRESSION; 1195 1196 csc_chan_ctl |= VC4_SET_FIELD(VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP_LEGACY_STYLE, 1197 VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP); 1198 1199 if_cfg |= VC4_SET_FIELD(VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422_FORMAT_422_LEGACY, 1200 VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422); 1201 1202 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_limited_yuv422_bt709); 1203 break; 1204 1205 case VC4_HDMI_OUTPUT_RGB: 1206 if_xbar = 0x354021; 1207 1208 if (!vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode)) 1209 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_limited_rgb); 1210 else 1211 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_unity); 1212 break; 1213 1214 default: 1215 break; 1216 } 1217 1218 HDMI_WRITE(HDMI_VEC_INTERFACE_CFG, if_cfg); 1219 HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, if_xbar); 1220 HDMI_WRITE(HDMI_CSC_CHANNEL_CTL, csc_chan_ctl); 1221 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl); 1222 1223 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1224 1225 drm_dev_exit(idx); 1226 } 1227 1228 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi, 1229 struct drm_connector_state *state, 1230 const struct drm_display_mode *mode) 1231 { 1232 struct drm_device *drm = vc4_hdmi->connector.dev; 1233 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 1234 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 1235 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 1236 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 1237 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 1238 VC4_HDMI_VERTA_VSP) | 1239 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 1240 VC4_HDMI_VERTA_VFP) | 1241 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL)); 1242 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 1243 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end + 1244 interlaced, 1245 VC4_HDMI_VERTB_VBP)); 1246 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 1247 VC4_SET_FIELD(mode->crtc_vtotal - 1248 mode->crtc_vsync_end, 1249 VC4_HDMI_VERTB_VBP)); 1250 unsigned long flags; 1251 u32 reg; 1252 int idx; 1253 1254 if (!drm_dev_enter(drm, &idx)) 1255 return; 1256 1257 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1258 1259 HDMI_WRITE(HDMI_HORZA, 1260 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) | 1261 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) | 1262 VC4_SET_FIELD(mode->hdisplay * pixel_rep, 1263 VC4_HDMI_HORZA_HAP)); 1264 1265 HDMI_WRITE(HDMI_HORZB, 1266 VC4_SET_FIELD((mode->htotal - 1267 mode->hsync_end) * pixel_rep, 1268 VC4_HDMI_HORZB_HBP) | 1269 VC4_SET_FIELD((mode->hsync_end - 1270 mode->hsync_start) * pixel_rep, 1271 VC4_HDMI_HORZB_HSP) | 1272 VC4_SET_FIELD((mode->hsync_start - 1273 mode->hdisplay) * pixel_rep, 1274 VC4_HDMI_HORZB_HFP)); 1275 1276 HDMI_WRITE(HDMI_VERTA0, verta); 1277 HDMI_WRITE(HDMI_VERTA1, verta); 1278 1279 HDMI_WRITE(HDMI_VERTB0, vertb_even); 1280 HDMI_WRITE(HDMI_VERTB1, vertb); 1281 1282 reg = HDMI_READ(HDMI_MISC_CONTROL); 1283 reg &= ~VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK; 1284 reg |= VC4_SET_FIELD(pixel_rep - 1, VC4_HDMI_MISC_CONTROL_PIXEL_REP); 1285 HDMI_WRITE(HDMI_MISC_CONTROL, reg); 1286 1287 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1288 1289 drm_dev_exit(idx); 1290 } 1291 1292 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi, 1293 struct drm_connector_state *state, 1294 const struct drm_display_mode *mode) 1295 { 1296 struct drm_device *drm = vc4_hdmi->connector.dev; 1297 const struct vc4_hdmi_connector_state *vc4_state = 1298 conn_state_to_vc4_hdmi_conn_state(state); 1299 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 1300 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 1301 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 1302 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 1303 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 1304 VC5_HDMI_VERTA_VSP) | 1305 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 1306 VC5_HDMI_VERTA_VFP) | 1307 VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL)); 1308 u32 vertb = (VC4_SET_FIELD(mode->htotal >> (2 - pixel_rep), 1309 VC5_HDMI_VERTB_VSPO) | 1310 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end + 1311 interlaced, 1312 VC4_HDMI_VERTB_VBP)); 1313 u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) | 1314 VC4_SET_FIELD(mode->crtc_vtotal - 1315 mode->crtc_vsync_end, 1316 VC4_HDMI_VERTB_VBP)); 1317 unsigned long flags; 1318 unsigned char gcp; 1319 bool gcp_en; 1320 u32 reg; 1321 int idx; 1322 1323 if (!drm_dev_enter(drm, &idx)) 1324 return; 1325 1326 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1327 1328 HDMI_WRITE(HDMI_HORZA, 1329 (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) | 1330 (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) | 1331 VC4_SET_FIELD(mode->hdisplay * pixel_rep, 1332 VC5_HDMI_HORZA_HAP) | 1333 VC4_SET_FIELD((mode->hsync_start - 1334 mode->hdisplay) * pixel_rep, 1335 VC5_HDMI_HORZA_HFP)); 1336 1337 HDMI_WRITE(HDMI_HORZB, 1338 VC4_SET_FIELD((mode->htotal - 1339 mode->hsync_end) * pixel_rep, 1340 VC5_HDMI_HORZB_HBP) | 1341 VC4_SET_FIELD((mode->hsync_end - 1342 mode->hsync_start) * pixel_rep, 1343 VC5_HDMI_HORZB_HSP)); 1344 1345 HDMI_WRITE(HDMI_VERTA0, verta); 1346 HDMI_WRITE(HDMI_VERTA1, verta); 1347 1348 HDMI_WRITE(HDMI_VERTB0, vertb_even); 1349 HDMI_WRITE(HDMI_VERTB1, vertb); 1350 1351 switch (vc4_state->output_bpc) { 1352 case 12: 1353 gcp = 6; 1354 gcp_en = true; 1355 break; 1356 case 10: 1357 gcp = 5; 1358 gcp_en = true; 1359 break; 1360 case 8: 1361 default: 1362 gcp = 4; 1363 gcp_en = false; 1364 break; 1365 } 1366 1367 /* 1368 * YCC422 is always 36-bit and not considered deep colour so 1369 * doesn't signal in GCP. 1370 */ 1371 if (vc4_state->output_format == VC4_HDMI_OUTPUT_YUV422) { 1372 gcp = 4; 1373 gcp_en = false; 1374 } 1375 1376 reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1); 1377 reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK | 1378 VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK); 1379 reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) | 1380 VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH); 1381 HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg); 1382 1383 reg = HDMI_READ(HDMI_GCP_WORD_1); 1384 reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK; 1385 reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1); 1386 HDMI_WRITE(HDMI_GCP_WORD_1, reg); 1387 1388 reg = HDMI_READ(HDMI_GCP_CONFIG); 1389 reg &= ~VC5_HDMI_GCP_CONFIG_GCP_ENABLE; 1390 reg |= gcp_en ? VC5_HDMI_GCP_CONFIG_GCP_ENABLE : 0; 1391 HDMI_WRITE(HDMI_GCP_CONFIG, reg); 1392 1393 reg = HDMI_READ(HDMI_MISC_CONTROL); 1394 reg &= ~VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK; 1395 reg |= VC4_SET_FIELD(pixel_rep - 1, VC5_HDMI_MISC_CONTROL_PIXEL_REP); 1396 HDMI_WRITE(HDMI_MISC_CONTROL, reg); 1397 1398 HDMI_WRITE(HDMI_CLOCK_STOP, 0); 1399 1400 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1401 1402 drm_dev_exit(idx); 1403 } 1404 1405 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi) 1406 { 1407 struct drm_device *drm = vc4_hdmi->connector.dev; 1408 unsigned long flags; 1409 u32 drift; 1410 int ret; 1411 int idx; 1412 1413 if (!drm_dev_enter(drm, &idx)) 1414 return; 1415 1416 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1417 1418 drift = HDMI_READ(HDMI_FIFO_CTL); 1419 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK; 1420 1421 HDMI_WRITE(HDMI_FIFO_CTL, 1422 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 1423 HDMI_WRITE(HDMI_FIFO_CTL, 1424 drift | VC4_HDMI_FIFO_CTL_RECENTER); 1425 1426 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1427 1428 usleep_range(1000, 1100); 1429 1430 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1431 1432 HDMI_WRITE(HDMI_FIFO_CTL, 1433 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 1434 HDMI_WRITE(HDMI_FIFO_CTL, 1435 drift | VC4_HDMI_FIFO_CTL_RECENTER); 1436 1437 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1438 1439 ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) & 1440 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1); 1441 WARN_ONCE(ret, "Timeout waiting for " 1442 "VC4_HDMI_FIFO_CTL_RECENTER_DONE"); 1443 1444 drm_dev_exit(idx); 1445 } 1446 1447 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder, 1448 struct drm_atomic_state *state) 1449 { 1450 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1451 struct drm_device *drm = vc4_hdmi->connector.dev; 1452 struct drm_connector *connector = &vc4_hdmi->connector; 1453 struct drm_connector_state *conn_state = 1454 drm_atomic_get_new_connector_state(state, connector); 1455 struct vc4_hdmi_connector_state *vc4_conn_state = 1456 conn_state_to_vc4_hdmi_conn_state(conn_state); 1457 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1458 unsigned long tmds_char_rate = vc4_conn_state->tmds_char_rate; 1459 unsigned long bvb_rate, hsm_rate; 1460 unsigned long flags; 1461 int ret; 1462 int idx; 1463 1464 mutex_lock(&vc4_hdmi->mutex); 1465 1466 if (!drm_dev_enter(drm, &idx)) 1467 goto out; 1468 1469 /* 1470 * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must 1471 * be faster than pixel clock, infinitesimally faster, tested in 1472 * simulation. Otherwise, exact value is unimportant for HDMI 1473 * operation." This conflicts with bcm2835's vc4 documentation, which 1474 * states HSM's clock has to be at least 108% of the pixel clock. 1475 * 1476 * Real life tests reveal that vc4's firmware statement holds up, and 1477 * users are able to use pixel clocks closer to HSM's, namely for 1478 * 1920x1200@60Hz. So it was decided to have leave a 1% margin between 1479 * both clocks. Which, for RPi0-3 implies a maximum pixel clock of 1480 * 162MHz. 1481 * 1482 * Additionally, the AXI clock needs to be at least 25% of 1483 * pixel clock, but HSM ends up being the limiting factor. 1484 */ 1485 hsm_rate = max_t(unsigned long, 120000000, (tmds_char_rate / 100) * 101); 1486 ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate); 1487 if (ret) { 1488 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret); 1489 goto err_dev_exit; 1490 } 1491 1492 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev); 1493 if (ret < 0) { 1494 DRM_ERROR("Failed to retain power domain: %d\n", ret); 1495 goto err_dev_exit; 1496 } 1497 1498 ret = clk_set_rate(vc4_hdmi->pixel_clock, tmds_char_rate); 1499 if (ret) { 1500 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret); 1501 goto err_put_runtime_pm; 1502 } 1503 1504 ret = clk_prepare_enable(vc4_hdmi->pixel_clock); 1505 if (ret) { 1506 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret); 1507 goto err_put_runtime_pm; 1508 } 1509 1510 1511 vc4_hdmi_cec_update_clk_div(vc4_hdmi); 1512 1513 if (tmds_char_rate > 297000000) 1514 bvb_rate = 300000000; 1515 else if (tmds_char_rate > 148500000) 1516 bvb_rate = 150000000; 1517 else 1518 bvb_rate = 75000000; 1519 1520 ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate); 1521 if (ret) { 1522 DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret); 1523 goto err_disable_pixel_clock; 1524 } 1525 1526 ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock); 1527 if (ret) { 1528 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret); 1529 goto err_disable_pixel_clock; 1530 } 1531 1532 if (vc4_hdmi->variant->phy_init) 1533 vc4_hdmi->variant->phy_init(vc4_hdmi, vc4_conn_state); 1534 1535 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1536 1537 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1538 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 1539 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT | 1540 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS); 1541 1542 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1543 1544 if (vc4_hdmi->variant->set_timings) 1545 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode); 1546 1547 drm_dev_exit(idx); 1548 1549 mutex_unlock(&vc4_hdmi->mutex); 1550 1551 return; 1552 1553 err_disable_pixel_clock: 1554 clk_disable_unprepare(vc4_hdmi->pixel_clock); 1555 err_put_runtime_pm: 1556 pm_runtime_put(&vc4_hdmi->pdev->dev); 1557 err_dev_exit: 1558 drm_dev_exit(idx); 1559 out: 1560 mutex_unlock(&vc4_hdmi->mutex); 1561 return; 1562 } 1563 1564 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder, 1565 struct drm_atomic_state *state) 1566 { 1567 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1568 struct drm_device *drm = vc4_hdmi->connector.dev; 1569 struct drm_connector *connector = &vc4_hdmi->connector; 1570 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1571 struct drm_connector_state *conn_state = 1572 drm_atomic_get_new_connector_state(state, connector); 1573 unsigned long flags; 1574 int idx; 1575 1576 mutex_lock(&vc4_hdmi->mutex); 1577 1578 if (!drm_dev_enter(drm, &idx)) 1579 goto out; 1580 1581 if (vc4_hdmi->variant->csc_setup) 1582 vc4_hdmi->variant->csc_setup(vc4_hdmi, conn_state, mode); 1583 1584 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1585 HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N); 1586 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1587 1588 drm_dev_exit(idx); 1589 1590 out: 1591 mutex_unlock(&vc4_hdmi->mutex); 1592 } 1593 1594 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder, 1595 struct drm_atomic_state *state) 1596 { 1597 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1598 struct drm_device *drm = vc4_hdmi->connector.dev; 1599 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1600 struct drm_display_info *display = &vc4_hdmi->connector.display_info; 1601 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 1602 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 1603 unsigned long flags; 1604 int ret; 1605 int idx; 1606 1607 mutex_lock(&vc4_hdmi->mutex); 1608 1609 if (!drm_dev_enter(drm, &idx)) 1610 goto out; 1611 1612 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1613 1614 HDMI_WRITE(HDMI_VID_CTL, 1615 VC4_HD_VID_CTL_ENABLE | 1616 VC4_HD_VID_CTL_CLRRGB | 1617 VC4_HD_VID_CTL_UNDERFLOW_ENABLE | 1618 VC4_HD_VID_CTL_FRAME_COUNTER_RESET | 1619 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) | 1620 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW)); 1621 1622 HDMI_WRITE(HDMI_VID_CTL, 1623 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX); 1624 1625 if (display->is_hdmi) { 1626 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1627 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 1628 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 1629 1630 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1631 1632 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1633 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000); 1634 WARN_ONCE(ret, "Timeout waiting for " 1635 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 1636 } else { 1637 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 1638 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & 1639 ~(VC4_HDMI_RAM_PACKET_ENABLE)); 1640 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1641 HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1642 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 1643 1644 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1645 1646 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1647 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000); 1648 WARN_ONCE(ret, "Timeout waiting for " 1649 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 1650 } 1651 1652 if (display->is_hdmi) { 1653 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1654 1655 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1656 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE)); 1657 1658 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 1659 VC4_HDMI_RAM_PACKET_ENABLE); 1660 1661 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1662 vc4_hdmi->packet_ram_enabled = true; 1663 1664 vc4_hdmi_set_infoframes(encoder); 1665 } 1666 1667 vc4_hdmi_recenter_fifo(vc4_hdmi); 1668 vc4_hdmi_enable_scrambling(encoder); 1669 1670 drm_dev_exit(idx); 1671 1672 out: 1673 mutex_unlock(&vc4_hdmi->mutex); 1674 } 1675 1676 static void vc4_hdmi_encoder_atomic_mode_set(struct drm_encoder *encoder, 1677 struct drm_crtc_state *crtc_state, 1678 struct drm_connector_state *conn_state) 1679 { 1680 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1681 struct vc4_hdmi_connector_state *vc4_state = 1682 conn_state_to_vc4_hdmi_conn_state(conn_state); 1683 1684 mutex_lock(&vc4_hdmi->mutex); 1685 drm_mode_copy(&vc4_hdmi->saved_adjusted_mode, 1686 &crtc_state->adjusted_mode); 1687 vc4_hdmi->output_bpc = vc4_state->output_bpc; 1688 vc4_hdmi->output_format = vc4_state->output_format; 1689 mutex_unlock(&vc4_hdmi->mutex); 1690 } 1691 1692 static bool 1693 vc4_hdmi_sink_supports_format_bpc(const struct vc4_hdmi *vc4_hdmi, 1694 const struct drm_display_info *info, 1695 const struct drm_display_mode *mode, 1696 unsigned int format, unsigned int bpc) 1697 { 1698 struct drm_device *dev = vc4_hdmi->connector.dev; 1699 u8 vic = drm_match_cea_mode(mode); 1700 1701 if (vic == 1 && bpc != 8) { 1702 drm_dbg(dev, "VIC1 requires a bpc of 8, got %u\n", bpc); 1703 return false; 1704 } 1705 1706 if (!info->is_hdmi && 1707 (format != VC4_HDMI_OUTPUT_RGB || bpc != 8)) { 1708 drm_dbg(dev, "DVI Monitors require an RGB output at 8 bpc\n"); 1709 return false; 1710 } 1711 1712 switch (format) { 1713 case VC4_HDMI_OUTPUT_RGB: 1714 drm_dbg(dev, "RGB Format, checking the constraints.\n"); 1715 1716 if (!(info->color_formats & DRM_COLOR_FORMAT_RGB444)) 1717 return false; 1718 1719 if (bpc == 10 && !(info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30)) { 1720 drm_dbg(dev, "10 BPC but sink doesn't support Deep Color 30.\n"); 1721 return false; 1722 } 1723 1724 if (bpc == 12 && !(info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36)) { 1725 drm_dbg(dev, "12 BPC but sink doesn't support Deep Color 36.\n"); 1726 return false; 1727 } 1728 1729 drm_dbg(dev, "RGB format supported in that configuration.\n"); 1730 1731 return true; 1732 1733 case VC4_HDMI_OUTPUT_YUV422: 1734 drm_dbg(dev, "YUV422 format, checking the constraints.\n"); 1735 1736 if (!(info->color_formats & DRM_COLOR_FORMAT_YCBCR422)) { 1737 drm_dbg(dev, "Sink doesn't support YUV422.\n"); 1738 return false; 1739 } 1740 1741 if (bpc != 12) { 1742 drm_dbg(dev, "YUV422 only supports 12 bpc.\n"); 1743 return false; 1744 } 1745 1746 drm_dbg(dev, "YUV422 format supported in that configuration.\n"); 1747 1748 return true; 1749 1750 case VC4_HDMI_OUTPUT_YUV444: 1751 drm_dbg(dev, "YUV444 format, checking the constraints.\n"); 1752 1753 if (!(info->color_formats & DRM_COLOR_FORMAT_YCBCR444)) { 1754 drm_dbg(dev, "Sink doesn't support YUV444.\n"); 1755 return false; 1756 } 1757 1758 if (bpc == 10 && !(info->edid_hdmi_ycbcr444_dc_modes & DRM_EDID_HDMI_DC_30)) { 1759 drm_dbg(dev, "10 BPC but sink doesn't support Deep Color 30.\n"); 1760 return false; 1761 } 1762 1763 if (bpc == 12 && !(info->edid_hdmi_ycbcr444_dc_modes & DRM_EDID_HDMI_DC_36)) { 1764 drm_dbg(dev, "12 BPC but sink doesn't support Deep Color 36.\n"); 1765 return false; 1766 } 1767 1768 drm_dbg(dev, "YUV444 format supported in that configuration.\n"); 1769 1770 return true; 1771 } 1772 1773 return false; 1774 } 1775 1776 static enum drm_mode_status 1777 vc4_hdmi_encoder_clock_valid(const struct vc4_hdmi *vc4_hdmi, 1778 const struct drm_display_mode *mode, 1779 unsigned long long clock) 1780 { 1781 const struct drm_connector *connector = &vc4_hdmi->connector; 1782 const struct drm_display_info *info = &connector->display_info; 1783 struct vc4_dev *vc4 = to_vc4_dev(connector->dev); 1784 1785 if (clock > vc4_hdmi->variant->max_pixel_clock) 1786 return MODE_CLOCK_HIGH; 1787 1788 if (!vc4->hvs->vc5_hdmi_enable_hdmi_20 && clock > HDMI_14_MAX_TMDS_CLK) 1789 return MODE_CLOCK_HIGH; 1790 1791 /* 4096x2160@60 is not reliable without overclocking core */ 1792 if (!vc4->hvs->vc5_hdmi_enable_4096by2160 && 1793 mode->hdisplay > 3840 && mode->vdisplay >= 2160 && 1794 drm_mode_vrefresh(mode) >= 50) 1795 return MODE_CLOCK_HIGH; 1796 1797 if (info->max_tmds_clock && clock > (info->max_tmds_clock * 1000)) 1798 return MODE_CLOCK_HIGH; 1799 1800 return MODE_OK; 1801 } 1802 1803 static unsigned long long 1804 vc4_hdmi_encoder_compute_mode_clock(const struct drm_display_mode *mode, 1805 unsigned int bpc, 1806 enum vc4_hdmi_output_format fmt) 1807 { 1808 unsigned long long clock = mode->clock * 1000ULL; 1809 1810 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 1811 clock = clock * 2; 1812 1813 if (fmt == VC4_HDMI_OUTPUT_YUV422) 1814 bpc = 8; 1815 1816 clock = clock * bpc; 1817 do_div(clock, 8); 1818 1819 return clock; 1820 } 1821 1822 static int 1823 vc4_hdmi_encoder_compute_clock(const struct vc4_hdmi *vc4_hdmi, 1824 struct vc4_hdmi_connector_state *vc4_state, 1825 const struct drm_display_mode *mode, 1826 unsigned int bpc, unsigned int fmt) 1827 { 1828 unsigned long long clock; 1829 1830 clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc, fmt); 1831 if (vc4_hdmi_encoder_clock_valid(vc4_hdmi, mode, clock) != MODE_OK) 1832 return -EINVAL; 1833 1834 vc4_state->tmds_char_rate = clock; 1835 1836 return 0; 1837 } 1838 1839 static int 1840 vc4_hdmi_encoder_compute_format(const struct vc4_hdmi *vc4_hdmi, 1841 struct vc4_hdmi_connector_state *vc4_state, 1842 const struct drm_display_mode *mode, 1843 unsigned int bpc) 1844 { 1845 struct drm_device *dev = vc4_hdmi->connector.dev; 1846 const struct drm_connector *connector = &vc4_hdmi->connector; 1847 const struct drm_display_info *info = &connector->display_info; 1848 unsigned int format; 1849 1850 drm_dbg(dev, "Trying with an RGB output\n"); 1851 1852 format = VC4_HDMI_OUTPUT_RGB; 1853 if (vc4_hdmi_sink_supports_format_bpc(vc4_hdmi, info, mode, format, bpc)) { 1854 int ret; 1855 1856 ret = vc4_hdmi_encoder_compute_clock(vc4_hdmi, vc4_state, 1857 mode, bpc, format); 1858 if (!ret) { 1859 vc4_state->output_format = format; 1860 return 0; 1861 } 1862 } 1863 1864 drm_dbg(dev, "Failed, Trying with an YUV422 output\n"); 1865 1866 format = VC4_HDMI_OUTPUT_YUV422; 1867 if (vc4_hdmi_sink_supports_format_bpc(vc4_hdmi, info, mode, format, bpc)) { 1868 int ret; 1869 1870 ret = vc4_hdmi_encoder_compute_clock(vc4_hdmi, vc4_state, 1871 mode, bpc, format); 1872 if (!ret) { 1873 vc4_state->output_format = format; 1874 return 0; 1875 } 1876 } 1877 1878 drm_dbg(dev, "Failed. No Format Supported for that bpc count.\n"); 1879 1880 return -EINVAL; 1881 } 1882 1883 static int 1884 vc4_hdmi_encoder_compute_config(const struct vc4_hdmi *vc4_hdmi, 1885 struct vc4_hdmi_connector_state *vc4_state, 1886 const struct drm_display_mode *mode) 1887 { 1888 struct drm_device *dev = vc4_hdmi->connector.dev; 1889 struct drm_connector_state *conn_state = &vc4_state->base; 1890 unsigned int max_bpc = clamp_t(unsigned int, conn_state->max_bpc, 8, 12); 1891 unsigned int bpc; 1892 int ret; 1893 1894 for (bpc = max_bpc; bpc >= 8; bpc -= 2) { 1895 drm_dbg(dev, "Trying with a %d bpc output\n", bpc); 1896 1897 ret = vc4_hdmi_encoder_compute_format(vc4_hdmi, vc4_state, 1898 mode, bpc); 1899 if (ret) 1900 continue; 1901 1902 vc4_state->output_bpc = bpc; 1903 1904 drm_dbg(dev, 1905 "Mode %ux%u @ %uHz: Found configuration: bpc: %u, fmt: %s, clock: %llu\n", 1906 mode->hdisplay, mode->vdisplay, drm_mode_vrefresh(mode), 1907 vc4_state->output_bpc, 1908 vc4_hdmi_output_fmt_str(vc4_state->output_format), 1909 vc4_state->tmds_char_rate); 1910 1911 break; 1912 } 1913 1914 return ret; 1915 } 1916 1917 #define WIFI_2_4GHz_CH1_MIN_FREQ 2400000000ULL 1918 #define WIFI_2_4GHz_CH1_MAX_FREQ 2422000000ULL 1919 1920 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder, 1921 struct drm_crtc_state *crtc_state, 1922 struct drm_connector_state *conn_state) 1923 { 1924 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1925 struct drm_connector *connector = &vc4_hdmi->connector; 1926 struct drm_connector_state *old_conn_state = 1927 drm_atomic_get_old_connector_state(conn_state->state, connector); 1928 struct vc4_hdmi_connector_state *old_vc4_state = 1929 conn_state_to_vc4_hdmi_conn_state(old_conn_state); 1930 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state); 1931 struct drm_display_mode *mode = &crtc_state->adjusted_mode; 1932 unsigned long long tmds_char_rate = mode->clock * 1000; 1933 unsigned long long tmds_bit_rate; 1934 int ret; 1935 1936 if (vc4_hdmi->variant->unsupported_odd_h_timings) { 1937 if (mode->flags & DRM_MODE_FLAG_DBLCLK) { 1938 /* Only try to fixup DBLCLK modes to get 480i and 576i 1939 * working. 1940 * A generic solution for all modes with odd horizontal 1941 * timing values seems impossible based on trying to 1942 * solve it for 1366x768 monitors. 1943 */ 1944 if ((mode->hsync_start - mode->hdisplay) & 1) 1945 mode->hsync_start--; 1946 if ((mode->hsync_end - mode->hsync_start) & 1) 1947 mode->hsync_end--; 1948 } 1949 1950 /* Now check whether we still have odd values remaining */ 1951 if ((mode->hdisplay % 2) || (mode->hsync_start % 2) || 1952 (mode->hsync_end % 2) || (mode->htotal % 2)) 1953 return -EINVAL; 1954 } 1955 1956 /* 1957 * The 1440p@60 pixel rate is in the same range than the first 1958 * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz 1959 * bandwidth). Slightly lower the frequency to bring it out of 1960 * the WiFi range. 1961 */ 1962 tmds_bit_rate = tmds_char_rate * 10; 1963 if (vc4_hdmi->disable_wifi_frequencies && 1964 (tmds_bit_rate >= WIFI_2_4GHz_CH1_MIN_FREQ && 1965 tmds_bit_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) { 1966 mode->clock = 238560; 1967 tmds_char_rate = mode->clock * 1000; 1968 } 1969 1970 ret = vc4_hdmi_encoder_compute_config(vc4_hdmi, vc4_state, mode); 1971 if (ret) 1972 return ret; 1973 1974 /* vc4_hdmi_encoder_compute_config may have changed output_bpc and/or output_format */ 1975 if (vc4_state->output_bpc != old_vc4_state->output_bpc || 1976 vc4_state->output_format != old_vc4_state->output_format) 1977 crtc_state->mode_changed = true; 1978 1979 return 0; 1980 } 1981 1982 static enum drm_mode_status 1983 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder, 1984 const struct drm_display_mode *mode) 1985 { 1986 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1987 1988 if (vc4_hdmi->variant->unsupported_odd_h_timings && 1989 !(mode->flags & DRM_MODE_FLAG_DBLCLK) && 1990 ((mode->hdisplay % 2) || (mode->hsync_start % 2) || 1991 (mode->hsync_end % 2) || (mode->htotal % 2))) 1992 return MODE_H_ILLEGAL; 1993 1994 return vc4_hdmi_encoder_clock_valid(vc4_hdmi, mode, mode->clock * 1000); 1995 } 1996 1997 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = { 1998 .atomic_check = vc4_hdmi_encoder_atomic_check, 1999 .atomic_mode_set = vc4_hdmi_encoder_atomic_mode_set, 2000 .mode_valid = vc4_hdmi_encoder_mode_valid, 2001 }; 2002 2003 static int vc4_hdmi_late_register(struct drm_encoder *encoder) 2004 { 2005 struct drm_device *drm = encoder->dev; 2006 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 2007 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant; 2008 2009 drm_debugfs_add_file(drm, variant->debugfs_name, 2010 vc4_hdmi_debugfs_regs, vc4_hdmi); 2011 2012 return 0; 2013 } 2014 2015 static const struct drm_encoder_funcs vc4_hdmi_encoder_funcs = { 2016 .late_register = vc4_hdmi_late_register, 2017 }; 2018 2019 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask) 2020 { 2021 int i; 2022 u32 channel_map = 0; 2023 2024 for (i = 0; i < 8; i++) { 2025 if (channel_mask & BIT(i)) 2026 channel_map |= i << (3 * i); 2027 } 2028 return channel_map; 2029 } 2030 2031 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask) 2032 { 2033 int i; 2034 u32 channel_map = 0; 2035 2036 for (i = 0; i < 8; i++) { 2037 if (channel_mask & BIT(i)) 2038 channel_map |= i << (4 * i); 2039 } 2040 return channel_map; 2041 } 2042 2043 static bool vc5_hdmi_hp_detect(struct vc4_hdmi *vc4_hdmi) 2044 { 2045 struct drm_device *drm = vc4_hdmi->connector.dev; 2046 unsigned long flags; 2047 u32 hotplug; 2048 int idx; 2049 2050 if (!drm_dev_enter(drm, &idx)) 2051 return false; 2052 2053 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2054 hotplug = HDMI_READ(HDMI_HOTPLUG); 2055 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2056 2057 drm_dev_exit(idx); 2058 2059 return !!(hotplug & VC4_HDMI_HOTPLUG_CONNECTED); 2060 } 2061 2062 /* HDMI audio codec callbacks */ 2063 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi, 2064 unsigned int samplerate) 2065 { 2066 struct drm_device *drm = vc4_hdmi->connector.dev; 2067 u32 hsm_clock; 2068 unsigned long flags; 2069 unsigned long n, m; 2070 int idx; 2071 2072 if (!drm_dev_enter(drm, &idx)) 2073 return; 2074 2075 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock); 2076 rational_best_approximation(hsm_clock, samplerate, 2077 VC4_HD_MAI_SMP_N_MASK >> 2078 VC4_HD_MAI_SMP_N_SHIFT, 2079 (VC4_HD_MAI_SMP_M_MASK >> 2080 VC4_HD_MAI_SMP_M_SHIFT) + 1, 2081 &n, &m); 2082 2083 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2084 HDMI_WRITE(HDMI_MAI_SMP, 2085 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) | 2086 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M)); 2087 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2088 2089 drm_dev_exit(idx); 2090 } 2091 2092 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi, unsigned int samplerate) 2093 { 2094 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 2095 u32 n, cts; 2096 u64 tmp; 2097 2098 lockdep_assert_held(&vc4_hdmi->mutex); 2099 lockdep_assert_held(&vc4_hdmi->hw_lock); 2100 2101 n = 128 * samplerate / 1000; 2102 tmp = (u64)(mode->clock * 1000) * n; 2103 do_div(tmp, 128 * samplerate); 2104 cts = tmp; 2105 2106 HDMI_WRITE(HDMI_CRP_CFG, 2107 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN | 2108 VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N)); 2109 2110 /* 2111 * We could get slightly more accurate clocks in some cases by 2112 * providing a CTS_1 value. The two CTS values are alternated 2113 * between based on the period fields 2114 */ 2115 HDMI_WRITE(HDMI_CTS_0, cts); 2116 HDMI_WRITE(HDMI_CTS_1, cts); 2117 } 2118 2119 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai) 2120 { 2121 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai); 2122 2123 return snd_soc_card_get_drvdata(card); 2124 } 2125 2126 static bool vc4_hdmi_audio_can_stream(struct vc4_hdmi *vc4_hdmi) 2127 { 2128 struct drm_display_info *display = &vc4_hdmi->connector.display_info; 2129 2130 lockdep_assert_held(&vc4_hdmi->mutex); 2131 2132 /* 2133 * If the encoder is currently in DVI mode, treat the codec DAI 2134 * as missing. 2135 */ 2136 if (!display->is_hdmi) 2137 return false; 2138 2139 return true; 2140 } 2141 2142 static int vc4_hdmi_audio_startup(struct device *dev, void *data) 2143 { 2144 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 2145 struct drm_device *drm = vc4_hdmi->connector.dev; 2146 unsigned long flags; 2147 int ret = 0; 2148 int idx; 2149 2150 mutex_lock(&vc4_hdmi->mutex); 2151 2152 if (!drm_dev_enter(drm, &idx)) { 2153 ret = -ENODEV; 2154 goto out; 2155 } 2156 2157 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) { 2158 ret = -ENODEV; 2159 goto out_dev_exit; 2160 } 2161 2162 vc4_hdmi->audio.streaming = true; 2163 2164 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2165 HDMI_WRITE(HDMI_MAI_CTL, 2166 VC4_HD_MAI_CTL_RESET | 2167 VC4_HD_MAI_CTL_FLUSH | 2168 VC4_HD_MAI_CTL_DLATE | 2169 VC4_HD_MAI_CTL_ERRORE | 2170 VC4_HD_MAI_CTL_ERRORF); 2171 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2172 2173 if (vc4_hdmi->variant->phy_rng_enable) 2174 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi); 2175 2176 out_dev_exit: 2177 drm_dev_exit(idx); 2178 out: 2179 mutex_unlock(&vc4_hdmi->mutex); 2180 2181 return ret; 2182 } 2183 2184 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi) 2185 { 2186 struct drm_encoder *encoder = &vc4_hdmi->encoder.base; 2187 struct device *dev = &vc4_hdmi->pdev->dev; 2188 unsigned long flags; 2189 int ret; 2190 2191 lockdep_assert_held(&vc4_hdmi->mutex); 2192 2193 vc4_hdmi->audio.streaming = false; 2194 ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO, false); 2195 if (ret) 2196 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret); 2197 2198 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2199 2200 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET); 2201 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF); 2202 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH); 2203 2204 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2205 } 2206 2207 static void vc4_hdmi_audio_shutdown(struct device *dev, void *data) 2208 { 2209 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 2210 struct drm_device *drm = vc4_hdmi->connector.dev; 2211 unsigned long flags; 2212 int idx; 2213 2214 mutex_lock(&vc4_hdmi->mutex); 2215 2216 if (!drm_dev_enter(drm, &idx)) 2217 goto out; 2218 2219 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2220 2221 HDMI_WRITE(HDMI_MAI_CTL, 2222 VC4_HD_MAI_CTL_DLATE | 2223 VC4_HD_MAI_CTL_ERRORE | 2224 VC4_HD_MAI_CTL_ERRORF); 2225 2226 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2227 2228 if (vc4_hdmi->variant->phy_rng_disable) 2229 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi); 2230 2231 vc4_hdmi->audio.streaming = false; 2232 vc4_hdmi_audio_reset(vc4_hdmi); 2233 2234 drm_dev_exit(idx); 2235 2236 out: 2237 mutex_unlock(&vc4_hdmi->mutex); 2238 } 2239 2240 static int sample_rate_to_mai_fmt(int samplerate) 2241 { 2242 switch (samplerate) { 2243 case 8000: 2244 return VC4_HDMI_MAI_SAMPLE_RATE_8000; 2245 case 11025: 2246 return VC4_HDMI_MAI_SAMPLE_RATE_11025; 2247 case 12000: 2248 return VC4_HDMI_MAI_SAMPLE_RATE_12000; 2249 case 16000: 2250 return VC4_HDMI_MAI_SAMPLE_RATE_16000; 2251 case 22050: 2252 return VC4_HDMI_MAI_SAMPLE_RATE_22050; 2253 case 24000: 2254 return VC4_HDMI_MAI_SAMPLE_RATE_24000; 2255 case 32000: 2256 return VC4_HDMI_MAI_SAMPLE_RATE_32000; 2257 case 44100: 2258 return VC4_HDMI_MAI_SAMPLE_RATE_44100; 2259 case 48000: 2260 return VC4_HDMI_MAI_SAMPLE_RATE_48000; 2261 case 64000: 2262 return VC4_HDMI_MAI_SAMPLE_RATE_64000; 2263 case 88200: 2264 return VC4_HDMI_MAI_SAMPLE_RATE_88200; 2265 case 96000: 2266 return VC4_HDMI_MAI_SAMPLE_RATE_96000; 2267 case 128000: 2268 return VC4_HDMI_MAI_SAMPLE_RATE_128000; 2269 case 176400: 2270 return VC4_HDMI_MAI_SAMPLE_RATE_176400; 2271 case 192000: 2272 return VC4_HDMI_MAI_SAMPLE_RATE_192000; 2273 default: 2274 return VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED; 2275 } 2276 } 2277 2278 /* HDMI audio codec callbacks */ 2279 static int vc4_hdmi_audio_prepare(struct device *dev, void *data, 2280 struct hdmi_codec_daifmt *daifmt, 2281 struct hdmi_codec_params *params) 2282 { 2283 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 2284 struct drm_device *drm = vc4_hdmi->connector.dev; 2285 struct drm_encoder *encoder = &vc4_hdmi->encoder.base; 2286 unsigned int sample_rate = params->sample_rate; 2287 unsigned int channels = params->channels; 2288 unsigned long flags; 2289 u32 audio_packet_config, channel_mask; 2290 u32 channel_map; 2291 u32 mai_audio_format; 2292 u32 mai_sample_rate; 2293 int ret = 0; 2294 int idx; 2295 2296 dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__, 2297 sample_rate, params->sample_width, channels); 2298 2299 mutex_lock(&vc4_hdmi->mutex); 2300 2301 if (!drm_dev_enter(drm, &idx)) { 2302 ret = -ENODEV; 2303 goto out; 2304 } 2305 2306 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) { 2307 ret = -EINVAL; 2308 goto out_dev_exit; 2309 } 2310 2311 vc4_hdmi_audio_set_mai_clock(vc4_hdmi, sample_rate); 2312 2313 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2314 HDMI_WRITE(HDMI_MAI_CTL, 2315 VC4_SET_FIELD(channels, VC4_HD_MAI_CTL_CHNUM) | 2316 VC4_HD_MAI_CTL_WHOLSMP | 2317 VC4_HD_MAI_CTL_CHALIGN | 2318 VC4_HD_MAI_CTL_ENABLE); 2319 2320 mai_sample_rate = sample_rate_to_mai_fmt(sample_rate); 2321 if (params->iec.status[0] & IEC958_AES0_NONAUDIO && 2322 params->channels == 8) 2323 mai_audio_format = VC4_HDMI_MAI_FORMAT_HBR; 2324 else 2325 mai_audio_format = VC4_HDMI_MAI_FORMAT_PCM; 2326 HDMI_WRITE(HDMI_MAI_FMT, 2327 VC4_SET_FIELD(mai_sample_rate, 2328 VC4_HDMI_MAI_FORMAT_SAMPLE_RATE) | 2329 VC4_SET_FIELD(mai_audio_format, 2330 VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT)); 2331 2332 /* The B frame identifier should match the value used by alsa-lib (8) */ 2333 audio_packet_config = 2334 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT | 2335 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS | 2336 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER); 2337 2338 channel_mask = GENMASK(channels - 1, 0); 2339 audio_packet_config |= VC4_SET_FIELD(channel_mask, 2340 VC4_HDMI_AUDIO_PACKET_CEA_MASK); 2341 2342 /* Set the MAI threshold */ 2343 HDMI_WRITE(HDMI_MAI_THR, 2344 VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICHIGH) | 2345 VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICLOW) | 2346 VC4_SET_FIELD(0x06, VC4_HD_MAI_THR_DREQHIGH) | 2347 VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_DREQLOW)); 2348 2349 HDMI_WRITE(HDMI_MAI_CONFIG, 2350 VC4_HDMI_MAI_CONFIG_BIT_REVERSE | 2351 VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE | 2352 VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK)); 2353 2354 channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask); 2355 HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map); 2356 HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config); 2357 2358 vc4_hdmi_set_n_cts(vc4_hdmi, sample_rate); 2359 2360 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2361 2362 memcpy(&vc4_hdmi->audio.infoframe, ¶ms->cea, sizeof(params->cea)); 2363 vc4_hdmi_set_audio_infoframe(encoder); 2364 2365 out_dev_exit: 2366 drm_dev_exit(idx); 2367 out: 2368 mutex_unlock(&vc4_hdmi->mutex); 2369 2370 return ret; 2371 } 2372 2373 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = { 2374 .name = "vc4-hdmi-cpu-dai-component", 2375 .legacy_dai_naming = 1, 2376 }; 2377 2378 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai) 2379 { 2380 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai); 2381 2382 snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL); 2383 2384 return 0; 2385 } 2386 2387 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = { 2388 .name = "vc4-hdmi-cpu-dai", 2389 .probe = vc4_hdmi_audio_cpu_dai_probe, 2390 .playback = { 2391 .stream_name = "Playback", 2392 .channels_min = 1, 2393 .channels_max = 8, 2394 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 2395 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 2396 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 2397 SNDRV_PCM_RATE_192000, 2398 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 2399 }, 2400 }; 2401 2402 static const struct snd_dmaengine_pcm_config pcm_conf = { 2403 .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx", 2404 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 2405 }; 2406 2407 static int vc4_hdmi_audio_get_eld(struct device *dev, void *data, 2408 uint8_t *buf, size_t len) 2409 { 2410 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 2411 struct drm_connector *connector = &vc4_hdmi->connector; 2412 2413 mutex_lock(&vc4_hdmi->mutex); 2414 memcpy(buf, connector->eld, min(sizeof(connector->eld), len)); 2415 mutex_unlock(&vc4_hdmi->mutex); 2416 2417 return 0; 2418 } 2419 2420 static const struct hdmi_codec_ops vc4_hdmi_codec_ops = { 2421 .get_eld = vc4_hdmi_audio_get_eld, 2422 .prepare = vc4_hdmi_audio_prepare, 2423 .audio_shutdown = vc4_hdmi_audio_shutdown, 2424 .audio_startup = vc4_hdmi_audio_startup, 2425 }; 2426 2427 static struct hdmi_codec_pdata vc4_hdmi_codec_pdata = { 2428 .ops = &vc4_hdmi_codec_ops, 2429 .max_i2s_channels = 8, 2430 .i2s = 1, 2431 }; 2432 2433 static void vc4_hdmi_audio_codec_release(void *ptr) 2434 { 2435 struct vc4_hdmi *vc4_hdmi = ptr; 2436 2437 platform_device_unregister(vc4_hdmi->audio.codec_pdev); 2438 vc4_hdmi->audio.codec_pdev = NULL; 2439 } 2440 2441 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi) 2442 { 2443 const struct vc4_hdmi_register *mai_data = 2444 &vc4_hdmi->variant->registers[HDMI_MAI_DATA]; 2445 struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link; 2446 struct snd_soc_card *card = &vc4_hdmi->audio.card; 2447 struct device *dev = &vc4_hdmi->pdev->dev; 2448 struct platform_device *codec_pdev; 2449 const __be32 *addr; 2450 int index, len; 2451 int ret; 2452 2453 /* 2454 * ASoC makes it a bit hard to retrieve a pointer to the 2455 * vc4_hdmi structure. Registering the card will overwrite our 2456 * device drvdata with a pointer to the snd_soc_card structure, 2457 * which can then be used to retrieve whatever drvdata we want 2458 * to associate. 2459 * 2460 * However, that doesn't fly in the case where we wouldn't 2461 * register an ASoC card (because of an old DT that is missing 2462 * the dmas properties for example), then the card isn't 2463 * registered and the device drvdata wouldn't be set. 2464 * 2465 * We can deal with both cases by making sure a snd_soc_card 2466 * pointer and a vc4_hdmi structure are pointing to the same 2467 * memory address, so we can treat them indistinctly without any 2468 * issue. 2469 */ 2470 BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0); 2471 BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0); 2472 2473 if (!of_find_property(dev->of_node, "dmas", &len) || !len) { 2474 dev_warn(dev, 2475 "'dmas' DT property is missing or empty, no HDMI audio\n"); 2476 return 0; 2477 } 2478 2479 if (mai_data->reg != VC4_HD) { 2480 WARN_ONCE(true, "MAI isn't in the HD block\n"); 2481 return -EINVAL; 2482 } 2483 2484 /* 2485 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve 2486 * the bus address specified in the DT, because the physical address 2487 * (the one returned by platform_get_resource()) is not appropriate 2488 * for DMA transfers. 2489 * This VC/MMU should probably be exposed to avoid this kind of hacks. 2490 */ 2491 index = of_property_match_string(dev->of_node, "reg-names", "hd"); 2492 /* Before BCM2711, we don't have a named register range */ 2493 if (index < 0) 2494 index = 1; 2495 2496 addr = of_get_address(dev->of_node, index, NULL, NULL); 2497 2498 vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset; 2499 vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 2500 vc4_hdmi->audio.dma_data.maxburst = 2; 2501 2502 /* 2503 * NOTE: Strictly speaking, we should probably use a DRM-managed 2504 * registration there to avoid removing all the audio components 2505 * by the time the driver doesn't have any user anymore. 2506 * 2507 * However, the ASoC core uses a number of devm_kzalloc calls 2508 * when registering, even when using non-device-managed 2509 * functions (such as in snd_soc_register_component()). 2510 * 2511 * If we call snd_soc_unregister_component() in a DRM-managed 2512 * action, the device-managed actions have already been executed 2513 * and thus we would access memory that has been freed. 2514 * 2515 * Using device-managed hooks here probably leaves us open to a 2516 * bunch of issues if userspace still has a handle on the ALSA 2517 * device when the device is removed. However, this is mitigated 2518 * by the use of drm_dev_enter()/drm_dev_exit() in the audio 2519 * path to prevent the access to the device resources if it 2520 * isn't there anymore. 2521 * 2522 * Then, the vc4_hdmi structure is DRM-managed and thus only 2523 * freed whenever the last user has closed the DRM device file. 2524 * It should thus outlive ALSA in most situations. 2525 */ 2526 ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0); 2527 if (ret) { 2528 dev_err(dev, "Could not register PCM component: %d\n", ret); 2529 return ret; 2530 } 2531 2532 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp, 2533 &vc4_hdmi_audio_cpu_dai_drv, 1); 2534 if (ret) { 2535 dev_err(dev, "Could not register CPU DAI: %d\n", ret); 2536 return ret; 2537 } 2538 2539 codec_pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME, 2540 PLATFORM_DEVID_AUTO, 2541 &vc4_hdmi_codec_pdata, 2542 sizeof(vc4_hdmi_codec_pdata)); 2543 if (IS_ERR(codec_pdev)) { 2544 dev_err(dev, "Couldn't register the HDMI codec: %ld\n", PTR_ERR(codec_pdev)); 2545 return PTR_ERR(codec_pdev); 2546 } 2547 vc4_hdmi->audio.codec_pdev = codec_pdev; 2548 2549 ret = devm_add_action_or_reset(dev, vc4_hdmi_audio_codec_release, vc4_hdmi); 2550 if (ret) 2551 return ret; 2552 2553 dai_link->cpus = &vc4_hdmi->audio.cpu; 2554 dai_link->codecs = &vc4_hdmi->audio.codec; 2555 dai_link->platforms = &vc4_hdmi->audio.platform; 2556 2557 dai_link->num_cpus = 1; 2558 dai_link->num_codecs = 1; 2559 dai_link->num_platforms = 1; 2560 2561 dai_link->name = "MAI"; 2562 dai_link->stream_name = "MAI PCM"; 2563 dai_link->codecs->dai_name = "i2s-hifi"; 2564 dai_link->cpus->dai_name = dev_name(dev); 2565 dai_link->codecs->name = dev_name(&codec_pdev->dev); 2566 dai_link->platforms->name = dev_name(dev); 2567 2568 card->dai_link = dai_link; 2569 card->num_links = 1; 2570 card->name = vc4_hdmi->variant->card_name; 2571 card->driver_name = "vc4-hdmi"; 2572 card->dev = dev; 2573 card->owner = THIS_MODULE; 2574 2575 /* 2576 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and 2577 * stores a pointer to the snd card object in dev->driver_data. This 2578 * means we cannot use it for something else. The hdmi back-pointer is 2579 * now stored in card->drvdata and should be retrieved with 2580 * snd_soc_card_get_drvdata() if needed. 2581 */ 2582 snd_soc_card_set_drvdata(card, vc4_hdmi); 2583 ret = devm_snd_soc_register_card(dev, card); 2584 if (ret) 2585 dev_err_probe(dev, ret, "Could not register sound card\n"); 2586 2587 return ret; 2588 2589 } 2590 2591 static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv) 2592 { 2593 struct vc4_hdmi *vc4_hdmi = priv; 2594 struct drm_connector *connector = &vc4_hdmi->connector; 2595 struct drm_device *dev = connector->dev; 2596 2597 if (dev && dev->registered) 2598 drm_connector_helper_hpd_irq_event(connector); 2599 2600 return IRQ_HANDLED; 2601 } 2602 2603 static int vc4_hdmi_hotplug_init(struct vc4_hdmi *vc4_hdmi) 2604 { 2605 struct drm_connector *connector = &vc4_hdmi->connector; 2606 struct platform_device *pdev = vc4_hdmi->pdev; 2607 int ret; 2608 2609 if (vc4_hdmi->variant->external_irq_controller) { 2610 unsigned int hpd_con = platform_get_irq_byname(pdev, "hpd-connected"); 2611 unsigned int hpd_rm = platform_get_irq_byname(pdev, "hpd-removed"); 2612 2613 ret = devm_request_threaded_irq(&pdev->dev, hpd_con, 2614 NULL, 2615 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT, 2616 "vc4 hdmi hpd connected", vc4_hdmi); 2617 if (ret) 2618 return ret; 2619 2620 ret = devm_request_threaded_irq(&pdev->dev, hpd_rm, 2621 NULL, 2622 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT, 2623 "vc4 hdmi hpd disconnected", vc4_hdmi); 2624 if (ret) 2625 return ret; 2626 2627 connector->polled = DRM_CONNECTOR_POLL_HPD; 2628 } 2629 2630 return 0; 2631 } 2632 2633 #ifdef CONFIG_DRM_VC4_HDMI_CEC 2634 static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv) 2635 { 2636 struct vc4_hdmi *vc4_hdmi = priv; 2637 2638 if (vc4_hdmi->cec_rx_msg.len) 2639 cec_received_msg(vc4_hdmi->cec_adap, 2640 &vc4_hdmi->cec_rx_msg); 2641 2642 return IRQ_HANDLED; 2643 } 2644 2645 static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv) 2646 { 2647 struct vc4_hdmi *vc4_hdmi = priv; 2648 2649 if (vc4_hdmi->cec_tx_ok) { 2650 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK, 2651 0, 0, 0, 0); 2652 } else { 2653 /* 2654 * This CEC implementation makes 1 retry, so if we 2655 * get a NACK, then that means it made 2 attempts. 2656 */ 2657 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK, 2658 0, 2, 0, 0); 2659 } 2660 return IRQ_HANDLED; 2661 } 2662 2663 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv) 2664 { 2665 struct vc4_hdmi *vc4_hdmi = priv; 2666 irqreturn_t ret; 2667 2668 if (vc4_hdmi->cec_irq_was_rx) 2669 ret = vc4_cec_irq_handler_rx_thread(irq, priv); 2670 else 2671 ret = vc4_cec_irq_handler_tx_thread(irq, priv); 2672 2673 return ret; 2674 } 2675 2676 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1) 2677 { 2678 struct drm_device *dev = vc4_hdmi->connector.dev; 2679 struct cec_msg *msg = &vc4_hdmi->cec_rx_msg; 2680 unsigned int i; 2681 2682 lockdep_assert_held(&vc4_hdmi->hw_lock); 2683 2684 msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >> 2685 VC4_HDMI_CEC_REC_WRD_CNT_SHIFT); 2686 2687 if (msg->len > 16) { 2688 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len); 2689 return; 2690 } 2691 2692 for (i = 0; i < msg->len; i += 4) { 2693 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2)); 2694 2695 msg->msg[i] = val & 0xff; 2696 msg->msg[i + 1] = (val >> 8) & 0xff; 2697 msg->msg[i + 2] = (val >> 16) & 0xff; 2698 msg->msg[i + 3] = (val >> 24) & 0xff; 2699 } 2700 } 2701 2702 static irqreturn_t vc4_cec_irq_handler_tx_bare_locked(struct vc4_hdmi *vc4_hdmi) 2703 { 2704 u32 cntrl1; 2705 2706 /* 2707 * We don't need to protect the register access using 2708 * drm_dev_enter() there because the interrupt handler lifetime 2709 * is tied to the device itself, and not to the DRM device. 2710 * 2711 * So when the device will be gone, one of the first thing we 2712 * will be doing will be to unregister the interrupt handler, 2713 * and then unregister the DRM device. drm_dev_enter() would 2714 * thus always succeed if we are here. 2715 */ 2716 2717 lockdep_assert_held(&vc4_hdmi->hw_lock); 2718 2719 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1); 2720 vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD; 2721 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 2722 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 2723 2724 return IRQ_WAKE_THREAD; 2725 } 2726 2727 static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv) 2728 { 2729 struct vc4_hdmi *vc4_hdmi = priv; 2730 irqreturn_t ret; 2731 2732 spin_lock(&vc4_hdmi->hw_lock); 2733 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi); 2734 spin_unlock(&vc4_hdmi->hw_lock); 2735 2736 return ret; 2737 } 2738 2739 static irqreturn_t vc4_cec_irq_handler_rx_bare_locked(struct vc4_hdmi *vc4_hdmi) 2740 { 2741 u32 cntrl1; 2742 2743 lockdep_assert_held(&vc4_hdmi->hw_lock); 2744 2745 /* 2746 * We don't need to protect the register access using 2747 * drm_dev_enter() there because the interrupt handler lifetime 2748 * is tied to the device itself, and not to the DRM device. 2749 * 2750 * So when the device will be gone, one of the first thing we 2751 * will be doing will be to unregister the interrupt handler, 2752 * and then unregister the DRM device. drm_dev_enter() would 2753 * thus always succeed if we are here. 2754 */ 2755 2756 vc4_hdmi->cec_rx_msg.len = 0; 2757 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1); 2758 vc4_cec_read_msg(vc4_hdmi, cntrl1); 2759 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 2760 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 2761 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 2762 2763 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 2764 2765 return IRQ_WAKE_THREAD; 2766 } 2767 2768 static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv) 2769 { 2770 struct vc4_hdmi *vc4_hdmi = priv; 2771 irqreturn_t ret; 2772 2773 spin_lock(&vc4_hdmi->hw_lock); 2774 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi); 2775 spin_unlock(&vc4_hdmi->hw_lock); 2776 2777 return ret; 2778 } 2779 2780 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv) 2781 { 2782 struct vc4_hdmi *vc4_hdmi = priv; 2783 u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS); 2784 irqreturn_t ret; 2785 u32 cntrl5; 2786 2787 /* 2788 * We don't need to protect the register access using 2789 * drm_dev_enter() there because the interrupt handler lifetime 2790 * is tied to the device itself, and not to the DRM device. 2791 * 2792 * So when the device will be gone, one of the first thing we 2793 * will be doing will be to unregister the interrupt handler, 2794 * and then unregister the DRM device. drm_dev_enter() would 2795 * thus always succeed if we are here. 2796 */ 2797 2798 if (!(stat & VC4_HDMI_CPU_CEC)) 2799 return IRQ_NONE; 2800 2801 spin_lock(&vc4_hdmi->hw_lock); 2802 cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5); 2803 vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT; 2804 if (vc4_hdmi->cec_irq_was_rx) 2805 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi); 2806 else 2807 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi); 2808 2809 HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC); 2810 spin_unlock(&vc4_hdmi->hw_lock); 2811 2812 return ret; 2813 } 2814 2815 static int vc4_hdmi_cec_enable(struct cec_adapter *adap) 2816 { 2817 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 2818 struct drm_device *drm = vc4_hdmi->connector.dev; 2819 /* clock period in microseconds */ 2820 const u32 usecs = 1000000 / CEC_CLOCK_FREQ; 2821 unsigned long flags; 2822 u32 val; 2823 int ret; 2824 int idx; 2825 2826 if (!drm_dev_enter(drm, &idx)) 2827 /* 2828 * We can't return an error code, because the CEC 2829 * framework will emit WARN_ON messages at unbind 2830 * otherwise. 2831 */ 2832 return 0; 2833 2834 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev); 2835 if (ret) { 2836 drm_dev_exit(idx); 2837 return ret; 2838 } 2839 2840 mutex_lock(&vc4_hdmi->mutex); 2841 2842 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2843 2844 val = HDMI_READ(HDMI_CEC_CNTRL_5); 2845 val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET | 2846 VC4_HDMI_CEC_CNT_TO_4700_US_MASK | 2847 VC4_HDMI_CEC_CNT_TO_4500_US_MASK); 2848 val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) | 2849 ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT); 2850 2851 HDMI_WRITE(HDMI_CEC_CNTRL_5, val | 2852 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 2853 HDMI_WRITE(HDMI_CEC_CNTRL_5, val); 2854 HDMI_WRITE(HDMI_CEC_CNTRL_2, 2855 ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) | 2856 ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) | 2857 ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) | 2858 ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) | 2859 ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT)); 2860 HDMI_WRITE(HDMI_CEC_CNTRL_3, 2861 ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) | 2862 ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) | 2863 ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) | 2864 ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT)); 2865 HDMI_WRITE(HDMI_CEC_CNTRL_4, 2866 ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) | 2867 ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) | 2868 ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) | 2869 ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT)); 2870 2871 if (!vc4_hdmi->variant->external_irq_controller) 2872 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC); 2873 2874 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2875 2876 mutex_unlock(&vc4_hdmi->mutex); 2877 drm_dev_exit(idx); 2878 2879 return 0; 2880 } 2881 2882 static int vc4_hdmi_cec_disable(struct cec_adapter *adap) 2883 { 2884 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 2885 struct drm_device *drm = vc4_hdmi->connector.dev; 2886 unsigned long flags; 2887 int idx; 2888 2889 if (!drm_dev_enter(drm, &idx)) 2890 /* 2891 * We can't return an error code, because the CEC 2892 * framework will emit WARN_ON messages at unbind 2893 * otherwise. 2894 */ 2895 return 0; 2896 2897 mutex_lock(&vc4_hdmi->mutex); 2898 2899 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2900 2901 if (!vc4_hdmi->variant->external_irq_controller) 2902 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC); 2903 2904 HDMI_WRITE(HDMI_CEC_CNTRL_5, HDMI_READ(HDMI_CEC_CNTRL_5) | 2905 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 2906 2907 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2908 2909 mutex_unlock(&vc4_hdmi->mutex); 2910 2911 pm_runtime_put(&vc4_hdmi->pdev->dev); 2912 2913 drm_dev_exit(idx); 2914 2915 return 0; 2916 } 2917 2918 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable) 2919 { 2920 if (enable) 2921 return vc4_hdmi_cec_enable(adap); 2922 else 2923 return vc4_hdmi_cec_disable(adap); 2924 } 2925 2926 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr) 2927 { 2928 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 2929 struct drm_device *drm = vc4_hdmi->connector.dev; 2930 unsigned long flags; 2931 int idx; 2932 2933 if (!drm_dev_enter(drm, &idx)) 2934 /* 2935 * We can't return an error code, because the CEC 2936 * framework will emit WARN_ON messages at unbind 2937 * otherwise. 2938 */ 2939 return 0; 2940 2941 mutex_lock(&vc4_hdmi->mutex); 2942 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2943 HDMI_WRITE(HDMI_CEC_CNTRL_1, 2944 (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) | 2945 (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT); 2946 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2947 mutex_unlock(&vc4_hdmi->mutex); 2948 2949 drm_dev_exit(idx); 2950 2951 return 0; 2952 } 2953 2954 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts, 2955 u32 signal_free_time, struct cec_msg *msg) 2956 { 2957 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 2958 struct drm_device *dev = vc4_hdmi->connector.dev; 2959 unsigned long flags; 2960 u32 val; 2961 unsigned int i; 2962 int idx; 2963 2964 if (!drm_dev_enter(dev, &idx)) 2965 return -ENODEV; 2966 2967 if (msg->len > 16) { 2968 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len); 2969 drm_dev_exit(idx); 2970 return -ENOMEM; 2971 } 2972 2973 mutex_lock(&vc4_hdmi->mutex); 2974 2975 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2976 2977 for (i = 0; i < msg->len; i += 4) 2978 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2), 2979 (msg->msg[i]) | 2980 (msg->msg[i + 1] << 8) | 2981 (msg->msg[i + 2] << 16) | 2982 (msg->msg[i + 3] << 24)); 2983 2984 val = HDMI_READ(HDMI_CEC_CNTRL_1); 2985 val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 2986 HDMI_WRITE(HDMI_CEC_CNTRL_1, val); 2987 val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK; 2988 val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT; 2989 val |= VC4_HDMI_CEC_START_XMIT_BEGIN; 2990 2991 HDMI_WRITE(HDMI_CEC_CNTRL_1, val); 2992 2993 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2994 mutex_unlock(&vc4_hdmi->mutex); 2995 drm_dev_exit(idx); 2996 2997 return 0; 2998 } 2999 3000 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = { 3001 .adap_enable = vc4_hdmi_cec_adap_enable, 3002 .adap_log_addr = vc4_hdmi_cec_adap_log_addr, 3003 .adap_transmit = vc4_hdmi_cec_adap_transmit, 3004 }; 3005 3006 static void vc4_hdmi_cec_release(void *ptr) 3007 { 3008 struct vc4_hdmi *vc4_hdmi = ptr; 3009 3010 cec_unregister_adapter(vc4_hdmi->cec_adap); 3011 vc4_hdmi->cec_adap = NULL; 3012 } 3013 3014 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi) 3015 { 3016 struct cec_connector_info conn_info; 3017 struct platform_device *pdev = vc4_hdmi->pdev; 3018 struct device *dev = &pdev->dev; 3019 int ret; 3020 3021 if (!of_find_property(dev->of_node, "interrupts", NULL)) { 3022 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n"); 3023 return 0; 3024 } 3025 3026 vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops, 3027 vc4_hdmi, "vc4", 3028 CEC_CAP_DEFAULTS | 3029 CEC_CAP_CONNECTOR_INFO, 1); 3030 ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap); 3031 if (ret < 0) 3032 return ret; 3033 3034 cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector); 3035 cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info); 3036 3037 if (vc4_hdmi->variant->external_irq_controller) { 3038 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-rx"), 3039 vc4_cec_irq_handler_rx_bare, 3040 vc4_cec_irq_handler_rx_thread, 0, 3041 "vc4 hdmi cec rx", vc4_hdmi); 3042 if (ret) 3043 goto err_delete_cec_adap; 3044 3045 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-tx"), 3046 vc4_cec_irq_handler_tx_bare, 3047 vc4_cec_irq_handler_tx_thread, 0, 3048 "vc4 hdmi cec tx", vc4_hdmi); 3049 if (ret) 3050 goto err_delete_cec_adap; 3051 } else { 3052 ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0), 3053 vc4_cec_irq_handler, 3054 vc4_cec_irq_handler_thread, 0, 3055 "vc4 hdmi cec", vc4_hdmi); 3056 if (ret) 3057 goto err_delete_cec_adap; 3058 } 3059 3060 ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev); 3061 if (ret < 0) 3062 goto err_delete_cec_adap; 3063 3064 /* 3065 * NOTE: Strictly speaking, we should probably use a DRM-managed 3066 * registration there to avoid removing the CEC adapter by the 3067 * time the DRM driver doesn't have any user anymore. 3068 * 3069 * However, the CEC framework already cleans up the CEC adapter 3070 * only when the last user has closed its file descriptor, so we 3071 * don't need to handle it in DRM. 3072 * 3073 * By the time the device-managed hook is executed, we will give 3074 * up our reference to the CEC adapter and therefore don't 3075 * really care when it's actually freed. 3076 * 3077 * There's still a problematic sequence: if we unregister our 3078 * CEC adapter, but the userspace keeps a handle on the CEC 3079 * adapter but not the DRM device for some reason. In such a 3080 * case, our vc4_hdmi structure will be freed, but the 3081 * cec_adapter structure will have a dangling pointer to what 3082 * used to be our HDMI controller. If we get a CEC call at that 3083 * moment, we could end up with a use-after-free. Fortunately, 3084 * the CEC framework already handles this too, by calling 3085 * cec_is_registered() in cec_ioctl() and cec_poll(). 3086 */ 3087 ret = devm_add_action_or_reset(dev, vc4_hdmi_cec_release, vc4_hdmi); 3088 if (ret) 3089 return ret; 3090 3091 return 0; 3092 3093 err_delete_cec_adap: 3094 cec_delete_adapter(vc4_hdmi->cec_adap); 3095 3096 return ret; 3097 } 3098 #else 3099 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi) 3100 { 3101 return 0; 3102 } 3103 #endif 3104 3105 static void vc4_hdmi_free_regset(struct drm_device *drm, void *ptr) 3106 { 3107 struct debugfs_reg32 *regs = ptr; 3108 3109 kfree(regs); 3110 } 3111 3112 static int vc4_hdmi_build_regset(struct drm_device *drm, 3113 struct vc4_hdmi *vc4_hdmi, 3114 struct debugfs_regset32 *regset, 3115 enum vc4_hdmi_regs reg) 3116 { 3117 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant; 3118 struct debugfs_reg32 *regs, *new_regs; 3119 unsigned int count = 0; 3120 unsigned int i; 3121 int ret; 3122 3123 regs = kcalloc(variant->num_registers, sizeof(*regs), 3124 GFP_KERNEL); 3125 if (!regs) 3126 return -ENOMEM; 3127 3128 for (i = 0; i < variant->num_registers; i++) { 3129 const struct vc4_hdmi_register *field = &variant->registers[i]; 3130 3131 if (field->reg != reg) 3132 continue; 3133 3134 regs[count].name = field->name; 3135 regs[count].offset = field->offset; 3136 count++; 3137 } 3138 3139 new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL); 3140 if (!new_regs) 3141 return -ENOMEM; 3142 3143 regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg); 3144 regset->regs = new_regs; 3145 regset->nregs = count; 3146 3147 ret = drmm_add_action_or_reset(drm, vc4_hdmi_free_regset, new_regs); 3148 if (ret) 3149 return ret; 3150 3151 return 0; 3152 } 3153 3154 static int vc4_hdmi_init_resources(struct drm_device *drm, 3155 struct vc4_hdmi *vc4_hdmi) 3156 { 3157 struct platform_device *pdev = vc4_hdmi->pdev; 3158 struct device *dev = &pdev->dev; 3159 int ret; 3160 3161 vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0); 3162 if (IS_ERR(vc4_hdmi->hdmicore_regs)) 3163 return PTR_ERR(vc4_hdmi->hdmicore_regs); 3164 3165 vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1); 3166 if (IS_ERR(vc4_hdmi->hd_regs)) 3167 return PTR_ERR(vc4_hdmi->hd_regs); 3168 3169 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD); 3170 if (ret) 3171 return ret; 3172 3173 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI); 3174 if (ret) 3175 return ret; 3176 3177 vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel"); 3178 if (IS_ERR(vc4_hdmi->pixel_clock)) { 3179 ret = PTR_ERR(vc4_hdmi->pixel_clock); 3180 if (ret != -EPROBE_DEFER) 3181 DRM_ERROR("Failed to get pixel clock\n"); 3182 return ret; 3183 } 3184 3185 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); 3186 if (IS_ERR(vc4_hdmi->hsm_clock)) { 3187 DRM_ERROR("Failed to get HDMI state machine clock\n"); 3188 return PTR_ERR(vc4_hdmi->hsm_clock); 3189 } 3190 3191 vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock; 3192 vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock; 3193 3194 vc4_hdmi->hsm_rpm_clock = devm_clk_get(dev, "hdmi"); 3195 if (IS_ERR(vc4_hdmi->hsm_rpm_clock)) { 3196 DRM_ERROR("Failed to get HDMI state machine clock\n"); 3197 return PTR_ERR(vc4_hdmi->hsm_rpm_clock); 3198 } 3199 3200 return 0; 3201 } 3202 3203 static int vc5_hdmi_init_resources(struct drm_device *drm, 3204 struct vc4_hdmi *vc4_hdmi) 3205 { 3206 struct platform_device *pdev = vc4_hdmi->pdev; 3207 struct device *dev = &pdev->dev; 3208 struct resource *res; 3209 int ret; 3210 3211 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi"); 3212 if (!res) 3213 return -ENODEV; 3214 3215 vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start, 3216 resource_size(res)); 3217 if (!vc4_hdmi->hdmicore_regs) 3218 return -ENOMEM; 3219 3220 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd"); 3221 if (!res) 3222 return -ENODEV; 3223 3224 vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res)); 3225 if (!vc4_hdmi->hd_regs) 3226 return -ENOMEM; 3227 3228 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec"); 3229 if (!res) 3230 return -ENODEV; 3231 3232 vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res)); 3233 if (!vc4_hdmi->cec_regs) 3234 return -ENOMEM; 3235 3236 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc"); 3237 if (!res) 3238 return -ENODEV; 3239 3240 vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res)); 3241 if (!vc4_hdmi->csc_regs) 3242 return -ENOMEM; 3243 3244 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp"); 3245 if (!res) 3246 return -ENODEV; 3247 3248 vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res)); 3249 if (!vc4_hdmi->dvp_regs) 3250 return -ENOMEM; 3251 3252 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy"); 3253 if (!res) 3254 return -ENODEV; 3255 3256 vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res)); 3257 if (!vc4_hdmi->phy_regs) 3258 return -ENOMEM; 3259 3260 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet"); 3261 if (!res) 3262 return -ENODEV; 3263 3264 vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res)); 3265 if (!vc4_hdmi->ram_regs) 3266 return -ENOMEM; 3267 3268 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm"); 3269 if (!res) 3270 return -ENODEV; 3271 3272 vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res)); 3273 if (!vc4_hdmi->rm_regs) 3274 return -ENOMEM; 3275 3276 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); 3277 if (IS_ERR(vc4_hdmi->hsm_clock)) { 3278 DRM_ERROR("Failed to get HDMI state machine clock\n"); 3279 return PTR_ERR(vc4_hdmi->hsm_clock); 3280 } 3281 3282 vc4_hdmi->hsm_rpm_clock = devm_clk_get(dev, "hdmi"); 3283 if (IS_ERR(vc4_hdmi->hsm_rpm_clock)) { 3284 DRM_ERROR("Failed to get HDMI state machine clock\n"); 3285 return PTR_ERR(vc4_hdmi->hsm_rpm_clock); 3286 } 3287 3288 vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb"); 3289 if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) { 3290 DRM_ERROR("Failed to get pixel bvb clock\n"); 3291 return PTR_ERR(vc4_hdmi->pixel_bvb_clock); 3292 } 3293 3294 vc4_hdmi->audio_clock = devm_clk_get(dev, "audio"); 3295 if (IS_ERR(vc4_hdmi->audio_clock)) { 3296 DRM_ERROR("Failed to get audio clock\n"); 3297 return PTR_ERR(vc4_hdmi->audio_clock); 3298 } 3299 3300 vc4_hdmi->cec_clock = devm_clk_get(dev, "cec"); 3301 if (IS_ERR(vc4_hdmi->cec_clock)) { 3302 DRM_ERROR("Failed to get CEC clock\n"); 3303 return PTR_ERR(vc4_hdmi->cec_clock); 3304 } 3305 3306 vc4_hdmi->reset = devm_reset_control_get(dev, NULL); 3307 if (IS_ERR(vc4_hdmi->reset)) { 3308 DRM_ERROR("Failed to get HDMI reset line\n"); 3309 return PTR_ERR(vc4_hdmi->reset); 3310 } 3311 3312 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI); 3313 if (ret) 3314 return ret; 3315 3316 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD); 3317 if (ret) 3318 return ret; 3319 3320 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->cec_regset, VC5_CEC); 3321 if (ret) 3322 return ret; 3323 3324 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->csc_regset, VC5_CSC); 3325 if (ret) 3326 return ret; 3327 3328 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->dvp_regset, VC5_DVP); 3329 if (ret) 3330 return ret; 3331 3332 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->phy_regset, VC5_PHY); 3333 if (ret) 3334 return ret; 3335 3336 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->ram_regset, VC5_RAM); 3337 if (ret) 3338 return ret; 3339 3340 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->rm_regset, VC5_RM); 3341 if (ret) 3342 return ret; 3343 3344 return 0; 3345 } 3346 3347 static int vc4_hdmi_runtime_suspend(struct device *dev) 3348 { 3349 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 3350 3351 clk_disable_unprepare(vc4_hdmi->hsm_rpm_clock); 3352 3353 return 0; 3354 } 3355 3356 static int vc4_hdmi_runtime_resume(struct device *dev) 3357 { 3358 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 3359 unsigned long __maybe_unused flags; 3360 u32 __maybe_unused value; 3361 unsigned long rate; 3362 int ret; 3363 3364 /* 3365 * The HSM clock is in the HDMI power domain, so we need to set 3366 * its frequency while the power domain is active so that it 3367 * keeps its rate. 3368 */ 3369 ret = clk_set_min_rate(vc4_hdmi->hsm_rpm_clock, HSM_MIN_CLOCK_FREQ); 3370 if (ret) 3371 return ret; 3372 3373 ret = clk_prepare_enable(vc4_hdmi->hsm_rpm_clock); 3374 if (ret) 3375 return ret; 3376 3377 /* 3378 * Whenever the RaspberryPi boots without an HDMI monitor 3379 * plugged in, the firmware won't have initialized the HSM clock 3380 * rate and it will be reported as 0. 3381 * 3382 * If we try to access a register of the controller in such a 3383 * case, it will lead to a silent CPU stall. Let's make sure we 3384 * prevent such a case. 3385 */ 3386 rate = clk_get_rate(vc4_hdmi->hsm_rpm_clock); 3387 if (!rate) { 3388 ret = -EINVAL; 3389 goto err_disable_clk; 3390 } 3391 3392 if (vc4_hdmi->variant->reset) 3393 vc4_hdmi->variant->reset(vc4_hdmi); 3394 3395 #ifdef CONFIG_DRM_VC4_HDMI_CEC 3396 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 3397 value = HDMI_READ(HDMI_CEC_CNTRL_1); 3398 /* Set the logical address to Unregistered */ 3399 value |= VC4_HDMI_CEC_ADDR_MASK; 3400 HDMI_WRITE(HDMI_CEC_CNTRL_1, value); 3401 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 3402 3403 vc4_hdmi_cec_update_clk_div(vc4_hdmi); 3404 3405 if (!vc4_hdmi->variant->external_irq_controller) { 3406 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 3407 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff); 3408 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 3409 } 3410 #endif 3411 3412 return 0; 3413 3414 err_disable_clk: 3415 clk_disable_unprepare(vc4_hdmi->hsm_clock); 3416 return ret; 3417 } 3418 3419 static void vc4_hdmi_put_ddc_device(void *ptr) 3420 { 3421 struct vc4_hdmi *vc4_hdmi = ptr; 3422 3423 put_device(&vc4_hdmi->ddc->dev); 3424 } 3425 3426 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data) 3427 { 3428 const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev); 3429 struct platform_device *pdev = to_platform_device(dev); 3430 struct drm_device *drm = dev_get_drvdata(master); 3431 struct vc4_hdmi *vc4_hdmi; 3432 struct drm_encoder *encoder; 3433 struct device_node *ddc_node; 3434 int ret; 3435 3436 vc4_hdmi = drmm_kzalloc(drm, sizeof(*vc4_hdmi), GFP_KERNEL); 3437 if (!vc4_hdmi) 3438 return -ENOMEM; 3439 3440 ret = drmm_mutex_init(drm, &vc4_hdmi->mutex); 3441 if (ret) 3442 return ret; 3443 3444 spin_lock_init(&vc4_hdmi->hw_lock); 3445 INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq); 3446 3447 dev_set_drvdata(dev, vc4_hdmi); 3448 encoder = &vc4_hdmi->encoder.base; 3449 vc4_hdmi->encoder.type = variant->encoder_type; 3450 vc4_hdmi->encoder.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure; 3451 vc4_hdmi->encoder.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable; 3452 vc4_hdmi->encoder.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable; 3453 vc4_hdmi->encoder.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable; 3454 vc4_hdmi->encoder.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown; 3455 vc4_hdmi->pdev = pdev; 3456 vc4_hdmi->variant = variant; 3457 3458 /* 3459 * Since we don't know the state of the controller and its 3460 * display (if any), let's assume it's always enabled. 3461 * vc4_hdmi_disable_scrambling() will thus run at boot, make 3462 * sure it's disabled, and avoid any inconsistency. 3463 */ 3464 if (variant->max_pixel_clock > HDMI_14_MAX_TMDS_CLK) 3465 vc4_hdmi->scdc_enabled = true; 3466 3467 ret = variant->init_resources(drm, vc4_hdmi); 3468 if (ret) 3469 return ret; 3470 3471 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0); 3472 if (!ddc_node) { 3473 DRM_ERROR("Failed to find ddc node in device tree\n"); 3474 return -ENODEV; 3475 } 3476 3477 vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node); 3478 of_node_put(ddc_node); 3479 if (!vc4_hdmi->ddc) { 3480 DRM_DEBUG("Failed to get ddc i2c adapter by node\n"); 3481 return -EPROBE_DEFER; 3482 } 3483 3484 ret = devm_add_action_or_reset(dev, vc4_hdmi_put_ddc_device, vc4_hdmi); 3485 if (ret) 3486 return ret; 3487 3488 /* Only use the GPIO HPD pin if present in the DT, otherwise 3489 * we'll use the HDMI core's register. 3490 */ 3491 vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN); 3492 if (IS_ERR(vc4_hdmi->hpd_gpio)) { 3493 return PTR_ERR(vc4_hdmi->hpd_gpio); 3494 } 3495 3496 vc4_hdmi->disable_wifi_frequencies = 3497 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence"); 3498 3499 ret = devm_pm_runtime_enable(dev); 3500 if (ret) 3501 return ret; 3502 3503 /* 3504 * We need to have the device powered up at this point to call 3505 * our reset hook and for the CEC init. 3506 */ 3507 ret = pm_runtime_resume_and_get(dev); 3508 if (ret) 3509 return ret; 3510 3511 if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") || 3512 of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1")) && 3513 HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) { 3514 clk_prepare_enable(vc4_hdmi->pixel_clock); 3515 clk_prepare_enable(vc4_hdmi->hsm_clock); 3516 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock); 3517 } 3518 3519 ret = drmm_encoder_init(drm, encoder, 3520 &vc4_hdmi_encoder_funcs, 3521 DRM_MODE_ENCODER_TMDS, 3522 NULL); 3523 if (ret) 3524 goto err_put_runtime_pm; 3525 3526 drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs); 3527 3528 ret = vc4_hdmi_connector_init(drm, vc4_hdmi); 3529 if (ret) 3530 goto err_put_runtime_pm; 3531 3532 ret = vc4_hdmi_hotplug_init(vc4_hdmi); 3533 if (ret) 3534 goto err_put_runtime_pm; 3535 3536 ret = vc4_hdmi_cec_init(vc4_hdmi); 3537 if (ret) 3538 goto err_put_runtime_pm; 3539 3540 ret = vc4_hdmi_audio_init(vc4_hdmi); 3541 if (ret) 3542 goto err_put_runtime_pm; 3543 3544 pm_runtime_put_sync(dev); 3545 3546 return 0; 3547 3548 err_put_runtime_pm: 3549 pm_runtime_put_sync(dev); 3550 3551 return ret; 3552 } 3553 3554 static const struct component_ops vc4_hdmi_ops = { 3555 .bind = vc4_hdmi_bind, 3556 }; 3557 3558 static int vc4_hdmi_dev_probe(struct platform_device *pdev) 3559 { 3560 return component_add(&pdev->dev, &vc4_hdmi_ops); 3561 } 3562 3563 static int vc4_hdmi_dev_remove(struct platform_device *pdev) 3564 { 3565 component_del(&pdev->dev, &vc4_hdmi_ops); 3566 return 0; 3567 } 3568 3569 static const struct vc4_hdmi_variant bcm2835_variant = { 3570 .encoder_type = VC4_ENCODER_TYPE_HDMI0, 3571 .debugfs_name = "hdmi_regs", 3572 .card_name = "vc4-hdmi", 3573 .max_pixel_clock = 162000000, 3574 .registers = vc4_hdmi_fields, 3575 .num_registers = ARRAY_SIZE(vc4_hdmi_fields), 3576 3577 .init_resources = vc4_hdmi_init_resources, 3578 .csc_setup = vc4_hdmi_csc_setup, 3579 .reset = vc4_hdmi_reset, 3580 .set_timings = vc4_hdmi_set_timings, 3581 .phy_init = vc4_hdmi_phy_init, 3582 .phy_disable = vc4_hdmi_phy_disable, 3583 .phy_rng_enable = vc4_hdmi_phy_rng_enable, 3584 .phy_rng_disable = vc4_hdmi_phy_rng_disable, 3585 .channel_map = vc4_hdmi_channel_map, 3586 .supports_hdr = false, 3587 }; 3588 3589 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = { 3590 .encoder_type = VC4_ENCODER_TYPE_HDMI0, 3591 .debugfs_name = "hdmi0_regs", 3592 .card_name = "vc4-hdmi-0", 3593 .max_pixel_clock = 600000000, 3594 .registers = vc5_hdmi_hdmi0_fields, 3595 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi0_fields), 3596 .phy_lane_mapping = { 3597 PHY_LANE_0, 3598 PHY_LANE_1, 3599 PHY_LANE_2, 3600 PHY_LANE_CK, 3601 }, 3602 .unsupported_odd_h_timings = true, 3603 .external_irq_controller = true, 3604 3605 .init_resources = vc5_hdmi_init_resources, 3606 .csc_setup = vc5_hdmi_csc_setup, 3607 .reset = vc5_hdmi_reset, 3608 .set_timings = vc5_hdmi_set_timings, 3609 .phy_init = vc5_hdmi_phy_init, 3610 .phy_disable = vc5_hdmi_phy_disable, 3611 .phy_rng_enable = vc5_hdmi_phy_rng_enable, 3612 .phy_rng_disable = vc5_hdmi_phy_rng_disable, 3613 .channel_map = vc5_hdmi_channel_map, 3614 .supports_hdr = true, 3615 .hp_detect = vc5_hdmi_hp_detect, 3616 }; 3617 3618 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = { 3619 .encoder_type = VC4_ENCODER_TYPE_HDMI1, 3620 .debugfs_name = "hdmi1_regs", 3621 .card_name = "vc4-hdmi-1", 3622 .max_pixel_clock = HDMI_14_MAX_TMDS_CLK, 3623 .registers = vc5_hdmi_hdmi1_fields, 3624 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi1_fields), 3625 .phy_lane_mapping = { 3626 PHY_LANE_1, 3627 PHY_LANE_0, 3628 PHY_LANE_CK, 3629 PHY_LANE_2, 3630 }, 3631 .unsupported_odd_h_timings = true, 3632 .external_irq_controller = true, 3633 3634 .init_resources = vc5_hdmi_init_resources, 3635 .csc_setup = vc5_hdmi_csc_setup, 3636 .reset = vc5_hdmi_reset, 3637 .set_timings = vc5_hdmi_set_timings, 3638 .phy_init = vc5_hdmi_phy_init, 3639 .phy_disable = vc5_hdmi_phy_disable, 3640 .phy_rng_enable = vc5_hdmi_phy_rng_enable, 3641 .phy_rng_disable = vc5_hdmi_phy_rng_disable, 3642 .channel_map = vc5_hdmi_channel_map, 3643 .supports_hdr = true, 3644 .hp_detect = vc5_hdmi_hp_detect, 3645 }; 3646 3647 static const struct of_device_id vc4_hdmi_dt_match[] = { 3648 { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant }, 3649 { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant }, 3650 { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant }, 3651 {} 3652 }; 3653 3654 static const struct dev_pm_ops vc4_hdmi_pm_ops = { 3655 SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend, 3656 vc4_hdmi_runtime_resume, 3657 NULL) 3658 }; 3659 3660 struct platform_driver vc4_hdmi_driver = { 3661 .probe = vc4_hdmi_dev_probe, 3662 .remove = vc4_hdmi_dev_remove, 3663 .driver = { 3664 .name = "vc4_hdmi", 3665 .of_match_table = vc4_hdmi_dt_match, 3666 .pm = &vc4_hdmi_pm_ops, 3667 }, 3668 }; 3669