1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 Broadcom 4 * Copyright (c) 2014 The Linux Foundation. All rights reserved. 5 * Copyright (C) 2013 Red Hat 6 * Author: Rob Clark <robdclark@gmail.com> 7 */ 8 9 /** 10 * DOC: VC4 Falcon HDMI module 11 * 12 * The HDMI core has a state machine and a PHY. On BCM2835, most of 13 * the unit operates off of the HSM clock from CPRMAN. It also 14 * internally uses the PLLH_PIX clock for the PHY. 15 * 16 * HDMI infoframes are kept within a small packet ram, where each 17 * packet can be individually enabled for including in a frame. 18 * 19 * HDMI audio is implemented entirely within the HDMI IP block. A 20 * register in the HDMI encoder takes SPDIF frames from the DMA engine 21 * and transfers them over an internal MAI (multi-channel audio 22 * interconnect) bus to the encoder side for insertion into the video 23 * blank regions. 24 * 25 * The driver's HDMI encoder does not yet support power management. 26 * The HDMI encoder's power domain and the HSM/pixel clocks are kept 27 * continuously running, and only the HDMI logic and packet ram are 28 * powered off/on at disable/enable time. 29 * 30 * The driver does not yet support CEC control, though the HDMI 31 * encoder block has CEC support. 32 */ 33 34 #include <drm/drm_atomic_helper.h> 35 #include <drm/drm_edid.h> 36 #include <drm/drm_probe_helper.h> 37 #include <drm/drm_simple_kms_helper.h> 38 #include <linux/clk.h> 39 #include <linux/component.h> 40 #include <linux/i2c.h> 41 #include <linux/of_address.h> 42 #include <linux/of_gpio.h> 43 #include <linux/of_platform.h> 44 #include <linux/pm_runtime.h> 45 #include <linux/rational.h> 46 #include <linux/reset.h> 47 #include <sound/dmaengine_pcm.h> 48 #include <sound/pcm_drm_eld.h> 49 #include <sound/pcm_params.h> 50 #include <sound/soc.h> 51 #include "media/cec.h" 52 #include "vc4_drv.h" 53 #include "vc4_hdmi.h" 54 #include "vc4_hdmi_regs.h" 55 #include "vc4_regs.h" 56 57 #define VC5_HDMI_HORZA_HFP_SHIFT 16 58 #define VC5_HDMI_HORZA_HFP_MASK VC4_MASK(28, 16) 59 #define VC5_HDMI_HORZA_VPOS BIT(15) 60 #define VC5_HDMI_HORZA_HPOS BIT(14) 61 #define VC5_HDMI_HORZA_HAP_SHIFT 0 62 #define VC5_HDMI_HORZA_HAP_MASK VC4_MASK(13, 0) 63 64 #define VC5_HDMI_HORZB_HBP_SHIFT 16 65 #define VC5_HDMI_HORZB_HBP_MASK VC4_MASK(26, 16) 66 #define VC5_HDMI_HORZB_HSP_SHIFT 0 67 #define VC5_HDMI_HORZB_HSP_MASK VC4_MASK(10, 0) 68 69 #define VC5_HDMI_VERTA_VSP_SHIFT 24 70 #define VC5_HDMI_VERTA_VSP_MASK VC4_MASK(28, 24) 71 #define VC5_HDMI_VERTA_VFP_SHIFT 16 72 #define VC5_HDMI_VERTA_VFP_MASK VC4_MASK(22, 16) 73 #define VC5_HDMI_VERTA_VAL_SHIFT 0 74 #define VC5_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0) 75 76 #define VC5_HDMI_VERTB_VSPO_SHIFT 16 77 #define VC5_HDMI_VERTB_VSPO_MASK VC4_MASK(29, 16) 78 79 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT 8 80 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK VC4_MASK(10, 8) 81 82 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT 0 83 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK VC4_MASK(3, 0) 84 85 #define VC5_HDMI_GCP_CONFIG_GCP_ENABLE BIT(31) 86 87 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT 8 88 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK VC4_MASK(15, 8) 89 90 # define VC4_HD_M_SW_RST BIT(2) 91 # define VC4_HD_M_ENABLE BIT(0) 92 93 #define CEC_CLOCK_FREQ 40000 94 #define VC4_HSM_MID_CLOCK 149985000 95 96 #define HDMI_14_MAX_TMDS_CLK (340 * 1000 * 1000) 97 98 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused) 99 { 100 struct drm_info_node *node = (struct drm_info_node *)m->private; 101 struct vc4_hdmi *vc4_hdmi = node->info_ent->data; 102 struct drm_printer p = drm_seq_file_printer(m); 103 104 drm_print_regset32(&p, &vc4_hdmi->hdmi_regset); 105 drm_print_regset32(&p, &vc4_hdmi->hd_regset); 106 107 return 0; 108 } 109 110 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi) 111 { 112 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST); 113 udelay(1); 114 HDMI_WRITE(HDMI_M_CTL, 0); 115 116 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE); 117 118 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 119 VC4_HDMI_SW_RESET_HDMI | 120 VC4_HDMI_SW_RESET_FORMAT_DETECT); 121 122 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0); 123 } 124 125 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi) 126 { 127 reset_control_reset(vc4_hdmi->reset); 128 129 HDMI_WRITE(HDMI_DVP_CTL, 0); 130 131 HDMI_WRITE(HDMI_CLOCK_STOP, 132 HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL); 133 } 134 135 static enum drm_connector_status 136 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force) 137 { 138 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 139 140 if (vc4_hdmi->hpd_gpio) { 141 if (gpio_get_value_cansleep(vc4_hdmi->hpd_gpio) ^ 142 vc4_hdmi->hpd_active_low) 143 return connector_status_connected; 144 cec_phys_addr_invalidate(vc4_hdmi->cec_adap); 145 return connector_status_disconnected; 146 } 147 148 if (drm_probe_ddc(vc4_hdmi->ddc)) 149 return connector_status_connected; 150 151 if (HDMI_READ(HDMI_HOTPLUG) & VC4_HDMI_HOTPLUG_CONNECTED) 152 return connector_status_connected; 153 cec_phys_addr_invalidate(vc4_hdmi->cec_adap); 154 return connector_status_disconnected; 155 } 156 157 static void vc4_hdmi_connector_destroy(struct drm_connector *connector) 158 { 159 drm_connector_unregister(connector); 160 drm_connector_cleanup(connector); 161 } 162 163 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector) 164 { 165 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 166 struct vc4_hdmi_encoder *vc4_encoder = &vc4_hdmi->encoder; 167 int ret = 0; 168 struct edid *edid; 169 170 edid = drm_get_edid(connector, vc4_hdmi->ddc); 171 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid); 172 if (!edid) 173 return -ENODEV; 174 175 vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid); 176 177 drm_connector_update_edid_property(connector, edid); 178 ret = drm_add_edid_modes(connector, edid); 179 kfree(edid); 180 181 return ret; 182 } 183 184 static void vc4_hdmi_connector_reset(struct drm_connector *connector) 185 { 186 struct vc4_hdmi_connector_state *old_state = 187 conn_state_to_vc4_hdmi_conn_state(connector->state); 188 struct vc4_hdmi_connector_state *new_state = 189 kzalloc(sizeof(*new_state), GFP_KERNEL); 190 191 if (connector->state) 192 __drm_atomic_helper_connector_destroy_state(connector->state); 193 194 kfree(old_state); 195 __drm_atomic_helper_connector_reset(connector, &new_state->base); 196 197 if (!new_state) 198 return; 199 200 new_state->base.max_bpc = 8; 201 new_state->base.max_requested_bpc = 8; 202 drm_atomic_helper_connector_tv_reset(connector); 203 } 204 205 static struct drm_connector_state * 206 vc4_hdmi_connector_duplicate_state(struct drm_connector *connector) 207 { 208 struct drm_connector_state *conn_state = connector->state; 209 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state); 210 struct vc4_hdmi_connector_state *new_state; 211 212 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL); 213 if (!new_state) 214 return NULL; 215 216 new_state->pixel_rate = vc4_state->pixel_rate; 217 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base); 218 219 return &new_state->base; 220 } 221 222 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = { 223 .detect = vc4_hdmi_connector_detect, 224 .fill_modes = drm_helper_probe_single_connector_modes, 225 .destroy = vc4_hdmi_connector_destroy, 226 .reset = vc4_hdmi_connector_reset, 227 .atomic_duplicate_state = vc4_hdmi_connector_duplicate_state, 228 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 229 }; 230 231 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = { 232 .get_modes = vc4_hdmi_connector_get_modes, 233 }; 234 235 static int vc4_hdmi_connector_init(struct drm_device *dev, 236 struct vc4_hdmi *vc4_hdmi) 237 { 238 struct drm_connector *connector = &vc4_hdmi->connector; 239 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base; 240 int ret; 241 242 drm_connector_init_with_ddc(dev, connector, 243 &vc4_hdmi_connector_funcs, 244 DRM_MODE_CONNECTOR_HDMIA, 245 vc4_hdmi->ddc); 246 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs); 247 248 /* 249 * Some of the properties below require access to state, like bpc. 250 * Allocate some default initial connector state with our reset helper. 251 */ 252 if (connector->funcs->reset) 253 connector->funcs->reset(connector); 254 255 /* Create and attach TV margin props to this connector. */ 256 ret = drm_mode_create_tv_margin_properties(dev); 257 if (ret) 258 return ret; 259 260 drm_connector_attach_tv_margin_properties(connector); 261 drm_connector_attach_max_bpc_property(connector, 8, 12); 262 263 connector->polled = (DRM_CONNECTOR_POLL_CONNECT | 264 DRM_CONNECTOR_POLL_DISCONNECT); 265 266 connector->interlace_allowed = 1; 267 connector->doublescan_allowed = 0; 268 269 drm_connector_attach_encoder(connector, encoder); 270 271 return 0; 272 } 273 274 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder, 275 enum hdmi_infoframe_type type, 276 bool poll) 277 { 278 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 279 u32 packet_id = type - 0x80; 280 281 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 282 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id)); 283 284 if (!poll) 285 return 0; 286 287 return wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) & 288 BIT(packet_id)), 100); 289 } 290 291 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder, 292 union hdmi_infoframe *frame) 293 { 294 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 295 u32 packet_id = frame->any.type - 0x80; 296 const struct vc4_hdmi_register *ram_packet_start = 297 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START]; 298 u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id; 299 void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi, 300 ram_packet_start->reg); 301 uint8_t buffer[VC4_HDMI_PACKET_STRIDE]; 302 ssize_t len, i; 303 int ret; 304 305 WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) & 306 VC4_HDMI_RAM_PACKET_ENABLE), 307 "Packet RAM has to be on to store the packet."); 308 309 len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer)); 310 if (len < 0) 311 return; 312 313 ret = vc4_hdmi_stop_packet(encoder, frame->any.type, true); 314 if (ret) { 315 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret); 316 return; 317 } 318 319 for (i = 0; i < len; i += 7) { 320 writel(buffer[i + 0] << 0 | 321 buffer[i + 1] << 8 | 322 buffer[i + 2] << 16, 323 base + packet_reg); 324 packet_reg += 4; 325 326 writel(buffer[i + 3] << 0 | 327 buffer[i + 4] << 8 | 328 buffer[i + 5] << 16 | 329 buffer[i + 6] << 24, 330 base + packet_reg); 331 packet_reg += 4; 332 } 333 334 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 335 HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id)); 336 ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) & 337 BIT(packet_id)), 100); 338 if (ret) 339 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret); 340 } 341 342 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder) 343 { 344 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 345 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 346 struct drm_connector *connector = &vc4_hdmi->connector; 347 struct drm_connector_state *cstate = connector->state; 348 struct drm_crtc *crtc = encoder->crtc; 349 const struct drm_display_mode *mode = &crtc->state->adjusted_mode; 350 union hdmi_infoframe frame; 351 int ret; 352 353 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, 354 connector, mode); 355 if (ret < 0) { 356 DRM_ERROR("couldn't fill AVI infoframe\n"); 357 return; 358 } 359 360 drm_hdmi_avi_infoframe_quant_range(&frame.avi, 361 connector, mode, 362 vc4_encoder->limited_rgb_range ? 363 HDMI_QUANTIZATION_RANGE_LIMITED : 364 HDMI_QUANTIZATION_RANGE_FULL); 365 366 drm_hdmi_avi_infoframe_bars(&frame.avi, cstate); 367 368 vc4_hdmi_write_infoframe(encoder, &frame); 369 } 370 371 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder) 372 { 373 union hdmi_infoframe frame; 374 int ret; 375 376 ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore"); 377 if (ret < 0) { 378 DRM_ERROR("couldn't fill SPD infoframe\n"); 379 return; 380 } 381 382 frame.spd.sdi = HDMI_SPD_SDI_PC; 383 384 vc4_hdmi_write_infoframe(encoder, &frame); 385 } 386 387 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder) 388 { 389 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 390 union hdmi_infoframe frame; 391 392 hdmi_audio_infoframe_init(&frame.audio); 393 394 frame.audio.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM; 395 frame.audio.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM; 396 frame.audio.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM; 397 frame.audio.channels = vc4_hdmi->audio.channels; 398 399 vc4_hdmi_write_infoframe(encoder, &frame); 400 } 401 402 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder) 403 { 404 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 405 406 vc4_hdmi_set_avi_infoframe(encoder); 407 vc4_hdmi_set_spd_infoframe(encoder); 408 /* 409 * If audio was streaming, then we need to reenabled the audio 410 * infoframe here during encoder_enable. 411 */ 412 if (vc4_hdmi->audio.streaming) 413 vc4_hdmi_set_audio_infoframe(encoder); 414 } 415 416 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder, 417 struct drm_atomic_state *state) 418 { 419 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 420 421 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0); 422 423 HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | 424 VC4_HD_VID_CTL_CLRRGB | VC4_HD_VID_CTL_CLRSYNC); 425 426 HDMI_WRITE(HDMI_VID_CTL, 427 HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX); 428 } 429 430 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder, 431 struct drm_atomic_state *state) 432 { 433 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 434 int ret; 435 436 if (vc4_hdmi->variant->phy_disable) 437 vc4_hdmi->variant->phy_disable(vc4_hdmi); 438 439 HDMI_WRITE(HDMI_VID_CTL, 440 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE); 441 442 clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock); 443 clk_disable_unprepare(vc4_hdmi->hsm_clock); 444 clk_disable_unprepare(vc4_hdmi->pixel_clock); 445 446 ret = pm_runtime_put(&vc4_hdmi->pdev->dev); 447 if (ret < 0) 448 DRM_ERROR("Failed to release power domain: %d\n", ret); 449 } 450 451 static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder) 452 { 453 } 454 455 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable) 456 { 457 u32 csc_ctl; 458 459 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR, 460 VC4_HD_CSC_CTL_ORDER); 461 462 if (enable) { 463 /* CEA VICs other than #1 requre limited range RGB 464 * output unless overridden by an AVI infoframe. 465 * Apply a colorspace conversion to squash 0-255 down 466 * to 16-235. The matrix here is: 467 * 468 * [ 0 0 0.8594 16] 469 * [ 0 0.8594 0 16] 470 * [ 0.8594 0 0 16] 471 * [ 0 0 0 1] 472 */ 473 csc_ctl |= VC4_HD_CSC_CTL_ENABLE; 474 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC; 475 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM, 476 VC4_HD_CSC_CTL_MODE); 477 478 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000); 479 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0); 480 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000); 481 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000); 482 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0); 483 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000); 484 } 485 486 /* The RGB order applies even when CSC is disabled. */ 487 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl); 488 } 489 490 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable) 491 { 492 u32 csc_ctl; 493 494 csc_ctl = 0x07; /* RGB_CONVERT_MODE = custom matrix, || USE_RGB_TO_YCBCR */ 495 496 if (enable) { 497 /* CEA VICs other than #1 requre limited range RGB 498 * output unless overridden by an AVI infoframe. 499 * Apply a colorspace conversion to squash 0-255 down 500 * to 16-235. The matrix here is: 501 * 502 * [ 0.8594 0 0 16] 503 * [ 0 0.8594 0 16] 504 * [ 0 0 0.8594 16] 505 * [ 0 0 0 1] 506 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets 507 */ 508 HDMI_WRITE(HDMI_CSC_12_11, (0x0000 << 16) | 0x1b80); 509 HDMI_WRITE(HDMI_CSC_14_13, (0x0400 << 16) | 0x0000); 510 HDMI_WRITE(HDMI_CSC_22_21, (0x1b80 << 16) | 0x0000); 511 HDMI_WRITE(HDMI_CSC_24_23, (0x0400 << 16) | 0x0000); 512 HDMI_WRITE(HDMI_CSC_32_31, (0x0000 << 16) | 0x0000); 513 HDMI_WRITE(HDMI_CSC_34_33, (0x0400 << 16) | 0x1b80); 514 } else { 515 /* Still use the matrix for full range, but make it unity. 516 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets 517 */ 518 HDMI_WRITE(HDMI_CSC_12_11, (0x0000 << 16) | 0x2000); 519 HDMI_WRITE(HDMI_CSC_14_13, (0x0000 << 16) | 0x0000); 520 HDMI_WRITE(HDMI_CSC_22_21, (0x2000 << 16) | 0x0000); 521 HDMI_WRITE(HDMI_CSC_24_23, (0x0000 << 16) | 0x0000); 522 HDMI_WRITE(HDMI_CSC_32_31, (0x0000 << 16) | 0x0000); 523 HDMI_WRITE(HDMI_CSC_34_33, (0x0000 << 16) | 0x2000); 524 } 525 526 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl); 527 } 528 529 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi, 530 struct drm_connector_state *state, 531 struct drm_display_mode *mode) 532 { 533 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 534 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 535 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 536 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 537 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 538 VC4_HDMI_VERTA_VSP) | 539 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 540 VC4_HDMI_VERTA_VFP) | 541 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL)); 542 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 543 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end, 544 VC4_HDMI_VERTB_VBP)); 545 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 546 VC4_SET_FIELD(mode->crtc_vtotal - 547 mode->crtc_vsync_end - 548 interlaced, 549 VC4_HDMI_VERTB_VBP)); 550 551 HDMI_WRITE(HDMI_HORZA, 552 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) | 553 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) | 554 VC4_SET_FIELD(mode->hdisplay * pixel_rep, 555 VC4_HDMI_HORZA_HAP)); 556 557 HDMI_WRITE(HDMI_HORZB, 558 VC4_SET_FIELD((mode->htotal - 559 mode->hsync_end) * pixel_rep, 560 VC4_HDMI_HORZB_HBP) | 561 VC4_SET_FIELD((mode->hsync_end - 562 mode->hsync_start) * pixel_rep, 563 VC4_HDMI_HORZB_HSP) | 564 VC4_SET_FIELD((mode->hsync_start - 565 mode->hdisplay) * pixel_rep, 566 VC4_HDMI_HORZB_HFP)); 567 568 HDMI_WRITE(HDMI_VERTA0, verta); 569 HDMI_WRITE(HDMI_VERTA1, verta); 570 571 HDMI_WRITE(HDMI_VERTB0, vertb_even); 572 HDMI_WRITE(HDMI_VERTB1, vertb); 573 } 574 575 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi, 576 struct drm_connector_state *state, 577 struct drm_display_mode *mode) 578 { 579 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 580 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 581 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 582 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 583 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 584 VC5_HDMI_VERTA_VSP) | 585 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 586 VC5_HDMI_VERTA_VFP) | 587 VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL)); 588 u32 vertb = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) | 589 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end, 590 VC4_HDMI_VERTB_VBP)); 591 u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) | 592 VC4_SET_FIELD(mode->crtc_vtotal - 593 mode->crtc_vsync_end - 594 interlaced, 595 VC4_HDMI_VERTB_VBP)); 596 unsigned char gcp; 597 bool gcp_en; 598 u32 reg; 599 600 HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, 0x354021); 601 HDMI_WRITE(HDMI_HORZA, 602 (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) | 603 (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) | 604 VC4_SET_FIELD(mode->hdisplay * pixel_rep, 605 VC5_HDMI_HORZA_HAP) | 606 VC4_SET_FIELD((mode->hsync_start - 607 mode->hdisplay) * pixel_rep, 608 VC5_HDMI_HORZA_HFP)); 609 610 HDMI_WRITE(HDMI_HORZB, 611 VC4_SET_FIELD((mode->htotal - 612 mode->hsync_end) * pixel_rep, 613 VC5_HDMI_HORZB_HBP) | 614 VC4_SET_FIELD((mode->hsync_end - 615 mode->hsync_start) * pixel_rep, 616 VC5_HDMI_HORZB_HSP)); 617 618 HDMI_WRITE(HDMI_VERTA0, verta); 619 HDMI_WRITE(HDMI_VERTA1, verta); 620 621 HDMI_WRITE(HDMI_VERTB0, vertb_even); 622 HDMI_WRITE(HDMI_VERTB1, vertb); 623 624 switch (state->max_bpc) { 625 case 12: 626 gcp = 6; 627 gcp_en = true; 628 break; 629 case 10: 630 gcp = 5; 631 gcp_en = true; 632 break; 633 case 8: 634 default: 635 gcp = 4; 636 gcp_en = false; 637 break; 638 } 639 640 reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1); 641 reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK | 642 VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK); 643 reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) | 644 VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH); 645 HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg); 646 647 reg = HDMI_READ(HDMI_GCP_WORD_1); 648 reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK; 649 reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1); 650 HDMI_WRITE(HDMI_GCP_WORD_1, reg); 651 652 reg = HDMI_READ(HDMI_GCP_CONFIG); 653 reg &= ~VC5_HDMI_GCP_CONFIG_GCP_ENABLE; 654 reg |= gcp_en ? VC5_HDMI_GCP_CONFIG_GCP_ENABLE : 0; 655 HDMI_WRITE(HDMI_GCP_CONFIG, reg); 656 657 HDMI_WRITE(HDMI_CLOCK_STOP, 0); 658 } 659 660 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi) 661 { 662 u32 drift; 663 int ret; 664 665 drift = HDMI_READ(HDMI_FIFO_CTL); 666 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK; 667 668 HDMI_WRITE(HDMI_FIFO_CTL, 669 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 670 HDMI_WRITE(HDMI_FIFO_CTL, 671 drift | VC4_HDMI_FIFO_CTL_RECENTER); 672 usleep_range(1000, 1100); 673 HDMI_WRITE(HDMI_FIFO_CTL, 674 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 675 HDMI_WRITE(HDMI_FIFO_CTL, 676 drift | VC4_HDMI_FIFO_CTL_RECENTER); 677 678 ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) & 679 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1); 680 WARN_ONCE(ret, "Timeout waiting for " 681 "VC4_HDMI_FIFO_CTL_RECENTER_DONE"); 682 } 683 684 static struct drm_connector_state * 685 vc4_hdmi_encoder_get_connector_state(struct drm_encoder *encoder, 686 struct drm_atomic_state *state) 687 { 688 struct drm_connector_state *conn_state; 689 struct drm_connector *connector; 690 unsigned int i; 691 692 for_each_new_connector_in_state(state, connector, conn_state, i) { 693 if (conn_state->best_encoder == encoder) 694 return conn_state; 695 } 696 697 return NULL; 698 } 699 700 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder, 701 struct drm_atomic_state *state) 702 { 703 struct drm_connector_state *conn_state = 704 vc4_hdmi_encoder_get_connector_state(encoder, state); 705 struct vc4_hdmi_connector_state *vc4_conn_state = 706 conn_state_to_vc4_hdmi_conn_state(conn_state); 707 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; 708 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 709 unsigned long pixel_rate, hsm_rate; 710 int ret; 711 712 ret = pm_runtime_get_sync(&vc4_hdmi->pdev->dev); 713 if (ret < 0) { 714 DRM_ERROR("Failed to retain power domain: %d\n", ret); 715 return; 716 } 717 718 pixel_rate = vc4_conn_state->pixel_rate; 719 ret = clk_set_rate(vc4_hdmi->pixel_clock, pixel_rate); 720 if (ret) { 721 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret); 722 return; 723 } 724 725 ret = clk_prepare_enable(vc4_hdmi->pixel_clock); 726 if (ret) { 727 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret); 728 return; 729 } 730 731 /* 732 * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must 733 * be faster than pixel clock, infinitesimally faster, tested in 734 * simulation. Otherwise, exact value is unimportant for HDMI 735 * operation." This conflicts with bcm2835's vc4 documentation, which 736 * states HSM's clock has to be at least 108% of the pixel clock. 737 * 738 * Real life tests reveal that vc4's firmware statement holds up, and 739 * users are able to use pixel clocks closer to HSM's, namely for 740 * 1920x1200@60Hz. So it was decided to have leave a 1% margin between 741 * both clocks. Which, for RPi0-3 implies a maximum pixel clock of 742 * 162MHz. 743 * 744 * Additionally, the AXI clock needs to be at least 25% of 745 * pixel clock, but HSM ends up being the limiting factor. 746 */ 747 hsm_rate = max_t(unsigned long, 120000000, (pixel_rate / 100) * 101); 748 ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate); 749 if (ret) { 750 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret); 751 return; 752 } 753 754 ret = clk_prepare_enable(vc4_hdmi->hsm_clock); 755 if (ret) { 756 DRM_ERROR("Failed to turn on HSM clock: %d\n", ret); 757 clk_disable_unprepare(vc4_hdmi->pixel_clock); 758 return; 759 } 760 761 /* 762 * FIXME: When the pixel freq is 594MHz (4k60), this needs to be setup 763 * at 300MHz. 764 */ 765 ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, 766 (hsm_rate > VC4_HSM_MID_CLOCK ? 150000000 : 75000000)); 767 if (ret) { 768 DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret); 769 clk_disable_unprepare(vc4_hdmi->hsm_clock); 770 clk_disable_unprepare(vc4_hdmi->pixel_clock); 771 return; 772 } 773 774 ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock); 775 if (ret) { 776 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret); 777 clk_disable_unprepare(vc4_hdmi->hsm_clock); 778 clk_disable_unprepare(vc4_hdmi->pixel_clock); 779 return; 780 } 781 782 if (vc4_hdmi->variant->reset) 783 vc4_hdmi->variant->reset(vc4_hdmi); 784 785 if (vc4_hdmi->variant->phy_init) 786 vc4_hdmi->variant->phy_init(vc4_hdmi, vc4_conn_state); 787 788 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 789 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 790 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT | 791 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS); 792 793 if (vc4_hdmi->variant->set_timings) 794 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode); 795 } 796 797 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder, 798 struct drm_atomic_state *state) 799 { 800 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; 801 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 802 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 803 804 if (vc4_encoder->hdmi_monitor && 805 drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_LIMITED) { 806 if (vc4_hdmi->variant->csc_setup) 807 vc4_hdmi->variant->csc_setup(vc4_hdmi, true); 808 809 vc4_encoder->limited_rgb_range = true; 810 } else { 811 if (vc4_hdmi->variant->csc_setup) 812 vc4_hdmi->variant->csc_setup(vc4_hdmi, false); 813 814 vc4_encoder->limited_rgb_range = false; 815 } 816 817 HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N); 818 } 819 820 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder, 821 struct drm_atomic_state *state) 822 { 823 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; 824 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 825 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 826 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 827 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 828 int ret; 829 830 HDMI_WRITE(HDMI_VID_CTL, 831 VC4_HD_VID_CTL_ENABLE | 832 VC4_HD_VID_CTL_UNDERFLOW_ENABLE | 833 VC4_HD_VID_CTL_FRAME_COUNTER_RESET | 834 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) | 835 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW)); 836 837 HDMI_WRITE(HDMI_VID_CTL, 838 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX); 839 840 if (vc4_encoder->hdmi_monitor) { 841 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 842 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 843 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 844 845 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 846 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000); 847 WARN_ONCE(ret, "Timeout waiting for " 848 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 849 } else { 850 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 851 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & 852 ~(VC4_HDMI_RAM_PACKET_ENABLE)); 853 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 854 HDMI_READ(HDMI_SCHEDULER_CONTROL) & 855 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 856 857 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 858 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000); 859 WARN_ONCE(ret, "Timeout waiting for " 860 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 861 } 862 863 if (vc4_encoder->hdmi_monitor) { 864 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 865 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE)); 866 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 867 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 868 VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT); 869 870 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 871 VC4_HDMI_RAM_PACKET_ENABLE); 872 873 vc4_hdmi_set_infoframes(encoder); 874 } 875 876 vc4_hdmi_recenter_fifo(vc4_hdmi); 877 } 878 879 static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder) 880 { 881 } 882 883 #define WIFI_2_4GHz_CH1_MIN_FREQ 2400000000ULL 884 #define WIFI_2_4GHz_CH1_MAX_FREQ 2422000000ULL 885 886 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder, 887 struct drm_crtc_state *crtc_state, 888 struct drm_connector_state *conn_state) 889 { 890 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state); 891 struct drm_display_mode *mode = &crtc_state->adjusted_mode; 892 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 893 unsigned long long pixel_rate = mode->clock * 1000; 894 unsigned long long tmds_rate; 895 896 if (vc4_hdmi->variant->unsupported_odd_h_timings && 897 ((mode->hdisplay % 2) || (mode->hsync_start % 2) || 898 (mode->hsync_end % 2) || (mode->htotal % 2))) 899 return -EINVAL; 900 901 /* 902 * The 1440p@60 pixel rate is in the same range than the first 903 * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz 904 * bandwidth). Slightly lower the frequency to bring it out of 905 * the WiFi range. 906 */ 907 tmds_rate = pixel_rate * 10; 908 if (vc4_hdmi->disable_wifi_frequencies && 909 (tmds_rate >= WIFI_2_4GHz_CH1_MIN_FREQ && 910 tmds_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) { 911 mode->clock = 238560; 912 pixel_rate = mode->clock * 1000; 913 } 914 915 if (conn_state->max_bpc == 12) { 916 pixel_rate = pixel_rate * 150; 917 do_div(pixel_rate, 100); 918 } else if (conn_state->max_bpc == 10) { 919 pixel_rate = pixel_rate * 125; 920 do_div(pixel_rate, 100); 921 } 922 923 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 924 pixel_rate = pixel_rate * 2; 925 926 if (pixel_rate > vc4_hdmi->variant->max_pixel_clock) 927 return -EINVAL; 928 929 vc4_state->pixel_rate = pixel_rate; 930 931 return 0; 932 } 933 934 static enum drm_mode_status 935 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder, 936 const struct drm_display_mode *mode) 937 { 938 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 939 940 if (vc4_hdmi->variant->unsupported_odd_h_timings && 941 ((mode->hdisplay % 2) || (mode->hsync_start % 2) || 942 (mode->hsync_end % 2) || (mode->htotal % 2))) 943 return MODE_H_ILLEGAL; 944 945 if ((mode->clock * 1000) > vc4_hdmi->variant->max_pixel_clock) 946 return MODE_CLOCK_HIGH; 947 948 return MODE_OK; 949 } 950 951 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = { 952 .atomic_check = vc4_hdmi_encoder_atomic_check, 953 .mode_valid = vc4_hdmi_encoder_mode_valid, 954 .disable = vc4_hdmi_encoder_disable, 955 .enable = vc4_hdmi_encoder_enable, 956 }; 957 958 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask) 959 { 960 int i; 961 u32 channel_map = 0; 962 963 for (i = 0; i < 8; i++) { 964 if (channel_mask & BIT(i)) 965 channel_map |= i << (3 * i); 966 } 967 return channel_map; 968 } 969 970 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask) 971 { 972 int i; 973 u32 channel_map = 0; 974 975 for (i = 0; i < 8; i++) { 976 if (channel_mask & BIT(i)) 977 channel_map |= i << (4 * i); 978 } 979 return channel_map; 980 } 981 982 /* HDMI audio codec callbacks */ 983 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi) 984 { 985 u32 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock); 986 unsigned long n, m; 987 988 rational_best_approximation(hsm_clock, vc4_hdmi->audio.samplerate, 989 VC4_HD_MAI_SMP_N_MASK >> 990 VC4_HD_MAI_SMP_N_SHIFT, 991 (VC4_HD_MAI_SMP_M_MASK >> 992 VC4_HD_MAI_SMP_M_SHIFT) + 1, 993 &n, &m); 994 995 HDMI_WRITE(HDMI_MAI_SMP, 996 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) | 997 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M)); 998 } 999 1000 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi) 1001 { 1002 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base; 1003 struct drm_crtc *crtc = encoder->crtc; 1004 const struct drm_display_mode *mode = &crtc->state->adjusted_mode; 1005 u32 samplerate = vc4_hdmi->audio.samplerate; 1006 u32 n, cts; 1007 u64 tmp; 1008 1009 n = 128 * samplerate / 1000; 1010 tmp = (u64)(mode->clock * 1000) * n; 1011 do_div(tmp, 128 * samplerate); 1012 cts = tmp; 1013 1014 HDMI_WRITE(HDMI_CRP_CFG, 1015 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN | 1016 VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N)); 1017 1018 /* 1019 * We could get slightly more accurate clocks in some cases by 1020 * providing a CTS_1 value. The two CTS values are alternated 1021 * between based on the period fields 1022 */ 1023 HDMI_WRITE(HDMI_CTS_0, cts); 1024 HDMI_WRITE(HDMI_CTS_1, cts); 1025 } 1026 1027 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai) 1028 { 1029 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai); 1030 1031 return snd_soc_card_get_drvdata(card); 1032 } 1033 1034 static int vc4_hdmi_audio_startup(struct snd_pcm_substream *substream, 1035 struct snd_soc_dai *dai) 1036 { 1037 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai); 1038 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base; 1039 struct drm_connector *connector = &vc4_hdmi->connector; 1040 int ret; 1041 1042 if (vc4_hdmi->audio.substream && vc4_hdmi->audio.substream != substream) 1043 return -EINVAL; 1044 1045 vc4_hdmi->audio.substream = substream; 1046 1047 /* 1048 * If the HDMI encoder hasn't probed, or the encoder is 1049 * currently in DVI mode, treat the codec dai as missing. 1050 */ 1051 if (!encoder->crtc || !(HDMI_READ(HDMI_RAM_PACKET_CONFIG) & 1052 VC4_HDMI_RAM_PACKET_ENABLE)) 1053 return -ENODEV; 1054 1055 ret = snd_pcm_hw_constraint_eld(substream->runtime, connector->eld); 1056 if (ret) 1057 return ret; 1058 1059 return 0; 1060 } 1061 1062 static int vc4_hdmi_audio_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 1063 { 1064 return 0; 1065 } 1066 1067 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi) 1068 { 1069 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base; 1070 struct device *dev = &vc4_hdmi->pdev->dev; 1071 int ret; 1072 1073 vc4_hdmi->audio.streaming = false; 1074 ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO, false); 1075 if (ret) 1076 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret); 1077 1078 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET); 1079 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF); 1080 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH); 1081 } 1082 1083 static void vc4_hdmi_audio_shutdown(struct snd_pcm_substream *substream, 1084 struct snd_soc_dai *dai) 1085 { 1086 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai); 1087 1088 if (substream != vc4_hdmi->audio.substream) 1089 return; 1090 1091 vc4_hdmi_audio_reset(vc4_hdmi); 1092 1093 vc4_hdmi->audio.substream = NULL; 1094 } 1095 1096 /* HDMI audio codec callbacks */ 1097 static int vc4_hdmi_audio_hw_params(struct snd_pcm_substream *substream, 1098 struct snd_pcm_hw_params *params, 1099 struct snd_soc_dai *dai) 1100 { 1101 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai); 1102 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base; 1103 struct device *dev = &vc4_hdmi->pdev->dev; 1104 u32 audio_packet_config, channel_mask; 1105 u32 channel_map; 1106 1107 if (substream != vc4_hdmi->audio.substream) 1108 return -EINVAL; 1109 1110 dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__, 1111 params_rate(params), params_width(params), 1112 params_channels(params)); 1113 1114 vc4_hdmi->audio.channels = params_channels(params); 1115 vc4_hdmi->audio.samplerate = params_rate(params); 1116 1117 HDMI_WRITE(HDMI_MAI_CTL, 1118 VC4_HD_MAI_CTL_RESET | 1119 VC4_HD_MAI_CTL_FLUSH | 1120 VC4_HD_MAI_CTL_DLATE | 1121 VC4_HD_MAI_CTL_ERRORE | 1122 VC4_HD_MAI_CTL_ERRORF); 1123 1124 vc4_hdmi_audio_set_mai_clock(vc4_hdmi); 1125 1126 /* The B frame identifier should match the value used by alsa-lib (8) */ 1127 audio_packet_config = 1128 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT | 1129 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS | 1130 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER); 1131 1132 channel_mask = GENMASK(vc4_hdmi->audio.channels - 1, 0); 1133 audio_packet_config |= VC4_SET_FIELD(channel_mask, 1134 VC4_HDMI_AUDIO_PACKET_CEA_MASK); 1135 1136 /* Set the MAI threshold. This logic mimics the firmware's. */ 1137 if (vc4_hdmi->audio.samplerate > 96000) { 1138 HDMI_WRITE(HDMI_MAI_THR, 1139 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQHIGH) | 1140 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW)); 1141 } else if (vc4_hdmi->audio.samplerate > 48000) { 1142 HDMI_WRITE(HDMI_MAI_THR, 1143 VC4_SET_FIELD(0x14, VC4_HD_MAI_THR_DREQHIGH) | 1144 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW)); 1145 } else { 1146 HDMI_WRITE(HDMI_MAI_THR, 1147 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) | 1148 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) | 1149 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQHIGH) | 1150 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQLOW)); 1151 } 1152 1153 HDMI_WRITE(HDMI_MAI_CONFIG, 1154 VC4_HDMI_MAI_CONFIG_BIT_REVERSE | 1155 VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK)); 1156 1157 channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask); 1158 HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map); 1159 HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config); 1160 vc4_hdmi_set_n_cts(vc4_hdmi); 1161 1162 vc4_hdmi_set_audio_infoframe(encoder); 1163 1164 return 0; 1165 } 1166 1167 static int vc4_hdmi_audio_trigger(struct snd_pcm_substream *substream, int cmd, 1168 struct snd_soc_dai *dai) 1169 { 1170 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai); 1171 1172 switch (cmd) { 1173 case SNDRV_PCM_TRIGGER_START: 1174 vc4_hdmi->audio.streaming = true; 1175 1176 if (vc4_hdmi->variant->phy_rng_enable) 1177 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi); 1178 1179 HDMI_WRITE(HDMI_MAI_CTL, 1180 VC4_SET_FIELD(vc4_hdmi->audio.channels, 1181 VC4_HD_MAI_CTL_CHNUM) | 1182 VC4_HD_MAI_CTL_ENABLE); 1183 break; 1184 case SNDRV_PCM_TRIGGER_STOP: 1185 HDMI_WRITE(HDMI_MAI_CTL, 1186 VC4_HD_MAI_CTL_DLATE | 1187 VC4_HD_MAI_CTL_ERRORE | 1188 VC4_HD_MAI_CTL_ERRORF); 1189 1190 if (vc4_hdmi->variant->phy_rng_disable) 1191 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi); 1192 1193 vc4_hdmi->audio.streaming = false; 1194 1195 break; 1196 default: 1197 break; 1198 } 1199 1200 return 0; 1201 } 1202 1203 static inline struct vc4_hdmi * 1204 snd_component_to_hdmi(struct snd_soc_component *component) 1205 { 1206 struct snd_soc_card *card = snd_soc_component_get_drvdata(component); 1207 1208 return snd_soc_card_get_drvdata(card); 1209 } 1210 1211 static int vc4_hdmi_audio_eld_ctl_info(struct snd_kcontrol *kcontrol, 1212 struct snd_ctl_elem_info *uinfo) 1213 { 1214 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1215 struct vc4_hdmi *vc4_hdmi = snd_component_to_hdmi(component); 1216 struct drm_connector *connector = &vc4_hdmi->connector; 1217 1218 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 1219 uinfo->count = sizeof(connector->eld); 1220 1221 return 0; 1222 } 1223 1224 static int vc4_hdmi_audio_eld_ctl_get(struct snd_kcontrol *kcontrol, 1225 struct snd_ctl_elem_value *ucontrol) 1226 { 1227 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 1228 struct vc4_hdmi *vc4_hdmi = snd_component_to_hdmi(component); 1229 struct drm_connector *connector = &vc4_hdmi->connector; 1230 1231 memcpy(ucontrol->value.bytes.data, connector->eld, 1232 sizeof(connector->eld)); 1233 1234 return 0; 1235 } 1236 1237 static const struct snd_kcontrol_new vc4_hdmi_audio_controls[] = { 1238 { 1239 .access = SNDRV_CTL_ELEM_ACCESS_READ | 1240 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 1241 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 1242 .name = "ELD", 1243 .info = vc4_hdmi_audio_eld_ctl_info, 1244 .get = vc4_hdmi_audio_eld_ctl_get, 1245 }, 1246 }; 1247 1248 static const struct snd_soc_dapm_widget vc4_hdmi_audio_widgets[] = { 1249 SND_SOC_DAPM_OUTPUT("TX"), 1250 }; 1251 1252 static const struct snd_soc_dapm_route vc4_hdmi_audio_routes[] = { 1253 { "TX", NULL, "Playback" }, 1254 }; 1255 1256 static const struct snd_soc_component_driver vc4_hdmi_audio_component_drv = { 1257 .name = "vc4-hdmi-codec-dai-component", 1258 .controls = vc4_hdmi_audio_controls, 1259 .num_controls = ARRAY_SIZE(vc4_hdmi_audio_controls), 1260 .dapm_widgets = vc4_hdmi_audio_widgets, 1261 .num_dapm_widgets = ARRAY_SIZE(vc4_hdmi_audio_widgets), 1262 .dapm_routes = vc4_hdmi_audio_routes, 1263 .num_dapm_routes = ARRAY_SIZE(vc4_hdmi_audio_routes), 1264 .idle_bias_on = 1, 1265 .use_pmdown_time = 1, 1266 .endianness = 1, 1267 .non_legacy_dai_naming = 1, 1268 }; 1269 1270 static const struct snd_soc_dai_ops vc4_hdmi_audio_dai_ops = { 1271 .startup = vc4_hdmi_audio_startup, 1272 .shutdown = vc4_hdmi_audio_shutdown, 1273 .hw_params = vc4_hdmi_audio_hw_params, 1274 .set_fmt = vc4_hdmi_audio_set_fmt, 1275 .trigger = vc4_hdmi_audio_trigger, 1276 }; 1277 1278 static struct snd_soc_dai_driver vc4_hdmi_audio_codec_dai_drv = { 1279 .name = "vc4-hdmi-hifi", 1280 .playback = { 1281 .stream_name = "Playback", 1282 .channels_min = 2, 1283 .channels_max = 8, 1284 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 1285 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 1286 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 1287 SNDRV_PCM_RATE_192000, 1288 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 1289 }, 1290 }; 1291 1292 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = { 1293 .name = "vc4-hdmi-cpu-dai-component", 1294 }; 1295 1296 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai) 1297 { 1298 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai); 1299 1300 snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL); 1301 1302 return 0; 1303 } 1304 1305 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = { 1306 .name = "vc4-hdmi-cpu-dai", 1307 .probe = vc4_hdmi_audio_cpu_dai_probe, 1308 .playback = { 1309 .stream_name = "Playback", 1310 .channels_min = 1, 1311 .channels_max = 8, 1312 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 1313 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 1314 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 1315 SNDRV_PCM_RATE_192000, 1316 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 1317 }, 1318 .ops = &vc4_hdmi_audio_dai_ops, 1319 }; 1320 1321 static const struct snd_dmaengine_pcm_config pcm_conf = { 1322 .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx", 1323 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 1324 }; 1325 1326 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi) 1327 { 1328 const struct vc4_hdmi_register *mai_data = 1329 &vc4_hdmi->variant->registers[HDMI_MAI_DATA]; 1330 struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link; 1331 struct snd_soc_card *card = &vc4_hdmi->audio.card; 1332 struct device *dev = &vc4_hdmi->pdev->dev; 1333 const __be32 *addr; 1334 int index; 1335 int ret; 1336 1337 if (!of_find_property(dev->of_node, "dmas", NULL)) { 1338 dev_warn(dev, 1339 "'dmas' DT property is missing, no HDMI audio\n"); 1340 return 0; 1341 } 1342 1343 if (mai_data->reg != VC4_HD) { 1344 WARN_ONCE(true, "MAI isn't in the HD block\n"); 1345 return -EINVAL; 1346 } 1347 1348 /* 1349 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve 1350 * the bus address specified in the DT, because the physical address 1351 * (the one returned by platform_get_resource()) is not appropriate 1352 * for DMA transfers. 1353 * This VC/MMU should probably be exposed to avoid this kind of hacks. 1354 */ 1355 index = of_property_match_string(dev->of_node, "reg-names", "hd"); 1356 /* Before BCM2711, we don't have a named register range */ 1357 if (index < 0) 1358 index = 1; 1359 1360 addr = of_get_address(dev->of_node, index, NULL, NULL); 1361 1362 vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset; 1363 vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1364 vc4_hdmi->audio.dma_data.maxburst = 2; 1365 1366 ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0); 1367 if (ret) { 1368 dev_err(dev, "Could not register PCM component: %d\n", ret); 1369 return ret; 1370 } 1371 1372 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp, 1373 &vc4_hdmi_audio_cpu_dai_drv, 1); 1374 if (ret) { 1375 dev_err(dev, "Could not register CPU DAI: %d\n", ret); 1376 return ret; 1377 } 1378 1379 /* register component and codec dai */ 1380 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_component_drv, 1381 &vc4_hdmi_audio_codec_dai_drv, 1); 1382 if (ret) { 1383 dev_err(dev, "Could not register component: %d\n", ret); 1384 return ret; 1385 } 1386 1387 dai_link->cpus = &vc4_hdmi->audio.cpu; 1388 dai_link->codecs = &vc4_hdmi->audio.codec; 1389 dai_link->platforms = &vc4_hdmi->audio.platform; 1390 1391 dai_link->num_cpus = 1; 1392 dai_link->num_codecs = 1; 1393 dai_link->num_platforms = 1; 1394 1395 dai_link->name = "MAI"; 1396 dai_link->stream_name = "MAI PCM"; 1397 dai_link->codecs->dai_name = vc4_hdmi_audio_codec_dai_drv.name; 1398 dai_link->cpus->dai_name = dev_name(dev); 1399 dai_link->codecs->name = dev_name(dev); 1400 dai_link->platforms->name = dev_name(dev); 1401 1402 card->dai_link = dai_link; 1403 card->num_links = 1; 1404 card->name = vc4_hdmi->variant->card_name; 1405 card->driver_name = "vc4-hdmi"; 1406 card->dev = dev; 1407 card->owner = THIS_MODULE; 1408 1409 /* 1410 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and 1411 * stores a pointer to the snd card object in dev->driver_data. This 1412 * means we cannot use it for something else. The hdmi back-pointer is 1413 * now stored in card->drvdata and should be retrieved with 1414 * snd_soc_card_get_drvdata() if needed. 1415 */ 1416 snd_soc_card_set_drvdata(card, vc4_hdmi); 1417 ret = devm_snd_soc_register_card(dev, card); 1418 if (ret) 1419 dev_err(dev, "Could not register sound card: %d\n", ret); 1420 1421 return ret; 1422 1423 } 1424 1425 #ifdef CONFIG_DRM_VC4_HDMI_CEC 1426 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv) 1427 { 1428 struct vc4_hdmi *vc4_hdmi = priv; 1429 1430 if (vc4_hdmi->cec_irq_was_rx) { 1431 if (vc4_hdmi->cec_rx_msg.len) 1432 cec_received_msg(vc4_hdmi->cec_adap, 1433 &vc4_hdmi->cec_rx_msg); 1434 } else if (vc4_hdmi->cec_tx_ok) { 1435 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK, 1436 0, 0, 0, 0); 1437 } else { 1438 /* 1439 * This CEC implementation makes 1 retry, so if we 1440 * get a NACK, then that means it made 2 attempts. 1441 */ 1442 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK, 1443 0, 2, 0, 0); 1444 } 1445 return IRQ_HANDLED; 1446 } 1447 1448 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1) 1449 { 1450 struct cec_msg *msg = &vc4_hdmi->cec_rx_msg; 1451 unsigned int i; 1452 1453 msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >> 1454 VC4_HDMI_CEC_REC_WRD_CNT_SHIFT); 1455 for (i = 0; i < msg->len; i += 4) { 1456 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + i); 1457 1458 msg->msg[i] = val & 0xff; 1459 msg->msg[i + 1] = (val >> 8) & 0xff; 1460 msg->msg[i + 2] = (val >> 16) & 0xff; 1461 msg->msg[i + 3] = (val >> 24) & 0xff; 1462 } 1463 } 1464 1465 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv) 1466 { 1467 struct vc4_hdmi *vc4_hdmi = priv; 1468 u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS); 1469 u32 cntrl1, cntrl5; 1470 1471 if (!(stat & VC4_HDMI_CPU_CEC)) 1472 return IRQ_NONE; 1473 vc4_hdmi->cec_rx_msg.len = 0; 1474 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1); 1475 cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5); 1476 vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT; 1477 if (vc4_hdmi->cec_irq_was_rx) { 1478 vc4_cec_read_msg(vc4_hdmi, cntrl1); 1479 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 1480 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 1481 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 1482 } else { 1483 vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD; 1484 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 1485 } 1486 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 1487 HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC); 1488 1489 return IRQ_WAKE_THREAD; 1490 } 1491 1492 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable) 1493 { 1494 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 1495 /* clock period in microseconds */ 1496 const u32 usecs = 1000000 / CEC_CLOCK_FREQ; 1497 u32 val = HDMI_READ(HDMI_CEC_CNTRL_5); 1498 1499 val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET | 1500 VC4_HDMI_CEC_CNT_TO_4700_US_MASK | 1501 VC4_HDMI_CEC_CNT_TO_4500_US_MASK); 1502 val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) | 1503 ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT); 1504 1505 if (enable) { 1506 HDMI_WRITE(HDMI_CEC_CNTRL_5, val | 1507 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 1508 HDMI_WRITE(HDMI_CEC_CNTRL_5, val); 1509 HDMI_WRITE(HDMI_CEC_CNTRL_2, 1510 ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) | 1511 ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) | 1512 ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) | 1513 ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) | 1514 ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT)); 1515 HDMI_WRITE(HDMI_CEC_CNTRL_3, 1516 ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) | 1517 ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) | 1518 ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) | 1519 ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT)); 1520 HDMI_WRITE(HDMI_CEC_CNTRL_4, 1521 ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) | 1522 ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) | 1523 ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) | 1524 ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT)); 1525 1526 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC); 1527 } else { 1528 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC); 1529 HDMI_WRITE(HDMI_CEC_CNTRL_5, val | 1530 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 1531 } 1532 return 0; 1533 } 1534 1535 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr) 1536 { 1537 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 1538 1539 HDMI_WRITE(HDMI_CEC_CNTRL_1, 1540 (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) | 1541 (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT); 1542 return 0; 1543 } 1544 1545 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts, 1546 u32 signal_free_time, struct cec_msg *msg) 1547 { 1548 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 1549 u32 val; 1550 unsigned int i; 1551 1552 for (i = 0; i < msg->len; i += 4) 1553 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + i, 1554 (msg->msg[i]) | 1555 (msg->msg[i + 1] << 8) | 1556 (msg->msg[i + 2] << 16) | 1557 (msg->msg[i + 3] << 24)); 1558 1559 val = HDMI_READ(HDMI_CEC_CNTRL_1); 1560 val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 1561 HDMI_WRITE(HDMI_CEC_CNTRL_1, val); 1562 val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK; 1563 val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT; 1564 val |= VC4_HDMI_CEC_START_XMIT_BEGIN; 1565 1566 HDMI_WRITE(HDMI_CEC_CNTRL_1, val); 1567 return 0; 1568 } 1569 1570 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = { 1571 .adap_enable = vc4_hdmi_cec_adap_enable, 1572 .adap_log_addr = vc4_hdmi_cec_adap_log_addr, 1573 .adap_transmit = vc4_hdmi_cec_adap_transmit, 1574 }; 1575 1576 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi) 1577 { 1578 struct cec_connector_info conn_info; 1579 struct platform_device *pdev = vc4_hdmi->pdev; 1580 u32 value; 1581 int ret; 1582 1583 if (!vc4_hdmi->variant->cec_available) 1584 return 0; 1585 1586 vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops, 1587 vc4_hdmi, "vc4", 1588 CEC_CAP_DEFAULTS | 1589 CEC_CAP_CONNECTOR_INFO, 1); 1590 ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap); 1591 if (ret < 0) 1592 return ret; 1593 1594 cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector); 1595 cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info); 1596 1597 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff); 1598 value = HDMI_READ(HDMI_CEC_CNTRL_1); 1599 value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK; 1600 /* 1601 * Set the logical address to Unregistered and set the clock 1602 * divider: the hsm_clock rate and this divider setting will 1603 * give a 40 kHz CEC clock. 1604 */ 1605 value |= VC4_HDMI_CEC_ADDR_MASK | 1606 (4091 << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT); 1607 HDMI_WRITE(HDMI_CEC_CNTRL_1, value); 1608 ret = devm_request_threaded_irq(&pdev->dev, platform_get_irq(pdev, 0), 1609 vc4_cec_irq_handler, 1610 vc4_cec_irq_handler_thread, 0, 1611 "vc4 hdmi cec", vc4_hdmi); 1612 if (ret) 1613 goto err_delete_cec_adap; 1614 1615 ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev); 1616 if (ret < 0) 1617 goto err_delete_cec_adap; 1618 1619 return 0; 1620 1621 err_delete_cec_adap: 1622 cec_delete_adapter(vc4_hdmi->cec_adap); 1623 1624 return ret; 1625 } 1626 1627 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi) 1628 { 1629 cec_unregister_adapter(vc4_hdmi->cec_adap); 1630 } 1631 #else 1632 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi) 1633 { 1634 return 0; 1635 } 1636 1637 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi) {}; 1638 1639 #endif 1640 1641 static int vc4_hdmi_build_regset(struct vc4_hdmi *vc4_hdmi, 1642 struct debugfs_regset32 *regset, 1643 enum vc4_hdmi_regs reg) 1644 { 1645 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant; 1646 struct debugfs_reg32 *regs, *new_regs; 1647 unsigned int count = 0; 1648 unsigned int i; 1649 1650 regs = kcalloc(variant->num_registers, sizeof(*regs), 1651 GFP_KERNEL); 1652 if (!regs) 1653 return -ENOMEM; 1654 1655 for (i = 0; i < variant->num_registers; i++) { 1656 const struct vc4_hdmi_register *field = &variant->registers[i]; 1657 1658 if (field->reg != reg) 1659 continue; 1660 1661 regs[count].name = field->name; 1662 regs[count].offset = field->offset; 1663 count++; 1664 } 1665 1666 new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL); 1667 if (!new_regs) 1668 return -ENOMEM; 1669 1670 regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg); 1671 regset->regs = new_regs; 1672 regset->nregs = count; 1673 1674 return 0; 1675 } 1676 1677 static int vc4_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi) 1678 { 1679 struct platform_device *pdev = vc4_hdmi->pdev; 1680 struct device *dev = &pdev->dev; 1681 int ret; 1682 1683 vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0); 1684 if (IS_ERR(vc4_hdmi->hdmicore_regs)) 1685 return PTR_ERR(vc4_hdmi->hdmicore_regs); 1686 1687 vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1); 1688 if (IS_ERR(vc4_hdmi->hd_regs)) 1689 return PTR_ERR(vc4_hdmi->hd_regs); 1690 1691 ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD); 1692 if (ret) 1693 return ret; 1694 1695 ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI); 1696 if (ret) 1697 return ret; 1698 1699 vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel"); 1700 if (IS_ERR(vc4_hdmi->pixel_clock)) { 1701 ret = PTR_ERR(vc4_hdmi->pixel_clock); 1702 if (ret != -EPROBE_DEFER) 1703 DRM_ERROR("Failed to get pixel clock\n"); 1704 return ret; 1705 } 1706 1707 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); 1708 if (IS_ERR(vc4_hdmi->hsm_clock)) { 1709 DRM_ERROR("Failed to get HDMI state machine clock\n"); 1710 return PTR_ERR(vc4_hdmi->hsm_clock); 1711 } 1712 vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock; 1713 1714 return 0; 1715 } 1716 1717 static int vc5_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi) 1718 { 1719 struct platform_device *pdev = vc4_hdmi->pdev; 1720 struct device *dev = &pdev->dev; 1721 struct resource *res; 1722 1723 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi"); 1724 if (!res) 1725 return -ENODEV; 1726 1727 vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start, 1728 resource_size(res)); 1729 if (!vc4_hdmi->hdmicore_regs) 1730 return -ENOMEM; 1731 1732 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd"); 1733 if (!res) 1734 return -ENODEV; 1735 1736 vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res)); 1737 if (!vc4_hdmi->hd_regs) 1738 return -ENOMEM; 1739 1740 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec"); 1741 if (!res) 1742 return -ENODEV; 1743 1744 vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res)); 1745 if (!vc4_hdmi->cec_regs) 1746 return -ENOMEM; 1747 1748 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc"); 1749 if (!res) 1750 return -ENODEV; 1751 1752 vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res)); 1753 if (!vc4_hdmi->csc_regs) 1754 return -ENOMEM; 1755 1756 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp"); 1757 if (!res) 1758 return -ENODEV; 1759 1760 vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res)); 1761 if (!vc4_hdmi->dvp_regs) 1762 return -ENOMEM; 1763 1764 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy"); 1765 if (!res) 1766 return -ENODEV; 1767 1768 vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res)); 1769 if (!vc4_hdmi->phy_regs) 1770 return -ENOMEM; 1771 1772 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet"); 1773 if (!res) 1774 return -ENODEV; 1775 1776 vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res)); 1777 if (!vc4_hdmi->ram_regs) 1778 return -ENOMEM; 1779 1780 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm"); 1781 if (!res) 1782 return -ENODEV; 1783 1784 vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res)); 1785 if (!vc4_hdmi->rm_regs) 1786 return -ENOMEM; 1787 1788 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); 1789 if (IS_ERR(vc4_hdmi->hsm_clock)) { 1790 DRM_ERROR("Failed to get HDMI state machine clock\n"); 1791 return PTR_ERR(vc4_hdmi->hsm_clock); 1792 } 1793 1794 vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb"); 1795 if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) { 1796 DRM_ERROR("Failed to get pixel bvb clock\n"); 1797 return PTR_ERR(vc4_hdmi->pixel_bvb_clock); 1798 } 1799 1800 vc4_hdmi->audio_clock = devm_clk_get(dev, "audio"); 1801 if (IS_ERR(vc4_hdmi->audio_clock)) { 1802 DRM_ERROR("Failed to get audio clock\n"); 1803 return PTR_ERR(vc4_hdmi->audio_clock); 1804 } 1805 1806 vc4_hdmi->reset = devm_reset_control_get(dev, NULL); 1807 if (IS_ERR(vc4_hdmi->reset)) { 1808 DRM_ERROR("Failed to get HDMI reset line\n"); 1809 return PTR_ERR(vc4_hdmi->reset); 1810 } 1811 1812 return 0; 1813 } 1814 1815 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data) 1816 { 1817 const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev); 1818 struct platform_device *pdev = to_platform_device(dev); 1819 struct drm_device *drm = dev_get_drvdata(master); 1820 struct vc4_hdmi *vc4_hdmi; 1821 struct drm_encoder *encoder; 1822 struct device_node *ddc_node; 1823 u32 value; 1824 int ret; 1825 1826 vc4_hdmi = devm_kzalloc(dev, sizeof(*vc4_hdmi), GFP_KERNEL); 1827 if (!vc4_hdmi) 1828 return -ENOMEM; 1829 1830 dev_set_drvdata(dev, vc4_hdmi); 1831 encoder = &vc4_hdmi->encoder.base.base; 1832 vc4_hdmi->encoder.base.type = variant->encoder_type; 1833 vc4_hdmi->encoder.base.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure; 1834 vc4_hdmi->encoder.base.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable; 1835 vc4_hdmi->encoder.base.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable; 1836 vc4_hdmi->encoder.base.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable; 1837 vc4_hdmi->encoder.base.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown; 1838 vc4_hdmi->pdev = pdev; 1839 vc4_hdmi->variant = variant; 1840 1841 ret = variant->init_resources(vc4_hdmi); 1842 if (ret) 1843 return ret; 1844 1845 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0); 1846 if (!ddc_node) { 1847 DRM_ERROR("Failed to find ddc node in device tree\n"); 1848 return -ENODEV; 1849 } 1850 1851 vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node); 1852 of_node_put(ddc_node); 1853 if (!vc4_hdmi->ddc) { 1854 DRM_DEBUG("Failed to get ddc i2c adapter by node\n"); 1855 return -EPROBE_DEFER; 1856 } 1857 1858 /* Only use the GPIO HPD pin if present in the DT, otherwise 1859 * we'll use the HDMI core's register. 1860 */ 1861 if (of_find_property(dev->of_node, "hpd-gpios", &value)) { 1862 enum of_gpio_flags hpd_gpio_flags; 1863 1864 vc4_hdmi->hpd_gpio = of_get_named_gpio_flags(dev->of_node, 1865 "hpd-gpios", 0, 1866 &hpd_gpio_flags); 1867 if (vc4_hdmi->hpd_gpio < 0) { 1868 ret = vc4_hdmi->hpd_gpio; 1869 goto err_unprepare_hsm; 1870 } 1871 1872 vc4_hdmi->hpd_active_low = hpd_gpio_flags & OF_GPIO_ACTIVE_LOW; 1873 } 1874 1875 vc4_hdmi->disable_wifi_frequencies = 1876 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence"); 1877 1878 pm_runtime_enable(dev); 1879 1880 drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS); 1881 drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs); 1882 1883 ret = vc4_hdmi_connector_init(drm, vc4_hdmi); 1884 if (ret) 1885 goto err_destroy_encoder; 1886 1887 ret = vc4_hdmi_cec_init(vc4_hdmi); 1888 if (ret) 1889 goto err_destroy_conn; 1890 1891 ret = vc4_hdmi_audio_init(vc4_hdmi); 1892 if (ret) 1893 goto err_free_cec; 1894 1895 vc4_debugfs_add_file(drm, variant->debugfs_name, 1896 vc4_hdmi_debugfs_regs, 1897 vc4_hdmi); 1898 1899 return 0; 1900 1901 err_free_cec: 1902 vc4_hdmi_cec_exit(vc4_hdmi); 1903 err_destroy_conn: 1904 vc4_hdmi_connector_destroy(&vc4_hdmi->connector); 1905 err_destroy_encoder: 1906 drm_encoder_cleanup(encoder); 1907 err_unprepare_hsm: 1908 pm_runtime_disable(dev); 1909 put_device(&vc4_hdmi->ddc->dev); 1910 1911 return ret; 1912 } 1913 1914 static void vc4_hdmi_unbind(struct device *dev, struct device *master, 1915 void *data) 1916 { 1917 struct vc4_hdmi *vc4_hdmi; 1918 1919 /* 1920 * ASoC makes it a bit hard to retrieve a pointer to the 1921 * vc4_hdmi structure. Registering the card will overwrite our 1922 * device drvdata with a pointer to the snd_soc_card structure, 1923 * which can then be used to retrieve whatever drvdata we want 1924 * to associate. 1925 * 1926 * However, that doesn't fly in the case where we wouldn't 1927 * register an ASoC card (because of an old DT that is missing 1928 * the dmas properties for example), then the card isn't 1929 * registered and the device drvdata wouldn't be set. 1930 * 1931 * We can deal with both cases by making sure a snd_soc_card 1932 * pointer and a vc4_hdmi structure are pointing to the same 1933 * memory address, so we can treat them indistinctly without any 1934 * issue. 1935 */ 1936 BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0); 1937 BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0); 1938 vc4_hdmi = dev_get_drvdata(dev); 1939 1940 kfree(vc4_hdmi->hdmi_regset.regs); 1941 kfree(vc4_hdmi->hd_regset.regs); 1942 1943 vc4_hdmi_cec_exit(vc4_hdmi); 1944 vc4_hdmi_connector_destroy(&vc4_hdmi->connector); 1945 drm_encoder_cleanup(&vc4_hdmi->encoder.base.base); 1946 1947 pm_runtime_disable(dev); 1948 1949 put_device(&vc4_hdmi->ddc->dev); 1950 } 1951 1952 static const struct component_ops vc4_hdmi_ops = { 1953 .bind = vc4_hdmi_bind, 1954 .unbind = vc4_hdmi_unbind, 1955 }; 1956 1957 static int vc4_hdmi_dev_probe(struct platform_device *pdev) 1958 { 1959 return component_add(&pdev->dev, &vc4_hdmi_ops); 1960 } 1961 1962 static int vc4_hdmi_dev_remove(struct platform_device *pdev) 1963 { 1964 component_del(&pdev->dev, &vc4_hdmi_ops); 1965 return 0; 1966 } 1967 1968 static const struct vc4_hdmi_variant bcm2835_variant = { 1969 .encoder_type = VC4_ENCODER_TYPE_HDMI0, 1970 .debugfs_name = "hdmi_regs", 1971 .card_name = "vc4-hdmi", 1972 .max_pixel_clock = 162000000, 1973 .cec_available = true, 1974 .registers = vc4_hdmi_fields, 1975 .num_registers = ARRAY_SIZE(vc4_hdmi_fields), 1976 1977 .init_resources = vc4_hdmi_init_resources, 1978 .csc_setup = vc4_hdmi_csc_setup, 1979 .reset = vc4_hdmi_reset, 1980 .set_timings = vc4_hdmi_set_timings, 1981 .phy_init = vc4_hdmi_phy_init, 1982 .phy_disable = vc4_hdmi_phy_disable, 1983 .phy_rng_enable = vc4_hdmi_phy_rng_enable, 1984 .phy_rng_disable = vc4_hdmi_phy_rng_disable, 1985 .channel_map = vc4_hdmi_channel_map, 1986 }; 1987 1988 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = { 1989 .encoder_type = VC4_ENCODER_TYPE_HDMI0, 1990 .debugfs_name = "hdmi0_regs", 1991 .card_name = "vc4-hdmi-0", 1992 .max_pixel_clock = HDMI_14_MAX_TMDS_CLK, 1993 .registers = vc5_hdmi_hdmi0_fields, 1994 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi0_fields), 1995 .phy_lane_mapping = { 1996 PHY_LANE_0, 1997 PHY_LANE_1, 1998 PHY_LANE_2, 1999 PHY_LANE_CK, 2000 }, 2001 .unsupported_odd_h_timings = true, 2002 2003 .init_resources = vc5_hdmi_init_resources, 2004 .csc_setup = vc5_hdmi_csc_setup, 2005 .reset = vc5_hdmi_reset, 2006 .set_timings = vc5_hdmi_set_timings, 2007 .phy_init = vc5_hdmi_phy_init, 2008 .phy_disable = vc5_hdmi_phy_disable, 2009 .phy_rng_enable = vc5_hdmi_phy_rng_enable, 2010 .phy_rng_disable = vc5_hdmi_phy_rng_disable, 2011 .channel_map = vc5_hdmi_channel_map, 2012 }; 2013 2014 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = { 2015 .encoder_type = VC4_ENCODER_TYPE_HDMI1, 2016 .debugfs_name = "hdmi1_regs", 2017 .card_name = "vc4-hdmi-1", 2018 .max_pixel_clock = HDMI_14_MAX_TMDS_CLK, 2019 .registers = vc5_hdmi_hdmi1_fields, 2020 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi1_fields), 2021 .phy_lane_mapping = { 2022 PHY_LANE_1, 2023 PHY_LANE_0, 2024 PHY_LANE_CK, 2025 PHY_LANE_2, 2026 }, 2027 .unsupported_odd_h_timings = true, 2028 2029 .init_resources = vc5_hdmi_init_resources, 2030 .csc_setup = vc5_hdmi_csc_setup, 2031 .reset = vc5_hdmi_reset, 2032 .set_timings = vc5_hdmi_set_timings, 2033 .phy_init = vc5_hdmi_phy_init, 2034 .phy_disable = vc5_hdmi_phy_disable, 2035 .phy_rng_enable = vc5_hdmi_phy_rng_enable, 2036 .phy_rng_disable = vc5_hdmi_phy_rng_disable, 2037 .channel_map = vc5_hdmi_channel_map, 2038 }; 2039 2040 static const struct of_device_id vc4_hdmi_dt_match[] = { 2041 { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant }, 2042 { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant }, 2043 { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant }, 2044 {} 2045 }; 2046 2047 struct platform_driver vc4_hdmi_driver = { 2048 .probe = vc4_hdmi_dev_probe, 2049 .remove = vc4_hdmi_dev_remove, 2050 .driver = { 2051 .name = "vc4_hdmi", 2052 .of_match_table = vc4_hdmi_dt_match, 2053 }, 2054 }; 2055