1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 Broadcom 4 * Copyright (c) 2014 The Linux Foundation. All rights reserved. 5 * Copyright (C) 2013 Red Hat 6 * Author: Rob Clark <robdclark@gmail.com> 7 */ 8 9 /** 10 * DOC: VC4 Falcon HDMI module 11 * 12 * The HDMI core has a state machine and a PHY. On BCM2835, most of 13 * the unit operates off of the HSM clock from CPRMAN. It also 14 * internally uses the PLLH_PIX clock for the PHY. 15 * 16 * HDMI infoframes are kept within a small packet ram, where each 17 * packet can be individually enabled for including in a frame. 18 * 19 * HDMI audio is implemented entirely within the HDMI IP block. A 20 * register in the HDMI encoder takes SPDIF frames from the DMA engine 21 * and transfers them over an internal MAI (multi-channel audio 22 * interconnect) bus to the encoder side for insertion into the video 23 * blank regions. 24 * 25 * The driver's HDMI encoder does not yet support power management. 26 * The HDMI encoder's power domain and the HSM/pixel clocks are kept 27 * continuously running, and only the HDMI logic and packet ram are 28 * powered off/on at disable/enable time. 29 * 30 * The driver does not yet support CEC control, though the HDMI 31 * encoder block has CEC support. 32 */ 33 34 #include <drm/drm_atomic_helper.h> 35 #include <drm/drm_edid.h> 36 #include <drm/drm_probe_helper.h> 37 #include <drm/drm_simple_kms_helper.h> 38 #include <drm/drm_scdc_helper.h> 39 #include <linux/clk.h> 40 #include <linux/component.h> 41 #include <linux/i2c.h> 42 #include <linux/of_address.h> 43 #include <linux/of_gpio.h> 44 #include <linux/of_platform.h> 45 #include <linux/pm_runtime.h> 46 #include <linux/rational.h> 47 #include <linux/reset.h> 48 #include <sound/dmaengine_pcm.h> 49 #include <sound/hdmi-codec.h> 50 #include <sound/pcm_drm_eld.h> 51 #include <sound/pcm_params.h> 52 #include <sound/soc.h> 53 #include "media/cec.h" 54 #include "vc4_drv.h" 55 #include "vc4_hdmi.h" 56 #include "vc4_hdmi_regs.h" 57 #include "vc4_regs.h" 58 59 #define VC5_HDMI_HORZA_HFP_SHIFT 16 60 #define VC5_HDMI_HORZA_HFP_MASK VC4_MASK(28, 16) 61 #define VC5_HDMI_HORZA_VPOS BIT(15) 62 #define VC5_HDMI_HORZA_HPOS BIT(14) 63 #define VC5_HDMI_HORZA_HAP_SHIFT 0 64 #define VC5_HDMI_HORZA_HAP_MASK VC4_MASK(13, 0) 65 66 #define VC5_HDMI_HORZB_HBP_SHIFT 16 67 #define VC5_HDMI_HORZB_HBP_MASK VC4_MASK(26, 16) 68 #define VC5_HDMI_HORZB_HSP_SHIFT 0 69 #define VC5_HDMI_HORZB_HSP_MASK VC4_MASK(10, 0) 70 71 #define VC5_HDMI_VERTA_VSP_SHIFT 24 72 #define VC5_HDMI_VERTA_VSP_MASK VC4_MASK(28, 24) 73 #define VC5_HDMI_VERTA_VFP_SHIFT 16 74 #define VC5_HDMI_VERTA_VFP_MASK VC4_MASK(22, 16) 75 #define VC5_HDMI_VERTA_VAL_SHIFT 0 76 #define VC5_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0) 77 78 #define VC5_HDMI_VERTB_VSPO_SHIFT 16 79 #define VC5_HDMI_VERTB_VSPO_MASK VC4_MASK(29, 16) 80 81 #define VC5_HDMI_SCRAMBLER_CTL_ENABLE BIT(0) 82 83 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT 8 84 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK VC4_MASK(10, 8) 85 86 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT 0 87 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK VC4_MASK(3, 0) 88 89 #define VC5_HDMI_GCP_CONFIG_GCP_ENABLE BIT(31) 90 91 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT 8 92 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK VC4_MASK(15, 8) 93 94 # define VC4_HD_M_SW_RST BIT(2) 95 # define VC4_HD_M_ENABLE BIT(0) 96 97 #define HSM_MIN_CLOCK_FREQ 120000000 98 #define CEC_CLOCK_FREQ 40000 99 100 #define HDMI_14_MAX_TMDS_CLK (340 * 1000 * 1000) 101 102 static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode) 103 { 104 return (mode->clock * 1000) > HDMI_14_MAX_TMDS_CLK; 105 } 106 107 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused) 108 { 109 struct drm_info_node *node = (struct drm_info_node *)m->private; 110 struct vc4_hdmi *vc4_hdmi = node->info_ent->data; 111 struct drm_printer p = drm_seq_file_printer(m); 112 113 drm_print_regset32(&p, &vc4_hdmi->hdmi_regset); 114 drm_print_regset32(&p, &vc4_hdmi->hd_regset); 115 116 return 0; 117 } 118 119 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi) 120 { 121 unsigned long flags; 122 123 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 124 125 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST); 126 udelay(1); 127 HDMI_WRITE(HDMI_M_CTL, 0); 128 129 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE); 130 131 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 132 VC4_HDMI_SW_RESET_HDMI | 133 VC4_HDMI_SW_RESET_FORMAT_DETECT); 134 135 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0); 136 137 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 138 } 139 140 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi) 141 { 142 unsigned long flags; 143 144 reset_control_reset(vc4_hdmi->reset); 145 146 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 147 148 HDMI_WRITE(HDMI_DVP_CTL, 0); 149 150 HDMI_WRITE(HDMI_CLOCK_STOP, 151 HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL); 152 153 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 154 } 155 156 #ifdef CONFIG_DRM_VC4_HDMI_CEC 157 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) 158 { 159 unsigned long cec_rate = clk_get_rate(vc4_hdmi->cec_clock); 160 unsigned long flags; 161 u16 clk_cnt; 162 u32 value; 163 164 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 165 166 value = HDMI_READ(HDMI_CEC_CNTRL_1); 167 value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK; 168 169 /* 170 * Set the clock divider: the hsm_clock rate and this divider 171 * setting will give a 40 kHz CEC clock. 172 */ 173 clk_cnt = cec_rate / CEC_CLOCK_FREQ; 174 value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT; 175 HDMI_WRITE(HDMI_CEC_CNTRL_1, value); 176 177 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 178 } 179 #else 180 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {} 181 #endif 182 183 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder); 184 185 static enum drm_connector_status 186 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force) 187 { 188 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 189 bool connected = false; 190 191 mutex_lock(&vc4_hdmi->mutex); 192 193 WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev)); 194 195 if (vc4_hdmi->hpd_gpio) { 196 if (gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio)) 197 connected = true; 198 } else { 199 unsigned long flags; 200 u32 hotplug; 201 202 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 203 hotplug = HDMI_READ(HDMI_HOTPLUG); 204 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 205 206 if (hotplug & VC4_HDMI_HOTPLUG_CONNECTED) 207 connected = true; 208 } 209 210 if (connected) { 211 if (connector->status != connector_status_connected) { 212 struct edid *edid = drm_get_edid(connector, vc4_hdmi->ddc); 213 214 if (edid) { 215 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid); 216 vc4_hdmi->encoder.hdmi_monitor = drm_detect_hdmi_monitor(edid); 217 kfree(edid); 218 } 219 } 220 221 vc4_hdmi_enable_scrambling(&vc4_hdmi->encoder.base.base); 222 pm_runtime_put(&vc4_hdmi->pdev->dev); 223 mutex_unlock(&vc4_hdmi->mutex); 224 return connector_status_connected; 225 } 226 227 cec_phys_addr_invalidate(vc4_hdmi->cec_adap); 228 pm_runtime_put(&vc4_hdmi->pdev->dev); 229 mutex_unlock(&vc4_hdmi->mutex); 230 return connector_status_disconnected; 231 } 232 233 static void vc4_hdmi_connector_destroy(struct drm_connector *connector) 234 { 235 drm_connector_unregister(connector); 236 drm_connector_cleanup(connector); 237 } 238 239 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector) 240 { 241 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 242 struct vc4_hdmi_encoder *vc4_encoder = &vc4_hdmi->encoder; 243 int ret = 0; 244 struct edid *edid; 245 246 mutex_lock(&vc4_hdmi->mutex); 247 248 edid = drm_get_edid(connector, vc4_hdmi->ddc); 249 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid); 250 if (!edid) { 251 ret = -ENODEV; 252 goto out; 253 } 254 255 vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid); 256 257 drm_connector_update_edid_property(connector, edid); 258 ret = drm_add_edid_modes(connector, edid); 259 kfree(edid); 260 261 if (vc4_hdmi->disable_4kp60) { 262 struct drm_device *drm = connector->dev; 263 struct drm_display_mode *mode; 264 265 list_for_each_entry(mode, &connector->probed_modes, head) { 266 if (vc4_hdmi_mode_needs_scrambling(mode)) { 267 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz."); 268 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60."); 269 } 270 } 271 } 272 273 out: 274 mutex_unlock(&vc4_hdmi->mutex); 275 276 return ret; 277 } 278 279 static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector, 280 struct drm_atomic_state *state) 281 { 282 struct drm_connector_state *old_state = 283 drm_atomic_get_old_connector_state(state, connector); 284 struct drm_connector_state *new_state = 285 drm_atomic_get_new_connector_state(state, connector); 286 struct drm_crtc *crtc = new_state->crtc; 287 288 if (!crtc) 289 return 0; 290 291 if (old_state->colorspace != new_state->colorspace || 292 !drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) { 293 struct drm_crtc_state *crtc_state; 294 295 crtc_state = drm_atomic_get_crtc_state(state, crtc); 296 if (IS_ERR(crtc_state)) 297 return PTR_ERR(crtc_state); 298 299 crtc_state->mode_changed = true; 300 } 301 302 return 0; 303 } 304 305 static void vc4_hdmi_connector_reset(struct drm_connector *connector) 306 { 307 struct vc4_hdmi_connector_state *old_state = 308 conn_state_to_vc4_hdmi_conn_state(connector->state); 309 struct vc4_hdmi_connector_state *new_state = 310 kzalloc(sizeof(*new_state), GFP_KERNEL); 311 312 if (connector->state) 313 __drm_atomic_helper_connector_destroy_state(connector->state); 314 315 kfree(old_state); 316 __drm_atomic_helper_connector_reset(connector, &new_state->base); 317 318 if (!new_state) 319 return; 320 321 new_state->base.max_bpc = 8; 322 new_state->base.max_requested_bpc = 8; 323 drm_atomic_helper_connector_tv_reset(connector); 324 } 325 326 static struct drm_connector_state * 327 vc4_hdmi_connector_duplicate_state(struct drm_connector *connector) 328 { 329 struct drm_connector_state *conn_state = connector->state; 330 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state); 331 struct vc4_hdmi_connector_state *new_state; 332 333 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL); 334 if (!new_state) 335 return NULL; 336 337 new_state->pixel_rate = vc4_state->pixel_rate; 338 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base); 339 340 return &new_state->base; 341 } 342 343 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = { 344 .detect = vc4_hdmi_connector_detect, 345 .fill_modes = drm_helper_probe_single_connector_modes, 346 .destroy = vc4_hdmi_connector_destroy, 347 .reset = vc4_hdmi_connector_reset, 348 .atomic_duplicate_state = vc4_hdmi_connector_duplicate_state, 349 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 350 }; 351 352 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = { 353 .get_modes = vc4_hdmi_connector_get_modes, 354 .atomic_check = vc4_hdmi_connector_atomic_check, 355 }; 356 357 static int vc4_hdmi_connector_init(struct drm_device *dev, 358 struct vc4_hdmi *vc4_hdmi) 359 { 360 struct drm_connector *connector = &vc4_hdmi->connector; 361 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base; 362 int ret; 363 364 drm_connector_init_with_ddc(dev, connector, 365 &vc4_hdmi_connector_funcs, 366 DRM_MODE_CONNECTOR_HDMIA, 367 vc4_hdmi->ddc); 368 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs); 369 370 /* 371 * Some of the properties below require access to state, like bpc. 372 * Allocate some default initial connector state with our reset helper. 373 */ 374 if (connector->funcs->reset) 375 connector->funcs->reset(connector); 376 377 /* Create and attach TV margin props to this connector. */ 378 ret = drm_mode_create_tv_margin_properties(dev); 379 if (ret) 380 return ret; 381 382 ret = drm_mode_create_hdmi_colorspace_property(connector); 383 if (ret) 384 return ret; 385 386 drm_connector_attach_colorspace_property(connector); 387 drm_connector_attach_tv_margin_properties(connector); 388 drm_connector_attach_max_bpc_property(connector, 8, 12); 389 390 connector->polled = (DRM_CONNECTOR_POLL_CONNECT | 391 DRM_CONNECTOR_POLL_DISCONNECT); 392 393 connector->interlace_allowed = 1; 394 connector->doublescan_allowed = 0; 395 396 if (vc4_hdmi->variant->supports_hdr) 397 drm_connector_attach_hdr_output_metadata_property(connector); 398 399 drm_connector_attach_encoder(connector, encoder); 400 401 return 0; 402 } 403 404 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder, 405 enum hdmi_infoframe_type type, 406 bool poll) 407 { 408 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 409 u32 packet_id = type - 0x80; 410 unsigned long flags; 411 412 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 413 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 414 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id)); 415 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 416 417 if (!poll) 418 return 0; 419 420 return wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) & 421 BIT(packet_id)), 100); 422 } 423 424 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder, 425 union hdmi_infoframe *frame) 426 { 427 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 428 u32 packet_id = frame->any.type - 0x80; 429 const struct vc4_hdmi_register *ram_packet_start = 430 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START]; 431 u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id; 432 void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi, 433 ram_packet_start->reg); 434 uint8_t buffer[VC4_HDMI_PACKET_STRIDE]; 435 unsigned long flags; 436 ssize_t len, i; 437 int ret; 438 439 WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) & 440 VC4_HDMI_RAM_PACKET_ENABLE), 441 "Packet RAM has to be on to store the packet."); 442 443 len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer)); 444 if (len < 0) 445 return; 446 447 ret = vc4_hdmi_stop_packet(encoder, frame->any.type, true); 448 if (ret) { 449 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret); 450 return; 451 } 452 453 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 454 455 for (i = 0; i < len; i += 7) { 456 writel(buffer[i + 0] << 0 | 457 buffer[i + 1] << 8 | 458 buffer[i + 2] << 16, 459 base + packet_reg); 460 packet_reg += 4; 461 462 writel(buffer[i + 3] << 0 | 463 buffer[i + 4] << 8 | 464 buffer[i + 5] << 16 | 465 buffer[i + 6] << 24, 466 base + packet_reg); 467 packet_reg += 4; 468 } 469 470 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 471 HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id)); 472 473 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 474 475 ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) & 476 BIT(packet_id)), 100); 477 if (ret) 478 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret); 479 } 480 481 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder) 482 { 483 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 484 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 485 struct drm_connector *connector = &vc4_hdmi->connector; 486 struct drm_connector_state *cstate = connector->state; 487 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 488 union hdmi_infoframe frame; 489 int ret; 490 491 lockdep_assert_held(&vc4_hdmi->mutex); 492 493 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, 494 connector, mode); 495 if (ret < 0) { 496 DRM_ERROR("couldn't fill AVI infoframe\n"); 497 return; 498 } 499 500 drm_hdmi_avi_infoframe_quant_range(&frame.avi, 501 connector, mode, 502 vc4_encoder->limited_rgb_range ? 503 HDMI_QUANTIZATION_RANGE_LIMITED : 504 HDMI_QUANTIZATION_RANGE_FULL); 505 drm_hdmi_avi_infoframe_colorspace(&frame.avi, cstate); 506 drm_hdmi_avi_infoframe_bars(&frame.avi, cstate); 507 508 vc4_hdmi_write_infoframe(encoder, &frame); 509 } 510 511 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder) 512 { 513 union hdmi_infoframe frame; 514 int ret; 515 516 ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore"); 517 if (ret < 0) { 518 DRM_ERROR("couldn't fill SPD infoframe\n"); 519 return; 520 } 521 522 frame.spd.sdi = HDMI_SPD_SDI_PC; 523 524 vc4_hdmi_write_infoframe(encoder, &frame); 525 } 526 527 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder) 528 { 529 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 530 struct hdmi_audio_infoframe *audio = &vc4_hdmi->audio.infoframe; 531 union hdmi_infoframe frame; 532 533 memcpy(&frame.audio, audio, sizeof(*audio)); 534 vc4_hdmi_write_infoframe(encoder, &frame); 535 } 536 537 static void vc4_hdmi_set_hdr_infoframe(struct drm_encoder *encoder) 538 { 539 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 540 struct drm_connector *connector = &vc4_hdmi->connector; 541 struct drm_connector_state *conn_state = connector->state; 542 union hdmi_infoframe frame; 543 544 lockdep_assert_held(&vc4_hdmi->mutex); 545 546 if (!vc4_hdmi->variant->supports_hdr) 547 return; 548 549 if (!conn_state->hdr_output_metadata) 550 return; 551 552 if (drm_hdmi_infoframe_set_hdr_metadata(&frame.drm, conn_state)) 553 return; 554 555 vc4_hdmi_write_infoframe(encoder, &frame); 556 } 557 558 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder) 559 { 560 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 561 562 lockdep_assert_held(&vc4_hdmi->mutex); 563 564 vc4_hdmi_set_avi_infoframe(encoder); 565 vc4_hdmi_set_spd_infoframe(encoder); 566 /* 567 * If audio was streaming, then we need to reenabled the audio 568 * infoframe here during encoder_enable. 569 */ 570 if (vc4_hdmi->audio.streaming) 571 vc4_hdmi_set_audio_infoframe(encoder); 572 573 vc4_hdmi_set_hdr_infoframe(encoder); 574 } 575 576 static bool vc4_hdmi_supports_scrambling(struct drm_encoder *encoder, 577 struct drm_display_mode *mode) 578 { 579 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 580 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 581 struct drm_display_info *display = &vc4_hdmi->connector.display_info; 582 583 lockdep_assert_held(&vc4_hdmi->mutex); 584 585 if (!vc4_encoder->hdmi_monitor) 586 return false; 587 588 if (!display->hdmi.scdc.supported || 589 !display->hdmi.scdc.scrambling.supported) 590 return false; 591 592 return true; 593 } 594 595 #define SCRAMBLING_POLLING_DELAY_MS 1000 596 597 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder) 598 { 599 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 600 struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 601 unsigned long flags; 602 603 lockdep_assert_held(&vc4_hdmi->mutex); 604 605 if (!vc4_hdmi_supports_scrambling(encoder, mode)) 606 return; 607 608 if (!vc4_hdmi_mode_needs_scrambling(mode)) 609 return; 610 611 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true); 612 drm_scdc_set_scrambling(vc4_hdmi->ddc, true); 613 614 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 615 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) | 616 VC5_HDMI_SCRAMBLER_CTL_ENABLE); 617 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 618 619 vc4_hdmi->scdc_enabled = true; 620 621 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work, 622 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS)); 623 } 624 625 static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder) 626 { 627 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 628 unsigned long flags; 629 630 lockdep_assert_held(&vc4_hdmi->mutex); 631 632 if (!vc4_hdmi->scdc_enabled) 633 return; 634 635 vc4_hdmi->scdc_enabled = false; 636 637 if (delayed_work_pending(&vc4_hdmi->scrambling_work)) 638 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work); 639 640 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 641 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) & 642 ~VC5_HDMI_SCRAMBLER_CTL_ENABLE); 643 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 644 645 drm_scdc_set_scrambling(vc4_hdmi->ddc, false); 646 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, false); 647 } 648 649 static void vc4_hdmi_scrambling_wq(struct work_struct *work) 650 { 651 struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work), 652 struct vc4_hdmi, 653 scrambling_work); 654 655 if (drm_scdc_get_scrambling_status(vc4_hdmi->ddc)) 656 return; 657 658 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true); 659 drm_scdc_set_scrambling(vc4_hdmi->ddc, true); 660 661 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work, 662 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS)); 663 } 664 665 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder, 666 struct drm_atomic_state *state) 667 { 668 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 669 unsigned long flags; 670 671 mutex_lock(&vc4_hdmi->mutex); 672 673 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 674 675 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0); 676 677 HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB); 678 679 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 680 681 mdelay(1); 682 683 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 684 HDMI_WRITE(HDMI_VID_CTL, 685 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE); 686 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 687 688 vc4_hdmi_disable_scrambling(encoder); 689 690 mutex_unlock(&vc4_hdmi->mutex); 691 } 692 693 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder, 694 struct drm_atomic_state *state) 695 { 696 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 697 unsigned long flags; 698 int ret; 699 700 mutex_lock(&vc4_hdmi->mutex); 701 702 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 703 HDMI_WRITE(HDMI_VID_CTL, 704 HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX); 705 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 706 707 if (vc4_hdmi->variant->phy_disable) 708 vc4_hdmi->variant->phy_disable(vc4_hdmi); 709 710 clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock); 711 clk_disable_unprepare(vc4_hdmi->pixel_clock); 712 713 ret = pm_runtime_put(&vc4_hdmi->pdev->dev); 714 if (ret < 0) 715 DRM_ERROR("Failed to release power domain: %d\n", ret); 716 717 mutex_unlock(&vc4_hdmi->mutex); 718 } 719 720 static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder) 721 { 722 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 723 724 mutex_lock(&vc4_hdmi->mutex); 725 vc4_hdmi->output_enabled = false; 726 mutex_unlock(&vc4_hdmi->mutex); 727 } 728 729 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable) 730 { 731 unsigned long flags; 732 u32 csc_ctl; 733 734 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 735 736 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR, 737 VC4_HD_CSC_CTL_ORDER); 738 739 if (enable) { 740 /* CEA VICs other than #1 requre limited range RGB 741 * output unless overridden by an AVI infoframe. 742 * Apply a colorspace conversion to squash 0-255 down 743 * to 16-235. The matrix here is: 744 * 745 * [ 0 0 0.8594 16] 746 * [ 0 0.8594 0 16] 747 * [ 0.8594 0 0 16] 748 * [ 0 0 0 1] 749 */ 750 csc_ctl |= VC4_HD_CSC_CTL_ENABLE; 751 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC; 752 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM, 753 VC4_HD_CSC_CTL_MODE); 754 755 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000); 756 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0); 757 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000); 758 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000); 759 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0); 760 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000); 761 } 762 763 /* The RGB order applies even when CSC is disabled. */ 764 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl); 765 766 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 767 } 768 769 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, bool enable) 770 { 771 unsigned long flags; 772 u32 csc_ctl; 773 774 csc_ctl = 0x07; /* RGB_CONVERT_MODE = custom matrix, || USE_RGB_TO_YCBCR */ 775 776 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 777 778 if (enable) { 779 /* CEA VICs other than #1 requre limited range RGB 780 * output unless overridden by an AVI infoframe. 781 * Apply a colorspace conversion to squash 0-255 down 782 * to 16-235. The matrix here is: 783 * 784 * [ 0.8594 0 0 16] 785 * [ 0 0.8594 0 16] 786 * [ 0 0 0.8594 16] 787 * [ 0 0 0 1] 788 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets 789 */ 790 HDMI_WRITE(HDMI_CSC_12_11, (0x0000 << 16) | 0x1b80); 791 HDMI_WRITE(HDMI_CSC_14_13, (0x0400 << 16) | 0x0000); 792 HDMI_WRITE(HDMI_CSC_22_21, (0x1b80 << 16) | 0x0000); 793 HDMI_WRITE(HDMI_CSC_24_23, (0x0400 << 16) | 0x0000); 794 HDMI_WRITE(HDMI_CSC_32_31, (0x0000 << 16) | 0x0000); 795 HDMI_WRITE(HDMI_CSC_34_33, (0x0400 << 16) | 0x1b80); 796 } else { 797 /* Still use the matrix for full range, but make it unity. 798 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets 799 */ 800 HDMI_WRITE(HDMI_CSC_12_11, (0x0000 << 16) | 0x2000); 801 HDMI_WRITE(HDMI_CSC_14_13, (0x0000 << 16) | 0x0000); 802 HDMI_WRITE(HDMI_CSC_22_21, (0x2000 << 16) | 0x0000); 803 HDMI_WRITE(HDMI_CSC_24_23, (0x0000 << 16) | 0x0000); 804 HDMI_WRITE(HDMI_CSC_32_31, (0x0000 << 16) | 0x0000); 805 HDMI_WRITE(HDMI_CSC_34_33, (0x0000 << 16) | 0x2000); 806 } 807 808 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl); 809 810 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 811 } 812 813 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi, 814 struct drm_connector_state *state, 815 struct drm_display_mode *mode) 816 { 817 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 818 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 819 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 820 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 821 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 822 VC4_HDMI_VERTA_VSP) | 823 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 824 VC4_HDMI_VERTA_VFP) | 825 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL)); 826 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 827 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end, 828 VC4_HDMI_VERTB_VBP)); 829 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 830 VC4_SET_FIELD(mode->crtc_vtotal - 831 mode->crtc_vsync_end - 832 interlaced, 833 VC4_HDMI_VERTB_VBP)); 834 unsigned long flags; 835 836 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 837 838 HDMI_WRITE(HDMI_HORZA, 839 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) | 840 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) | 841 VC4_SET_FIELD(mode->hdisplay * pixel_rep, 842 VC4_HDMI_HORZA_HAP)); 843 844 HDMI_WRITE(HDMI_HORZB, 845 VC4_SET_FIELD((mode->htotal - 846 mode->hsync_end) * pixel_rep, 847 VC4_HDMI_HORZB_HBP) | 848 VC4_SET_FIELD((mode->hsync_end - 849 mode->hsync_start) * pixel_rep, 850 VC4_HDMI_HORZB_HSP) | 851 VC4_SET_FIELD((mode->hsync_start - 852 mode->hdisplay) * pixel_rep, 853 VC4_HDMI_HORZB_HFP)); 854 855 HDMI_WRITE(HDMI_VERTA0, verta); 856 HDMI_WRITE(HDMI_VERTA1, verta); 857 858 HDMI_WRITE(HDMI_VERTB0, vertb_even); 859 HDMI_WRITE(HDMI_VERTB1, vertb); 860 861 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 862 } 863 864 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi, 865 struct drm_connector_state *state, 866 struct drm_display_mode *mode) 867 { 868 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 869 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 870 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 871 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 872 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 873 VC5_HDMI_VERTA_VSP) | 874 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 875 VC5_HDMI_VERTA_VFP) | 876 VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL)); 877 u32 vertb = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) | 878 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end, 879 VC4_HDMI_VERTB_VBP)); 880 u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) | 881 VC4_SET_FIELD(mode->crtc_vtotal - 882 mode->crtc_vsync_end - 883 interlaced, 884 VC4_HDMI_VERTB_VBP)); 885 unsigned long flags; 886 unsigned char gcp; 887 bool gcp_en; 888 u32 reg; 889 890 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 891 892 HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, 0x354021); 893 HDMI_WRITE(HDMI_HORZA, 894 (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) | 895 (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) | 896 VC4_SET_FIELD(mode->hdisplay * pixel_rep, 897 VC5_HDMI_HORZA_HAP) | 898 VC4_SET_FIELD((mode->hsync_start - 899 mode->hdisplay) * pixel_rep, 900 VC5_HDMI_HORZA_HFP)); 901 902 HDMI_WRITE(HDMI_HORZB, 903 VC4_SET_FIELD((mode->htotal - 904 mode->hsync_end) * pixel_rep, 905 VC5_HDMI_HORZB_HBP) | 906 VC4_SET_FIELD((mode->hsync_end - 907 mode->hsync_start) * pixel_rep, 908 VC5_HDMI_HORZB_HSP)); 909 910 HDMI_WRITE(HDMI_VERTA0, verta); 911 HDMI_WRITE(HDMI_VERTA1, verta); 912 913 HDMI_WRITE(HDMI_VERTB0, vertb_even); 914 HDMI_WRITE(HDMI_VERTB1, vertb); 915 916 switch (state->max_bpc) { 917 case 12: 918 gcp = 6; 919 gcp_en = true; 920 break; 921 case 10: 922 gcp = 5; 923 gcp_en = true; 924 break; 925 case 8: 926 default: 927 gcp = 4; 928 gcp_en = false; 929 break; 930 } 931 932 reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1); 933 reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK | 934 VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK); 935 reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) | 936 VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH); 937 HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg); 938 939 reg = HDMI_READ(HDMI_GCP_WORD_1); 940 reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK; 941 reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1); 942 HDMI_WRITE(HDMI_GCP_WORD_1, reg); 943 944 reg = HDMI_READ(HDMI_GCP_CONFIG); 945 reg &= ~VC5_HDMI_GCP_CONFIG_GCP_ENABLE; 946 reg |= gcp_en ? VC5_HDMI_GCP_CONFIG_GCP_ENABLE : 0; 947 HDMI_WRITE(HDMI_GCP_CONFIG, reg); 948 949 HDMI_WRITE(HDMI_CLOCK_STOP, 0); 950 951 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 952 } 953 954 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi) 955 { 956 unsigned long flags; 957 u32 drift; 958 int ret; 959 960 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 961 962 drift = HDMI_READ(HDMI_FIFO_CTL); 963 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK; 964 965 HDMI_WRITE(HDMI_FIFO_CTL, 966 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 967 HDMI_WRITE(HDMI_FIFO_CTL, 968 drift | VC4_HDMI_FIFO_CTL_RECENTER); 969 970 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 971 972 usleep_range(1000, 1100); 973 974 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 975 976 HDMI_WRITE(HDMI_FIFO_CTL, 977 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 978 HDMI_WRITE(HDMI_FIFO_CTL, 979 drift | VC4_HDMI_FIFO_CTL_RECENTER); 980 981 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 982 983 ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) & 984 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1); 985 WARN_ONCE(ret, "Timeout waiting for " 986 "VC4_HDMI_FIFO_CTL_RECENTER_DONE"); 987 } 988 989 static struct drm_connector_state * 990 vc4_hdmi_encoder_get_connector_state(struct drm_encoder *encoder, 991 struct drm_atomic_state *state) 992 { 993 struct drm_connector_state *conn_state; 994 struct drm_connector *connector; 995 unsigned int i; 996 997 for_each_new_connector_in_state(state, connector, conn_state, i) { 998 if (conn_state->best_encoder == encoder) 999 return conn_state; 1000 } 1001 1002 return NULL; 1003 } 1004 1005 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder, 1006 struct drm_atomic_state *state) 1007 { 1008 struct drm_connector_state *conn_state = 1009 vc4_hdmi_encoder_get_connector_state(encoder, state); 1010 struct vc4_hdmi_connector_state *vc4_conn_state = 1011 conn_state_to_vc4_hdmi_conn_state(conn_state); 1012 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1013 struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1014 unsigned long pixel_rate = vc4_conn_state->pixel_rate; 1015 unsigned long bvb_rate, hsm_rate; 1016 unsigned long flags; 1017 int ret; 1018 1019 mutex_lock(&vc4_hdmi->mutex); 1020 1021 /* 1022 * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must 1023 * be faster than pixel clock, infinitesimally faster, tested in 1024 * simulation. Otherwise, exact value is unimportant for HDMI 1025 * operation." This conflicts with bcm2835's vc4 documentation, which 1026 * states HSM's clock has to be at least 108% of the pixel clock. 1027 * 1028 * Real life tests reveal that vc4's firmware statement holds up, and 1029 * users are able to use pixel clocks closer to HSM's, namely for 1030 * 1920x1200@60Hz. So it was decided to have leave a 1% margin between 1031 * both clocks. Which, for RPi0-3 implies a maximum pixel clock of 1032 * 162MHz. 1033 * 1034 * Additionally, the AXI clock needs to be at least 25% of 1035 * pixel clock, but HSM ends up being the limiting factor. 1036 */ 1037 hsm_rate = max_t(unsigned long, 120000000, (pixel_rate / 100) * 101); 1038 ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate); 1039 if (ret) { 1040 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret); 1041 goto out; 1042 } 1043 1044 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev); 1045 if (ret < 0) { 1046 DRM_ERROR("Failed to retain power domain: %d\n", ret); 1047 goto out; 1048 } 1049 1050 ret = clk_set_rate(vc4_hdmi->pixel_clock, pixel_rate); 1051 if (ret) { 1052 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret); 1053 goto err_put_runtime_pm; 1054 } 1055 1056 ret = clk_prepare_enable(vc4_hdmi->pixel_clock); 1057 if (ret) { 1058 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret); 1059 goto err_put_runtime_pm; 1060 } 1061 1062 1063 vc4_hdmi_cec_update_clk_div(vc4_hdmi); 1064 1065 if (pixel_rate > 297000000) 1066 bvb_rate = 300000000; 1067 else if (pixel_rate > 148500000) 1068 bvb_rate = 150000000; 1069 else 1070 bvb_rate = 75000000; 1071 1072 ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate); 1073 if (ret) { 1074 DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret); 1075 goto err_disable_pixel_clock; 1076 } 1077 1078 ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock); 1079 if (ret) { 1080 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret); 1081 goto err_disable_pixel_clock; 1082 } 1083 1084 if (vc4_hdmi->variant->phy_init) 1085 vc4_hdmi->variant->phy_init(vc4_hdmi, vc4_conn_state); 1086 1087 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1088 1089 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1090 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 1091 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT | 1092 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS); 1093 1094 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1095 1096 if (vc4_hdmi->variant->set_timings) 1097 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode); 1098 1099 mutex_unlock(&vc4_hdmi->mutex); 1100 1101 return; 1102 1103 err_disable_pixel_clock: 1104 clk_disable_unprepare(vc4_hdmi->pixel_clock); 1105 err_put_runtime_pm: 1106 pm_runtime_put(&vc4_hdmi->pdev->dev); 1107 out: 1108 mutex_unlock(&vc4_hdmi->mutex); 1109 return; 1110 } 1111 1112 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder, 1113 struct drm_atomic_state *state) 1114 { 1115 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1116 struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1117 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 1118 unsigned long flags; 1119 1120 mutex_lock(&vc4_hdmi->mutex); 1121 1122 if (vc4_encoder->hdmi_monitor && 1123 drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_LIMITED) { 1124 if (vc4_hdmi->variant->csc_setup) 1125 vc4_hdmi->variant->csc_setup(vc4_hdmi, true); 1126 1127 vc4_encoder->limited_rgb_range = true; 1128 } else { 1129 if (vc4_hdmi->variant->csc_setup) 1130 vc4_hdmi->variant->csc_setup(vc4_hdmi, false); 1131 1132 vc4_encoder->limited_rgb_range = false; 1133 } 1134 1135 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1136 HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N); 1137 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1138 1139 mutex_unlock(&vc4_hdmi->mutex); 1140 } 1141 1142 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder, 1143 struct drm_atomic_state *state) 1144 { 1145 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1146 struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1147 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 1148 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 1149 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 1150 unsigned long flags; 1151 int ret; 1152 1153 mutex_lock(&vc4_hdmi->mutex); 1154 1155 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1156 1157 HDMI_WRITE(HDMI_VID_CTL, 1158 VC4_HD_VID_CTL_ENABLE | 1159 VC4_HD_VID_CTL_CLRRGB | 1160 VC4_HD_VID_CTL_UNDERFLOW_ENABLE | 1161 VC4_HD_VID_CTL_FRAME_COUNTER_RESET | 1162 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) | 1163 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW)); 1164 1165 HDMI_WRITE(HDMI_VID_CTL, 1166 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX); 1167 1168 if (vc4_encoder->hdmi_monitor) { 1169 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1170 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 1171 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 1172 1173 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1174 1175 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1176 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000); 1177 WARN_ONCE(ret, "Timeout waiting for " 1178 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 1179 } else { 1180 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 1181 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & 1182 ~(VC4_HDMI_RAM_PACKET_ENABLE)); 1183 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1184 HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1185 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 1186 1187 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1188 1189 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1190 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000); 1191 WARN_ONCE(ret, "Timeout waiting for " 1192 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 1193 } 1194 1195 if (vc4_encoder->hdmi_monitor) { 1196 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1197 1198 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1199 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE)); 1200 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1201 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 1202 VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT); 1203 1204 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 1205 VC4_HDMI_RAM_PACKET_ENABLE); 1206 1207 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1208 1209 vc4_hdmi_set_infoframes(encoder); 1210 } 1211 1212 vc4_hdmi_recenter_fifo(vc4_hdmi); 1213 vc4_hdmi_enable_scrambling(encoder); 1214 1215 mutex_unlock(&vc4_hdmi->mutex); 1216 } 1217 1218 static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder) 1219 { 1220 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1221 1222 mutex_lock(&vc4_hdmi->mutex); 1223 vc4_hdmi->output_enabled = true; 1224 mutex_unlock(&vc4_hdmi->mutex); 1225 } 1226 1227 static void vc4_hdmi_encoder_atomic_mode_set(struct drm_encoder *encoder, 1228 struct drm_crtc_state *crtc_state, 1229 struct drm_connector_state *conn_state) 1230 { 1231 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1232 1233 mutex_lock(&vc4_hdmi->mutex); 1234 memcpy(&vc4_hdmi->saved_adjusted_mode, 1235 &crtc_state->adjusted_mode, 1236 sizeof(vc4_hdmi->saved_adjusted_mode)); 1237 mutex_unlock(&vc4_hdmi->mutex); 1238 } 1239 1240 #define WIFI_2_4GHz_CH1_MIN_FREQ 2400000000ULL 1241 #define WIFI_2_4GHz_CH1_MAX_FREQ 2422000000ULL 1242 1243 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder, 1244 struct drm_crtc_state *crtc_state, 1245 struct drm_connector_state *conn_state) 1246 { 1247 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state); 1248 struct drm_display_mode *mode = &crtc_state->adjusted_mode; 1249 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1250 unsigned long long pixel_rate = mode->clock * 1000; 1251 unsigned long long tmds_rate; 1252 1253 if (vc4_hdmi->variant->unsupported_odd_h_timings && 1254 ((mode->hdisplay % 2) || (mode->hsync_start % 2) || 1255 (mode->hsync_end % 2) || (mode->htotal % 2))) 1256 return -EINVAL; 1257 1258 /* 1259 * The 1440p@60 pixel rate is in the same range than the first 1260 * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz 1261 * bandwidth). Slightly lower the frequency to bring it out of 1262 * the WiFi range. 1263 */ 1264 tmds_rate = pixel_rate * 10; 1265 if (vc4_hdmi->disable_wifi_frequencies && 1266 (tmds_rate >= WIFI_2_4GHz_CH1_MIN_FREQ && 1267 tmds_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) { 1268 mode->clock = 238560; 1269 pixel_rate = mode->clock * 1000; 1270 } 1271 1272 if (conn_state->max_bpc == 12) { 1273 pixel_rate = pixel_rate * 150; 1274 do_div(pixel_rate, 100); 1275 } else if (conn_state->max_bpc == 10) { 1276 pixel_rate = pixel_rate * 125; 1277 do_div(pixel_rate, 100); 1278 } 1279 1280 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 1281 pixel_rate = pixel_rate * 2; 1282 1283 if (pixel_rate > vc4_hdmi->variant->max_pixel_clock) 1284 return -EINVAL; 1285 1286 if (vc4_hdmi->disable_4kp60 && (pixel_rate > HDMI_14_MAX_TMDS_CLK)) 1287 return -EINVAL; 1288 1289 vc4_state->pixel_rate = pixel_rate; 1290 1291 return 0; 1292 } 1293 1294 static enum drm_mode_status 1295 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder, 1296 const struct drm_display_mode *mode) 1297 { 1298 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1299 1300 if (vc4_hdmi->variant->unsupported_odd_h_timings && 1301 ((mode->hdisplay % 2) || (mode->hsync_start % 2) || 1302 (mode->hsync_end % 2) || (mode->htotal % 2))) 1303 return MODE_H_ILLEGAL; 1304 1305 if ((mode->clock * 1000) > vc4_hdmi->variant->max_pixel_clock) 1306 return MODE_CLOCK_HIGH; 1307 1308 if (vc4_hdmi->disable_4kp60 && vc4_hdmi_mode_needs_scrambling(mode)) 1309 return MODE_CLOCK_HIGH; 1310 1311 return MODE_OK; 1312 } 1313 1314 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = { 1315 .atomic_check = vc4_hdmi_encoder_atomic_check, 1316 .atomic_mode_set = vc4_hdmi_encoder_atomic_mode_set, 1317 .mode_valid = vc4_hdmi_encoder_mode_valid, 1318 .disable = vc4_hdmi_encoder_disable, 1319 .enable = vc4_hdmi_encoder_enable, 1320 }; 1321 1322 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask) 1323 { 1324 int i; 1325 u32 channel_map = 0; 1326 1327 for (i = 0; i < 8; i++) { 1328 if (channel_mask & BIT(i)) 1329 channel_map |= i << (3 * i); 1330 } 1331 return channel_map; 1332 } 1333 1334 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask) 1335 { 1336 int i; 1337 u32 channel_map = 0; 1338 1339 for (i = 0; i < 8; i++) { 1340 if (channel_mask & BIT(i)) 1341 channel_map |= i << (4 * i); 1342 } 1343 return channel_map; 1344 } 1345 1346 /* HDMI audio codec callbacks */ 1347 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi, 1348 unsigned int samplerate) 1349 { 1350 u32 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock); 1351 unsigned long flags; 1352 unsigned long n, m; 1353 1354 rational_best_approximation(hsm_clock, samplerate, 1355 VC4_HD_MAI_SMP_N_MASK >> 1356 VC4_HD_MAI_SMP_N_SHIFT, 1357 (VC4_HD_MAI_SMP_M_MASK >> 1358 VC4_HD_MAI_SMP_M_SHIFT) + 1, 1359 &n, &m); 1360 1361 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1362 HDMI_WRITE(HDMI_MAI_SMP, 1363 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) | 1364 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M)); 1365 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1366 } 1367 1368 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi, unsigned int samplerate) 1369 { 1370 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1371 u32 n, cts; 1372 u64 tmp; 1373 1374 lockdep_assert_held(&vc4_hdmi->mutex); 1375 lockdep_assert_held(&vc4_hdmi->hw_lock); 1376 1377 n = 128 * samplerate / 1000; 1378 tmp = (u64)(mode->clock * 1000) * n; 1379 do_div(tmp, 128 * samplerate); 1380 cts = tmp; 1381 1382 HDMI_WRITE(HDMI_CRP_CFG, 1383 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN | 1384 VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N)); 1385 1386 /* 1387 * We could get slightly more accurate clocks in some cases by 1388 * providing a CTS_1 value. The two CTS values are alternated 1389 * between based on the period fields 1390 */ 1391 HDMI_WRITE(HDMI_CTS_0, cts); 1392 HDMI_WRITE(HDMI_CTS_1, cts); 1393 } 1394 1395 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai) 1396 { 1397 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai); 1398 1399 return snd_soc_card_get_drvdata(card); 1400 } 1401 1402 static bool vc4_hdmi_audio_can_stream(struct vc4_hdmi *vc4_hdmi) 1403 { 1404 lockdep_assert_held(&vc4_hdmi->mutex); 1405 1406 /* 1407 * If the controller is disabled, prevent any ALSA output. 1408 */ 1409 if (!vc4_hdmi->output_enabled) 1410 return false; 1411 1412 /* 1413 * If the encoder is currently in DVI mode, treat the codec DAI 1414 * as missing. 1415 */ 1416 if (!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) & VC4_HDMI_RAM_PACKET_ENABLE)) 1417 return false; 1418 1419 return true; 1420 } 1421 1422 static int vc4_hdmi_audio_startup(struct device *dev, void *data) 1423 { 1424 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 1425 unsigned long flags; 1426 1427 mutex_lock(&vc4_hdmi->mutex); 1428 1429 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) { 1430 mutex_unlock(&vc4_hdmi->mutex); 1431 return -ENODEV; 1432 } 1433 1434 vc4_hdmi->audio.streaming = true; 1435 1436 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1437 HDMI_WRITE(HDMI_MAI_CTL, 1438 VC4_HD_MAI_CTL_RESET | 1439 VC4_HD_MAI_CTL_FLUSH | 1440 VC4_HD_MAI_CTL_DLATE | 1441 VC4_HD_MAI_CTL_ERRORE | 1442 VC4_HD_MAI_CTL_ERRORF); 1443 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1444 1445 if (vc4_hdmi->variant->phy_rng_enable) 1446 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi); 1447 1448 mutex_unlock(&vc4_hdmi->mutex); 1449 1450 return 0; 1451 } 1452 1453 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi) 1454 { 1455 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base; 1456 struct device *dev = &vc4_hdmi->pdev->dev; 1457 unsigned long flags; 1458 int ret; 1459 1460 lockdep_assert_held(&vc4_hdmi->mutex); 1461 1462 vc4_hdmi->audio.streaming = false; 1463 ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO, false); 1464 if (ret) 1465 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret); 1466 1467 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1468 1469 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET); 1470 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF); 1471 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH); 1472 1473 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1474 } 1475 1476 static void vc4_hdmi_audio_shutdown(struct device *dev, void *data) 1477 { 1478 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 1479 unsigned long flags; 1480 1481 mutex_lock(&vc4_hdmi->mutex); 1482 1483 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1484 1485 HDMI_WRITE(HDMI_MAI_CTL, 1486 VC4_HD_MAI_CTL_DLATE | 1487 VC4_HD_MAI_CTL_ERRORE | 1488 VC4_HD_MAI_CTL_ERRORF); 1489 1490 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1491 1492 if (vc4_hdmi->variant->phy_rng_disable) 1493 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi); 1494 1495 vc4_hdmi->audio.streaming = false; 1496 vc4_hdmi_audio_reset(vc4_hdmi); 1497 1498 mutex_unlock(&vc4_hdmi->mutex); 1499 } 1500 1501 static int sample_rate_to_mai_fmt(int samplerate) 1502 { 1503 switch (samplerate) { 1504 case 8000: 1505 return VC4_HDMI_MAI_SAMPLE_RATE_8000; 1506 case 11025: 1507 return VC4_HDMI_MAI_SAMPLE_RATE_11025; 1508 case 12000: 1509 return VC4_HDMI_MAI_SAMPLE_RATE_12000; 1510 case 16000: 1511 return VC4_HDMI_MAI_SAMPLE_RATE_16000; 1512 case 22050: 1513 return VC4_HDMI_MAI_SAMPLE_RATE_22050; 1514 case 24000: 1515 return VC4_HDMI_MAI_SAMPLE_RATE_24000; 1516 case 32000: 1517 return VC4_HDMI_MAI_SAMPLE_RATE_32000; 1518 case 44100: 1519 return VC4_HDMI_MAI_SAMPLE_RATE_44100; 1520 case 48000: 1521 return VC4_HDMI_MAI_SAMPLE_RATE_48000; 1522 case 64000: 1523 return VC4_HDMI_MAI_SAMPLE_RATE_64000; 1524 case 88200: 1525 return VC4_HDMI_MAI_SAMPLE_RATE_88200; 1526 case 96000: 1527 return VC4_HDMI_MAI_SAMPLE_RATE_96000; 1528 case 128000: 1529 return VC4_HDMI_MAI_SAMPLE_RATE_128000; 1530 case 176400: 1531 return VC4_HDMI_MAI_SAMPLE_RATE_176400; 1532 case 192000: 1533 return VC4_HDMI_MAI_SAMPLE_RATE_192000; 1534 default: 1535 return VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED; 1536 } 1537 } 1538 1539 /* HDMI audio codec callbacks */ 1540 static int vc4_hdmi_audio_prepare(struct device *dev, void *data, 1541 struct hdmi_codec_daifmt *daifmt, 1542 struct hdmi_codec_params *params) 1543 { 1544 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 1545 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base; 1546 unsigned int sample_rate = params->sample_rate; 1547 unsigned int channels = params->channels; 1548 unsigned long flags; 1549 u32 audio_packet_config, channel_mask; 1550 u32 channel_map; 1551 u32 mai_audio_format; 1552 u32 mai_sample_rate; 1553 1554 dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__, 1555 sample_rate, params->sample_width, channels); 1556 1557 mutex_lock(&vc4_hdmi->mutex); 1558 1559 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) { 1560 mutex_unlock(&vc4_hdmi->mutex); 1561 return -EINVAL; 1562 } 1563 1564 vc4_hdmi_audio_set_mai_clock(vc4_hdmi, sample_rate); 1565 1566 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1567 HDMI_WRITE(HDMI_MAI_CTL, 1568 VC4_SET_FIELD(channels, VC4_HD_MAI_CTL_CHNUM) | 1569 VC4_HD_MAI_CTL_WHOLSMP | 1570 VC4_HD_MAI_CTL_CHALIGN | 1571 VC4_HD_MAI_CTL_ENABLE); 1572 1573 mai_sample_rate = sample_rate_to_mai_fmt(sample_rate); 1574 if (params->iec.status[0] & IEC958_AES0_NONAUDIO && 1575 params->channels == 8) 1576 mai_audio_format = VC4_HDMI_MAI_FORMAT_HBR; 1577 else 1578 mai_audio_format = VC4_HDMI_MAI_FORMAT_PCM; 1579 HDMI_WRITE(HDMI_MAI_FMT, 1580 VC4_SET_FIELD(mai_sample_rate, 1581 VC4_HDMI_MAI_FORMAT_SAMPLE_RATE) | 1582 VC4_SET_FIELD(mai_audio_format, 1583 VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT)); 1584 1585 /* The B frame identifier should match the value used by alsa-lib (8) */ 1586 audio_packet_config = 1587 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT | 1588 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS | 1589 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER); 1590 1591 channel_mask = GENMASK(channels - 1, 0); 1592 audio_packet_config |= VC4_SET_FIELD(channel_mask, 1593 VC4_HDMI_AUDIO_PACKET_CEA_MASK); 1594 1595 /* Set the MAI threshold */ 1596 HDMI_WRITE(HDMI_MAI_THR, 1597 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) | 1598 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) | 1599 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQHIGH) | 1600 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQLOW)); 1601 1602 HDMI_WRITE(HDMI_MAI_CONFIG, 1603 VC4_HDMI_MAI_CONFIG_BIT_REVERSE | 1604 VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE | 1605 VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK)); 1606 1607 channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask); 1608 HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map); 1609 HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config); 1610 1611 vc4_hdmi_set_n_cts(vc4_hdmi, sample_rate); 1612 1613 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1614 1615 memcpy(&vc4_hdmi->audio.infoframe, ¶ms->cea, sizeof(params->cea)); 1616 vc4_hdmi_set_audio_infoframe(encoder); 1617 1618 mutex_unlock(&vc4_hdmi->mutex); 1619 1620 return 0; 1621 } 1622 1623 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = { 1624 .name = "vc4-hdmi-cpu-dai-component", 1625 }; 1626 1627 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai) 1628 { 1629 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai); 1630 1631 snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL); 1632 1633 return 0; 1634 } 1635 1636 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = { 1637 .name = "vc4-hdmi-cpu-dai", 1638 .probe = vc4_hdmi_audio_cpu_dai_probe, 1639 .playback = { 1640 .stream_name = "Playback", 1641 .channels_min = 1, 1642 .channels_max = 8, 1643 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 1644 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 1645 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 1646 SNDRV_PCM_RATE_192000, 1647 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 1648 }, 1649 }; 1650 1651 static const struct snd_dmaengine_pcm_config pcm_conf = { 1652 .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx", 1653 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 1654 }; 1655 1656 static int vc4_hdmi_audio_get_eld(struct device *dev, void *data, 1657 uint8_t *buf, size_t len) 1658 { 1659 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 1660 struct drm_connector *connector = &vc4_hdmi->connector; 1661 1662 mutex_lock(&vc4_hdmi->mutex); 1663 memcpy(buf, connector->eld, min(sizeof(connector->eld), len)); 1664 mutex_unlock(&vc4_hdmi->mutex); 1665 1666 return 0; 1667 } 1668 1669 static const struct hdmi_codec_ops vc4_hdmi_codec_ops = { 1670 .get_eld = vc4_hdmi_audio_get_eld, 1671 .prepare = vc4_hdmi_audio_prepare, 1672 .audio_shutdown = vc4_hdmi_audio_shutdown, 1673 .audio_startup = vc4_hdmi_audio_startup, 1674 }; 1675 1676 static struct hdmi_codec_pdata vc4_hdmi_codec_pdata = { 1677 .ops = &vc4_hdmi_codec_ops, 1678 .max_i2s_channels = 8, 1679 .i2s = 1, 1680 }; 1681 1682 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi) 1683 { 1684 const struct vc4_hdmi_register *mai_data = 1685 &vc4_hdmi->variant->registers[HDMI_MAI_DATA]; 1686 struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link; 1687 struct snd_soc_card *card = &vc4_hdmi->audio.card; 1688 struct device *dev = &vc4_hdmi->pdev->dev; 1689 struct platform_device *codec_pdev; 1690 const __be32 *addr; 1691 int index; 1692 int ret; 1693 1694 if (!of_find_property(dev->of_node, "dmas", NULL)) { 1695 dev_warn(dev, 1696 "'dmas' DT property is missing, no HDMI audio\n"); 1697 return 0; 1698 } 1699 1700 if (mai_data->reg != VC4_HD) { 1701 WARN_ONCE(true, "MAI isn't in the HD block\n"); 1702 return -EINVAL; 1703 } 1704 1705 /* 1706 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve 1707 * the bus address specified in the DT, because the physical address 1708 * (the one returned by platform_get_resource()) is not appropriate 1709 * for DMA transfers. 1710 * This VC/MMU should probably be exposed to avoid this kind of hacks. 1711 */ 1712 index = of_property_match_string(dev->of_node, "reg-names", "hd"); 1713 /* Before BCM2711, we don't have a named register range */ 1714 if (index < 0) 1715 index = 1; 1716 1717 addr = of_get_address(dev->of_node, index, NULL, NULL); 1718 1719 vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset; 1720 vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1721 vc4_hdmi->audio.dma_data.maxburst = 2; 1722 1723 ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0); 1724 if (ret) { 1725 dev_err(dev, "Could not register PCM component: %d\n", ret); 1726 return ret; 1727 } 1728 1729 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp, 1730 &vc4_hdmi_audio_cpu_dai_drv, 1); 1731 if (ret) { 1732 dev_err(dev, "Could not register CPU DAI: %d\n", ret); 1733 return ret; 1734 } 1735 1736 codec_pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME, 1737 PLATFORM_DEVID_AUTO, 1738 &vc4_hdmi_codec_pdata, 1739 sizeof(vc4_hdmi_codec_pdata)); 1740 if (IS_ERR(codec_pdev)) { 1741 dev_err(dev, "Couldn't register the HDMI codec: %ld\n", PTR_ERR(codec_pdev)); 1742 return PTR_ERR(codec_pdev); 1743 } 1744 1745 dai_link->cpus = &vc4_hdmi->audio.cpu; 1746 dai_link->codecs = &vc4_hdmi->audio.codec; 1747 dai_link->platforms = &vc4_hdmi->audio.platform; 1748 1749 dai_link->num_cpus = 1; 1750 dai_link->num_codecs = 1; 1751 dai_link->num_platforms = 1; 1752 1753 dai_link->name = "MAI"; 1754 dai_link->stream_name = "MAI PCM"; 1755 dai_link->codecs->dai_name = "i2s-hifi"; 1756 dai_link->cpus->dai_name = dev_name(dev); 1757 dai_link->codecs->name = dev_name(&codec_pdev->dev); 1758 dai_link->platforms->name = dev_name(dev); 1759 1760 card->dai_link = dai_link; 1761 card->num_links = 1; 1762 card->name = vc4_hdmi->variant->card_name; 1763 card->driver_name = "vc4-hdmi"; 1764 card->dev = dev; 1765 card->owner = THIS_MODULE; 1766 1767 /* 1768 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and 1769 * stores a pointer to the snd card object in dev->driver_data. This 1770 * means we cannot use it for something else. The hdmi back-pointer is 1771 * now stored in card->drvdata and should be retrieved with 1772 * snd_soc_card_get_drvdata() if needed. 1773 */ 1774 snd_soc_card_set_drvdata(card, vc4_hdmi); 1775 ret = devm_snd_soc_register_card(dev, card); 1776 if (ret) 1777 dev_err_probe(dev, ret, "Could not register sound card\n"); 1778 1779 return ret; 1780 1781 } 1782 1783 static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv) 1784 { 1785 struct vc4_hdmi *vc4_hdmi = priv; 1786 struct drm_connector *connector = &vc4_hdmi->connector; 1787 struct drm_device *dev = connector->dev; 1788 1789 if (dev && dev->registered) 1790 drm_connector_helper_hpd_irq_event(connector); 1791 1792 return IRQ_HANDLED; 1793 } 1794 1795 static int vc4_hdmi_hotplug_init(struct vc4_hdmi *vc4_hdmi) 1796 { 1797 struct drm_connector *connector = &vc4_hdmi->connector; 1798 struct platform_device *pdev = vc4_hdmi->pdev; 1799 int ret; 1800 1801 if (vc4_hdmi->variant->external_irq_controller) { 1802 unsigned int hpd_con = platform_get_irq_byname(pdev, "hpd-connected"); 1803 unsigned int hpd_rm = platform_get_irq_byname(pdev, "hpd-removed"); 1804 1805 ret = request_threaded_irq(hpd_con, 1806 NULL, 1807 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT, 1808 "vc4 hdmi hpd connected", vc4_hdmi); 1809 if (ret) 1810 return ret; 1811 1812 ret = request_threaded_irq(hpd_rm, 1813 NULL, 1814 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT, 1815 "vc4 hdmi hpd disconnected", vc4_hdmi); 1816 if (ret) { 1817 free_irq(hpd_con, vc4_hdmi); 1818 return ret; 1819 } 1820 1821 connector->polled = DRM_CONNECTOR_POLL_HPD; 1822 } 1823 1824 return 0; 1825 } 1826 1827 static void vc4_hdmi_hotplug_exit(struct vc4_hdmi *vc4_hdmi) 1828 { 1829 struct platform_device *pdev = vc4_hdmi->pdev; 1830 1831 if (vc4_hdmi->variant->external_irq_controller) { 1832 free_irq(platform_get_irq_byname(pdev, "hpd-connected"), vc4_hdmi); 1833 free_irq(platform_get_irq_byname(pdev, "hpd-removed"), vc4_hdmi); 1834 } 1835 } 1836 1837 #ifdef CONFIG_DRM_VC4_HDMI_CEC 1838 static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv) 1839 { 1840 struct vc4_hdmi *vc4_hdmi = priv; 1841 1842 if (vc4_hdmi->cec_rx_msg.len) 1843 cec_received_msg(vc4_hdmi->cec_adap, 1844 &vc4_hdmi->cec_rx_msg); 1845 1846 return IRQ_HANDLED; 1847 } 1848 1849 static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv) 1850 { 1851 struct vc4_hdmi *vc4_hdmi = priv; 1852 1853 if (vc4_hdmi->cec_tx_ok) { 1854 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK, 1855 0, 0, 0, 0); 1856 } else { 1857 /* 1858 * This CEC implementation makes 1 retry, so if we 1859 * get a NACK, then that means it made 2 attempts. 1860 */ 1861 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK, 1862 0, 2, 0, 0); 1863 } 1864 return IRQ_HANDLED; 1865 } 1866 1867 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv) 1868 { 1869 struct vc4_hdmi *vc4_hdmi = priv; 1870 irqreturn_t ret; 1871 1872 if (vc4_hdmi->cec_irq_was_rx) 1873 ret = vc4_cec_irq_handler_rx_thread(irq, priv); 1874 else 1875 ret = vc4_cec_irq_handler_tx_thread(irq, priv); 1876 1877 return ret; 1878 } 1879 1880 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1) 1881 { 1882 struct drm_device *dev = vc4_hdmi->connector.dev; 1883 struct cec_msg *msg = &vc4_hdmi->cec_rx_msg; 1884 unsigned int i; 1885 1886 lockdep_assert_held(&vc4_hdmi->hw_lock); 1887 1888 msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >> 1889 VC4_HDMI_CEC_REC_WRD_CNT_SHIFT); 1890 1891 if (msg->len > 16) { 1892 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len); 1893 return; 1894 } 1895 1896 for (i = 0; i < msg->len; i += 4) { 1897 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2)); 1898 1899 msg->msg[i] = val & 0xff; 1900 msg->msg[i + 1] = (val >> 8) & 0xff; 1901 msg->msg[i + 2] = (val >> 16) & 0xff; 1902 msg->msg[i + 3] = (val >> 24) & 0xff; 1903 } 1904 } 1905 1906 static irqreturn_t vc4_cec_irq_handler_tx_bare_locked(struct vc4_hdmi *vc4_hdmi) 1907 { 1908 u32 cntrl1; 1909 1910 lockdep_assert_held(&vc4_hdmi->hw_lock); 1911 1912 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1); 1913 vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD; 1914 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 1915 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 1916 1917 return IRQ_WAKE_THREAD; 1918 } 1919 1920 static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv) 1921 { 1922 struct vc4_hdmi *vc4_hdmi = priv; 1923 irqreturn_t ret; 1924 1925 spin_lock(&vc4_hdmi->hw_lock); 1926 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi); 1927 spin_unlock(&vc4_hdmi->hw_lock); 1928 1929 return ret; 1930 } 1931 1932 static irqreturn_t vc4_cec_irq_handler_rx_bare_locked(struct vc4_hdmi *vc4_hdmi) 1933 { 1934 u32 cntrl1; 1935 1936 lockdep_assert_held(&vc4_hdmi->hw_lock); 1937 1938 vc4_hdmi->cec_rx_msg.len = 0; 1939 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1); 1940 vc4_cec_read_msg(vc4_hdmi, cntrl1); 1941 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 1942 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 1943 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 1944 1945 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 1946 1947 return IRQ_WAKE_THREAD; 1948 } 1949 1950 static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv) 1951 { 1952 struct vc4_hdmi *vc4_hdmi = priv; 1953 irqreturn_t ret; 1954 1955 spin_lock(&vc4_hdmi->hw_lock); 1956 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi); 1957 spin_unlock(&vc4_hdmi->hw_lock); 1958 1959 return ret; 1960 } 1961 1962 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv) 1963 { 1964 struct vc4_hdmi *vc4_hdmi = priv; 1965 u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS); 1966 irqreturn_t ret; 1967 u32 cntrl5; 1968 1969 if (!(stat & VC4_HDMI_CPU_CEC)) 1970 return IRQ_NONE; 1971 1972 spin_lock(&vc4_hdmi->hw_lock); 1973 cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5); 1974 vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT; 1975 if (vc4_hdmi->cec_irq_was_rx) 1976 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi); 1977 else 1978 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi); 1979 1980 HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC); 1981 spin_unlock(&vc4_hdmi->hw_lock); 1982 1983 return ret; 1984 } 1985 1986 static int vc4_hdmi_cec_enable(struct cec_adapter *adap) 1987 { 1988 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 1989 /* clock period in microseconds */ 1990 const u32 usecs = 1000000 / CEC_CLOCK_FREQ; 1991 unsigned long flags; 1992 u32 val; 1993 int ret; 1994 1995 /* 1996 * NOTE: This function should really take vc4_hdmi->mutex, but doing so 1997 * results in a reentrancy since cec_s_phys_addr_from_edid() called in 1998 * .detect or .get_modes might call .adap_enable, which leads to this 1999 * function being called with that mutex held. 2000 * 2001 * Concurrency is not an issue for the moment since we don't share any 2002 * state with KMS, so we can ignore the lock for now, but we need to 2003 * keep it in mind if we were to change that assumption. 2004 */ 2005 2006 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev); 2007 if (ret) 2008 return ret; 2009 2010 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2011 2012 val = HDMI_READ(HDMI_CEC_CNTRL_5); 2013 val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET | 2014 VC4_HDMI_CEC_CNT_TO_4700_US_MASK | 2015 VC4_HDMI_CEC_CNT_TO_4500_US_MASK); 2016 val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) | 2017 ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT); 2018 2019 HDMI_WRITE(HDMI_CEC_CNTRL_5, val | 2020 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 2021 HDMI_WRITE(HDMI_CEC_CNTRL_5, val); 2022 HDMI_WRITE(HDMI_CEC_CNTRL_2, 2023 ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) | 2024 ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) | 2025 ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) | 2026 ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) | 2027 ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT)); 2028 HDMI_WRITE(HDMI_CEC_CNTRL_3, 2029 ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) | 2030 ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) | 2031 ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) | 2032 ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT)); 2033 HDMI_WRITE(HDMI_CEC_CNTRL_4, 2034 ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) | 2035 ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) | 2036 ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) | 2037 ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT)); 2038 2039 if (!vc4_hdmi->variant->external_irq_controller) 2040 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC); 2041 2042 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2043 2044 return 0; 2045 } 2046 2047 static int vc4_hdmi_cec_disable(struct cec_adapter *adap) 2048 { 2049 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 2050 unsigned long flags; 2051 2052 /* 2053 * NOTE: This function should really take vc4_hdmi->mutex, but doing so 2054 * results in a reentrancy since cec_s_phys_addr_from_edid() called in 2055 * .detect or .get_modes might call .adap_enable, which leads to this 2056 * function being called with that mutex held. 2057 * 2058 * Concurrency is not an issue for the moment since we don't share any 2059 * state with KMS, so we can ignore the lock for now, but we need to 2060 * keep it in mind if we were to change that assumption. 2061 */ 2062 2063 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2064 2065 if (!vc4_hdmi->variant->external_irq_controller) 2066 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC); 2067 2068 HDMI_WRITE(HDMI_CEC_CNTRL_5, HDMI_READ(HDMI_CEC_CNTRL_5) | 2069 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 2070 2071 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2072 2073 pm_runtime_put(&vc4_hdmi->pdev->dev); 2074 2075 return 0; 2076 } 2077 2078 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable) 2079 { 2080 if (enable) 2081 return vc4_hdmi_cec_enable(adap); 2082 else 2083 return vc4_hdmi_cec_disable(adap); 2084 } 2085 2086 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr) 2087 { 2088 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 2089 unsigned long flags; 2090 2091 /* 2092 * NOTE: This function should really take vc4_hdmi->mutex, but doing so 2093 * results in a reentrancy since cec_s_phys_addr_from_edid() called in 2094 * .detect or .get_modes might call .adap_enable, which leads to this 2095 * function being called with that mutex held. 2096 * 2097 * Concurrency is not an issue for the moment since we don't share any 2098 * state with KMS, so we can ignore the lock for now, but we need to 2099 * keep it in mind if we were to change that assumption. 2100 */ 2101 2102 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2103 HDMI_WRITE(HDMI_CEC_CNTRL_1, 2104 (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) | 2105 (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT); 2106 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2107 2108 return 0; 2109 } 2110 2111 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts, 2112 u32 signal_free_time, struct cec_msg *msg) 2113 { 2114 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 2115 struct drm_device *dev = vc4_hdmi->connector.dev; 2116 unsigned long flags; 2117 u32 val; 2118 unsigned int i; 2119 2120 /* 2121 * NOTE: This function should really take vc4_hdmi->mutex, but doing so 2122 * results in a reentrancy since cec_s_phys_addr_from_edid() called in 2123 * .detect or .get_modes might call .adap_enable, which leads to this 2124 * function being called with that mutex held. 2125 * 2126 * Concurrency is not an issue for the moment since we don't share any 2127 * state with KMS, so we can ignore the lock for now, but we need to 2128 * keep it in mind if we were to change that assumption. 2129 */ 2130 2131 if (msg->len > 16) { 2132 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len); 2133 return -ENOMEM; 2134 } 2135 2136 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2137 2138 for (i = 0; i < msg->len; i += 4) 2139 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2), 2140 (msg->msg[i]) | 2141 (msg->msg[i + 1] << 8) | 2142 (msg->msg[i + 2] << 16) | 2143 (msg->msg[i + 3] << 24)); 2144 2145 val = HDMI_READ(HDMI_CEC_CNTRL_1); 2146 val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 2147 HDMI_WRITE(HDMI_CEC_CNTRL_1, val); 2148 val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK; 2149 val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT; 2150 val |= VC4_HDMI_CEC_START_XMIT_BEGIN; 2151 2152 HDMI_WRITE(HDMI_CEC_CNTRL_1, val); 2153 2154 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2155 2156 return 0; 2157 } 2158 2159 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = { 2160 .adap_enable = vc4_hdmi_cec_adap_enable, 2161 .adap_log_addr = vc4_hdmi_cec_adap_log_addr, 2162 .adap_transmit = vc4_hdmi_cec_adap_transmit, 2163 }; 2164 2165 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi) 2166 { 2167 struct cec_connector_info conn_info; 2168 struct platform_device *pdev = vc4_hdmi->pdev; 2169 struct device *dev = &pdev->dev; 2170 unsigned long flags; 2171 u32 value; 2172 int ret; 2173 2174 if (!of_find_property(dev->of_node, "interrupts", NULL)) { 2175 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n"); 2176 return 0; 2177 } 2178 2179 vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops, 2180 vc4_hdmi, "vc4", 2181 CEC_CAP_DEFAULTS | 2182 CEC_CAP_CONNECTOR_INFO, 1); 2183 ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap); 2184 if (ret < 0) 2185 return ret; 2186 2187 cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector); 2188 cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info); 2189 2190 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2191 value = HDMI_READ(HDMI_CEC_CNTRL_1); 2192 /* Set the logical address to Unregistered */ 2193 value |= VC4_HDMI_CEC_ADDR_MASK; 2194 HDMI_WRITE(HDMI_CEC_CNTRL_1, value); 2195 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2196 2197 vc4_hdmi_cec_update_clk_div(vc4_hdmi); 2198 2199 if (vc4_hdmi->variant->external_irq_controller) { 2200 ret = request_threaded_irq(platform_get_irq_byname(pdev, "cec-rx"), 2201 vc4_cec_irq_handler_rx_bare, 2202 vc4_cec_irq_handler_rx_thread, 0, 2203 "vc4 hdmi cec rx", vc4_hdmi); 2204 if (ret) 2205 goto err_delete_cec_adap; 2206 2207 ret = request_threaded_irq(platform_get_irq_byname(pdev, "cec-tx"), 2208 vc4_cec_irq_handler_tx_bare, 2209 vc4_cec_irq_handler_tx_thread, 0, 2210 "vc4 hdmi cec tx", vc4_hdmi); 2211 if (ret) 2212 goto err_remove_cec_rx_handler; 2213 } else { 2214 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2215 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff); 2216 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2217 2218 ret = request_threaded_irq(platform_get_irq(pdev, 0), 2219 vc4_cec_irq_handler, 2220 vc4_cec_irq_handler_thread, 0, 2221 "vc4 hdmi cec", vc4_hdmi); 2222 if (ret) 2223 goto err_delete_cec_adap; 2224 } 2225 2226 ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev); 2227 if (ret < 0) 2228 goto err_remove_handlers; 2229 2230 return 0; 2231 2232 err_remove_handlers: 2233 if (vc4_hdmi->variant->external_irq_controller) 2234 free_irq(platform_get_irq_byname(pdev, "cec-tx"), vc4_hdmi); 2235 else 2236 free_irq(platform_get_irq(pdev, 0), vc4_hdmi); 2237 2238 err_remove_cec_rx_handler: 2239 if (vc4_hdmi->variant->external_irq_controller) 2240 free_irq(platform_get_irq_byname(pdev, "cec-rx"), vc4_hdmi); 2241 2242 err_delete_cec_adap: 2243 cec_delete_adapter(vc4_hdmi->cec_adap); 2244 2245 return ret; 2246 } 2247 2248 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi) 2249 { 2250 struct platform_device *pdev = vc4_hdmi->pdev; 2251 2252 if (vc4_hdmi->variant->external_irq_controller) { 2253 free_irq(platform_get_irq_byname(pdev, "cec-rx"), vc4_hdmi); 2254 free_irq(platform_get_irq_byname(pdev, "cec-tx"), vc4_hdmi); 2255 } else { 2256 free_irq(platform_get_irq(pdev, 0), vc4_hdmi); 2257 } 2258 2259 cec_unregister_adapter(vc4_hdmi->cec_adap); 2260 } 2261 #else 2262 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi) 2263 { 2264 return 0; 2265 } 2266 2267 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi) {}; 2268 2269 #endif 2270 2271 static int vc4_hdmi_build_regset(struct vc4_hdmi *vc4_hdmi, 2272 struct debugfs_regset32 *regset, 2273 enum vc4_hdmi_regs reg) 2274 { 2275 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant; 2276 struct debugfs_reg32 *regs, *new_regs; 2277 unsigned int count = 0; 2278 unsigned int i; 2279 2280 regs = kcalloc(variant->num_registers, sizeof(*regs), 2281 GFP_KERNEL); 2282 if (!regs) 2283 return -ENOMEM; 2284 2285 for (i = 0; i < variant->num_registers; i++) { 2286 const struct vc4_hdmi_register *field = &variant->registers[i]; 2287 2288 if (field->reg != reg) 2289 continue; 2290 2291 regs[count].name = field->name; 2292 regs[count].offset = field->offset; 2293 count++; 2294 } 2295 2296 new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL); 2297 if (!new_regs) 2298 return -ENOMEM; 2299 2300 regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg); 2301 regset->regs = new_regs; 2302 regset->nregs = count; 2303 2304 return 0; 2305 } 2306 2307 static int vc4_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi) 2308 { 2309 struct platform_device *pdev = vc4_hdmi->pdev; 2310 struct device *dev = &pdev->dev; 2311 int ret; 2312 2313 vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0); 2314 if (IS_ERR(vc4_hdmi->hdmicore_regs)) 2315 return PTR_ERR(vc4_hdmi->hdmicore_regs); 2316 2317 vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1); 2318 if (IS_ERR(vc4_hdmi->hd_regs)) 2319 return PTR_ERR(vc4_hdmi->hd_regs); 2320 2321 ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD); 2322 if (ret) 2323 return ret; 2324 2325 ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI); 2326 if (ret) 2327 return ret; 2328 2329 vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel"); 2330 if (IS_ERR(vc4_hdmi->pixel_clock)) { 2331 ret = PTR_ERR(vc4_hdmi->pixel_clock); 2332 if (ret != -EPROBE_DEFER) 2333 DRM_ERROR("Failed to get pixel clock\n"); 2334 return ret; 2335 } 2336 2337 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); 2338 if (IS_ERR(vc4_hdmi->hsm_clock)) { 2339 DRM_ERROR("Failed to get HDMI state machine clock\n"); 2340 return PTR_ERR(vc4_hdmi->hsm_clock); 2341 } 2342 vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock; 2343 vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock; 2344 2345 return 0; 2346 } 2347 2348 static int vc5_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi) 2349 { 2350 struct platform_device *pdev = vc4_hdmi->pdev; 2351 struct device *dev = &pdev->dev; 2352 struct resource *res; 2353 2354 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi"); 2355 if (!res) 2356 return -ENODEV; 2357 2358 vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start, 2359 resource_size(res)); 2360 if (!vc4_hdmi->hdmicore_regs) 2361 return -ENOMEM; 2362 2363 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd"); 2364 if (!res) 2365 return -ENODEV; 2366 2367 vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res)); 2368 if (!vc4_hdmi->hd_regs) 2369 return -ENOMEM; 2370 2371 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec"); 2372 if (!res) 2373 return -ENODEV; 2374 2375 vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res)); 2376 if (!vc4_hdmi->cec_regs) 2377 return -ENOMEM; 2378 2379 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc"); 2380 if (!res) 2381 return -ENODEV; 2382 2383 vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res)); 2384 if (!vc4_hdmi->csc_regs) 2385 return -ENOMEM; 2386 2387 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp"); 2388 if (!res) 2389 return -ENODEV; 2390 2391 vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res)); 2392 if (!vc4_hdmi->dvp_regs) 2393 return -ENOMEM; 2394 2395 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy"); 2396 if (!res) 2397 return -ENODEV; 2398 2399 vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res)); 2400 if (!vc4_hdmi->phy_regs) 2401 return -ENOMEM; 2402 2403 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet"); 2404 if (!res) 2405 return -ENODEV; 2406 2407 vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res)); 2408 if (!vc4_hdmi->ram_regs) 2409 return -ENOMEM; 2410 2411 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm"); 2412 if (!res) 2413 return -ENODEV; 2414 2415 vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res)); 2416 if (!vc4_hdmi->rm_regs) 2417 return -ENOMEM; 2418 2419 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); 2420 if (IS_ERR(vc4_hdmi->hsm_clock)) { 2421 DRM_ERROR("Failed to get HDMI state machine clock\n"); 2422 return PTR_ERR(vc4_hdmi->hsm_clock); 2423 } 2424 2425 vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb"); 2426 if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) { 2427 DRM_ERROR("Failed to get pixel bvb clock\n"); 2428 return PTR_ERR(vc4_hdmi->pixel_bvb_clock); 2429 } 2430 2431 vc4_hdmi->audio_clock = devm_clk_get(dev, "audio"); 2432 if (IS_ERR(vc4_hdmi->audio_clock)) { 2433 DRM_ERROR("Failed to get audio clock\n"); 2434 return PTR_ERR(vc4_hdmi->audio_clock); 2435 } 2436 2437 vc4_hdmi->cec_clock = devm_clk_get(dev, "cec"); 2438 if (IS_ERR(vc4_hdmi->cec_clock)) { 2439 DRM_ERROR("Failed to get CEC clock\n"); 2440 return PTR_ERR(vc4_hdmi->cec_clock); 2441 } 2442 2443 vc4_hdmi->reset = devm_reset_control_get(dev, NULL); 2444 if (IS_ERR(vc4_hdmi->reset)) { 2445 DRM_ERROR("Failed to get HDMI reset line\n"); 2446 return PTR_ERR(vc4_hdmi->reset); 2447 } 2448 2449 return 0; 2450 } 2451 2452 static int __maybe_unused vc4_hdmi_runtime_suspend(struct device *dev) 2453 { 2454 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 2455 2456 clk_disable_unprepare(vc4_hdmi->hsm_clock); 2457 2458 return 0; 2459 } 2460 2461 static int vc4_hdmi_runtime_resume(struct device *dev) 2462 { 2463 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 2464 int ret; 2465 2466 ret = clk_prepare_enable(vc4_hdmi->hsm_clock); 2467 if (ret) 2468 return ret; 2469 2470 return 0; 2471 } 2472 2473 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data) 2474 { 2475 const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev); 2476 struct platform_device *pdev = to_platform_device(dev); 2477 struct drm_device *drm = dev_get_drvdata(master); 2478 struct vc4_hdmi *vc4_hdmi; 2479 struct drm_encoder *encoder; 2480 struct device_node *ddc_node; 2481 int ret; 2482 2483 vc4_hdmi = devm_kzalloc(dev, sizeof(*vc4_hdmi), GFP_KERNEL); 2484 if (!vc4_hdmi) 2485 return -ENOMEM; 2486 mutex_init(&vc4_hdmi->mutex); 2487 spin_lock_init(&vc4_hdmi->hw_lock); 2488 INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq); 2489 2490 dev_set_drvdata(dev, vc4_hdmi); 2491 encoder = &vc4_hdmi->encoder.base.base; 2492 vc4_hdmi->encoder.base.type = variant->encoder_type; 2493 vc4_hdmi->encoder.base.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure; 2494 vc4_hdmi->encoder.base.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable; 2495 vc4_hdmi->encoder.base.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable; 2496 vc4_hdmi->encoder.base.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable; 2497 vc4_hdmi->encoder.base.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown; 2498 vc4_hdmi->pdev = pdev; 2499 vc4_hdmi->variant = variant; 2500 2501 /* 2502 * Since we don't know the state of the controller and its 2503 * display (if any), let's assume it's always enabled. 2504 * vc4_hdmi_disable_scrambling() will thus run at boot, make 2505 * sure it's disabled, and avoid any inconsistency. 2506 */ 2507 vc4_hdmi->scdc_enabled = true; 2508 2509 ret = variant->init_resources(vc4_hdmi); 2510 if (ret) 2511 return ret; 2512 2513 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0); 2514 if (!ddc_node) { 2515 DRM_ERROR("Failed to find ddc node in device tree\n"); 2516 return -ENODEV; 2517 } 2518 2519 vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node); 2520 of_node_put(ddc_node); 2521 if (!vc4_hdmi->ddc) { 2522 DRM_DEBUG("Failed to get ddc i2c adapter by node\n"); 2523 return -EPROBE_DEFER; 2524 } 2525 2526 /* Only use the GPIO HPD pin if present in the DT, otherwise 2527 * we'll use the HDMI core's register. 2528 */ 2529 vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN); 2530 if (IS_ERR(vc4_hdmi->hpd_gpio)) { 2531 ret = PTR_ERR(vc4_hdmi->hpd_gpio); 2532 goto err_put_ddc; 2533 } 2534 2535 vc4_hdmi->disable_wifi_frequencies = 2536 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence"); 2537 2538 if (variant->max_pixel_clock == 600000000) { 2539 struct vc4_dev *vc4 = to_vc4_dev(drm); 2540 long max_rate = clk_round_rate(vc4->hvs->core_clk, 550000000); 2541 2542 if (max_rate < 550000000) 2543 vc4_hdmi->disable_4kp60 = true; 2544 } 2545 2546 /* 2547 * If we boot without any cable connected to the HDMI connector, 2548 * the firmware will skip the HSM initialization and leave it 2549 * with a rate of 0, resulting in a bus lockup when we're 2550 * accessing the registers even if it's enabled. 2551 * 2552 * Let's put a sensible default at runtime_resume so that we 2553 * don't end up in this situation. 2554 */ 2555 ret = clk_set_min_rate(vc4_hdmi->hsm_clock, HSM_MIN_CLOCK_FREQ); 2556 if (ret) 2557 goto err_put_ddc; 2558 2559 /* 2560 * We need to have the device powered up at this point to call 2561 * our reset hook and for the CEC init. 2562 */ 2563 ret = vc4_hdmi_runtime_resume(dev); 2564 if (ret) 2565 goto err_put_ddc; 2566 2567 pm_runtime_get_noresume(dev); 2568 pm_runtime_set_active(dev); 2569 pm_runtime_enable(dev); 2570 2571 if (vc4_hdmi->variant->reset) 2572 vc4_hdmi->variant->reset(vc4_hdmi); 2573 2574 if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") || 2575 of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1")) && 2576 HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) { 2577 clk_prepare_enable(vc4_hdmi->pixel_clock); 2578 clk_prepare_enable(vc4_hdmi->hsm_clock); 2579 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock); 2580 } 2581 2582 drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS); 2583 drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs); 2584 2585 ret = vc4_hdmi_connector_init(drm, vc4_hdmi); 2586 if (ret) 2587 goto err_destroy_encoder; 2588 2589 ret = vc4_hdmi_hotplug_init(vc4_hdmi); 2590 if (ret) 2591 goto err_destroy_conn; 2592 2593 ret = vc4_hdmi_cec_init(vc4_hdmi); 2594 if (ret) 2595 goto err_free_hotplug; 2596 2597 ret = vc4_hdmi_audio_init(vc4_hdmi); 2598 if (ret) 2599 goto err_free_cec; 2600 2601 vc4_debugfs_add_file(drm, variant->debugfs_name, 2602 vc4_hdmi_debugfs_regs, 2603 vc4_hdmi); 2604 2605 pm_runtime_put_sync(dev); 2606 2607 return 0; 2608 2609 err_free_cec: 2610 vc4_hdmi_cec_exit(vc4_hdmi); 2611 err_free_hotplug: 2612 vc4_hdmi_hotplug_exit(vc4_hdmi); 2613 err_destroy_conn: 2614 vc4_hdmi_connector_destroy(&vc4_hdmi->connector); 2615 err_destroy_encoder: 2616 drm_encoder_cleanup(encoder); 2617 pm_runtime_put_sync(dev); 2618 pm_runtime_disable(dev); 2619 err_put_ddc: 2620 put_device(&vc4_hdmi->ddc->dev); 2621 2622 return ret; 2623 } 2624 2625 static void vc4_hdmi_unbind(struct device *dev, struct device *master, 2626 void *data) 2627 { 2628 struct vc4_hdmi *vc4_hdmi; 2629 2630 /* 2631 * ASoC makes it a bit hard to retrieve a pointer to the 2632 * vc4_hdmi structure. Registering the card will overwrite our 2633 * device drvdata with a pointer to the snd_soc_card structure, 2634 * which can then be used to retrieve whatever drvdata we want 2635 * to associate. 2636 * 2637 * However, that doesn't fly in the case where we wouldn't 2638 * register an ASoC card (because of an old DT that is missing 2639 * the dmas properties for example), then the card isn't 2640 * registered and the device drvdata wouldn't be set. 2641 * 2642 * We can deal with both cases by making sure a snd_soc_card 2643 * pointer and a vc4_hdmi structure are pointing to the same 2644 * memory address, so we can treat them indistinctly without any 2645 * issue. 2646 */ 2647 BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0); 2648 BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0); 2649 vc4_hdmi = dev_get_drvdata(dev); 2650 2651 kfree(vc4_hdmi->hdmi_regset.regs); 2652 kfree(vc4_hdmi->hd_regset.regs); 2653 2654 vc4_hdmi_cec_exit(vc4_hdmi); 2655 vc4_hdmi_hotplug_exit(vc4_hdmi); 2656 vc4_hdmi_connector_destroy(&vc4_hdmi->connector); 2657 drm_encoder_cleanup(&vc4_hdmi->encoder.base.base); 2658 2659 pm_runtime_disable(dev); 2660 2661 put_device(&vc4_hdmi->ddc->dev); 2662 } 2663 2664 static const struct component_ops vc4_hdmi_ops = { 2665 .bind = vc4_hdmi_bind, 2666 .unbind = vc4_hdmi_unbind, 2667 }; 2668 2669 static int vc4_hdmi_dev_probe(struct platform_device *pdev) 2670 { 2671 return component_add(&pdev->dev, &vc4_hdmi_ops); 2672 } 2673 2674 static int vc4_hdmi_dev_remove(struct platform_device *pdev) 2675 { 2676 component_del(&pdev->dev, &vc4_hdmi_ops); 2677 return 0; 2678 } 2679 2680 static const struct vc4_hdmi_variant bcm2835_variant = { 2681 .encoder_type = VC4_ENCODER_TYPE_HDMI0, 2682 .debugfs_name = "hdmi_regs", 2683 .card_name = "vc4-hdmi", 2684 .max_pixel_clock = 162000000, 2685 .registers = vc4_hdmi_fields, 2686 .num_registers = ARRAY_SIZE(vc4_hdmi_fields), 2687 2688 .init_resources = vc4_hdmi_init_resources, 2689 .csc_setup = vc4_hdmi_csc_setup, 2690 .reset = vc4_hdmi_reset, 2691 .set_timings = vc4_hdmi_set_timings, 2692 .phy_init = vc4_hdmi_phy_init, 2693 .phy_disable = vc4_hdmi_phy_disable, 2694 .phy_rng_enable = vc4_hdmi_phy_rng_enable, 2695 .phy_rng_disable = vc4_hdmi_phy_rng_disable, 2696 .channel_map = vc4_hdmi_channel_map, 2697 .supports_hdr = false, 2698 }; 2699 2700 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = { 2701 .encoder_type = VC4_ENCODER_TYPE_HDMI0, 2702 .debugfs_name = "hdmi0_regs", 2703 .card_name = "vc4-hdmi-0", 2704 .max_pixel_clock = 600000000, 2705 .registers = vc5_hdmi_hdmi0_fields, 2706 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi0_fields), 2707 .phy_lane_mapping = { 2708 PHY_LANE_0, 2709 PHY_LANE_1, 2710 PHY_LANE_2, 2711 PHY_LANE_CK, 2712 }, 2713 .unsupported_odd_h_timings = true, 2714 .external_irq_controller = true, 2715 2716 .init_resources = vc5_hdmi_init_resources, 2717 .csc_setup = vc5_hdmi_csc_setup, 2718 .reset = vc5_hdmi_reset, 2719 .set_timings = vc5_hdmi_set_timings, 2720 .phy_init = vc5_hdmi_phy_init, 2721 .phy_disable = vc5_hdmi_phy_disable, 2722 .phy_rng_enable = vc5_hdmi_phy_rng_enable, 2723 .phy_rng_disable = vc5_hdmi_phy_rng_disable, 2724 .channel_map = vc5_hdmi_channel_map, 2725 .supports_hdr = true, 2726 }; 2727 2728 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = { 2729 .encoder_type = VC4_ENCODER_TYPE_HDMI1, 2730 .debugfs_name = "hdmi1_regs", 2731 .card_name = "vc4-hdmi-1", 2732 .max_pixel_clock = HDMI_14_MAX_TMDS_CLK, 2733 .registers = vc5_hdmi_hdmi1_fields, 2734 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi1_fields), 2735 .phy_lane_mapping = { 2736 PHY_LANE_1, 2737 PHY_LANE_0, 2738 PHY_LANE_CK, 2739 PHY_LANE_2, 2740 }, 2741 .unsupported_odd_h_timings = true, 2742 .external_irq_controller = true, 2743 2744 .init_resources = vc5_hdmi_init_resources, 2745 .csc_setup = vc5_hdmi_csc_setup, 2746 .reset = vc5_hdmi_reset, 2747 .set_timings = vc5_hdmi_set_timings, 2748 .phy_init = vc5_hdmi_phy_init, 2749 .phy_disable = vc5_hdmi_phy_disable, 2750 .phy_rng_enable = vc5_hdmi_phy_rng_enable, 2751 .phy_rng_disable = vc5_hdmi_phy_rng_disable, 2752 .channel_map = vc5_hdmi_channel_map, 2753 .supports_hdr = true, 2754 }; 2755 2756 static const struct of_device_id vc4_hdmi_dt_match[] = { 2757 { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant }, 2758 { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant }, 2759 { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant }, 2760 {} 2761 }; 2762 2763 static const struct dev_pm_ops vc4_hdmi_pm_ops = { 2764 SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend, 2765 vc4_hdmi_runtime_resume, 2766 NULL) 2767 }; 2768 2769 struct platform_driver vc4_hdmi_driver = { 2770 .probe = vc4_hdmi_dev_probe, 2771 .remove = vc4_hdmi_dev_remove, 2772 .driver = { 2773 .name = "vc4_hdmi", 2774 .of_match_table = vc4_hdmi_dt_match, 2775 .pm = &vc4_hdmi_pm_ops, 2776 }, 2777 }; 2778