1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 Broadcom 4 * Copyright (c) 2014 The Linux Foundation. All rights reserved. 5 * Copyright (C) 2013 Red Hat 6 * Author: Rob Clark <robdclark@gmail.com> 7 */ 8 9 /** 10 * DOC: VC4 Falcon HDMI module 11 * 12 * The HDMI core has a state machine and a PHY. On BCM2835, most of 13 * the unit operates off of the HSM clock from CPRMAN. It also 14 * internally uses the PLLH_PIX clock for the PHY. 15 * 16 * HDMI infoframes are kept within a small packet ram, where each 17 * packet can be individually enabled for including in a frame. 18 * 19 * HDMI audio is implemented entirely within the HDMI IP block. A 20 * register in the HDMI encoder takes SPDIF frames from the DMA engine 21 * and transfers them over an internal MAI (multi-channel audio 22 * interconnect) bus to the encoder side for insertion into the video 23 * blank regions. 24 * 25 * The driver's HDMI encoder does not yet support power management. 26 * The HDMI encoder's power domain and the HSM/pixel clocks are kept 27 * continuously running, and only the HDMI logic and packet ram are 28 * powered off/on at disable/enable time. 29 * 30 * The driver does not yet support CEC control, though the HDMI 31 * encoder block has CEC support. 32 */ 33 34 #include <drm/display/drm_hdmi_helper.h> 35 #include <drm/display/drm_scdc_helper.h> 36 #include <drm/drm_atomic_helper.h> 37 #include <drm/drm_probe_helper.h> 38 #include <drm/drm_simple_kms_helper.h> 39 #include <linux/clk.h> 40 #include <linux/component.h> 41 #include <linux/gpio/consumer.h> 42 #include <linux/i2c.h> 43 #include <linux/of_address.h> 44 #include <linux/of_gpio.h> 45 #include <linux/of_platform.h> 46 #include <linux/pm_runtime.h> 47 #include <linux/rational.h> 48 #include <linux/reset.h> 49 #include <sound/dmaengine_pcm.h> 50 #include <sound/hdmi-codec.h> 51 #include <sound/pcm_drm_eld.h> 52 #include <sound/pcm_params.h> 53 #include <sound/soc.h> 54 #include "media/cec.h" 55 #include "vc4_drv.h" 56 #include "vc4_hdmi.h" 57 #include "vc4_hdmi_regs.h" 58 #include "vc4_regs.h" 59 60 #define VC5_HDMI_HORZA_HFP_SHIFT 16 61 #define VC5_HDMI_HORZA_HFP_MASK VC4_MASK(28, 16) 62 #define VC5_HDMI_HORZA_VPOS BIT(15) 63 #define VC5_HDMI_HORZA_HPOS BIT(14) 64 #define VC5_HDMI_HORZA_HAP_SHIFT 0 65 #define VC5_HDMI_HORZA_HAP_MASK VC4_MASK(13, 0) 66 67 #define VC5_HDMI_HORZB_HBP_SHIFT 16 68 #define VC5_HDMI_HORZB_HBP_MASK VC4_MASK(26, 16) 69 #define VC5_HDMI_HORZB_HSP_SHIFT 0 70 #define VC5_HDMI_HORZB_HSP_MASK VC4_MASK(10, 0) 71 72 #define VC5_HDMI_VERTA_VSP_SHIFT 24 73 #define VC5_HDMI_VERTA_VSP_MASK VC4_MASK(28, 24) 74 #define VC5_HDMI_VERTA_VFP_SHIFT 16 75 #define VC5_HDMI_VERTA_VFP_MASK VC4_MASK(22, 16) 76 #define VC5_HDMI_VERTA_VAL_SHIFT 0 77 #define VC5_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0) 78 79 #define VC5_HDMI_VERTB_VSPO_SHIFT 16 80 #define VC5_HDMI_VERTB_VSPO_MASK VC4_MASK(29, 16) 81 82 #define VC5_HDMI_SCRAMBLER_CTL_ENABLE BIT(0) 83 84 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT 8 85 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK VC4_MASK(10, 8) 86 87 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT 0 88 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK VC4_MASK(3, 0) 89 90 #define VC5_HDMI_GCP_CONFIG_GCP_ENABLE BIT(31) 91 92 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT 8 93 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK VC4_MASK(15, 8) 94 95 # define VC4_HD_M_SW_RST BIT(2) 96 # define VC4_HD_M_ENABLE BIT(0) 97 98 #define HSM_MIN_CLOCK_FREQ 120000000 99 #define CEC_CLOCK_FREQ 40000 100 101 #define HDMI_14_MAX_TMDS_CLK (340 * 1000 * 1000) 102 103 static const char * const output_format_str[] = { 104 [VC4_HDMI_OUTPUT_RGB] = "RGB", 105 [VC4_HDMI_OUTPUT_YUV420] = "YUV 4:2:0", 106 [VC4_HDMI_OUTPUT_YUV422] = "YUV 4:2:2", 107 [VC4_HDMI_OUTPUT_YUV444] = "YUV 4:4:4", 108 }; 109 110 static const char *vc4_hdmi_output_fmt_str(enum vc4_hdmi_output_format fmt) 111 { 112 if (fmt >= ARRAY_SIZE(output_format_str)) 113 return "invalid"; 114 115 return output_format_str[fmt]; 116 } 117 118 static unsigned long long 119 vc4_hdmi_encoder_compute_mode_clock(const struct drm_display_mode *mode, 120 unsigned int bpc, enum vc4_hdmi_output_format fmt); 121 122 static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode, 123 unsigned int bpc, 124 enum vc4_hdmi_output_format fmt) 125 { 126 unsigned long long clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc, fmt); 127 128 return clock > HDMI_14_MAX_TMDS_CLK; 129 } 130 131 static bool vc4_hdmi_is_full_range_rgb(struct vc4_hdmi *vc4_hdmi, 132 const struct drm_display_mode *mode) 133 { 134 struct drm_display_info *display = &vc4_hdmi->connector.display_info; 135 136 return !display->is_hdmi || 137 drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_FULL; 138 } 139 140 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused) 141 { 142 struct drm_info_node *node = (struct drm_info_node *)m->private; 143 struct vc4_hdmi *vc4_hdmi = node->info_ent->data; 144 struct drm_printer p = drm_seq_file_printer(m); 145 146 drm_print_regset32(&p, &vc4_hdmi->hdmi_regset); 147 drm_print_regset32(&p, &vc4_hdmi->hd_regset); 148 149 return 0; 150 } 151 152 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi) 153 { 154 unsigned long flags; 155 156 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 157 158 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST); 159 udelay(1); 160 HDMI_WRITE(HDMI_M_CTL, 0); 161 162 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE); 163 164 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 165 VC4_HDMI_SW_RESET_HDMI | 166 VC4_HDMI_SW_RESET_FORMAT_DETECT); 167 168 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0); 169 170 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 171 } 172 173 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi) 174 { 175 unsigned long flags; 176 177 reset_control_reset(vc4_hdmi->reset); 178 179 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 180 181 HDMI_WRITE(HDMI_DVP_CTL, 0); 182 183 HDMI_WRITE(HDMI_CLOCK_STOP, 184 HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL); 185 186 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 187 } 188 189 #ifdef CONFIG_DRM_VC4_HDMI_CEC 190 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) 191 { 192 unsigned long cec_rate = clk_get_rate(vc4_hdmi->cec_clock); 193 unsigned long flags; 194 u16 clk_cnt; 195 u32 value; 196 197 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 198 199 value = HDMI_READ(HDMI_CEC_CNTRL_1); 200 value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK; 201 202 /* 203 * Set the clock divider: the hsm_clock rate and this divider 204 * setting will give a 40 kHz CEC clock. 205 */ 206 clk_cnt = cec_rate / CEC_CLOCK_FREQ; 207 value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT; 208 HDMI_WRITE(HDMI_CEC_CNTRL_1, value); 209 210 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 211 } 212 #else 213 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {} 214 #endif 215 216 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder); 217 218 static enum drm_connector_status 219 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force) 220 { 221 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 222 bool connected = false; 223 224 mutex_lock(&vc4_hdmi->mutex); 225 226 WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev)); 227 228 if (vc4_hdmi->hpd_gpio) { 229 if (gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio)) 230 connected = true; 231 } else { 232 if (vc4_hdmi->variant->hp_detect && 233 vc4_hdmi->variant->hp_detect(vc4_hdmi)) 234 connected = true; 235 } 236 237 if (connected) { 238 if (connector->status != connector_status_connected) { 239 struct edid *edid = drm_get_edid(connector, vc4_hdmi->ddc); 240 241 if (edid) { 242 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid); 243 kfree(edid); 244 } 245 } 246 247 vc4_hdmi_enable_scrambling(&vc4_hdmi->encoder.base); 248 pm_runtime_put(&vc4_hdmi->pdev->dev); 249 mutex_unlock(&vc4_hdmi->mutex); 250 return connector_status_connected; 251 } 252 253 cec_phys_addr_invalidate(vc4_hdmi->cec_adap); 254 pm_runtime_put(&vc4_hdmi->pdev->dev); 255 mutex_unlock(&vc4_hdmi->mutex); 256 return connector_status_disconnected; 257 } 258 259 static void vc4_hdmi_connector_destroy(struct drm_connector *connector) 260 { 261 drm_connector_unregister(connector); 262 drm_connector_cleanup(connector); 263 } 264 265 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector) 266 { 267 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 268 int ret = 0; 269 struct edid *edid; 270 271 mutex_lock(&vc4_hdmi->mutex); 272 273 edid = drm_get_edid(connector, vc4_hdmi->ddc); 274 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid); 275 if (!edid) { 276 ret = -ENODEV; 277 goto out; 278 } 279 280 drm_connector_update_edid_property(connector, edid); 281 ret = drm_add_edid_modes(connector, edid); 282 kfree(edid); 283 284 if (vc4_hdmi->disable_4kp60) { 285 struct drm_device *drm = connector->dev; 286 struct drm_display_mode *mode; 287 288 list_for_each_entry(mode, &connector->probed_modes, head) { 289 if (vc4_hdmi_mode_needs_scrambling(mode, 8, VC4_HDMI_OUTPUT_RGB)) { 290 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz."); 291 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60."); 292 } 293 } 294 } 295 296 out: 297 mutex_unlock(&vc4_hdmi->mutex); 298 299 return ret; 300 } 301 302 static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector, 303 struct drm_atomic_state *state) 304 { 305 struct drm_connector_state *old_state = 306 drm_atomic_get_old_connector_state(state, connector); 307 struct drm_connector_state *new_state = 308 drm_atomic_get_new_connector_state(state, connector); 309 struct drm_crtc *crtc = new_state->crtc; 310 311 if (!crtc) 312 return 0; 313 314 if (old_state->colorspace != new_state->colorspace || 315 !drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) { 316 struct drm_crtc_state *crtc_state; 317 318 crtc_state = drm_atomic_get_crtc_state(state, crtc); 319 if (IS_ERR(crtc_state)) 320 return PTR_ERR(crtc_state); 321 322 crtc_state->mode_changed = true; 323 } 324 325 return 0; 326 } 327 328 static void vc4_hdmi_connector_reset(struct drm_connector *connector) 329 { 330 struct vc4_hdmi_connector_state *old_state = 331 conn_state_to_vc4_hdmi_conn_state(connector->state); 332 struct vc4_hdmi_connector_state *new_state = 333 kzalloc(sizeof(*new_state), GFP_KERNEL); 334 335 if (connector->state) 336 __drm_atomic_helper_connector_destroy_state(connector->state); 337 338 kfree(old_state); 339 __drm_atomic_helper_connector_reset(connector, &new_state->base); 340 341 if (!new_state) 342 return; 343 344 new_state->base.max_bpc = 8; 345 new_state->base.max_requested_bpc = 8; 346 new_state->output_format = VC4_HDMI_OUTPUT_RGB; 347 drm_atomic_helper_connector_tv_reset(connector); 348 } 349 350 static struct drm_connector_state * 351 vc4_hdmi_connector_duplicate_state(struct drm_connector *connector) 352 { 353 struct drm_connector_state *conn_state = connector->state; 354 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state); 355 struct vc4_hdmi_connector_state *new_state; 356 357 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL); 358 if (!new_state) 359 return NULL; 360 361 new_state->tmds_char_rate = vc4_state->tmds_char_rate; 362 new_state->output_bpc = vc4_state->output_bpc; 363 new_state->output_format = vc4_state->output_format; 364 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base); 365 366 return &new_state->base; 367 } 368 369 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = { 370 .detect = vc4_hdmi_connector_detect, 371 .fill_modes = drm_helper_probe_single_connector_modes, 372 .destroy = vc4_hdmi_connector_destroy, 373 .reset = vc4_hdmi_connector_reset, 374 .atomic_duplicate_state = vc4_hdmi_connector_duplicate_state, 375 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 376 }; 377 378 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = { 379 .get_modes = vc4_hdmi_connector_get_modes, 380 .atomic_check = vc4_hdmi_connector_atomic_check, 381 }; 382 383 static int vc4_hdmi_connector_init(struct drm_device *dev, 384 struct vc4_hdmi *vc4_hdmi) 385 { 386 struct drm_connector *connector = &vc4_hdmi->connector; 387 struct drm_encoder *encoder = &vc4_hdmi->encoder.base; 388 int ret; 389 390 drm_connector_init_with_ddc(dev, connector, 391 &vc4_hdmi_connector_funcs, 392 DRM_MODE_CONNECTOR_HDMIA, 393 vc4_hdmi->ddc); 394 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs); 395 396 /* 397 * Some of the properties below require access to state, like bpc. 398 * Allocate some default initial connector state with our reset helper. 399 */ 400 if (connector->funcs->reset) 401 connector->funcs->reset(connector); 402 403 /* Create and attach TV margin props to this connector. */ 404 ret = drm_mode_create_tv_margin_properties(dev); 405 if (ret) 406 return ret; 407 408 ret = drm_mode_create_hdmi_colorspace_property(connector); 409 if (ret) 410 return ret; 411 412 drm_connector_attach_colorspace_property(connector); 413 drm_connector_attach_tv_margin_properties(connector); 414 drm_connector_attach_max_bpc_property(connector, 8, 12); 415 416 connector->polled = (DRM_CONNECTOR_POLL_CONNECT | 417 DRM_CONNECTOR_POLL_DISCONNECT); 418 419 connector->interlace_allowed = 1; 420 connector->doublescan_allowed = 0; 421 422 if (vc4_hdmi->variant->supports_hdr) 423 drm_connector_attach_hdr_output_metadata_property(connector); 424 425 drm_connector_attach_encoder(connector, encoder); 426 427 return 0; 428 } 429 430 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder, 431 enum hdmi_infoframe_type type, 432 bool poll) 433 { 434 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 435 u32 packet_id = type - 0x80; 436 unsigned long flags; 437 438 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 439 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 440 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id)); 441 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 442 443 if (!poll) 444 return 0; 445 446 return wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) & 447 BIT(packet_id)), 100); 448 } 449 450 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder, 451 union hdmi_infoframe *frame) 452 { 453 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 454 u32 packet_id = frame->any.type - 0x80; 455 const struct vc4_hdmi_register *ram_packet_start = 456 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START]; 457 u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id; 458 void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi, 459 ram_packet_start->reg); 460 uint8_t buffer[VC4_HDMI_PACKET_STRIDE]; 461 unsigned long flags; 462 ssize_t len, i; 463 int ret; 464 465 WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) & 466 VC4_HDMI_RAM_PACKET_ENABLE), 467 "Packet RAM has to be on to store the packet."); 468 469 len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer)); 470 if (len < 0) 471 return; 472 473 ret = vc4_hdmi_stop_packet(encoder, frame->any.type, true); 474 if (ret) { 475 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret); 476 return; 477 } 478 479 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 480 481 for (i = 0; i < len; i += 7) { 482 writel(buffer[i + 0] << 0 | 483 buffer[i + 1] << 8 | 484 buffer[i + 2] << 16, 485 base + packet_reg); 486 packet_reg += 4; 487 488 writel(buffer[i + 3] << 0 | 489 buffer[i + 4] << 8 | 490 buffer[i + 5] << 16 | 491 buffer[i + 6] << 24, 492 base + packet_reg); 493 packet_reg += 4; 494 } 495 496 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 497 HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id)); 498 499 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 500 501 ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) & 502 BIT(packet_id)), 100); 503 if (ret) 504 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret); 505 } 506 507 static void vc4_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame, 508 enum vc4_hdmi_output_format fmt) 509 { 510 switch (fmt) { 511 case VC4_HDMI_OUTPUT_RGB: 512 frame->colorspace = HDMI_COLORSPACE_RGB; 513 break; 514 515 case VC4_HDMI_OUTPUT_YUV420: 516 frame->colorspace = HDMI_COLORSPACE_YUV420; 517 break; 518 519 case VC4_HDMI_OUTPUT_YUV422: 520 frame->colorspace = HDMI_COLORSPACE_YUV422; 521 break; 522 523 case VC4_HDMI_OUTPUT_YUV444: 524 frame->colorspace = HDMI_COLORSPACE_YUV444; 525 break; 526 527 default: 528 break; 529 } 530 } 531 532 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder) 533 { 534 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 535 struct drm_connector *connector = &vc4_hdmi->connector; 536 struct drm_connector_state *cstate = connector->state; 537 struct vc4_hdmi_connector_state *vc4_state = 538 conn_state_to_vc4_hdmi_conn_state(cstate); 539 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 540 union hdmi_infoframe frame; 541 int ret; 542 543 lockdep_assert_held(&vc4_hdmi->mutex); 544 545 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, 546 connector, mode); 547 if (ret < 0) { 548 DRM_ERROR("couldn't fill AVI infoframe\n"); 549 return; 550 } 551 552 drm_hdmi_avi_infoframe_quant_range(&frame.avi, 553 connector, mode, 554 vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode) ? 555 HDMI_QUANTIZATION_RANGE_FULL : 556 HDMI_QUANTIZATION_RANGE_LIMITED); 557 drm_hdmi_avi_infoframe_colorimetry(&frame.avi, cstate); 558 vc4_hdmi_avi_infoframe_colorspace(&frame.avi, vc4_state->output_format); 559 drm_hdmi_avi_infoframe_bars(&frame.avi, cstate); 560 561 vc4_hdmi_write_infoframe(encoder, &frame); 562 } 563 564 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder) 565 { 566 union hdmi_infoframe frame; 567 int ret; 568 569 ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore"); 570 if (ret < 0) { 571 DRM_ERROR("couldn't fill SPD infoframe\n"); 572 return; 573 } 574 575 frame.spd.sdi = HDMI_SPD_SDI_PC; 576 577 vc4_hdmi_write_infoframe(encoder, &frame); 578 } 579 580 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder) 581 { 582 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 583 struct hdmi_audio_infoframe *audio = &vc4_hdmi->audio.infoframe; 584 union hdmi_infoframe frame; 585 586 memcpy(&frame.audio, audio, sizeof(*audio)); 587 vc4_hdmi_write_infoframe(encoder, &frame); 588 } 589 590 static void vc4_hdmi_set_hdr_infoframe(struct drm_encoder *encoder) 591 { 592 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 593 struct drm_connector *connector = &vc4_hdmi->connector; 594 struct drm_connector_state *conn_state = connector->state; 595 union hdmi_infoframe frame; 596 597 lockdep_assert_held(&vc4_hdmi->mutex); 598 599 if (!vc4_hdmi->variant->supports_hdr) 600 return; 601 602 if (!conn_state->hdr_output_metadata) 603 return; 604 605 if (drm_hdmi_infoframe_set_hdr_metadata(&frame.drm, conn_state)) 606 return; 607 608 vc4_hdmi_write_infoframe(encoder, &frame); 609 } 610 611 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder) 612 { 613 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 614 615 lockdep_assert_held(&vc4_hdmi->mutex); 616 617 vc4_hdmi_set_avi_infoframe(encoder); 618 vc4_hdmi_set_spd_infoframe(encoder); 619 /* 620 * If audio was streaming, then we need to reenabled the audio 621 * infoframe here during encoder_enable. 622 */ 623 if (vc4_hdmi->audio.streaming) 624 vc4_hdmi_set_audio_infoframe(encoder); 625 626 vc4_hdmi_set_hdr_infoframe(encoder); 627 } 628 629 static bool vc4_hdmi_supports_scrambling(struct drm_encoder *encoder, 630 struct drm_display_mode *mode) 631 { 632 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 633 struct drm_display_info *display = &vc4_hdmi->connector.display_info; 634 635 lockdep_assert_held(&vc4_hdmi->mutex); 636 637 if (!display->is_hdmi) 638 return false; 639 640 if (!display->hdmi.scdc.supported || 641 !display->hdmi.scdc.scrambling.supported) 642 return false; 643 644 return true; 645 } 646 647 #define SCRAMBLING_POLLING_DELAY_MS 1000 648 649 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder) 650 { 651 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 652 struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 653 unsigned long flags; 654 655 lockdep_assert_held(&vc4_hdmi->mutex); 656 657 if (!vc4_hdmi_supports_scrambling(encoder, mode)) 658 return; 659 660 if (!vc4_hdmi_mode_needs_scrambling(mode, 661 vc4_hdmi->output_bpc, 662 vc4_hdmi->output_format)) 663 return; 664 665 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true); 666 drm_scdc_set_scrambling(vc4_hdmi->ddc, true); 667 668 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 669 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) | 670 VC5_HDMI_SCRAMBLER_CTL_ENABLE); 671 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 672 673 vc4_hdmi->scdc_enabled = true; 674 675 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work, 676 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS)); 677 } 678 679 static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder) 680 { 681 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 682 unsigned long flags; 683 684 lockdep_assert_held(&vc4_hdmi->mutex); 685 686 if (!vc4_hdmi->scdc_enabled) 687 return; 688 689 vc4_hdmi->scdc_enabled = false; 690 691 if (delayed_work_pending(&vc4_hdmi->scrambling_work)) 692 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work); 693 694 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 695 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) & 696 ~VC5_HDMI_SCRAMBLER_CTL_ENABLE); 697 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 698 699 drm_scdc_set_scrambling(vc4_hdmi->ddc, false); 700 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, false); 701 } 702 703 static void vc4_hdmi_scrambling_wq(struct work_struct *work) 704 { 705 struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work), 706 struct vc4_hdmi, 707 scrambling_work); 708 709 if (drm_scdc_get_scrambling_status(vc4_hdmi->ddc)) 710 return; 711 712 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true); 713 drm_scdc_set_scrambling(vc4_hdmi->ddc, true); 714 715 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work, 716 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS)); 717 } 718 719 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder, 720 struct drm_atomic_state *state) 721 { 722 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 723 unsigned long flags; 724 725 mutex_lock(&vc4_hdmi->mutex); 726 727 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 728 729 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0); 730 731 HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB); 732 733 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 734 735 mdelay(1); 736 737 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 738 HDMI_WRITE(HDMI_VID_CTL, 739 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE); 740 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 741 742 vc4_hdmi_disable_scrambling(encoder); 743 744 mutex_unlock(&vc4_hdmi->mutex); 745 } 746 747 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder, 748 struct drm_atomic_state *state) 749 { 750 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 751 unsigned long flags; 752 int ret; 753 754 mutex_lock(&vc4_hdmi->mutex); 755 756 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 757 HDMI_WRITE(HDMI_VID_CTL, 758 HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX); 759 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 760 761 if (vc4_hdmi->variant->phy_disable) 762 vc4_hdmi->variant->phy_disable(vc4_hdmi); 763 764 clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock); 765 clk_disable_unprepare(vc4_hdmi->pixel_clock); 766 767 ret = pm_runtime_put(&vc4_hdmi->pdev->dev); 768 if (ret < 0) 769 DRM_ERROR("Failed to release power domain: %d\n", ret); 770 771 mutex_unlock(&vc4_hdmi->mutex); 772 } 773 774 static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder) 775 { 776 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 777 778 mutex_lock(&vc4_hdmi->mutex); 779 vc4_hdmi->output_enabled = false; 780 mutex_unlock(&vc4_hdmi->mutex); 781 } 782 783 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, 784 struct drm_connector_state *state, 785 const struct drm_display_mode *mode) 786 { 787 unsigned long flags; 788 u32 csc_ctl; 789 790 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 791 792 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR, 793 VC4_HD_CSC_CTL_ORDER); 794 795 if (!vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode)) { 796 /* CEA VICs other than #1 requre limited range RGB 797 * output unless overridden by an AVI infoframe. 798 * Apply a colorspace conversion to squash 0-255 down 799 * to 16-235. The matrix here is: 800 * 801 * [ 0 0 0.8594 16] 802 * [ 0 0.8594 0 16] 803 * [ 0.8594 0 0 16] 804 * [ 0 0 0 1] 805 */ 806 csc_ctl |= VC4_HD_CSC_CTL_ENABLE; 807 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC; 808 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM, 809 VC4_HD_CSC_CTL_MODE); 810 811 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000); 812 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0); 813 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000); 814 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000); 815 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0); 816 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000); 817 } 818 819 /* The RGB order applies even when CSC is disabled. */ 820 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl); 821 822 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 823 } 824 825 /* 826 * If we need to output Full Range RGB, then use the unity matrix 827 * 828 * [ 1 0 0 0] 829 * [ 0 1 0 0] 830 * [ 0 0 1 0] 831 * 832 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets 833 */ 834 static const u16 vc5_hdmi_csc_full_rgb_unity[3][4] = { 835 { 0x2000, 0x0000, 0x0000, 0x0000 }, 836 { 0x0000, 0x2000, 0x0000, 0x0000 }, 837 { 0x0000, 0x0000, 0x2000, 0x0000 }, 838 }; 839 840 /* 841 * CEA VICs other than #1 require limited range RGB output unless 842 * overridden by an AVI infoframe. Apply a colorspace conversion to 843 * squash 0-255 down to 16-235. The matrix here is: 844 * 845 * [ 0.8594 0 0 16] 846 * [ 0 0.8594 0 16] 847 * [ 0 0 0.8594 16] 848 * 849 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets 850 */ 851 static const u16 vc5_hdmi_csc_full_rgb_to_limited_rgb[3][4] = { 852 { 0x1b80, 0x0000, 0x0000, 0x0400 }, 853 { 0x0000, 0x1b80, 0x0000, 0x0400 }, 854 { 0x0000, 0x0000, 0x1b80, 0x0400 }, 855 }; 856 857 /* 858 * Conversion between Full Range RGB and Full Range YUV422 using the 859 * BT.709 Colorspace 860 * 861 * 862 * [ 0.181906 0.611804 0.061758 16 ] 863 * [ -0.100268 -0.337232 0.437500 128 ] 864 * [ 0.437500 -0.397386 -0.040114 128 ] 865 * 866 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets 867 */ 868 static const u16 vc5_hdmi_csc_full_rgb_to_limited_yuv422_bt709[3][4] = { 869 { 0x05d2, 0x1394, 0x01fa, 0x0400 }, 870 { 0xfccc, 0xf536, 0x0e00, 0x2000 }, 871 { 0x0e00, 0xf34a, 0xfeb8, 0x2000 }, 872 }; 873 874 /* 875 * Conversion between Full Range RGB and Full Range YUV444 using the 876 * BT.709 Colorspace 877 * 878 * [ -0.100268 -0.337232 0.437500 128 ] 879 * [ 0.437500 -0.397386 -0.040114 128 ] 880 * [ 0.181906 0.611804 0.061758 16 ] 881 * 882 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets 883 */ 884 static const u16 vc5_hdmi_csc_full_rgb_to_limited_yuv444_bt709[3][4] = { 885 { 0xfccc, 0xf536, 0x0e00, 0x2000 }, 886 { 0x0e00, 0xf34a, 0xfeb8, 0x2000 }, 887 { 0x05d2, 0x1394, 0x01fa, 0x0400 }, 888 }; 889 890 static void vc5_hdmi_set_csc_coeffs(struct vc4_hdmi *vc4_hdmi, 891 const u16 coeffs[3][4]) 892 { 893 lockdep_assert_held(&vc4_hdmi->hw_lock); 894 895 HDMI_WRITE(HDMI_CSC_12_11, (coeffs[0][1] << 16) | coeffs[0][0]); 896 HDMI_WRITE(HDMI_CSC_14_13, (coeffs[0][3] << 16) | coeffs[0][2]); 897 HDMI_WRITE(HDMI_CSC_22_21, (coeffs[1][1] << 16) | coeffs[1][0]); 898 HDMI_WRITE(HDMI_CSC_24_23, (coeffs[1][3] << 16) | coeffs[1][2]); 899 HDMI_WRITE(HDMI_CSC_32_31, (coeffs[2][1] << 16) | coeffs[2][0]); 900 HDMI_WRITE(HDMI_CSC_34_33, (coeffs[2][3] << 16) | coeffs[2][2]); 901 } 902 903 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, 904 struct drm_connector_state *state, 905 const struct drm_display_mode *mode) 906 { 907 struct vc4_hdmi_connector_state *vc4_state = 908 conn_state_to_vc4_hdmi_conn_state(state); 909 unsigned long flags; 910 u32 if_cfg = 0; 911 u32 if_xbar = 0x543210; 912 u32 csc_chan_ctl = 0; 913 u32 csc_ctl = VC5_MT_CP_CSC_CTL_ENABLE | VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM, 914 VC5_MT_CP_CSC_CTL_MODE); 915 916 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 917 918 switch (vc4_state->output_format) { 919 case VC4_HDMI_OUTPUT_YUV444: 920 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_limited_yuv444_bt709); 921 break; 922 923 case VC4_HDMI_OUTPUT_YUV422: 924 csc_ctl |= VC4_SET_FIELD(VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422_STANDARD, 925 VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422) | 926 VC5_MT_CP_CSC_CTL_USE_444_TO_422 | 927 VC5_MT_CP_CSC_CTL_USE_RNG_SUPPRESSION; 928 929 csc_chan_ctl |= VC4_SET_FIELD(VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP_LEGACY_STYLE, 930 VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP); 931 932 if_cfg |= VC4_SET_FIELD(VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422_FORMAT_422_LEGACY, 933 VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422); 934 935 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_limited_yuv422_bt709); 936 break; 937 938 case VC4_HDMI_OUTPUT_RGB: 939 if_xbar = 0x354021; 940 941 if (!vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode)) 942 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_limited_rgb); 943 else 944 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_unity); 945 break; 946 947 default: 948 break; 949 } 950 951 HDMI_WRITE(HDMI_VEC_INTERFACE_CFG, if_cfg); 952 HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, if_xbar); 953 HDMI_WRITE(HDMI_CSC_CHANNEL_CTL, csc_chan_ctl); 954 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl); 955 956 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 957 } 958 959 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi, 960 struct drm_connector_state *state, 961 struct drm_display_mode *mode) 962 { 963 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 964 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 965 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 966 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 967 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 968 VC4_HDMI_VERTA_VSP) | 969 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 970 VC4_HDMI_VERTA_VFP) | 971 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL)); 972 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 973 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end, 974 VC4_HDMI_VERTB_VBP)); 975 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 976 VC4_SET_FIELD(mode->crtc_vtotal - 977 mode->crtc_vsync_end - 978 interlaced, 979 VC4_HDMI_VERTB_VBP)); 980 unsigned long flags; 981 982 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 983 984 HDMI_WRITE(HDMI_HORZA, 985 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) | 986 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) | 987 VC4_SET_FIELD(mode->hdisplay * pixel_rep, 988 VC4_HDMI_HORZA_HAP)); 989 990 HDMI_WRITE(HDMI_HORZB, 991 VC4_SET_FIELD((mode->htotal - 992 mode->hsync_end) * pixel_rep, 993 VC4_HDMI_HORZB_HBP) | 994 VC4_SET_FIELD((mode->hsync_end - 995 mode->hsync_start) * pixel_rep, 996 VC4_HDMI_HORZB_HSP) | 997 VC4_SET_FIELD((mode->hsync_start - 998 mode->hdisplay) * pixel_rep, 999 VC4_HDMI_HORZB_HFP)); 1000 1001 HDMI_WRITE(HDMI_VERTA0, verta); 1002 HDMI_WRITE(HDMI_VERTA1, verta); 1003 1004 HDMI_WRITE(HDMI_VERTB0, vertb_even); 1005 HDMI_WRITE(HDMI_VERTB1, vertb); 1006 1007 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1008 } 1009 1010 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi, 1011 struct drm_connector_state *state, 1012 struct drm_display_mode *mode) 1013 { 1014 const struct vc4_hdmi_connector_state *vc4_state = 1015 conn_state_to_vc4_hdmi_conn_state(state); 1016 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 1017 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 1018 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 1019 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 1020 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 1021 VC5_HDMI_VERTA_VSP) | 1022 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 1023 VC5_HDMI_VERTA_VFP) | 1024 VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL)); 1025 u32 vertb = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) | 1026 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end, 1027 VC4_HDMI_VERTB_VBP)); 1028 u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) | 1029 VC4_SET_FIELD(mode->crtc_vtotal - 1030 mode->crtc_vsync_end - 1031 interlaced, 1032 VC4_HDMI_VERTB_VBP)); 1033 unsigned long flags; 1034 unsigned char gcp; 1035 bool gcp_en; 1036 u32 reg; 1037 1038 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1039 1040 HDMI_WRITE(HDMI_HORZA, 1041 (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) | 1042 (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) | 1043 VC4_SET_FIELD(mode->hdisplay * pixel_rep, 1044 VC5_HDMI_HORZA_HAP) | 1045 VC4_SET_FIELD((mode->hsync_start - 1046 mode->hdisplay) * pixel_rep, 1047 VC5_HDMI_HORZA_HFP)); 1048 1049 HDMI_WRITE(HDMI_HORZB, 1050 VC4_SET_FIELD((mode->htotal - 1051 mode->hsync_end) * pixel_rep, 1052 VC5_HDMI_HORZB_HBP) | 1053 VC4_SET_FIELD((mode->hsync_end - 1054 mode->hsync_start) * pixel_rep, 1055 VC5_HDMI_HORZB_HSP)); 1056 1057 HDMI_WRITE(HDMI_VERTA0, verta); 1058 HDMI_WRITE(HDMI_VERTA1, verta); 1059 1060 HDMI_WRITE(HDMI_VERTB0, vertb_even); 1061 HDMI_WRITE(HDMI_VERTB1, vertb); 1062 1063 switch (vc4_state->output_bpc) { 1064 case 12: 1065 gcp = 6; 1066 gcp_en = true; 1067 break; 1068 case 10: 1069 gcp = 5; 1070 gcp_en = true; 1071 break; 1072 case 8: 1073 default: 1074 gcp = 4; 1075 gcp_en = false; 1076 break; 1077 } 1078 1079 /* 1080 * YCC422 is always 36-bit and not considered deep colour so 1081 * doesn't signal in GCP. 1082 */ 1083 if (vc4_state->output_format == VC4_HDMI_OUTPUT_YUV422) { 1084 gcp = 4; 1085 gcp_en = false; 1086 } 1087 1088 reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1); 1089 reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK | 1090 VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK); 1091 reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) | 1092 VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH); 1093 HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg); 1094 1095 reg = HDMI_READ(HDMI_GCP_WORD_1); 1096 reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK; 1097 reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1); 1098 HDMI_WRITE(HDMI_GCP_WORD_1, reg); 1099 1100 reg = HDMI_READ(HDMI_GCP_CONFIG); 1101 reg &= ~VC5_HDMI_GCP_CONFIG_GCP_ENABLE; 1102 reg |= gcp_en ? VC5_HDMI_GCP_CONFIG_GCP_ENABLE : 0; 1103 HDMI_WRITE(HDMI_GCP_CONFIG, reg); 1104 1105 HDMI_WRITE(HDMI_CLOCK_STOP, 0); 1106 1107 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1108 } 1109 1110 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi) 1111 { 1112 unsigned long flags; 1113 u32 drift; 1114 int ret; 1115 1116 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1117 1118 drift = HDMI_READ(HDMI_FIFO_CTL); 1119 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK; 1120 1121 HDMI_WRITE(HDMI_FIFO_CTL, 1122 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 1123 HDMI_WRITE(HDMI_FIFO_CTL, 1124 drift | VC4_HDMI_FIFO_CTL_RECENTER); 1125 1126 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1127 1128 usleep_range(1000, 1100); 1129 1130 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1131 1132 HDMI_WRITE(HDMI_FIFO_CTL, 1133 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 1134 HDMI_WRITE(HDMI_FIFO_CTL, 1135 drift | VC4_HDMI_FIFO_CTL_RECENTER); 1136 1137 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1138 1139 ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) & 1140 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1); 1141 WARN_ONCE(ret, "Timeout waiting for " 1142 "VC4_HDMI_FIFO_CTL_RECENTER_DONE"); 1143 } 1144 1145 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder, 1146 struct drm_atomic_state *state) 1147 { 1148 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1149 struct drm_connector *connector = &vc4_hdmi->connector; 1150 struct drm_connector_state *conn_state = 1151 drm_atomic_get_new_connector_state(state, connector); 1152 struct vc4_hdmi_connector_state *vc4_conn_state = 1153 conn_state_to_vc4_hdmi_conn_state(conn_state); 1154 struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1155 unsigned long tmds_char_rate = vc4_conn_state->tmds_char_rate; 1156 unsigned long bvb_rate, hsm_rate; 1157 unsigned long flags; 1158 int ret; 1159 1160 mutex_lock(&vc4_hdmi->mutex); 1161 1162 /* 1163 * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must 1164 * be faster than pixel clock, infinitesimally faster, tested in 1165 * simulation. Otherwise, exact value is unimportant for HDMI 1166 * operation." This conflicts with bcm2835's vc4 documentation, which 1167 * states HSM's clock has to be at least 108% of the pixel clock. 1168 * 1169 * Real life tests reveal that vc4's firmware statement holds up, and 1170 * users are able to use pixel clocks closer to HSM's, namely for 1171 * 1920x1200@60Hz. So it was decided to have leave a 1% margin between 1172 * both clocks. Which, for RPi0-3 implies a maximum pixel clock of 1173 * 162MHz. 1174 * 1175 * Additionally, the AXI clock needs to be at least 25% of 1176 * pixel clock, but HSM ends up being the limiting factor. 1177 */ 1178 hsm_rate = max_t(unsigned long, 120000000, (tmds_char_rate / 100) * 101); 1179 ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate); 1180 if (ret) { 1181 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret); 1182 goto out; 1183 } 1184 1185 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev); 1186 if (ret < 0) { 1187 DRM_ERROR("Failed to retain power domain: %d\n", ret); 1188 goto out; 1189 } 1190 1191 ret = clk_set_rate(vc4_hdmi->pixel_clock, tmds_char_rate); 1192 if (ret) { 1193 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret); 1194 goto err_put_runtime_pm; 1195 } 1196 1197 ret = clk_prepare_enable(vc4_hdmi->pixel_clock); 1198 if (ret) { 1199 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret); 1200 goto err_put_runtime_pm; 1201 } 1202 1203 1204 vc4_hdmi_cec_update_clk_div(vc4_hdmi); 1205 1206 if (tmds_char_rate > 297000000) 1207 bvb_rate = 300000000; 1208 else if (tmds_char_rate > 148500000) 1209 bvb_rate = 150000000; 1210 else 1211 bvb_rate = 75000000; 1212 1213 ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate); 1214 if (ret) { 1215 DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret); 1216 goto err_disable_pixel_clock; 1217 } 1218 1219 ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock); 1220 if (ret) { 1221 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret); 1222 goto err_disable_pixel_clock; 1223 } 1224 1225 if (vc4_hdmi->variant->phy_init) 1226 vc4_hdmi->variant->phy_init(vc4_hdmi, vc4_conn_state); 1227 1228 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1229 1230 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1231 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 1232 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT | 1233 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS); 1234 1235 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1236 1237 if (vc4_hdmi->variant->set_timings) 1238 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode); 1239 1240 mutex_unlock(&vc4_hdmi->mutex); 1241 1242 return; 1243 1244 err_disable_pixel_clock: 1245 clk_disable_unprepare(vc4_hdmi->pixel_clock); 1246 err_put_runtime_pm: 1247 pm_runtime_put(&vc4_hdmi->pdev->dev); 1248 out: 1249 mutex_unlock(&vc4_hdmi->mutex); 1250 return; 1251 } 1252 1253 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder, 1254 struct drm_atomic_state *state) 1255 { 1256 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1257 struct drm_connector *connector = &vc4_hdmi->connector; 1258 struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1259 struct drm_connector_state *conn_state = 1260 drm_atomic_get_new_connector_state(state, connector); 1261 unsigned long flags; 1262 1263 mutex_lock(&vc4_hdmi->mutex); 1264 1265 if (vc4_hdmi->variant->csc_setup) 1266 vc4_hdmi->variant->csc_setup(vc4_hdmi, conn_state, mode); 1267 1268 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1269 HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N); 1270 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1271 1272 mutex_unlock(&vc4_hdmi->mutex); 1273 } 1274 1275 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder, 1276 struct drm_atomic_state *state) 1277 { 1278 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1279 struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1280 struct drm_display_info *display = &vc4_hdmi->connector.display_info; 1281 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 1282 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 1283 unsigned long flags; 1284 int ret; 1285 1286 mutex_lock(&vc4_hdmi->mutex); 1287 1288 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1289 1290 HDMI_WRITE(HDMI_VID_CTL, 1291 VC4_HD_VID_CTL_ENABLE | 1292 VC4_HD_VID_CTL_CLRRGB | 1293 VC4_HD_VID_CTL_UNDERFLOW_ENABLE | 1294 VC4_HD_VID_CTL_FRAME_COUNTER_RESET | 1295 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) | 1296 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW)); 1297 1298 HDMI_WRITE(HDMI_VID_CTL, 1299 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX); 1300 1301 if (display->is_hdmi) { 1302 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1303 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 1304 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 1305 1306 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1307 1308 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1309 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000); 1310 WARN_ONCE(ret, "Timeout waiting for " 1311 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 1312 } else { 1313 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 1314 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & 1315 ~(VC4_HDMI_RAM_PACKET_ENABLE)); 1316 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1317 HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1318 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 1319 1320 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1321 1322 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1323 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000); 1324 WARN_ONCE(ret, "Timeout waiting for " 1325 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 1326 } 1327 1328 if (display->is_hdmi) { 1329 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1330 1331 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1332 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE)); 1333 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1334 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 1335 VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT); 1336 1337 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 1338 VC4_HDMI_RAM_PACKET_ENABLE); 1339 1340 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1341 1342 vc4_hdmi_set_infoframes(encoder); 1343 } 1344 1345 vc4_hdmi_recenter_fifo(vc4_hdmi); 1346 vc4_hdmi_enable_scrambling(encoder); 1347 1348 mutex_unlock(&vc4_hdmi->mutex); 1349 } 1350 1351 static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder) 1352 { 1353 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1354 1355 mutex_lock(&vc4_hdmi->mutex); 1356 vc4_hdmi->output_enabled = true; 1357 mutex_unlock(&vc4_hdmi->mutex); 1358 } 1359 1360 static void vc4_hdmi_encoder_atomic_mode_set(struct drm_encoder *encoder, 1361 struct drm_crtc_state *crtc_state, 1362 struct drm_connector_state *conn_state) 1363 { 1364 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1365 struct vc4_hdmi_connector_state *vc4_state = 1366 conn_state_to_vc4_hdmi_conn_state(conn_state); 1367 1368 mutex_lock(&vc4_hdmi->mutex); 1369 drm_mode_copy(&vc4_hdmi->saved_adjusted_mode, 1370 &crtc_state->adjusted_mode); 1371 vc4_hdmi->output_bpc = vc4_state->output_bpc; 1372 vc4_hdmi->output_format = vc4_state->output_format; 1373 mutex_unlock(&vc4_hdmi->mutex); 1374 } 1375 1376 static bool 1377 vc4_hdmi_sink_supports_format_bpc(const struct vc4_hdmi *vc4_hdmi, 1378 const struct drm_display_info *info, 1379 const struct drm_display_mode *mode, 1380 unsigned int format, unsigned int bpc) 1381 { 1382 struct drm_device *dev = vc4_hdmi->connector.dev; 1383 u8 vic = drm_match_cea_mode(mode); 1384 1385 if (vic == 1 && bpc != 8) { 1386 drm_dbg(dev, "VIC1 requires a bpc of 8, got %u\n", bpc); 1387 return false; 1388 } 1389 1390 if (!info->is_hdmi && 1391 (format != VC4_HDMI_OUTPUT_RGB || bpc != 8)) { 1392 drm_dbg(dev, "DVI Monitors require an RGB output at 8 bpc\n"); 1393 return false; 1394 } 1395 1396 switch (format) { 1397 case VC4_HDMI_OUTPUT_RGB: 1398 drm_dbg(dev, "RGB Format, checking the constraints.\n"); 1399 1400 if (!(info->color_formats & DRM_COLOR_FORMAT_RGB444)) 1401 return false; 1402 1403 if (bpc == 10 && !(info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30)) { 1404 drm_dbg(dev, "10 BPC but sink doesn't support Deep Color 30.\n"); 1405 return false; 1406 } 1407 1408 if (bpc == 12 && !(info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36)) { 1409 drm_dbg(dev, "12 BPC but sink doesn't support Deep Color 36.\n"); 1410 return false; 1411 } 1412 1413 drm_dbg(dev, "RGB format supported in that configuration.\n"); 1414 1415 return true; 1416 1417 case VC4_HDMI_OUTPUT_YUV422: 1418 drm_dbg(dev, "YUV422 format, checking the constraints.\n"); 1419 1420 if (!(info->color_formats & DRM_COLOR_FORMAT_YCBCR422)) { 1421 drm_dbg(dev, "Sink doesn't support YUV422.\n"); 1422 return false; 1423 } 1424 1425 if (bpc != 12) { 1426 drm_dbg(dev, "YUV422 only supports 12 bpc.\n"); 1427 return false; 1428 } 1429 1430 drm_dbg(dev, "YUV422 format supported in that configuration.\n"); 1431 1432 return true; 1433 1434 case VC4_HDMI_OUTPUT_YUV444: 1435 drm_dbg(dev, "YUV444 format, checking the constraints.\n"); 1436 1437 if (!(info->color_formats & DRM_COLOR_FORMAT_YCBCR444)) { 1438 drm_dbg(dev, "Sink doesn't support YUV444.\n"); 1439 return false; 1440 } 1441 1442 if (bpc == 10 && !(info->edid_hdmi_ycbcr444_dc_modes & DRM_EDID_HDMI_DC_30)) { 1443 drm_dbg(dev, "10 BPC but sink doesn't support Deep Color 30.\n"); 1444 return false; 1445 } 1446 1447 if (bpc == 12 && !(info->edid_hdmi_ycbcr444_dc_modes & DRM_EDID_HDMI_DC_36)) { 1448 drm_dbg(dev, "12 BPC but sink doesn't support Deep Color 36.\n"); 1449 return false; 1450 } 1451 1452 drm_dbg(dev, "YUV444 format supported in that configuration.\n"); 1453 1454 return true; 1455 } 1456 1457 return false; 1458 } 1459 1460 static enum drm_mode_status 1461 vc4_hdmi_encoder_clock_valid(const struct vc4_hdmi *vc4_hdmi, 1462 unsigned long long clock) 1463 { 1464 const struct drm_connector *connector = &vc4_hdmi->connector; 1465 const struct drm_display_info *info = &connector->display_info; 1466 1467 if (clock > vc4_hdmi->variant->max_pixel_clock) 1468 return MODE_CLOCK_HIGH; 1469 1470 if (vc4_hdmi->disable_4kp60 && clock > HDMI_14_MAX_TMDS_CLK) 1471 return MODE_CLOCK_HIGH; 1472 1473 if (info->max_tmds_clock && clock > (info->max_tmds_clock * 1000)) 1474 return MODE_CLOCK_HIGH; 1475 1476 return MODE_OK; 1477 } 1478 1479 static unsigned long long 1480 vc4_hdmi_encoder_compute_mode_clock(const struct drm_display_mode *mode, 1481 unsigned int bpc, 1482 enum vc4_hdmi_output_format fmt) 1483 { 1484 unsigned long long clock = mode->clock * 1000; 1485 1486 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 1487 clock = clock * 2; 1488 1489 if (fmt == VC4_HDMI_OUTPUT_YUV422) 1490 bpc = 8; 1491 1492 clock = clock * bpc; 1493 do_div(clock, 8); 1494 1495 return clock; 1496 } 1497 1498 static int 1499 vc4_hdmi_encoder_compute_clock(const struct vc4_hdmi *vc4_hdmi, 1500 struct vc4_hdmi_connector_state *vc4_state, 1501 const struct drm_display_mode *mode, 1502 unsigned int bpc, unsigned int fmt) 1503 { 1504 unsigned long long clock; 1505 1506 clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc, fmt); 1507 if (vc4_hdmi_encoder_clock_valid(vc4_hdmi, clock) != MODE_OK) 1508 return -EINVAL; 1509 1510 vc4_state->tmds_char_rate = clock; 1511 1512 return 0; 1513 } 1514 1515 static int 1516 vc4_hdmi_encoder_compute_format(const struct vc4_hdmi *vc4_hdmi, 1517 struct vc4_hdmi_connector_state *vc4_state, 1518 const struct drm_display_mode *mode, 1519 unsigned int bpc) 1520 { 1521 struct drm_device *dev = vc4_hdmi->connector.dev; 1522 const struct drm_connector *connector = &vc4_hdmi->connector; 1523 const struct drm_display_info *info = &connector->display_info; 1524 unsigned int format; 1525 1526 drm_dbg(dev, "Trying with an RGB output\n"); 1527 1528 format = VC4_HDMI_OUTPUT_RGB; 1529 if (vc4_hdmi_sink_supports_format_bpc(vc4_hdmi, info, mode, format, bpc)) { 1530 int ret; 1531 1532 ret = vc4_hdmi_encoder_compute_clock(vc4_hdmi, vc4_state, 1533 mode, bpc, format); 1534 if (!ret) { 1535 vc4_state->output_format = format; 1536 return 0; 1537 } 1538 } 1539 1540 drm_dbg(dev, "Failed, Trying with an YUV422 output\n"); 1541 1542 format = VC4_HDMI_OUTPUT_YUV422; 1543 if (vc4_hdmi_sink_supports_format_bpc(vc4_hdmi, info, mode, format, bpc)) { 1544 int ret; 1545 1546 ret = vc4_hdmi_encoder_compute_clock(vc4_hdmi, vc4_state, 1547 mode, bpc, format); 1548 if (!ret) { 1549 vc4_state->output_format = format; 1550 return 0; 1551 } 1552 } 1553 1554 drm_dbg(dev, "Failed. No Format Supported for that bpc count.\n"); 1555 1556 return -EINVAL; 1557 } 1558 1559 static int 1560 vc4_hdmi_encoder_compute_config(const struct vc4_hdmi *vc4_hdmi, 1561 struct vc4_hdmi_connector_state *vc4_state, 1562 const struct drm_display_mode *mode) 1563 { 1564 struct drm_device *dev = vc4_hdmi->connector.dev; 1565 struct drm_connector_state *conn_state = &vc4_state->base; 1566 unsigned int max_bpc = clamp_t(unsigned int, conn_state->max_bpc, 8, 12); 1567 unsigned int bpc; 1568 int ret; 1569 1570 for (bpc = max_bpc; bpc >= 8; bpc -= 2) { 1571 drm_dbg(dev, "Trying with a %d bpc output\n", bpc); 1572 1573 ret = vc4_hdmi_encoder_compute_format(vc4_hdmi, vc4_state, 1574 mode, bpc); 1575 if (ret) 1576 continue; 1577 1578 vc4_state->output_bpc = bpc; 1579 1580 drm_dbg(dev, 1581 "Mode %ux%u @ %uHz: Found configuration: bpc: %u, fmt: %s, clock: %llu\n", 1582 mode->hdisplay, mode->vdisplay, drm_mode_vrefresh(mode), 1583 vc4_state->output_bpc, 1584 vc4_hdmi_output_fmt_str(vc4_state->output_format), 1585 vc4_state->tmds_char_rate); 1586 1587 break; 1588 } 1589 1590 return ret; 1591 } 1592 1593 #define WIFI_2_4GHz_CH1_MIN_FREQ 2400000000ULL 1594 #define WIFI_2_4GHz_CH1_MAX_FREQ 2422000000ULL 1595 1596 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder, 1597 struct drm_crtc_state *crtc_state, 1598 struct drm_connector_state *conn_state) 1599 { 1600 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state); 1601 struct drm_display_mode *mode = &crtc_state->adjusted_mode; 1602 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1603 unsigned long long tmds_char_rate = mode->clock * 1000; 1604 unsigned long long tmds_bit_rate; 1605 int ret; 1606 1607 if (vc4_hdmi->variant->unsupported_odd_h_timings && 1608 !(mode->flags & DRM_MODE_FLAG_DBLCLK) && 1609 ((mode->hdisplay % 2) || (mode->hsync_start % 2) || 1610 (mode->hsync_end % 2) || (mode->htotal % 2))) 1611 return -EINVAL; 1612 1613 /* 1614 * The 1440p@60 pixel rate is in the same range than the first 1615 * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz 1616 * bandwidth). Slightly lower the frequency to bring it out of 1617 * the WiFi range. 1618 */ 1619 tmds_bit_rate = tmds_char_rate * 10; 1620 if (vc4_hdmi->disable_wifi_frequencies && 1621 (tmds_bit_rate >= WIFI_2_4GHz_CH1_MIN_FREQ && 1622 tmds_bit_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) { 1623 mode->clock = 238560; 1624 tmds_char_rate = mode->clock * 1000; 1625 } 1626 1627 ret = vc4_hdmi_encoder_compute_config(vc4_hdmi, vc4_state, mode); 1628 if (ret) 1629 return ret; 1630 1631 return 0; 1632 } 1633 1634 static enum drm_mode_status 1635 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder, 1636 const struct drm_display_mode *mode) 1637 { 1638 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1639 1640 if (vc4_hdmi->variant->unsupported_odd_h_timings && 1641 !(mode->flags & DRM_MODE_FLAG_DBLCLK) && 1642 ((mode->hdisplay % 2) || (mode->hsync_start % 2) || 1643 (mode->hsync_end % 2) || (mode->htotal % 2))) 1644 return MODE_H_ILLEGAL; 1645 1646 return vc4_hdmi_encoder_clock_valid(vc4_hdmi, mode->clock * 1000); 1647 } 1648 1649 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = { 1650 .atomic_check = vc4_hdmi_encoder_atomic_check, 1651 .atomic_mode_set = vc4_hdmi_encoder_atomic_mode_set, 1652 .mode_valid = vc4_hdmi_encoder_mode_valid, 1653 .disable = vc4_hdmi_encoder_disable, 1654 .enable = vc4_hdmi_encoder_enable, 1655 }; 1656 1657 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask) 1658 { 1659 int i; 1660 u32 channel_map = 0; 1661 1662 for (i = 0; i < 8; i++) { 1663 if (channel_mask & BIT(i)) 1664 channel_map |= i << (3 * i); 1665 } 1666 return channel_map; 1667 } 1668 1669 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask) 1670 { 1671 int i; 1672 u32 channel_map = 0; 1673 1674 for (i = 0; i < 8; i++) { 1675 if (channel_mask & BIT(i)) 1676 channel_map |= i << (4 * i); 1677 } 1678 return channel_map; 1679 } 1680 1681 static bool vc5_hdmi_hp_detect(struct vc4_hdmi *vc4_hdmi) 1682 { 1683 unsigned long flags; 1684 u32 hotplug; 1685 1686 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1687 hotplug = HDMI_READ(HDMI_HOTPLUG); 1688 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1689 1690 return !!(hotplug & VC4_HDMI_HOTPLUG_CONNECTED); 1691 } 1692 1693 /* HDMI audio codec callbacks */ 1694 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi, 1695 unsigned int samplerate) 1696 { 1697 u32 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock); 1698 unsigned long flags; 1699 unsigned long n, m; 1700 1701 rational_best_approximation(hsm_clock, samplerate, 1702 VC4_HD_MAI_SMP_N_MASK >> 1703 VC4_HD_MAI_SMP_N_SHIFT, 1704 (VC4_HD_MAI_SMP_M_MASK >> 1705 VC4_HD_MAI_SMP_M_SHIFT) + 1, 1706 &n, &m); 1707 1708 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1709 HDMI_WRITE(HDMI_MAI_SMP, 1710 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) | 1711 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M)); 1712 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1713 } 1714 1715 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi, unsigned int samplerate) 1716 { 1717 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1718 u32 n, cts; 1719 u64 tmp; 1720 1721 lockdep_assert_held(&vc4_hdmi->mutex); 1722 lockdep_assert_held(&vc4_hdmi->hw_lock); 1723 1724 n = 128 * samplerate / 1000; 1725 tmp = (u64)(mode->clock * 1000) * n; 1726 do_div(tmp, 128 * samplerate); 1727 cts = tmp; 1728 1729 HDMI_WRITE(HDMI_CRP_CFG, 1730 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN | 1731 VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N)); 1732 1733 /* 1734 * We could get slightly more accurate clocks in some cases by 1735 * providing a CTS_1 value. The two CTS values are alternated 1736 * between based on the period fields 1737 */ 1738 HDMI_WRITE(HDMI_CTS_0, cts); 1739 HDMI_WRITE(HDMI_CTS_1, cts); 1740 } 1741 1742 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai) 1743 { 1744 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai); 1745 1746 return snd_soc_card_get_drvdata(card); 1747 } 1748 1749 static bool vc4_hdmi_audio_can_stream(struct vc4_hdmi *vc4_hdmi) 1750 { 1751 lockdep_assert_held(&vc4_hdmi->mutex); 1752 1753 /* 1754 * If the controller is disabled, prevent any ALSA output. 1755 */ 1756 if (!vc4_hdmi->output_enabled) 1757 return false; 1758 1759 /* 1760 * If the encoder is currently in DVI mode, treat the codec DAI 1761 * as missing. 1762 */ 1763 if (!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) & VC4_HDMI_RAM_PACKET_ENABLE)) 1764 return false; 1765 1766 return true; 1767 } 1768 1769 static int vc4_hdmi_audio_startup(struct device *dev, void *data) 1770 { 1771 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 1772 unsigned long flags; 1773 1774 mutex_lock(&vc4_hdmi->mutex); 1775 1776 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) { 1777 mutex_unlock(&vc4_hdmi->mutex); 1778 return -ENODEV; 1779 } 1780 1781 vc4_hdmi->audio.streaming = true; 1782 1783 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1784 HDMI_WRITE(HDMI_MAI_CTL, 1785 VC4_HD_MAI_CTL_RESET | 1786 VC4_HD_MAI_CTL_FLUSH | 1787 VC4_HD_MAI_CTL_DLATE | 1788 VC4_HD_MAI_CTL_ERRORE | 1789 VC4_HD_MAI_CTL_ERRORF); 1790 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1791 1792 if (vc4_hdmi->variant->phy_rng_enable) 1793 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi); 1794 1795 mutex_unlock(&vc4_hdmi->mutex); 1796 1797 return 0; 1798 } 1799 1800 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi) 1801 { 1802 struct drm_encoder *encoder = &vc4_hdmi->encoder.base; 1803 struct device *dev = &vc4_hdmi->pdev->dev; 1804 unsigned long flags; 1805 int ret; 1806 1807 lockdep_assert_held(&vc4_hdmi->mutex); 1808 1809 vc4_hdmi->audio.streaming = false; 1810 ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO, false); 1811 if (ret) 1812 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret); 1813 1814 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1815 1816 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET); 1817 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF); 1818 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH); 1819 1820 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1821 } 1822 1823 static void vc4_hdmi_audio_shutdown(struct device *dev, void *data) 1824 { 1825 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 1826 unsigned long flags; 1827 1828 mutex_lock(&vc4_hdmi->mutex); 1829 1830 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1831 1832 HDMI_WRITE(HDMI_MAI_CTL, 1833 VC4_HD_MAI_CTL_DLATE | 1834 VC4_HD_MAI_CTL_ERRORE | 1835 VC4_HD_MAI_CTL_ERRORF); 1836 1837 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1838 1839 if (vc4_hdmi->variant->phy_rng_disable) 1840 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi); 1841 1842 vc4_hdmi->audio.streaming = false; 1843 vc4_hdmi_audio_reset(vc4_hdmi); 1844 1845 mutex_unlock(&vc4_hdmi->mutex); 1846 } 1847 1848 static int sample_rate_to_mai_fmt(int samplerate) 1849 { 1850 switch (samplerate) { 1851 case 8000: 1852 return VC4_HDMI_MAI_SAMPLE_RATE_8000; 1853 case 11025: 1854 return VC4_HDMI_MAI_SAMPLE_RATE_11025; 1855 case 12000: 1856 return VC4_HDMI_MAI_SAMPLE_RATE_12000; 1857 case 16000: 1858 return VC4_HDMI_MAI_SAMPLE_RATE_16000; 1859 case 22050: 1860 return VC4_HDMI_MAI_SAMPLE_RATE_22050; 1861 case 24000: 1862 return VC4_HDMI_MAI_SAMPLE_RATE_24000; 1863 case 32000: 1864 return VC4_HDMI_MAI_SAMPLE_RATE_32000; 1865 case 44100: 1866 return VC4_HDMI_MAI_SAMPLE_RATE_44100; 1867 case 48000: 1868 return VC4_HDMI_MAI_SAMPLE_RATE_48000; 1869 case 64000: 1870 return VC4_HDMI_MAI_SAMPLE_RATE_64000; 1871 case 88200: 1872 return VC4_HDMI_MAI_SAMPLE_RATE_88200; 1873 case 96000: 1874 return VC4_HDMI_MAI_SAMPLE_RATE_96000; 1875 case 128000: 1876 return VC4_HDMI_MAI_SAMPLE_RATE_128000; 1877 case 176400: 1878 return VC4_HDMI_MAI_SAMPLE_RATE_176400; 1879 case 192000: 1880 return VC4_HDMI_MAI_SAMPLE_RATE_192000; 1881 default: 1882 return VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED; 1883 } 1884 } 1885 1886 /* HDMI audio codec callbacks */ 1887 static int vc4_hdmi_audio_prepare(struct device *dev, void *data, 1888 struct hdmi_codec_daifmt *daifmt, 1889 struct hdmi_codec_params *params) 1890 { 1891 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 1892 struct drm_encoder *encoder = &vc4_hdmi->encoder.base; 1893 unsigned int sample_rate = params->sample_rate; 1894 unsigned int channels = params->channels; 1895 unsigned long flags; 1896 u32 audio_packet_config, channel_mask; 1897 u32 channel_map; 1898 u32 mai_audio_format; 1899 u32 mai_sample_rate; 1900 1901 dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__, 1902 sample_rate, params->sample_width, channels); 1903 1904 mutex_lock(&vc4_hdmi->mutex); 1905 1906 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) { 1907 mutex_unlock(&vc4_hdmi->mutex); 1908 return -EINVAL; 1909 } 1910 1911 vc4_hdmi_audio_set_mai_clock(vc4_hdmi, sample_rate); 1912 1913 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1914 HDMI_WRITE(HDMI_MAI_CTL, 1915 VC4_SET_FIELD(channels, VC4_HD_MAI_CTL_CHNUM) | 1916 VC4_HD_MAI_CTL_WHOLSMP | 1917 VC4_HD_MAI_CTL_CHALIGN | 1918 VC4_HD_MAI_CTL_ENABLE); 1919 1920 mai_sample_rate = sample_rate_to_mai_fmt(sample_rate); 1921 if (params->iec.status[0] & IEC958_AES0_NONAUDIO && 1922 params->channels == 8) 1923 mai_audio_format = VC4_HDMI_MAI_FORMAT_HBR; 1924 else 1925 mai_audio_format = VC4_HDMI_MAI_FORMAT_PCM; 1926 HDMI_WRITE(HDMI_MAI_FMT, 1927 VC4_SET_FIELD(mai_sample_rate, 1928 VC4_HDMI_MAI_FORMAT_SAMPLE_RATE) | 1929 VC4_SET_FIELD(mai_audio_format, 1930 VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT)); 1931 1932 /* The B frame identifier should match the value used by alsa-lib (8) */ 1933 audio_packet_config = 1934 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT | 1935 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS | 1936 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER); 1937 1938 channel_mask = GENMASK(channels - 1, 0); 1939 audio_packet_config |= VC4_SET_FIELD(channel_mask, 1940 VC4_HDMI_AUDIO_PACKET_CEA_MASK); 1941 1942 /* Set the MAI threshold */ 1943 HDMI_WRITE(HDMI_MAI_THR, 1944 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) | 1945 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) | 1946 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQHIGH) | 1947 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQLOW)); 1948 1949 HDMI_WRITE(HDMI_MAI_CONFIG, 1950 VC4_HDMI_MAI_CONFIG_BIT_REVERSE | 1951 VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE | 1952 VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK)); 1953 1954 channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask); 1955 HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map); 1956 HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config); 1957 1958 vc4_hdmi_set_n_cts(vc4_hdmi, sample_rate); 1959 1960 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1961 1962 memcpy(&vc4_hdmi->audio.infoframe, ¶ms->cea, sizeof(params->cea)); 1963 vc4_hdmi_set_audio_infoframe(encoder); 1964 1965 mutex_unlock(&vc4_hdmi->mutex); 1966 1967 return 0; 1968 } 1969 1970 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = { 1971 .name = "vc4-hdmi-cpu-dai-component", 1972 }; 1973 1974 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai) 1975 { 1976 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai); 1977 1978 snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL); 1979 1980 return 0; 1981 } 1982 1983 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = { 1984 .name = "vc4-hdmi-cpu-dai", 1985 .probe = vc4_hdmi_audio_cpu_dai_probe, 1986 .playback = { 1987 .stream_name = "Playback", 1988 .channels_min = 1, 1989 .channels_max = 8, 1990 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 1991 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 1992 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 1993 SNDRV_PCM_RATE_192000, 1994 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 1995 }, 1996 }; 1997 1998 static const struct snd_dmaengine_pcm_config pcm_conf = { 1999 .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx", 2000 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 2001 }; 2002 2003 static int vc4_hdmi_audio_get_eld(struct device *dev, void *data, 2004 uint8_t *buf, size_t len) 2005 { 2006 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 2007 struct drm_connector *connector = &vc4_hdmi->connector; 2008 2009 mutex_lock(&vc4_hdmi->mutex); 2010 memcpy(buf, connector->eld, min(sizeof(connector->eld), len)); 2011 mutex_unlock(&vc4_hdmi->mutex); 2012 2013 return 0; 2014 } 2015 2016 static const struct hdmi_codec_ops vc4_hdmi_codec_ops = { 2017 .get_eld = vc4_hdmi_audio_get_eld, 2018 .prepare = vc4_hdmi_audio_prepare, 2019 .audio_shutdown = vc4_hdmi_audio_shutdown, 2020 .audio_startup = vc4_hdmi_audio_startup, 2021 }; 2022 2023 static struct hdmi_codec_pdata vc4_hdmi_codec_pdata = { 2024 .ops = &vc4_hdmi_codec_ops, 2025 .max_i2s_channels = 8, 2026 .i2s = 1, 2027 }; 2028 2029 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi) 2030 { 2031 const struct vc4_hdmi_register *mai_data = 2032 &vc4_hdmi->variant->registers[HDMI_MAI_DATA]; 2033 struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link; 2034 struct snd_soc_card *card = &vc4_hdmi->audio.card; 2035 struct device *dev = &vc4_hdmi->pdev->dev; 2036 struct platform_device *codec_pdev; 2037 const __be32 *addr; 2038 int index; 2039 int ret; 2040 2041 if (!of_find_property(dev->of_node, "dmas", NULL)) { 2042 dev_warn(dev, 2043 "'dmas' DT property is missing, no HDMI audio\n"); 2044 return 0; 2045 } 2046 2047 if (mai_data->reg != VC4_HD) { 2048 WARN_ONCE(true, "MAI isn't in the HD block\n"); 2049 return -EINVAL; 2050 } 2051 2052 /* 2053 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve 2054 * the bus address specified in the DT, because the physical address 2055 * (the one returned by platform_get_resource()) is not appropriate 2056 * for DMA transfers. 2057 * This VC/MMU should probably be exposed to avoid this kind of hacks. 2058 */ 2059 index = of_property_match_string(dev->of_node, "reg-names", "hd"); 2060 /* Before BCM2711, we don't have a named register range */ 2061 if (index < 0) 2062 index = 1; 2063 2064 addr = of_get_address(dev->of_node, index, NULL, NULL); 2065 2066 vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset; 2067 vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 2068 vc4_hdmi->audio.dma_data.maxburst = 2; 2069 2070 ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0); 2071 if (ret) { 2072 dev_err(dev, "Could not register PCM component: %d\n", ret); 2073 return ret; 2074 } 2075 2076 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp, 2077 &vc4_hdmi_audio_cpu_dai_drv, 1); 2078 if (ret) { 2079 dev_err(dev, "Could not register CPU DAI: %d\n", ret); 2080 return ret; 2081 } 2082 2083 codec_pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME, 2084 PLATFORM_DEVID_AUTO, 2085 &vc4_hdmi_codec_pdata, 2086 sizeof(vc4_hdmi_codec_pdata)); 2087 if (IS_ERR(codec_pdev)) { 2088 dev_err(dev, "Couldn't register the HDMI codec: %ld\n", PTR_ERR(codec_pdev)); 2089 return PTR_ERR(codec_pdev); 2090 } 2091 vc4_hdmi->audio.codec_pdev = codec_pdev; 2092 2093 dai_link->cpus = &vc4_hdmi->audio.cpu; 2094 dai_link->codecs = &vc4_hdmi->audio.codec; 2095 dai_link->platforms = &vc4_hdmi->audio.platform; 2096 2097 dai_link->num_cpus = 1; 2098 dai_link->num_codecs = 1; 2099 dai_link->num_platforms = 1; 2100 2101 dai_link->name = "MAI"; 2102 dai_link->stream_name = "MAI PCM"; 2103 dai_link->codecs->dai_name = "i2s-hifi"; 2104 dai_link->cpus->dai_name = dev_name(dev); 2105 dai_link->codecs->name = dev_name(&codec_pdev->dev); 2106 dai_link->platforms->name = dev_name(dev); 2107 2108 card->dai_link = dai_link; 2109 card->num_links = 1; 2110 card->name = vc4_hdmi->variant->card_name; 2111 card->driver_name = "vc4-hdmi"; 2112 card->dev = dev; 2113 card->owner = THIS_MODULE; 2114 2115 /* 2116 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and 2117 * stores a pointer to the snd card object in dev->driver_data. This 2118 * means we cannot use it for something else. The hdmi back-pointer is 2119 * now stored in card->drvdata and should be retrieved with 2120 * snd_soc_card_get_drvdata() if needed. 2121 */ 2122 snd_soc_card_set_drvdata(card, vc4_hdmi); 2123 ret = devm_snd_soc_register_card(dev, card); 2124 if (ret) 2125 dev_err_probe(dev, ret, "Could not register sound card\n"); 2126 2127 return ret; 2128 2129 } 2130 2131 static void vc4_hdmi_audio_exit(struct vc4_hdmi *vc4_hdmi) 2132 { 2133 platform_device_unregister(vc4_hdmi->audio.codec_pdev); 2134 vc4_hdmi->audio.codec_pdev = NULL; 2135 } 2136 2137 static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv) 2138 { 2139 struct vc4_hdmi *vc4_hdmi = priv; 2140 struct drm_connector *connector = &vc4_hdmi->connector; 2141 struct drm_device *dev = connector->dev; 2142 2143 if (dev && dev->registered) 2144 drm_connector_helper_hpd_irq_event(connector); 2145 2146 return IRQ_HANDLED; 2147 } 2148 2149 static int vc4_hdmi_hotplug_init(struct vc4_hdmi *vc4_hdmi) 2150 { 2151 struct drm_connector *connector = &vc4_hdmi->connector; 2152 struct platform_device *pdev = vc4_hdmi->pdev; 2153 int ret; 2154 2155 if (vc4_hdmi->variant->external_irq_controller) { 2156 unsigned int hpd_con = platform_get_irq_byname(pdev, "hpd-connected"); 2157 unsigned int hpd_rm = platform_get_irq_byname(pdev, "hpd-removed"); 2158 2159 ret = request_threaded_irq(hpd_con, 2160 NULL, 2161 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT, 2162 "vc4 hdmi hpd connected", vc4_hdmi); 2163 if (ret) 2164 return ret; 2165 2166 ret = request_threaded_irq(hpd_rm, 2167 NULL, 2168 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT, 2169 "vc4 hdmi hpd disconnected", vc4_hdmi); 2170 if (ret) { 2171 free_irq(hpd_con, vc4_hdmi); 2172 return ret; 2173 } 2174 2175 connector->polled = DRM_CONNECTOR_POLL_HPD; 2176 } 2177 2178 return 0; 2179 } 2180 2181 static void vc4_hdmi_hotplug_exit(struct vc4_hdmi *vc4_hdmi) 2182 { 2183 struct platform_device *pdev = vc4_hdmi->pdev; 2184 2185 if (vc4_hdmi->variant->external_irq_controller) { 2186 free_irq(platform_get_irq_byname(pdev, "hpd-connected"), vc4_hdmi); 2187 free_irq(platform_get_irq_byname(pdev, "hpd-removed"), vc4_hdmi); 2188 } 2189 } 2190 2191 #ifdef CONFIG_DRM_VC4_HDMI_CEC 2192 static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv) 2193 { 2194 struct vc4_hdmi *vc4_hdmi = priv; 2195 2196 if (vc4_hdmi->cec_rx_msg.len) 2197 cec_received_msg(vc4_hdmi->cec_adap, 2198 &vc4_hdmi->cec_rx_msg); 2199 2200 return IRQ_HANDLED; 2201 } 2202 2203 static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv) 2204 { 2205 struct vc4_hdmi *vc4_hdmi = priv; 2206 2207 if (vc4_hdmi->cec_tx_ok) { 2208 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK, 2209 0, 0, 0, 0); 2210 } else { 2211 /* 2212 * This CEC implementation makes 1 retry, so if we 2213 * get a NACK, then that means it made 2 attempts. 2214 */ 2215 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK, 2216 0, 2, 0, 0); 2217 } 2218 return IRQ_HANDLED; 2219 } 2220 2221 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv) 2222 { 2223 struct vc4_hdmi *vc4_hdmi = priv; 2224 irqreturn_t ret; 2225 2226 if (vc4_hdmi->cec_irq_was_rx) 2227 ret = vc4_cec_irq_handler_rx_thread(irq, priv); 2228 else 2229 ret = vc4_cec_irq_handler_tx_thread(irq, priv); 2230 2231 return ret; 2232 } 2233 2234 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1) 2235 { 2236 struct drm_device *dev = vc4_hdmi->connector.dev; 2237 struct cec_msg *msg = &vc4_hdmi->cec_rx_msg; 2238 unsigned int i; 2239 2240 lockdep_assert_held(&vc4_hdmi->hw_lock); 2241 2242 msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >> 2243 VC4_HDMI_CEC_REC_WRD_CNT_SHIFT); 2244 2245 if (msg->len > 16) { 2246 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len); 2247 return; 2248 } 2249 2250 for (i = 0; i < msg->len; i += 4) { 2251 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2)); 2252 2253 msg->msg[i] = val & 0xff; 2254 msg->msg[i + 1] = (val >> 8) & 0xff; 2255 msg->msg[i + 2] = (val >> 16) & 0xff; 2256 msg->msg[i + 3] = (val >> 24) & 0xff; 2257 } 2258 } 2259 2260 static irqreturn_t vc4_cec_irq_handler_tx_bare_locked(struct vc4_hdmi *vc4_hdmi) 2261 { 2262 u32 cntrl1; 2263 2264 lockdep_assert_held(&vc4_hdmi->hw_lock); 2265 2266 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1); 2267 vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD; 2268 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 2269 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 2270 2271 return IRQ_WAKE_THREAD; 2272 } 2273 2274 static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv) 2275 { 2276 struct vc4_hdmi *vc4_hdmi = priv; 2277 irqreturn_t ret; 2278 2279 spin_lock(&vc4_hdmi->hw_lock); 2280 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi); 2281 spin_unlock(&vc4_hdmi->hw_lock); 2282 2283 return ret; 2284 } 2285 2286 static irqreturn_t vc4_cec_irq_handler_rx_bare_locked(struct vc4_hdmi *vc4_hdmi) 2287 { 2288 u32 cntrl1; 2289 2290 lockdep_assert_held(&vc4_hdmi->hw_lock); 2291 2292 vc4_hdmi->cec_rx_msg.len = 0; 2293 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1); 2294 vc4_cec_read_msg(vc4_hdmi, cntrl1); 2295 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 2296 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 2297 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 2298 2299 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 2300 2301 return IRQ_WAKE_THREAD; 2302 } 2303 2304 static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv) 2305 { 2306 struct vc4_hdmi *vc4_hdmi = priv; 2307 irqreturn_t ret; 2308 2309 spin_lock(&vc4_hdmi->hw_lock); 2310 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi); 2311 spin_unlock(&vc4_hdmi->hw_lock); 2312 2313 return ret; 2314 } 2315 2316 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv) 2317 { 2318 struct vc4_hdmi *vc4_hdmi = priv; 2319 u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS); 2320 irqreturn_t ret; 2321 u32 cntrl5; 2322 2323 if (!(stat & VC4_HDMI_CPU_CEC)) 2324 return IRQ_NONE; 2325 2326 spin_lock(&vc4_hdmi->hw_lock); 2327 cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5); 2328 vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT; 2329 if (vc4_hdmi->cec_irq_was_rx) 2330 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi); 2331 else 2332 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi); 2333 2334 HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC); 2335 spin_unlock(&vc4_hdmi->hw_lock); 2336 2337 return ret; 2338 } 2339 2340 static int vc4_hdmi_cec_enable(struct cec_adapter *adap) 2341 { 2342 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 2343 /* clock period in microseconds */ 2344 const u32 usecs = 1000000 / CEC_CLOCK_FREQ; 2345 unsigned long flags; 2346 u32 val; 2347 int ret; 2348 2349 /* 2350 * NOTE: This function should really take vc4_hdmi->mutex, but doing so 2351 * results in a reentrancy since cec_s_phys_addr_from_edid() called in 2352 * .detect or .get_modes might call .adap_enable, which leads to this 2353 * function being called with that mutex held. 2354 * 2355 * Concurrency is not an issue for the moment since we don't share any 2356 * state with KMS, so we can ignore the lock for now, but we need to 2357 * keep it in mind if we were to change that assumption. 2358 */ 2359 2360 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev); 2361 if (ret) 2362 return ret; 2363 2364 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2365 2366 val = HDMI_READ(HDMI_CEC_CNTRL_5); 2367 val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET | 2368 VC4_HDMI_CEC_CNT_TO_4700_US_MASK | 2369 VC4_HDMI_CEC_CNT_TO_4500_US_MASK); 2370 val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) | 2371 ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT); 2372 2373 HDMI_WRITE(HDMI_CEC_CNTRL_5, val | 2374 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 2375 HDMI_WRITE(HDMI_CEC_CNTRL_5, val); 2376 HDMI_WRITE(HDMI_CEC_CNTRL_2, 2377 ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) | 2378 ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) | 2379 ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) | 2380 ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) | 2381 ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT)); 2382 HDMI_WRITE(HDMI_CEC_CNTRL_3, 2383 ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) | 2384 ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) | 2385 ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) | 2386 ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT)); 2387 HDMI_WRITE(HDMI_CEC_CNTRL_4, 2388 ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) | 2389 ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) | 2390 ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) | 2391 ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT)); 2392 2393 if (!vc4_hdmi->variant->external_irq_controller) 2394 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC); 2395 2396 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2397 2398 return 0; 2399 } 2400 2401 static int vc4_hdmi_cec_disable(struct cec_adapter *adap) 2402 { 2403 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 2404 unsigned long flags; 2405 2406 /* 2407 * NOTE: This function should really take vc4_hdmi->mutex, but doing so 2408 * results in a reentrancy since cec_s_phys_addr_from_edid() called in 2409 * .detect or .get_modes might call .adap_enable, which leads to this 2410 * function being called with that mutex held. 2411 * 2412 * Concurrency is not an issue for the moment since we don't share any 2413 * state with KMS, so we can ignore the lock for now, but we need to 2414 * keep it in mind if we were to change that assumption. 2415 */ 2416 2417 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2418 2419 if (!vc4_hdmi->variant->external_irq_controller) 2420 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC); 2421 2422 HDMI_WRITE(HDMI_CEC_CNTRL_5, HDMI_READ(HDMI_CEC_CNTRL_5) | 2423 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 2424 2425 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2426 2427 pm_runtime_put(&vc4_hdmi->pdev->dev); 2428 2429 return 0; 2430 } 2431 2432 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable) 2433 { 2434 if (enable) 2435 return vc4_hdmi_cec_enable(adap); 2436 else 2437 return vc4_hdmi_cec_disable(adap); 2438 } 2439 2440 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr) 2441 { 2442 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 2443 unsigned long flags; 2444 2445 /* 2446 * NOTE: This function should really take vc4_hdmi->mutex, but doing so 2447 * results in a reentrancy since cec_s_phys_addr_from_edid() called in 2448 * .detect or .get_modes might call .adap_enable, which leads to this 2449 * function being called with that mutex held. 2450 * 2451 * Concurrency is not an issue for the moment since we don't share any 2452 * state with KMS, so we can ignore the lock for now, but we need to 2453 * keep it in mind if we were to change that assumption. 2454 */ 2455 2456 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2457 HDMI_WRITE(HDMI_CEC_CNTRL_1, 2458 (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) | 2459 (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT); 2460 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2461 2462 return 0; 2463 } 2464 2465 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts, 2466 u32 signal_free_time, struct cec_msg *msg) 2467 { 2468 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 2469 struct drm_device *dev = vc4_hdmi->connector.dev; 2470 unsigned long flags; 2471 u32 val; 2472 unsigned int i; 2473 2474 /* 2475 * NOTE: This function should really take vc4_hdmi->mutex, but doing so 2476 * results in a reentrancy since cec_s_phys_addr_from_edid() called in 2477 * .detect or .get_modes might call .adap_enable, which leads to this 2478 * function being called with that mutex held. 2479 * 2480 * Concurrency is not an issue for the moment since we don't share any 2481 * state with KMS, so we can ignore the lock for now, but we need to 2482 * keep it in mind if we were to change that assumption. 2483 */ 2484 2485 if (msg->len > 16) { 2486 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len); 2487 return -ENOMEM; 2488 } 2489 2490 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2491 2492 for (i = 0; i < msg->len; i += 4) 2493 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2), 2494 (msg->msg[i]) | 2495 (msg->msg[i + 1] << 8) | 2496 (msg->msg[i + 2] << 16) | 2497 (msg->msg[i + 3] << 24)); 2498 2499 val = HDMI_READ(HDMI_CEC_CNTRL_1); 2500 val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 2501 HDMI_WRITE(HDMI_CEC_CNTRL_1, val); 2502 val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK; 2503 val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT; 2504 val |= VC4_HDMI_CEC_START_XMIT_BEGIN; 2505 2506 HDMI_WRITE(HDMI_CEC_CNTRL_1, val); 2507 2508 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2509 2510 return 0; 2511 } 2512 2513 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = { 2514 .adap_enable = vc4_hdmi_cec_adap_enable, 2515 .adap_log_addr = vc4_hdmi_cec_adap_log_addr, 2516 .adap_transmit = vc4_hdmi_cec_adap_transmit, 2517 }; 2518 2519 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi) 2520 { 2521 struct cec_connector_info conn_info; 2522 struct platform_device *pdev = vc4_hdmi->pdev; 2523 struct device *dev = &pdev->dev; 2524 unsigned long flags; 2525 u32 value; 2526 int ret; 2527 2528 if (!of_find_property(dev->of_node, "interrupts", NULL)) { 2529 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n"); 2530 return 0; 2531 } 2532 2533 vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops, 2534 vc4_hdmi, "vc4", 2535 CEC_CAP_DEFAULTS | 2536 CEC_CAP_CONNECTOR_INFO, 1); 2537 ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap); 2538 if (ret < 0) 2539 return ret; 2540 2541 cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector); 2542 cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info); 2543 2544 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2545 value = HDMI_READ(HDMI_CEC_CNTRL_1); 2546 /* Set the logical address to Unregistered */ 2547 value |= VC4_HDMI_CEC_ADDR_MASK; 2548 HDMI_WRITE(HDMI_CEC_CNTRL_1, value); 2549 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2550 2551 vc4_hdmi_cec_update_clk_div(vc4_hdmi); 2552 2553 if (vc4_hdmi->variant->external_irq_controller) { 2554 ret = request_threaded_irq(platform_get_irq_byname(pdev, "cec-rx"), 2555 vc4_cec_irq_handler_rx_bare, 2556 vc4_cec_irq_handler_rx_thread, 0, 2557 "vc4 hdmi cec rx", vc4_hdmi); 2558 if (ret) 2559 goto err_delete_cec_adap; 2560 2561 ret = request_threaded_irq(platform_get_irq_byname(pdev, "cec-tx"), 2562 vc4_cec_irq_handler_tx_bare, 2563 vc4_cec_irq_handler_tx_thread, 0, 2564 "vc4 hdmi cec tx", vc4_hdmi); 2565 if (ret) 2566 goto err_remove_cec_rx_handler; 2567 } else { 2568 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2569 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff); 2570 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2571 2572 ret = request_threaded_irq(platform_get_irq(pdev, 0), 2573 vc4_cec_irq_handler, 2574 vc4_cec_irq_handler_thread, 0, 2575 "vc4 hdmi cec", vc4_hdmi); 2576 if (ret) 2577 goto err_delete_cec_adap; 2578 } 2579 2580 ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev); 2581 if (ret < 0) 2582 goto err_remove_handlers; 2583 2584 return 0; 2585 2586 err_remove_handlers: 2587 if (vc4_hdmi->variant->external_irq_controller) 2588 free_irq(platform_get_irq_byname(pdev, "cec-tx"), vc4_hdmi); 2589 else 2590 free_irq(platform_get_irq(pdev, 0), vc4_hdmi); 2591 2592 err_remove_cec_rx_handler: 2593 if (vc4_hdmi->variant->external_irq_controller) 2594 free_irq(platform_get_irq_byname(pdev, "cec-rx"), vc4_hdmi); 2595 2596 err_delete_cec_adap: 2597 cec_delete_adapter(vc4_hdmi->cec_adap); 2598 2599 return ret; 2600 } 2601 2602 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi) 2603 { 2604 struct platform_device *pdev = vc4_hdmi->pdev; 2605 2606 if (vc4_hdmi->variant->external_irq_controller) { 2607 free_irq(platform_get_irq_byname(pdev, "cec-rx"), vc4_hdmi); 2608 free_irq(platform_get_irq_byname(pdev, "cec-tx"), vc4_hdmi); 2609 } else { 2610 free_irq(platform_get_irq(pdev, 0), vc4_hdmi); 2611 } 2612 2613 cec_unregister_adapter(vc4_hdmi->cec_adap); 2614 } 2615 #else 2616 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi) 2617 { 2618 return 0; 2619 } 2620 2621 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi) {}; 2622 2623 #endif 2624 2625 static int vc4_hdmi_build_regset(struct vc4_hdmi *vc4_hdmi, 2626 struct debugfs_regset32 *regset, 2627 enum vc4_hdmi_regs reg) 2628 { 2629 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant; 2630 struct debugfs_reg32 *regs, *new_regs; 2631 unsigned int count = 0; 2632 unsigned int i; 2633 2634 regs = kcalloc(variant->num_registers, sizeof(*regs), 2635 GFP_KERNEL); 2636 if (!regs) 2637 return -ENOMEM; 2638 2639 for (i = 0; i < variant->num_registers; i++) { 2640 const struct vc4_hdmi_register *field = &variant->registers[i]; 2641 2642 if (field->reg != reg) 2643 continue; 2644 2645 regs[count].name = field->name; 2646 regs[count].offset = field->offset; 2647 count++; 2648 } 2649 2650 new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL); 2651 if (!new_regs) 2652 return -ENOMEM; 2653 2654 regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg); 2655 regset->regs = new_regs; 2656 regset->nregs = count; 2657 2658 return 0; 2659 } 2660 2661 static int vc4_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi) 2662 { 2663 struct platform_device *pdev = vc4_hdmi->pdev; 2664 struct device *dev = &pdev->dev; 2665 int ret; 2666 2667 vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0); 2668 if (IS_ERR(vc4_hdmi->hdmicore_regs)) 2669 return PTR_ERR(vc4_hdmi->hdmicore_regs); 2670 2671 vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1); 2672 if (IS_ERR(vc4_hdmi->hd_regs)) 2673 return PTR_ERR(vc4_hdmi->hd_regs); 2674 2675 ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD); 2676 if (ret) 2677 return ret; 2678 2679 ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI); 2680 if (ret) 2681 return ret; 2682 2683 vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel"); 2684 if (IS_ERR(vc4_hdmi->pixel_clock)) { 2685 ret = PTR_ERR(vc4_hdmi->pixel_clock); 2686 if (ret != -EPROBE_DEFER) 2687 DRM_ERROR("Failed to get pixel clock\n"); 2688 return ret; 2689 } 2690 2691 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); 2692 if (IS_ERR(vc4_hdmi->hsm_clock)) { 2693 DRM_ERROR("Failed to get HDMI state machine clock\n"); 2694 return PTR_ERR(vc4_hdmi->hsm_clock); 2695 } 2696 vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock; 2697 vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock; 2698 2699 return 0; 2700 } 2701 2702 static int vc5_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi) 2703 { 2704 struct platform_device *pdev = vc4_hdmi->pdev; 2705 struct device *dev = &pdev->dev; 2706 struct resource *res; 2707 2708 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi"); 2709 if (!res) 2710 return -ENODEV; 2711 2712 vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start, 2713 resource_size(res)); 2714 if (!vc4_hdmi->hdmicore_regs) 2715 return -ENOMEM; 2716 2717 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd"); 2718 if (!res) 2719 return -ENODEV; 2720 2721 vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res)); 2722 if (!vc4_hdmi->hd_regs) 2723 return -ENOMEM; 2724 2725 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec"); 2726 if (!res) 2727 return -ENODEV; 2728 2729 vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res)); 2730 if (!vc4_hdmi->cec_regs) 2731 return -ENOMEM; 2732 2733 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc"); 2734 if (!res) 2735 return -ENODEV; 2736 2737 vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res)); 2738 if (!vc4_hdmi->csc_regs) 2739 return -ENOMEM; 2740 2741 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp"); 2742 if (!res) 2743 return -ENODEV; 2744 2745 vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res)); 2746 if (!vc4_hdmi->dvp_regs) 2747 return -ENOMEM; 2748 2749 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy"); 2750 if (!res) 2751 return -ENODEV; 2752 2753 vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res)); 2754 if (!vc4_hdmi->phy_regs) 2755 return -ENOMEM; 2756 2757 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet"); 2758 if (!res) 2759 return -ENODEV; 2760 2761 vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res)); 2762 if (!vc4_hdmi->ram_regs) 2763 return -ENOMEM; 2764 2765 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm"); 2766 if (!res) 2767 return -ENODEV; 2768 2769 vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res)); 2770 if (!vc4_hdmi->rm_regs) 2771 return -ENOMEM; 2772 2773 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); 2774 if (IS_ERR(vc4_hdmi->hsm_clock)) { 2775 DRM_ERROR("Failed to get HDMI state machine clock\n"); 2776 return PTR_ERR(vc4_hdmi->hsm_clock); 2777 } 2778 2779 vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb"); 2780 if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) { 2781 DRM_ERROR("Failed to get pixel bvb clock\n"); 2782 return PTR_ERR(vc4_hdmi->pixel_bvb_clock); 2783 } 2784 2785 vc4_hdmi->audio_clock = devm_clk_get(dev, "audio"); 2786 if (IS_ERR(vc4_hdmi->audio_clock)) { 2787 DRM_ERROR("Failed to get audio clock\n"); 2788 return PTR_ERR(vc4_hdmi->audio_clock); 2789 } 2790 2791 vc4_hdmi->cec_clock = devm_clk_get(dev, "cec"); 2792 if (IS_ERR(vc4_hdmi->cec_clock)) { 2793 DRM_ERROR("Failed to get CEC clock\n"); 2794 return PTR_ERR(vc4_hdmi->cec_clock); 2795 } 2796 2797 vc4_hdmi->reset = devm_reset_control_get(dev, NULL); 2798 if (IS_ERR(vc4_hdmi->reset)) { 2799 DRM_ERROR("Failed to get HDMI reset line\n"); 2800 return PTR_ERR(vc4_hdmi->reset); 2801 } 2802 2803 return 0; 2804 } 2805 2806 static int __maybe_unused vc4_hdmi_runtime_suspend(struct device *dev) 2807 { 2808 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 2809 2810 clk_disable_unprepare(vc4_hdmi->hsm_clock); 2811 2812 return 0; 2813 } 2814 2815 static int vc4_hdmi_runtime_resume(struct device *dev) 2816 { 2817 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 2818 int ret; 2819 2820 ret = clk_prepare_enable(vc4_hdmi->hsm_clock); 2821 if (ret) 2822 return ret; 2823 2824 return 0; 2825 } 2826 2827 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data) 2828 { 2829 const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev); 2830 struct platform_device *pdev = to_platform_device(dev); 2831 struct drm_device *drm = dev_get_drvdata(master); 2832 struct vc4_hdmi *vc4_hdmi; 2833 struct drm_encoder *encoder; 2834 struct device_node *ddc_node; 2835 int ret; 2836 2837 vc4_hdmi = devm_kzalloc(dev, sizeof(*vc4_hdmi), GFP_KERNEL); 2838 if (!vc4_hdmi) 2839 return -ENOMEM; 2840 mutex_init(&vc4_hdmi->mutex); 2841 spin_lock_init(&vc4_hdmi->hw_lock); 2842 INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq); 2843 2844 dev_set_drvdata(dev, vc4_hdmi); 2845 encoder = &vc4_hdmi->encoder.base; 2846 vc4_hdmi->encoder.type = variant->encoder_type; 2847 vc4_hdmi->encoder.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure; 2848 vc4_hdmi->encoder.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable; 2849 vc4_hdmi->encoder.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable; 2850 vc4_hdmi->encoder.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable; 2851 vc4_hdmi->encoder.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown; 2852 vc4_hdmi->pdev = pdev; 2853 vc4_hdmi->variant = variant; 2854 2855 /* 2856 * Since we don't know the state of the controller and its 2857 * display (if any), let's assume it's always enabled. 2858 * vc4_hdmi_disable_scrambling() will thus run at boot, make 2859 * sure it's disabled, and avoid any inconsistency. 2860 */ 2861 if (variant->max_pixel_clock > HDMI_14_MAX_TMDS_CLK) 2862 vc4_hdmi->scdc_enabled = true; 2863 2864 ret = variant->init_resources(vc4_hdmi); 2865 if (ret) 2866 return ret; 2867 2868 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0); 2869 if (!ddc_node) { 2870 DRM_ERROR("Failed to find ddc node in device tree\n"); 2871 return -ENODEV; 2872 } 2873 2874 vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node); 2875 of_node_put(ddc_node); 2876 if (!vc4_hdmi->ddc) { 2877 DRM_DEBUG("Failed to get ddc i2c adapter by node\n"); 2878 return -EPROBE_DEFER; 2879 } 2880 2881 /* Only use the GPIO HPD pin if present in the DT, otherwise 2882 * we'll use the HDMI core's register. 2883 */ 2884 vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN); 2885 if (IS_ERR(vc4_hdmi->hpd_gpio)) { 2886 ret = PTR_ERR(vc4_hdmi->hpd_gpio); 2887 goto err_put_ddc; 2888 } 2889 2890 vc4_hdmi->disable_wifi_frequencies = 2891 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence"); 2892 2893 if (variant->max_pixel_clock == 600000000) { 2894 struct vc4_dev *vc4 = to_vc4_dev(drm); 2895 long max_rate = clk_round_rate(vc4->hvs->core_clk, 550000000); 2896 2897 if (max_rate < 550000000) 2898 vc4_hdmi->disable_4kp60 = true; 2899 } 2900 2901 /* 2902 * We need to have the device powered up at this point to call 2903 * our reset hook and for the CEC init. 2904 */ 2905 ret = vc4_hdmi_runtime_resume(dev); 2906 if (ret) 2907 goto err_put_ddc; 2908 2909 pm_runtime_get_noresume(dev); 2910 pm_runtime_set_active(dev); 2911 pm_runtime_enable(dev); 2912 2913 if (vc4_hdmi->variant->reset) 2914 vc4_hdmi->variant->reset(vc4_hdmi); 2915 2916 if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") || 2917 of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1")) && 2918 HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) { 2919 clk_prepare_enable(vc4_hdmi->pixel_clock); 2920 clk_prepare_enable(vc4_hdmi->hsm_clock); 2921 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock); 2922 } 2923 2924 drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS); 2925 drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs); 2926 2927 ret = vc4_hdmi_connector_init(drm, vc4_hdmi); 2928 if (ret) 2929 goto err_destroy_encoder; 2930 2931 ret = vc4_hdmi_hotplug_init(vc4_hdmi); 2932 if (ret) 2933 goto err_destroy_conn; 2934 2935 ret = vc4_hdmi_cec_init(vc4_hdmi); 2936 if (ret) 2937 goto err_free_hotplug; 2938 2939 ret = vc4_hdmi_audio_init(vc4_hdmi); 2940 if (ret) 2941 goto err_free_cec; 2942 2943 vc4_debugfs_add_file(drm, variant->debugfs_name, 2944 vc4_hdmi_debugfs_regs, 2945 vc4_hdmi); 2946 2947 pm_runtime_put_sync(dev); 2948 2949 return 0; 2950 2951 err_free_cec: 2952 vc4_hdmi_cec_exit(vc4_hdmi); 2953 err_free_hotplug: 2954 vc4_hdmi_hotplug_exit(vc4_hdmi); 2955 err_destroy_conn: 2956 vc4_hdmi_connector_destroy(&vc4_hdmi->connector); 2957 err_destroy_encoder: 2958 drm_encoder_cleanup(encoder); 2959 pm_runtime_put_sync(dev); 2960 pm_runtime_disable(dev); 2961 err_put_ddc: 2962 put_device(&vc4_hdmi->ddc->dev); 2963 2964 return ret; 2965 } 2966 2967 static void vc4_hdmi_unbind(struct device *dev, struct device *master, 2968 void *data) 2969 { 2970 struct vc4_hdmi *vc4_hdmi; 2971 2972 /* 2973 * ASoC makes it a bit hard to retrieve a pointer to the 2974 * vc4_hdmi structure. Registering the card will overwrite our 2975 * device drvdata with a pointer to the snd_soc_card structure, 2976 * which can then be used to retrieve whatever drvdata we want 2977 * to associate. 2978 * 2979 * However, that doesn't fly in the case where we wouldn't 2980 * register an ASoC card (because of an old DT that is missing 2981 * the dmas properties for example), then the card isn't 2982 * registered and the device drvdata wouldn't be set. 2983 * 2984 * We can deal with both cases by making sure a snd_soc_card 2985 * pointer and a vc4_hdmi structure are pointing to the same 2986 * memory address, so we can treat them indistinctly without any 2987 * issue. 2988 */ 2989 BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0); 2990 BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0); 2991 vc4_hdmi = dev_get_drvdata(dev); 2992 2993 kfree(vc4_hdmi->hdmi_regset.regs); 2994 kfree(vc4_hdmi->hd_regset.regs); 2995 2996 vc4_hdmi_audio_exit(vc4_hdmi); 2997 vc4_hdmi_cec_exit(vc4_hdmi); 2998 vc4_hdmi_hotplug_exit(vc4_hdmi); 2999 vc4_hdmi_connector_destroy(&vc4_hdmi->connector); 3000 drm_encoder_cleanup(&vc4_hdmi->encoder.base); 3001 3002 pm_runtime_disable(dev); 3003 3004 put_device(&vc4_hdmi->ddc->dev); 3005 } 3006 3007 static const struct component_ops vc4_hdmi_ops = { 3008 .bind = vc4_hdmi_bind, 3009 .unbind = vc4_hdmi_unbind, 3010 }; 3011 3012 static int vc4_hdmi_dev_probe(struct platform_device *pdev) 3013 { 3014 return component_add(&pdev->dev, &vc4_hdmi_ops); 3015 } 3016 3017 static int vc4_hdmi_dev_remove(struct platform_device *pdev) 3018 { 3019 component_del(&pdev->dev, &vc4_hdmi_ops); 3020 return 0; 3021 } 3022 3023 static const struct vc4_hdmi_variant bcm2835_variant = { 3024 .encoder_type = VC4_ENCODER_TYPE_HDMI0, 3025 .debugfs_name = "hdmi_regs", 3026 .card_name = "vc4-hdmi", 3027 .max_pixel_clock = 162000000, 3028 .registers = vc4_hdmi_fields, 3029 .num_registers = ARRAY_SIZE(vc4_hdmi_fields), 3030 3031 .init_resources = vc4_hdmi_init_resources, 3032 .csc_setup = vc4_hdmi_csc_setup, 3033 .reset = vc4_hdmi_reset, 3034 .set_timings = vc4_hdmi_set_timings, 3035 .phy_init = vc4_hdmi_phy_init, 3036 .phy_disable = vc4_hdmi_phy_disable, 3037 .phy_rng_enable = vc4_hdmi_phy_rng_enable, 3038 .phy_rng_disable = vc4_hdmi_phy_rng_disable, 3039 .channel_map = vc4_hdmi_channel_map, 3040 .supports_hdr = false, 3041 }; 3042 3043 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = { 3044 .encoder_type = VC4_ENCODER_TYPE_HDMI0, 3045 .debugfs_name = "hdmi0_regs", 3046 .card_name = "vc4-hdmi-0", 3047 .max_pixel_clock = 600000000, 3048 .registers = vc5_hdmi_hdmi0_fields, 3049 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi0_fields), 3050 .phy_lane_mapping = { 3051 PHY_LANE_0, 3052 PHY_LANE_1, 3053 PHY_LANE_2, 3054 PHY_LANE_CK, 3055 }, 3056 .unsupported_odd_h_timings = true, 3057 .external_irq_controller = true, 3058 3059 .init_resources = vc5_hdmi_init_resources, 3060 .csc_setup = vc5_hdmi_csc_setup, 3061 .reset = vc5_hdmi_reset, 3062 .set_timings = vc5_hdmi_set_timings, 3063 .phy_init = vc5_hdmi_phy_init, 3064 .phy_disable = vc5_hdmi_phy_disable, 3065 .phy_rng_enable = vc5_hdmi_phy_rng_enable, 3066 .phy_rng_disable = vc5_hdmi_phy_rng_disable, 3067 .channel_map = vc5_hdmi_channel_map, 3068 .supports_hdr = true, 3069 .hp_detect = vc5_hdmi_hp_detect, 3070 }; 3071 3072 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = { 3073 .encoder_type = VC4_ENCODER_TYPE_HDMI1, 3074 .debugfs_name = "hdmi1_regs", 3075 .card_name = "vc4-hdmi-1", 3076 .max_pixel_clock = HDMI_14_MAX_TMDS_CLK, 3077 .registers = vc5_hdmi_hdmi1_fields, 3078 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi1_fields), 3079 .phy_lane_mapping = { 3080 PHY_LANE_1, 3081 PHY_LANE_0, 3082 PHY_LANE_CK, 3083 PHY_LANE_2, 3084 }, 3085 .unsupported_odd_h_timings = true, 3086 .external_irq_controller = true, 3087 3088 .init_resources = vc5_hdmi_init_resources, 3089 .csc_setup = vc5_hdmi_csc_setup, 3090 .reset = vc5_hdmi_reset, 3091 .set_timings = vc5_hdmi_set_timings, 3092 .phy_init = vc5_hdmi_phy_init, 3093 .phy_disable = vc5_hdmi_phy_disable, 3094 .phy_rng_enable = vc5_hdmi_phy_rng_enable, 3095 .phy_rng_disable = vc5_hdmi_phy_rng_disable, 3096 .channel_map = vc5_hdmi_channel_map, 3097 .supports_hdr = true, 3098 .hp_detect = vc5_hdmi_hp_detect, 3099 }; 3100 3101 static const struct of_device_id vc4_hdmi_dt_match[] = { 3102 { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant }, 3103 { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant }, 3104 { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant }, 3105 {} 3106 }; 3107 3108 static const struct dev_pm_ops vc4_hdmi_pm_ops = { 3109 SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend, 3110 vc4_hdmi_runtime_resume, 3111 NULL) 3112 }; 3113 3114 struct platform_driver vc4_hdmi_driver = { 3115 .probe = vc4_hdmi_dev_probe, 3116 .remove = vc4_hdmi_dev_remove, 3117 .driver = { 3118 .name = "vc4_hdmi", 3119 .of_match_table = vc4_hdmi_dt_match, 3120 .pm = &vc4_hdmi_pm_ops, 3121 }, 3122 }; 3123