1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 Broadcom 4 * Copyright (c) 2014 The Linux Foundation. All rights reserved. 5 * Copyright (C) 2013 Red Hat 6 * Author: Rob Clark <robdclark@gmail.com> 7 */ 8 9 /** 10 * DOC: VC4 Falcon HDMI module 11 * 12 * The HDMI core has a state machine and a PHY. On BCM2835, most of 13 * the unit operates off of the HSM clock from CPRMAN. It also 14 * internally uses the PLLH_PIX clock for the PHY. 15 * 16 * HDMI infoframes are kept within a small packet ram, where each 17 * packet can be individually enabled for including in a frame. 18 * 19 * HDMI audio is implemented entirely within the HDMI IP block. A 20 * register in the HDMI encoder takes SPDIF frames from the DMA engine 21 * and transfers them over an internal MAI (multi-channel audio 22 * interconnect) bus to the encoder side for insertion into the video 23 * blank regions. 24 * 25 * The driver's HDMI encoder does not yet support power management. 26 * The HDMI encoder's power domain and the HSM/pixel clocks are kept 27 * continuously running, and only the HDMI logic and packet ram are 28 * powered off/on at disable/enable time. 29 * 30 * The driver does not yet support CEC control, though the HDMI 31 * encoder block has CEC support. 32 */ 33 34 #include <drm/drm_atomic_helper.h> 35 #include <drm/drm_edid.h> 36 #include <drm/drm_probe_helper.h> 37 #include <drm/drm_simple_kms_helper.h> 38 #include <drm/drm_scdc_helper.h> 39 #include <linux/clk.h> 40 #include <linux/component.h> 41 #include <linux/i2c.h> 42 #include <linux/of_address.h> 43 #include <linux/of_gpio.h> 44 #include <linux/of_platform.h> 45 #include <linux/pm_runtime.h> 46 #include <linux/rational.h> 47 #include <linux/reset.h> 48 #include <sound/dmaengine_pcm.h> 49 #include <sound/hdmi-codec.h> 50 #include <sound/pcm_drm_eld.h> 51 #include <sound/pcm_params.h> 52 #include <sound/soc.h> 53 #include "media/cec.h" 54 #include "vc4_drv.h" 55 #include "vc4_hdmi.h" 56 #include "vc4_hdmi_regs.h" 57 #include "vc4_regs.h" 58 59 #define VC5_HDMI_HORZA_HFP_SHIFT 16 60 #define VC5_HDMI_HORZA_HFP_MASK VC4_MASK(28, 16) 61 #define VC5_HDMI_HORZA_VPOS BIT(15) 62 #define VC5_HDMI_HORZA_HPOS BIT(14) 63 #define VC5_HDMI_HORZA_HAP_SHIFT 0 64 #define VC5_HDMI_HORZA_HAP_MASK VC4_MASK(13, 0) 65 66 #define VC5_HDMI_HORZB_HBP_SHIFT 16 67 #define VC5_HDMI_HORZB_HBP_MASK VC4_MASK(26, 16) 68 #define VC5_HDMI_HORZB_HSP_SHIFT 0 69 #define VC5_HDMI_HORZB_HSP_MASK VC4_MASK(10, 0) 70 71 #define VC5_HDMI_VERTA_VSP_SHIFT 24 72 #define VC5_HDMI_VERTA_VSP_MASK VC4_MASK(28, 24) 73 #define VC5_HDMI_VERTA_VFP_SHIFT 16 74 #define VC5_HDMI_VERTA_VFP_MASK VC4_MASK(22, 16) 75 #define VC5_HDMI_VERTA_VAL_SHIFT 0 76 #define VC5_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0) 77 78 #define VC5_HDMI_VERTB_VSPO_SHIFT 16 79 #define VC5_HDMI_VERTB_VSPO_MASK VC4_MASK(29, 16) 80 81 #define VC5_HDMI_SCRAMBLER_CTL_ENABLE BIT(0) 82 83 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT 8 84 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK VC4_MASK(10, 8) 85 86 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT 0 87 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK VC4_MASK(3, 0) 88 89 #define VC5_HDMI_GCP_CONFIG_GCP_ENABLE BIT(31) 90 91 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT 8 92 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK VC4_MASK(15, 8) 93 94 # define VC4_HD_M_SW_RST BIT(2) 95 # define VC4_HD_M_ENABLE BIT(0) 96 97 #define HSM_MIN_CLOCK_FREQ 120000000 98 #define CEC_CLOCK_FREQ 40000 99 100 #define HDMI_14_MAX_TMDS_CLK (340 * 1000 * 1000) 101 102 static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode) 103 { 104 return (mode->clock * 1000) > HDMI_14_MAX_TMDS_CLK; 105 } 106 107 static bool vc4_hdmi_is_full_range_rgb(struct vc4_hdmi *vc4_hdmi, 108 const struct drm_display_mode *mode) 109 { 110 struct vc4_hdmi_encoder *vc4_encoder = &vc4_hdmi->encoder; 111 112 return !vc4_encoder->hdmi_monitor || 113 drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_FULL; 114 } 115 116 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused) 117 { 118 struct drm_info_node *node = (struct drm_info_node *)m->private; 119 struct vc4_hdmi *vc4_hdmi = node->info_ent->data; 120 struct drm_printer p = drm_seq_file_printer(m); 121 122 drm_print_regset32(&p, &vc4_hdmi->hdmi_regset); 123 drm_print_regset32(&p, &vc4_hdmi->hd_regset); 124 125 return 0; 126 } 127 128 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi) 129 { 130 unsigned long flags; 131 132 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 133 134 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST); 135 udelay(1); 136 HDMI_WRITE(HDMI_M_CTL, 0); 137 138 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE); 139 140 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 141 VC4_HDMI_SW_RESET_HDMI | 142 VC4_HDMI_SW_RESET_FORMAT_DETECT); 143 144 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0); 145 146 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 147 } 148 149 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi) 150 { 151 unsigned long flags; 152 153 reset_control_reset(vc4_hdmi->reset); 154 155 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 156 157 HDMI_WRITE(HDMI_DVP_CTL, 0); 158 159 HDMI_WRITE(HDMI_CLOCK_STOP, 160 HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL); 161 162 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 163 } 164 165 #ifdef CONFIG_DRM_VC4_HDMI_CEC 166 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) 167 { 168 unsigned long cec_rate = clk_get_rate(vc4_hdmi->cec_clock); 169 unsigned long flags; 170 u16 clk_cnt; 171 u32 value; 172 173 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 174 175 value = HDMI_READ(HDMI_CEC_CNTRL_1); 176 value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK; 177 178 /* 179 * Set the clock divider: the hsm_clock rate and this divider 180 * setting will give a 40 kHz CEC clock. 181 */ 182 clk_cnt = cec_rate / CEC_CLOCK_FREQ; 183 value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT; 184 HDMI_WRITE(HDMI_CEC_CNTRL_1, value); 185 186 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 187 } 188 #else 189 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {} 190 #endif 191 192 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder); 193 194 static enum drm_connector_status 195 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force) 196 { 197 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 198 bool connected = false; 199 200 mutex_lock(&vc4_hdmi->mutex); 201 202 WARN_ON(pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev)); 203 204 if (vc4_hdmi->hpd_gpio) { 205 if (gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio)) 206 connected = true; 207 } else { 208 unsigned long flags; 209 u32 hotplug; 210 211 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 212 hotplug = HDMI_READ(HDMI_HOTPLUG); 213 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 214 215 if (hotplug & VC4_HDMI_HOTPLUG_CONNECTED) 216 connected = true; 217 } 218 219 if (connected) { 220 if (connector->status != connector_status_connected) { 221 struct edid *edid = drm_get_edid(connector, vc4_hdmi->ddc); 222 223 if (edid) { 224 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid); 225 vc4_hdmi->encoder.hdmi_monitor = drm_detect_hdmi_monitor(edid); 226 kfree(edid); 227 } 228 } 229 230 vc4_hdmi_enable_scrambling(&vc4_hdmi->encoder.base.base); 231 pm_runtime_put(&vc4_hdmi->pdev->dev); 232 mutex_unlock(&vc4_hdmi->mutex); 233 return connector_status_connected; 234 } 235 236 cec_phys_addr_invalidate(vc4_hdmi->cec_adap); 237 pm_runtime_put(&vc4_hdmi->pdev->dev); 238 mutex_unlock(&vc4_hdmi->mutex); 239 return connector_status_disconnected; 240 } 241 242 static void vc4_hdmi_connector_destroy(struct drm_connector *connector) 243 { 244 drm_connector_unregister(connector); 245 drm_connector_cleanup(connector); 246 } 247 248 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector) 249 { 250 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 251 struct vc4_hdmi_encoder *vc4_encoder = &vc4_hdmi->encoder; 252 int ret = 0; 253 struct edid *edid; 254 255 mutex_lock(&vc4_hdmi->mutex); 256 257 edid = drm_get_edid(connector, vc4_hdmi->ddc); 258 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid); 259 if (!edid) { 260 ret = -ENODEV; 261 goto out; 262 } 263 264 vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid); 265 266 drm_connector_update_edid_property(connector, edid); 267 ret = drm_add_edid_modes(connector, edid); 268 kfree(edid); 269 270 if (vc4_hdmi->disable_4kp60) { 271 struct drm_device *drm = connector->dev; 272 struct drm_display_mode *mode; 273 274 list_for_each_entry(mode, &connector->probed_modes, head) { 275 if (vc4_hdmi_mode_needs_scrambling(mode)) { 276 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz."); 277 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60."); 278 } 279 } 280 } 281 282 out: 283 mutex_unlock(&vc4_hdmi->mutex); 284 285 return ret; 286 } 287 288 static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector, 289 struct drm_atomic_state *state) 290 { 291 struct drm_connector_state *old_state = 292 drm_atomic_get_old_connector_state(state, connector); 293 struct drm_connector_state *new_state = 294 drm_atomic_get_new_connector_state(state, connector); 295 struct drm_crtc *crtc = new_state->crtc; 296 297 if (!crtc) 298 return 0; 299 300 if (old_state->colorspace != new_state->colorspace || 301 !drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) { 302 struct drm_crtc_state *crtc_state; 303 304 crtc_state = drm_atomic_get_crtc_state(state, crtc); 305 if (IS_ERR(crtc_state)) 306 return PTR_ERR(crtc_state); 307 308 crtc_state->mode_changed = true; 309 } 310 311 return 0; 312 } 313 314 static void vc4_hdmi_connector_reset(struct drm_connector *connector) 315 { 316 struct vc4_hdmi_connector_state *old_state = 317 conn_state_to_vc4_hdmi_conn_state(connector->state); 318 struct vc4_hdmi_connector_state *new_state = 319 kzalloc(sizeof(*new_state), GFP_KERNEL); 320 321 if (connector->state) 322 __drm_atomic_helper_connector_destroy_state(connector->state); 323 324 kfree(old_state); 325 __drm_atomic_helper_connector_reset(connector, &new_state->base); 326 327 if (!new_state) 328 return; 329 330 new_state->base.max_bpc = 8; 331 new_state->base.max_requested_bpc = 8; 332 drm_atomic_helper_connector_tv_reset(connector); 333 } 334 335 static struct drm_connector_state * 336 vc4_hdmi_connector_duplicate_state(struct drm_connector *connector) 337 { 338 struct drm_connector_state *conn_state = connector->state; 339 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state); 340 struct vc4_hdmi_connector_state *new_state; 341 342 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL); 343 if (!new_state) 344 return NULL; 345 346 new_state->pixel_rate = vc4_state->pixel_rate; 347 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base); 348 349 return &new_state->base; 350 } 351 352 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = { 353 .detect = vc4_hdmi_connector_detect, 354 .fill_modes = drm_helper_probe_single_connector_modes, 355 .destroy = vc4_hdmi_connector_destroy, 356 .reset = vc4_hdmi_connector_reset, 357 .atomic_duplicate_state = vc4_hdmi_connector_duplicate_state, 358 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 359 }; 360 361 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = { 362 .get_modes = vc4_hdmi_connector_get_modes, 363 .atomic_check = vc4_hdmi_connector_atomic_check, 364 }; 365 366 static int vc4_hdmi_connector_init(struct drm_device *dev, 367 struct vc4_hdmi *vc4_hdmi) 368 { 369 struct drm_connector *connector = &vc4_hdmi->connector; 370 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base; 371 int ret; 372 373 drm_connector_init_with_ddc(dev, connector, 374 &vc4_hdmi_connector_funcs, 375 DRM_MODE_CONNECTOR_HDMIA, 376 vc4_hdmi->ddc); 377 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs); 378 379 /* 380 * Some of the properties below require access to state, like bpc. 381 * Allocate some default initial connector state with our reset helper. 382 */ 383 if (connector->funcs->reset) 384 connector->funcs->reset(connector); 385 386 /* Create and attach TV margin props to this connector. */ 387 ret = drm_mode_create_tv_margin_properties(dev); 388 if (ret) 389 return ret; 390 391 ret = drm_mode_create_hdmi_colorspace_property(connector); 392 if (ret) 393 return ret; 394 395 drm_connector_attach_colorspace_property(connector); 396 drm_connector_attach_tv_margin_properties(connector); 397 drm_connector_attach_max_bpc_property(connector, 8, 12); 398 399 connector->polled = (DRM_CONNECTOR_POLL_CONNECT | 400 DRM_CONNECTOR_POLL_DISCONNECT); 401 402 connector->interlace_allowed = 1; 403 connector->doublescan_allowed = 0; 404 405 if (vc4_hdmi->variant->supports_hdr) 406 drm_connector_attach_hdr_output_metadata_property(connector); 407 408 drm_connector_attach_encoder(connector, encoder); 409 410 return 0; 411 } 412 413 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder, 414 enum hdmi_infoframe_type type, 415 bool poll) 416 { 417 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 418 u32 packet_id = type - 0x80; 419 unsigned long flags; 420 421 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 422 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 423 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id)); 424 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 425 426 if (!poll) 427 return 0; 428 429 return wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) & 430 BIT(packet_id)), 100); 431 } 432 433 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder, 434 union hdmi_infoframe *frame) 435 { 436 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 437 u32 packet_id = frame->any.type - 0x80; 438 const struct vc4_hdmi_register *ram_packet_start = 439 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START]; 440 u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id; 441 void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi, 442 ram_packet_start->reg); 443 uint8_t buffer[VC4_HDMI_PACKET_STRIDE]; 444 unsigned long flags; 445 ssize_t len, i; 446 int ret; 447 448 WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) & 449 VC4_HDMI_RAM_PACKET_ENABLE), 450 "Packet RAM has to be on to store the packet."); 451 452 len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer)); 453 if (len < 0) 454 return; 455 456 ret = vc4_hdmi_stop_packet(encoder, frame->any.type, true); 457 if (ret) { 458 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret); 459 return; 460 } 461 462 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 463 464 for (i = 0; i < len; i += 7) { 465 writel(buffer[i + 0] << 0 | 466 buffer[i + 1] << 8 | 467 buffer[i + 2] << 16, 468 base + packet_reg); 469 packet_reg += 4; 470 471 writel(buffer[i + 3] << 0 | 472 buffer[i + 4] << 8 | 473 buffer[i + 5] << 16 | 474 buffer[i + 6] << 24, 475 base + packet_reg); 476 packet_reg += 4; 477 } 478 479 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 480 HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id)); 481 482 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 483 484 ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) & 485 BIT(packet_id)), 100); 486 if (ret) 487 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret); 488 } 489 490 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder) 491 { 492 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 493 struct drm_connector *connector = &vc4_hdmi->connector; 494 struct drm_connector_state *cstate = connector->state; 495 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 496 union hdmi_infoframe frame; 497 int ret; 498 499 lockdep_assert_held(&vc4_hdmi->mutex); 500 501 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, 502 connector, mode); 503 if (ret < 0) { 504 DRM_ERROR("couldn't fill AVI infoframe\n"); 505 return; 506 } 507 508 drm_hdmi_avi_infoframe_quant_range(&frame.avi, 509 connector, mode, 510 vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode) ? 511 HDMI_QUANTIZATION_RANGE_FULL : 512 HDMI_QUANTIZATION_RANGE_LIMITED); 513 drm_hdmi_avi_infoframe_colorimetry(&frame.avi, cstate); 514 drm_hdmi_avi_infoframe_bars(&frame.avi, cstate); 515 516 vc4_hdmi_write_infoframe(encoder, &frame); 517 } 518 519 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder) 520 { 521 union hdmi_infoframe frame; 522 int ret; 523 524 ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore"); 525 if (ret < 0) { 526 DRM_ERROR("couldn't fill SPD infoframe\n"); 527 return; 528 } 529 530 frame.spd.sdi = HDMI_SPD_SDI_PC; 531 532 vc4_hdmi_write_infoframe(encoder, &frame); 533 } 534 535 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder) 536 { 537 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 538 struct hdmi_audio_infoframe *audio = &vc4_hdmi->audio.infoframe; 539 union hdmi_infoframe frame; 540 541 memcpy(&frame.audio, audio, sizeof(*audio)); 542 vc4_hdmi_write_infoframe(encoder, &frame); 543 } 544 545 static void vc4_hdmi_set_hdr_infoframe(struct drm_encoder *encoder) 546 { 547 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 548 struct drm_connector *connector = &vc4_hdmi->connector; 549 struct drm_connector_state *conn_state = connector->state; 550 union hdmi_infoframe frame; 551 552 lockdep_assert_held(&vc4_hdmi->mutex); 553 554 if (!vc4_hdmi->variant->supports_hdr) 555 return; 556 557 if (!conn_state->hdr_output_metadata) 558 return; 559 560 if (drm_hdmi_infoframe_set_hdr_metadata(&frame.drm, conn_state)) 561 return; 562 563 vc4_hdmi_write_infoframe(encoder, &frame); 564 } 565 566 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder) 567 { 568 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 569 570 lockdep_assert_held(&vc4_hdmi->mutex); 571 572 vc4_hdmi_set_avi_infoframe(encoder); 573 vc4_hdmi_set_spd_infoframe(encoder); 574 /* 575 * If audio was streaming, then we need to reenabled the audio 576 * infoframe here during encoder_enable. 577 */ 578 if (vc4_hdmi->audio.streaming) 579 vc4_hdmi_set_audio_infoframe(encoder); 580 581 vc4_hdmi_set_hdr_infoframe(encoder); 582 } 583 584 static bool vc4_hdmi_supports_scrambling(struct drm_encoder *encoder, 585 struct drm_display_mode *mode) 586 { 587 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 588 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 589 struct drm_display_info *display = &vc4_hdmi->connector.display_info; 590 591 lockdep_assert_held(&vc4_hdmi->mutex); 592 593 if (!vc4_encoder->hdmi_monitor) 594 return false; 595 596 if (!display->hdmi.scdc.supported || 597 !display->hdmi.scdc.scrambling.supported) 598 return false; 599 600 return true; 601 } 602 603 #define SCRAMBLING_POLLING_DELAY_MS 1000 604 605 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder) 606 { 607 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 608 struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 609 unsigned long flags; 610 611 lockdep_assert_held(&vc4_hdmi->mutex); 612 613 if (!vc4_hdmi_supports_scrambling(encoder, mode)) 614 return; 615 616 if (!vc4_hdmi_mode_needs_scrambling(mode)) 617 return; 618 619 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true); 620 drm_scdc_set_scrambling(vc4_hdmi->ddc, true); 621 622 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 623 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) | 624 VC5_HDMI_SCRAMBLER_CTL_ENABLE); 625 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 626 627 vc4_hdmi->scdc_enabled = true; 628 629 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work, 630 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS)); 631 } 632 633 static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder) 634 { 635 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 636 unsigned long flags; 637 638 lockdep_assert_held(&vc4_hdmi->mutex); 639 640 if (!vc4_hdmi->scdc_enabled) 641 return; 642 643 vc4_hdmi->scdc_enabled = false; 644 645 if (delayed_work_pending(&vc4_hdmi->scrambling_work)) 646 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work); 647 648 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 649 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) & 650 ~VC5_HDMI_SCRAMBLER_CTL_ENABLE); 651 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 652 653 drm_scdc_set_scrambling(vc4_hdmi->ddc, false); 654 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, false); 655 } 656 657 static void vc4_hdmi_scrambling_wq(struct work_struct *work) 658 { 659 struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work), 660 struct vc4_hdmi, 661 scrambling_work); 662 663 if (drm_scdc_get_scrambling_status(vc4_hdmi->ddc)) 664 return; 665 666 drm_scdc_set_high_tmds_clock_ratio(vc4_hdmi->ddc, true); 667 drm_scdc_set_scrambling(vc4_hdmi->ddc, true); 668 669 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work, 670 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS)); 671 } 672 673 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder, 674 struct drm_atomic_state *state) 675 { 676 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 677 unsigned long flags; 678 679 mutex_lock(&vc4_hdmi->mutex); 680 681 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 682 683 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0); 684 685 HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB); 686 687 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 688 689 mdelay(1); 690 691 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 692 HDMI_WRITE(HDMI_VID_CTL, 693 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE); 694 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 695 696 vc4_hdmi_disable_scrambling(encoder); 697 698 mutex_unlock(&vc4_hdmi->mutex); 699 } 700 701 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder, 702 struct drm_atomic_state *state) 703 { 704 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 705 unsigned long flags; 706 int ret; 707 708 mutex_lock(&vc4_hdmi->mutex); 709 710 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 711 HDMI_WRITE(HDMI_VID_CTL, 712 HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX); 713 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 714 715 if (vc4_hdmi->variant->phy_disable) 716 vc4_hdmi->variant->phy_disable(vc4_hdmi); 717 718 clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock); 719 clk_disable_unprepare(vc4_hdmi->pixel_clock); 720 721 ret = pm_runtime_put(&vc4_hdmi->pdev->dev); 722 if (ret < 0) 723 DRM_ERROR("Failed to release power domain: %d\n", ret); 724 725 mutex_unlock(&vc4_hdmi->mutex); 726 } 727 728 static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder) 729 { 730 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 731 732 mutex_lock(&vc4_hdmi->mutex); 733 vc4_hdmi->output_enabled = false; 734 mutex_unlock(&vc4_hdmi->mutex); 735 } 736 737 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, 738 struct drm_connector_state *state, 739 const struct drm_display_mode *mode) 740 { 741 unsigned long flags; 742 u32 csc_ctl; 743 744 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 745 746 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR, 747 VC4_HD_CSC_CTL_ORDER); 748 749 if (!vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode)) { 750 /* CEA VICs other than #1 requre limited range RGB 751 * output unless overridden by an AVI infoframe. 752 * Apply a colorspace conversion to squash 0-255 down 753 * to 16-235. The matrix here is: 754 * 755 * [ 0 0 0.8594 16] 756 * [ 0 0.8594 0 16] 757 * [ 0.8594 0 0 16] 758 * [ 0 0 0 1] 759 */ 760 csc_ctl |= VC4_HD_CSC_CTL_ENABLE; 761 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC; 762 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM, 763 VC4_HD_CSC_CTL_MODE); 764 765 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000); 766 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0); 767 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000); 768 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000); 769 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0); 770 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000); 771 } 772 773 /* The RGB order applies even when CSC is disabled. */ 774 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl); 775 776 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 777 } 778 779 /* 780 * If we need to output Full Range RGB, then use the unity matrix 781 * 782 * [ 1 0 0 0] 783 * [ 0 1 0 0] 784 * [ 0 0 1 0] 785 * 786 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets 787 */ 788 static const u16 vc5_hdmi_csc_full_rgb_unity[3][4] = { 789 { 0x2000, 0x0000, 0x0000, 0x0000 }, 790 { 0x0000, 0x2000, 0x0000, 0x0000 }, 791 { 0x0000, 0x0000, 0x2000, 0x0000 }, 792 }; 793 794 /* 795 * CEA VICs other than #1 require limited range RGB output unless 796 * overridden by an AVI infoframe. Apply a colorspace conversion to 797 * squash 0-255 down to 16-235. The matrix here is: 798 * 799 * [ 0.8594 0 0 16] 800 * [ 0 0.8594 0 16] 801 * [ 0 0 0.8594 16] 802 * 803 * Matrix is signed 2p13 fixed point, with signed 9p6 offsets 804 */ 805 static const u16 vc5_hdmi_csc_full_rgb_to_limited_rgb[3][4] = { 806 { 0x1b80, 0x0000, 0x0000, 0x0400 }, 807 { 0x0000, 0x1b80, 0x0000, 0x0400 }, 808 { 0x0000, 0x0000, 0x1b80, 0x0400 }, 809 }; 810 811 static void vc5_hdmi_set_csc_coeffs(struct vc4_hdmi *vc4_hdmi, 812 const u16 coeffs[3][4]) 813 { 814 lockdep_assert_held(&vc4_hdmi->hw_lock); 815 816 HDMI_WRITE(HDMI_CSC_12_11, (coeffs[0][1] << 16) | coeffs[0][0]); 817 HDMI_WRITE(HDMI_CSC_14_13, (coeffs[0][3] << 16) | coeffs[0][2]); 818 HDMI_WRITE(HDMI_CSC_22_21, (coeffs[1][1] << 16) | coeffs[1][0]); 819 HDMI_WRITE(HDMI_CSC_24_23, (coeffs[1][3] << 16) | coeffs[1][2]); 820 HDMI_WRITE(HDMI_CSC_32_31, (coeffs[2][1] << 16) | coeffs[2][0]); 821 HDMI_WRITE(HDMI_CSC_34_33, (coeffs[2][3] << 16) | coeffs[2][2]); 822 } 823 824 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, 825 struct drm_connector_state *state, 826 const struct drm_display_mode *mode) 827 { 828 unsigned long flags; 829 u32 csc_ctl = VC5_MT_CP_CSC_CTL_ENABLE | VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM, 830 VC5_MT_CP_CSC_CTL_MODE); 831 832 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 833 834 HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, 0x354021); 835 836 if (!vc4_hdmi_is_full_range_rgb(vc4_hdmi, mode)) 837 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_limited_rgb); 838 else 839 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_unity); 840 841 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl); 842 843 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 844 } 845 846 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi, 847 struct drm_connector_state *state, 848 struct drm_display_mode *mode) 849 { 850 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 851 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 852 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 853 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 854 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 855 VC4_HDMI_VERTA_VSP) | 856 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 857 VC4_HDMI_VERTA_VFP) | 858 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL)); 859 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 860 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end, 861 VC4_HDMI_VERTB_VBP)); 862 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 863 VC4_SET_FIELD(mode->crtc_vtotal - 864 mode->crtc_vsync_end - 865 interlaced, 866 VC4_HDMI_VERTB_VBP)); 867 unsigned long flags; 868 869 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 870 871 HDMI_WRITE(HDMI_HORZA, 872 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) | 873 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) | 874 VC4_SET_FIELD(mode->hdisplay * pixel_rep, 875 VC4_HDMI_HORZA_HAP)); 876 877 HDMI_WRITE(HDMI_HORZB, 878 VC4_SET_FIELD((mode->htotal - 879 mode->hsync_end) * pixel_rep, 880 VC4_HDMI_HORZB_HBP) | 881 VC4_SET_FIELD((mode->hsync_end - 882 mode->hsync_start) * pixel_rep, 883 VC4_HDMI_HORZB_HSP) | 884 VC4_SET_FIELD((mode->hsync_start - 885 mode->hdisplay) * pixel_rep, 886 VC4_HDMI_HORZB_HFP)); 887 888 HDMI_WRITE(HDMI_VERTA0, verta); 889 HDMI_WRITE(HDMI_VERTA1, verta); 890 891 HDMI_WRITE(HDMI_VERTB0, vertb_even); 892 HDMI_WRITE(HDMI_VERTB1, vertb); 893 894 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 895 } 896 897 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi, 898 struct drm_connector_state *state, 899 struct drm_display_mode *mode) 900 { 901 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 902 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 903 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 904 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 905 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 906 VC5_HDMI_VERTA_VSP) | 907 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 908 VC5_HDMI_VERTA_VFP) | 909 VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL)); 910 u32 vertb = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) | 911 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end, 912 VC4_HDMI_VERTB_VBP)); 913 u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) | 914 VC4_SET_FIELD(mode->crtc_vtotal - 915 mode->crtc_vsync_end - 916 interlaced, 917 VC4_HDMI_VERTB_VBP)); 918 unsigned long flags; 919 unsigned char gcp; 920 bool gcp_en; 921 u32 reg; 922 923 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 924 925 HDMI_WRITE(HDMI_HORZA, 926 (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) | 927 (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) | 928 VC4_SET_FIELD(mode->hdisplay * pixel_rep, 929 VC5_HDMI_HORZA_HAP) | 930 VC4_SET_FIELD((mode->hsync_start - 931 mode->hdisplay) * pixel_rep, 932 VC5_HDMI_HORZA_HFP)); 933 934 HDMI_WRITE(HDMI_HORZB, 935 VC4_SET_FIELD((mode->htotal - 936 mode->hsync_end) * pixel_rep, 937 VC5_HDMI_HORZB_HBP) | 938 VC4_SET_FIELD((mode->hsync_end - 939 mode->hsync_start) * pixel_rep, 940 VC5_HDMI_HORZB_HSP)); 941 942 HDMI_WRITE(HDMI_VERTA0, verta); 943 HDMI_WRITE(HDMI_VERTA1, verta); 944 945 HDMI_WRITE(HDMI_VERTB0, vertb_even); 946 HDMI_WRITE(HDMI_VERTB1, vertb); 947 948 switch (state->max_bpc) { 949 case 12: 950 gcp = 6; 951 gcp_en = true; 952 break; 953 case 10: 954 gcp = 5; 955 gcp_en = true; 956 break; 957 case 8: 958 default: 959 gcp = 4; 960 gcp_en = false; 961 break; 962 } 963 964 reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1); 965 reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK | 966 VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK); 967 reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) | 968 VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH); 969 HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg); 970 971 reg = HDMI_READ(HDMI_GCP_WORD_1); 972 reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK; 973 reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1); 974 HDMI_WRITE(HDMI_GCP_WORD_1, reg); 975 976 reg = HDMI_READ(HDMI_GCP_CONFIG); 977 reg &= ~VC5_HDMI_GCP_CONFIG_GCP_ENABLE; 978 reg |= gcp_en ? VC5_HDMI_GCP_CONFIG_GCP_ENABLE : 0; 979 HDMI_WRITE(HDMI_GCP_CONFIG, reg); 980 981 HDMI_WRITE(HDMI_CLOCK_STOP, 0); 982 983 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 984 } 985 986 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi) 987 { 988 unsigned long flags; 989 u32 drift; 990 int ret; 991 992 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 993 994 drift = HDMI_READ(HDMI_FIFO_CTL); 995 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK; 996 997 HDMI_WRITE(HDMI_FIFO_CTL, 998 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 999 HDMI_WRITE(HDMI_FIFO_CTL, 1000 drift | VC4_HDMI_FIFO_CTL_RECENTER); 1001 1002 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1003 1004 usleep_range(1000, 1100); 1005 1006 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1007 1008 HDMI_WRITE(HDMI_FIFO_CTL, 1009 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 1010 HDMI_WRITE(HDMI_FIFO_CTL, 1011 drift | VC4_HDMI_FIFO_CTL_RECENTER); 1012 1013 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1014 1015 ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) & 1016 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1); 1017 WARN_ONCE(ret, "Timeout waiting for " 1018 "VC4_HDMI_FIFO_CTL_RECENTER_DONE"); 1019 } 1020 1021 static struct drm_connector_state * 1022 vc4_hdmi_encoder_get_connector_state(struct drm_encoder *encoder, 1023 struct drm_atomic_state *state) 1024 { 1025 struct drm_connector_state *conn_state; 1026 struct drm_connector *connector; 1027 unsigned int i; 1028 1029 for_each_new_connector_in_state(state, connector, conn_state, i) { 1030 if (conn_state->best_encoder == encoder) 1031 return conn_state; 1032 } 1033 1034 return NULL; 1035 } 1036 1037 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder, 1038 struct drm_atomic_state *state) 1039 { 1040 struct drm_connector_state *conn_state = 1041 vc4_hdmi_encoder_get_connector_state(encoder, state); 1042 struct vc4_hdmi_connector_state *vc4_conn_state = 1043 conn_state_to_vc4_hdmi_conn_state(conn_state); 1044 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1045 struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1046 unsigned long pixel_rate = vc4_conn_state->pixel_rate; 1047 unsigned long bvb_rate, hsm_rate; 1048 unsigned long flags; 1049 int ret; 1050 1051 mutex_lock(&vc4_hdmi->mutex); 1052 1053 /* 1054 * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must 1055 * be faster than pixel clock, infinitesimally faster, tested in 1056 * simulation. Otherwise, exact value is unimportant for HDMI 1057 * operation." This conflicts with bcm2835's vc4 documentation, which 1058 * states HSM's clock has to be at least 108% of the pixel clock. 1059 * 1060 * Real life tests reveal that vc4's firmware statement holds up, and 1061 * users are able to use pixel clocks closer to HSM's, namely for 1062 * 1920x1200@60Hz. So it was decided to have leave a 1% margin between 1063 * both clocks. Which, for RPi0-3 implies a maximum pixel clock of 1064 * 162MHz. 1065 * 1066 * Additionally, the AXI clock needs to be at least 25% of 1067 * pixel clock, but HSM ends up being the limiting factor. 1068 */ 1069 hsm_rate = max_t(unsigned long, 120000000, (pixel_rate / 100) * 101); 1070 ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate); 1071 if (ret) { 1072 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret); 1073 goto out; 1074 } 1075 1076 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev); 1077 if (ret < 0) { 1078 DRM_ERROR("Failed to retain power domain: %d\n", ret); 1079 goto out; 1080 } 1081 1082 ret = clk_set_rate(vc4_hdmi->pixel_clock, pixel_rate); 1083 if (ret) { 1084 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret); 1085 goto err_put_runtime_pm; 1086 } 1087 1088 ret = clk_prepare_enable(vc4_hdmi->pixel_clock); 1089 if (ret) { 1090 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret); 1091 goto err_put_runtime_pm; 1092 } 1093 1094 1095 vc4_hdmi_cec_update_clk_div(vc4_hdmi); 1096 1097 if (pixel_rate > 297000000) 1098 bvb_rate = 300000000; 1099 else if (pixel_rate > 148500000) 1100 bvb_rate = 150000000; 1101 else 1102 bvb_rate = 75000000; 1103 1104 ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate); 1105 if (ret) { 1106 DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret); 1107 goto err_disable_pixel_clock; 1108 } 1109 1110 ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock); 1111 if (ret) { 1112 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret); 1113 goto err_disable_pixel_clock; 1114 } 1115 1116 if (vc4_hdmi->variant->phy_init) 1117 vc4_hdmi->variant->phy_init(vc4_hdmi, vc4_conn_state); 1118 1119 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1120 1121 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1122 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 1123 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT | 1124 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS); 1125 1126 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1127 1128 if (vc4_hdmi->variant->set_timings) 1129 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode); 1130 1131 mutex_unlock(&vc4_hdmi->mutex); 1132 1133 return; 1134 1135 err_disable_pixel_clock: 1136 clk_disable_unprepare(vc4_hdmi->pixel_clock); 1137 err_put_runtime_pm: 1138 pm_runtime_put(&vc4_hdmi->pdev->dev); 1139 out: 1140 mutex_unlock(&vc4_hdmi->mutex); 1141 return; 1142 } 1143 1144 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder, 1145 struct drm_atomic_state *state) 1146 { 1147 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1148 struct drm_connector *connector = &vc4_hdmi->connector; 1149 struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1150 struct drm_connector_state *conn_state = 1151 drm_atomic_get_new_connector_state(state, connector); 1152 unsigned long flags; 1153 1154 mutex_lock(&vc4_hdmi->mutex); 1155 1156 if (vc4_hdmi->variant->csc_setup) 1157 vc4_hdmi->variant->csc_setup(vc4_hdmi, conn_state, mode); 1158 1159 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1160 HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N); 1161 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1162 1163 mutex_unlock(&vc4_hdmi->mutex); 1164 } 1165 1166 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder, 1167 struct drm_atomic_state *state) 1168 { 1169 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1170 struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1171 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 1172 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 1173 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 1174 unsigned long flags; 1175 int ret; 1176 1177 mutex_lock(&vc4_hdmi->mutex); 1178 1179 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1180 1181 HDMI_WRITE(HDMI_VID_CTL, 1182 VC4_HD_VID_CTL_ENABLE | 1183 VC4_HD_VID_CTL_CLRRGB | 1184 VC4_HD_VID_CTL_UNDERFLOW_ENABLE | 1185 VC4_HD_VID_CTL_FRAME_COUNTER_RESET | 1186 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) | 1187 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW)); 1188 1189 HDMI_WRITE(HDMI_VID_CTL, 1190 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX); 1191 1192 if (vc4_encoder->hdmi_monitor) { 1193 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1194 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 1195 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 1196 1197 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1198 1199 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1200 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000); 1201 WARN_ONCE(ret, "Timeout waiting for " 1202 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 1203 } else { 1204 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 1205 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & 1206 ~(VC4_HDMI_RAM_PACKET_ENABLE)); 1207 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1208 HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1209 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 1210 1211 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1212 1213 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1214 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000); 1215 WARN_ONCE(ret, "Timeout waiting for " 1216 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 1217 } 1218 1219 if (vc4_encoder->hdmi_monitor) { 1220 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1221 1222 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1223 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE)); 1224 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1225 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 1226 VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT); 1227 1228 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 1229 VC4_HDMI_RAM_PACKET_ENABLE); 1230 1231 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1232 1233 vc4_hdmi_set_infoframes(encoder); 1234 } 1235 1236 vc4_hdmi_recenter_fifo(vc4_hdmi); 1237 vc4_hdmi_enable_scrambling(encoder); 1238 1239 mutex_unlock(&vc4_hdmi->mutex); 1240 } 1241 1242 static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder) 1243 { 1244 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1245 1246 mutex_lock(&vc4_hdmi->mutex); 1247 vc4_hdmi->output_enabled = true; 1248 mutex_unlock(&vc4_hdmi->mutex); 1249 } 1250 1251 static void vc4_hdmi_encoder_atomic_mode_set(struct drm_encoder *encoder, 1252 struct drm_crtc_state *crtc_state, 1253 struct drm_connector_state *conn_state) 1254 { 1255 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1256 1257 mutex_lock(&vc4_hdmi->mutex); 1258 memcpy(&vc4_hdmi->saved_adjusted_mode, 1259 &crtc_state->adjusted_mode, 1260 sizeof(vc4_hdmi->saved_adjusted_mode)); 1261 mutex_unlock(&vc4_hdmi->mutex); 1262 } 1263 1264 #define WIFI_2_4GHz_CH1_MIN_FREQ 2400000000ULL 1265 #define WIFI_2_4GHz_CH1_MAX_FREQ 2422000000ULL 1266 1267 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder, 1268 struct drm_crtc_state *crtc_state, 1269 struct drm_connector_state *conn_state) 1270 { 1271 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state); 1272 struct drm_display_mode *mode = &crtc_state->adjusted_mode; 1273 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1274 unsigned long long pixel_rate = mode->clock * 1000; 1275 unsigned long long tmds_rate; 1276 1277 if (vc4_hdmi->variant->unsupported_odd_h_timings && 1278 ((mode->hdisplay % 2) || (mode->hsync_start % 2) || 1279 (mode->hsync_end % 2) || (mode->htotal % 2))) 1280 return -EINVAL; 1281 1282 /* 1283 * The 1440p@60 pixel rate is in the same range than the first 1284 * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz 1285 * bandwidth). Slightly lower the frequency to bring it out of 1286 * the WiFi range. 1287 */ 1288 tmds_rate = pixel_rate * 10; 1289 if (vc4_hdmi->disable_wifi_frequencies && 1290 (tmds_rate >= WIFI_2_4GHz_CH1_MIN_FREQ && 1291 tmds_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) { 1292 mode->clock = 238560; 1293 pixel_rate = mode->clock * 1000; 1294 } 1295 1296 if (conn_state->max_bpc == 12) { 1297 pixel_rate = pixel_rate * 150; 1298 do_div(pixel_rate, 100); 1299 } else if (conn_state->max_bpc == 10) { 1300 pixel_rate = pixel_rate * 125; 1301 do_div(pixel_rate, 100); 1302 } 1303 1304 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 1305 pixel_rate = pixel_rate * 2; 1306 1307 if (pixel_rate > vc4_hdmi->variant->max_pixel_clock) 1308 return -EINVAL; 1309 1310 if (vc4_hdmi->disable_4kp60 && (pixel_rate > HDMI_14_MAX_TMDS_CLK)) 1311 return -EINVAL; 1312 1313 vc4_state->pixel_rate = pixel_rate; 1314 1315 return 0; 1316 } 1317 1318 static enum drm_mode_status 1319 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder, 1320 const struct drm_display_mode *mode) 1321 { 1322 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1323 1324 if (vc4_hdmi->variant->unsupported_odd_h_timings && 1325 ((mode->hdisplay % 2) || (mode->hsync_start % 2) || 1326 (mode->hsync_end % 2) || (mode->htotal % 2))) 1327 return MODE_H_ILLEGAL; 1328 1329 if ((mode->clock * 1000) > vc4_hdmi->variant->max_pixel_clock) 1330 return MODE_CLOCK_HIGH; 1331 1332 if (vc4_hdmi->disable_4kp60 && vc4_hdmi_mode_needs_scrambling(mode)) 1333 return MODE_CLOCK_HIGH; 1334 1335 return MODE_OK; 1336 } 1337 1338 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = { 1339 .atomic_check = vc4_hdmi_encoder_atomic_check, 1340 .atomic_mode_set = vc4_hdmi_encoder_atomic_mode_set, 1341 .mode_valid = vc4_hdmi_encoder_mode_valid, 1342 .disable = vc4_hdmi_encoder_disable, 1343 .enable = vc4_hdmi_encoder_enable, 1344 }; 1345 1346 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask) 1347 { 1348 int i; 1349 u32 channel_map = 0; 1350 1351 for (i = 0; i < 8; i++) { 1352 if (channel_mask & BIT(i)) 1353 channel_map |= i << (3 * i); 1354 } 1355 return channel_map; 1356 } 1357 1358 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask) 1359 { 1360 int i; 1361 u32 channel_map = 0; 1362 1363 for (i = 0; i < 8; i++) { 1364 if (channel_mask & BIT(i)) 1365 channel_map |= i << (4 * i); 1366 } 1367 return channel_map; 1368 } 1369 1370 /* HDMI audio codec callbacks */ 1371 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi, 1372 unsigned int samplerate) 1373 { 1374 u32 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock); 1375 unsigned long flags; 1376 unsigned long n, m; 1377 1378 rational_best_approximation(hsm_clock, samplerate, 1379 VC4_HD_MAI_SMP_N_MASK >> 1380 VC4_HD_MAI_SMP_N_SHIFT, 1381 (VC4_HD_MAI_SMP_M_MASK >> 1382 VC4_HD_MAI_SMP_M_SHIFT) + 1, 1383 &n, &m); 1384 1385 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1386 HDMI_WRITE(HDMI_MAI_SMP, 1387 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) | 1388 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M)); 1389 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1390 } 1391 1392 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi, unsigned int samplerate) 1393 { 1394 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1395 u32 n, cts; 1396 u64 tmp; 1397 1398 lockdep_assert_held(&vc4_hdmi->mutex); 1399 lockdep_assert_held(&vc4_hdmi->hw_lock); 1400 1401 n = 128 * samplerate / 1000; 1402 tmp = (u64)(mode->clock * 1000) * n; 1403 do_div(tmp, 128 * samplerate); 1404 cts = tmp; 1405 1406 HDMI_WRITE(HDMI_CRP_CFG, 1407 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN | 1408 VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N)); 1409 1410 /* 1411 * We could get slightly more accurate clocks in some cases by 1412 * providing a CTS_1 value. The two CTS values are alternated 1413 * between based on the period fields 1414 */ 1415 HDMI_WRITE(HDMI_CTS_0, cts); 1416 HDMI_WRITE(HDMI_CTS_1, cts); 1417 } 1418 1419 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai) 1420 { 1421 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai); 1422 1423 return snd_soc_card_get_drvdata(card); 1424 } 1425 1426 static bool vc4_hdmi_audio_can_stream(struct vc4_hdmi *vc4_hdmi) 1427 { 1428 lockdep_assert_held(&vc4_hdmi->mutex); 1429 1430 /* 1431 * If the controller is disabled, prevent any ALSA output. 1432 */ 1433 if (!vc4_hdmi->output_enabled) 1434 return false; 1435 1436 /* 1437 * If the encoder is currently in DVI mode, treat the codec DAI 1438 * as missing. 1439 */ 1440 if (!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) & VC4_HDMI_RAM_PACKET_ENABLE)) 1441 return false; 1442 1443 return true; 1444 } 1445 1446 static int vc4_hdmi_audio_startup(struct device *dev, void *data) 1447 { 1448 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 1449 unsigned long flags; 1450 1451 mutex_lock(&vc4_hdmi->mutex); 1452 1453 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) { 1454 mutex_unlock(&vc4_hdmi->mutex); 1455 return -ENODEV; 1456 } 1457 1458 vc4_hdmi->audio.streaming = true; 1459 1460 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1461 HDMI_WRITE(HDMI_MAI_CTL, 1462 VC4_HD_MAI_CTL_RESET | 1463 VC4_HD_MAI_CTL_FLUSH | 1464 VC4_HD_MAI_CTL_DLATE | 1465 VC4_HD_MAI_CTL_ERRORE | 1466 VC4_HD_MAI_CTL_ERRORF); 1467 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1468 1469 if (vc4_hdmi->variant->phy_rng_enable) 1470 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi); 1471 1472 mutex_unlock(&vc4_hdmi->mutex); 1473 1474 return 0; 1475 } 1476 1477 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi) 1478 { 1479 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base; 1480 struct device *dev = &vc4_hdmi->pdev->dev; 1481 unsigned long flags; 1482 int ret; 1483 1484 lockdep_assert_held(&vc4_hdmi->mutex); 1485 1486 vc4_hdmi->audio.streaming = false; 1487 ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO, false); 1488 if (ret) 1489 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret); 1490 1491 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1492 1493 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET); 1494 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF); 1495 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH); 1496 1497 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1498 } 1499 1500 static void vc4_hdmi_audio_shutdown(struct device *dev, void *data) 1501 { 1502 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 1503 unsigned long flags; 1504 1505 mutex_lock(&vc4_hdmi->mutex); 1506 1507 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1508 1509 HDMI_WRITE(HDMI_MAI_CTL, 1510 VC4_HD_MAI_CTL_DLATE | 1511 VC4_HD_MAI_CTL_ERRORE | 1512 VC4_HD_MAI_CTL_ERRORF); 1513 1514 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1515 1516 if (vc4_hdmi->variant->phy_rng_disable) 1517 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi); 1518 1519 vc4_hdmi->audio.streaming = false; 1520 vc4_hdmi_audio_reset(vc4_hdmi); 1521 1522 mutex_unlock(&vc4_hdmi->mutex); 1523 } 1524 1525 static int sample_rate_to_mai_fmt(int samplerate) 1526 { 1527 switch (samplerate) { 1528 case 8000: 1529 return VC4_HDMI_MAI_SAMPLE_RATE_8000; 1530 case 11025: 1531 return VC4_HDMI_MAI_SAMPLE_RATE_11025; 1532 case 12000: 1533 return VC4_HDMI_MAI_SAMPLE_RATE_12000; 1534 case 16000: 1535 return VC4_HDMI_MAI_SAMPLE_RATE_16000; 1536 case 22050: 1537 return VC4_HDMI_MAI_SAMPLE_RATE_22050; 1538 case 24000: 1539 return VC4_HDMI_MAI_SAMPLE_RATE_24000; 1540 case 32000: 1541 return VC4_HDMI_MAI_SAMPLE_RATE_32000; 1542 case 44100: 1543 return VC4_HDMI_MAI_SAMPLE_RATE_44100; 1544 case 48000: 1545 return VC4_HDMI_MAI_SAMPLE_RATE_48000; 1546 case 64000: 1547 return VC4_HDMI_MAI_SAMPLE_RATE_64000; 1548 case 88200: 1549 return VC4_HDMI_MAI_SAMPLE_RATE_88200; 1550 case 96000: 1551 return VC4_HDMI_MAI_SAMPLE_RATE_96000; 1552 case 128000: 1553 return VC4_HDMI_MAI_SAMPLE_RATE_128000; 1554 case 176400: 1555 return VC4_HDMI_MAI_SAMPLE_RATE_176400; 1556 case 192000: 1557 return VC4_HDMI_MAI_SAMPLE_RATE_192000; 1558 default: 1559 return VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED; 1560 } 1561 } 1562 1563 /* HDMI audio codec callbacks */ 1564 static int vc4_hdmi_audio_prepare(struct device *dev, void *data, 1565 struct hdmi_codec_daifmt *daifmt, 1566 struct hdmi_codec_params *params) 1567 { 1568 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 1569 struct drm_encoder *encoder = &vc4_hdmi->encoder.base.base; 1570 unsigned int sample_rate = params->sample_rate; 1571 unsigned int channels = params->channels; 1572 unsigned long flags; 1573 u32 audio_packet_config, channel_mask; 1574 u32 channel_map; 1575 u32 mai_audio_format; 1576 u32 mai_sample_rate; 1577 1578 dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__, 1579 sample_rate, params->sample_width, channels); 1580 1581 mutex_lock(&vc4_hdmi->mutex); 1582 1583 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) { 1584 mutex_unlock(&vc4_hdmi->mutex); 1585 return -EINVAL; 1586 } 1587 1588 vc4_hdmi_audio_set_mai_clock(vc4_hdmi, sample_rate); 1589 1590 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1591 HDMI_WRITE(HDMI_MAI_CTL, 1592 VC4_SET_FIELD(channels, VC4_HD_MAI_CTL_CHNUM) | 1593 VC4_HD_MAI_CTL_WHOLSMP | 1594 VC4_HD_MAI_CTL_CHALIGN | 1595 VC4_HD_MAI_CTL_ENABLE); 1596 1597 mai_sample_rate = sample_rate_to_mai_fmt(sample_rate); 1598 if (params->iec.status[0] & IEC958_AES0_NONAUDIO && 1599 params->channels == 8) 1600 mai_audio_format = VC4_HDMI_MAI_FORMAT_HBR; 1601 else 1602 mai_audio_format = VC4_HDMI_MAI_FORMAT_PCM; 1603 HDMI_WRITE(HDMI_MAI_FMT, 1604 VC4_SET_FIELD(mai_sample_rate, 1605 VC4_HDMI_MAI_FORMAT_SAMPLE_RATE) | 1606 VC4_SET_FIELD(mai_audio_format, 1607 VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT)); 1608 1609 /* The B frame identifier should match the value used by alsa-lib (8) */ 1610 audio_packet_config = 1611 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT | 1612 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS | 1613 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER); 1614 1615 channel_mask = GENMASK(channels - 1, 0); 1616 audio_packet_config |= VC4_SET_FIELD(channel_mask, 1617 VC4_HDMI_AUDIO_PACKET_CEA_MASK); 1618 1619 /* Set the MAI threshold */ 1620 HDMI_WRITE(HDMI_MAI_THR, 1621 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) | 1622 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) | 1623 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQHIGH) | 1624 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQLOW)); 1625 1626 HDMI_WRITE(HDMI_MAI_CONFIG, 1627 VC4_HDMI_MAI_CONFIG_BIT_REVERSE | 1628 VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE | 1629 VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK)); 1630 1631 channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask); 1632 HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map); 1633 HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config); 1634 1635 vc4_hdmi_set_n_cts(vc4_hdmi, sample_rate); 1636 1637 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1638 1639 memcpy(&vc4_hdmi->audio.infoframe, ¶ms->cea, sizeof(params->cea)); 1640 vc4_hdmi_set_audio_infoframe(encoder); 1641 1642 mutex_unlock(&vc4_hdmi->mutex); 1643 1644 return 0; 1645 } 1646 1647 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = { 1648 .name = "vc4-hdmi-cpu-dai-component", 1649 }; 1650 1651 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai) 1652 { 1653 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai); 1654 1655 snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL); 1656 1657 return 0; 1658 } 1659 1660 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = { 1661 .name = "vc4-hdmi-cpu-dai", 1662 .probe = vc4_hdmi_audio_cpu_dai_probe, 1663 .playback = { 1664 .stream_name = "Playback", 1665 .channels_min = 1, 1666 .channels_max = 8, 1667 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 1668 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 1669 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 1670 SNDRV_PCM_RATE_192000, 1671 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 1672 }, 1673 }; 1674 1675 static const struct snd_dmaengine_pcm_config pcm_conf = { 1676 .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx", 1677 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 1678 }; 1679 1680 static int vc4_hdmi_audio_get_eld(struct device *dev, void *data, 1681 uint8_t *buf, size_t len) 1682 { 1683 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 1684 struct drm_connector *connector = &vc4_hdmi->connector; 1685 1686 mutex_lock(&vc4_hdmi->mutex); 1687 memcpy(buf, connector->eld, min(sizeof(connector->eld), len)); 1688 mutex_unlock(&vc4_hdmi->mutex); 1689 1690 return 0; 1691 } 1692 1693 static const struct hdmi_codec_ops vc4_hdmi_codec_ops = { 1694 .get_eld = vc4_hdmi_audio_get_eld, 1695 .prepare = vc4_hdmi_audio_prepare, 1696 .audio_shutdown = vc4_hdmi_audio_shutdown, 1697 .audio_startup = vc4_hdmi_audio_startup, 1698 }; 1699 1700 static struct hdmi_codec_pdata vc4_hdmi_codec_pdata = { 1701 .ops = &vc4_hdmi_codec_ops, 1702 .max_i2s_channels = 8, 1703 .i2s = 1, 1704 }; 1705 1706 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi) 1707 { 1708 const struct vc4_hdmi_register *mai_data = 1709 &vc4_hdmi->variant->registers[HDMI_MAI_DATA]; 1710 struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link; 1711 struct snd_soc_card *card = &vc4_hdmi->audio.card; 1712 struct device *dev = &vc4_hdmi->pdev->dev; 1713 struct platform_device *codec_pdev; 1714 const __be32 *addr; 1715 int index; 1716 int ret; 1717 1718 if (!of_find_property(dev->of_node, "dmas", NULL)) { 1719 dev_warn(dev, 1720 "'dmas' DT property is missing, no HDMI audio\n"); 1721 return 0; 1722 } 1723 1724 if (mai_data->reg != VC4_HD) { 1725 WARN_ONCE(true, "MAI isn't in the HD block\n"); 1726 return -EINVAL; 1727 } 1728 1729 /* 1730 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve 1731 * the bus address specified in the DT, because the physical address 1732 * (the one returned by platform_get_resource()) is not appropriate 1733 * for DMA transfers. 1734 * This VC/MMU should probably be exposed to avoid this kind of hacks. 1735 */ 1736 index = of_property_match_string(dev->of_node, "reg-names", "hd"); 1737 /* Before BCM2711, we don't have a named register range */ 1738 if (index < 0) 1739 index = 1; 1740 1741 addr = of_get_address(dev->of_node, index, NULL, NULL); 1742 1743 vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset; 1744 vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1745 vc4_hdmi->audio.dma_data.maxburst = 2; 1746 1747 ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0); 1748 if (ret) { 1749 dev_err(dev, "Could not register PCM component: %d\n", ret); 1750 return ret; 1751 } 1752 1753 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp, 1754 &vc4_hdmi_audio_cpu_dai_drv, 1); 1755 if (ret) { 1756 dev_err(dev, "Could not register CPU DAI: %d\n", ret); 1757 return ret; 1758 } 1759 1760 codec_pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME, 1761 PLATFORM_DEVID_AUTO, 1762 &vc4_hdmi_codec_pdata, 1763 sizeof(vc4_hdmi_codec_pdata)); 1764 if (IS_ERR(codec_pdev)) { 1765 dev_err(dev, "Couldn't register the HDMI codec: %ld\n", PTR_ERR(codec_pdev)); 1766 return PTR_ERR(codec_pdev); 1767 } 1768 1769 dai_link->cpus = &vc4_hdmi->audio.cpu; 1770 dai_link->codecs = &vc4_hdmi->audio.codec; 1771 dai_link->platforms = &vc4_hdmi->audio.platform; 1772 1773 dai_link->num_cpus = 1; 1774 dai_link->num_codecs = 1; 1775 dai_link->num_platforms = 1; 1776 1777 dai_link->name = "MAI"; 1778 dai_link->stream_name = "MAI PCM"; 1779 dai_link->codecs->dai_name = "i2s-hifi"; 1780 dai_link->cpus->dai_name = dev_name(dev); 1781 dai_link->codecs->name = dev_name(&codec_pdev->dev); 1782 dai_link->platforms->name = dev_name(dev); 1783 1784 card->dai_link = dai_link; 1785 card->num_links = 1; 1786 card->name = vc4_hdmi->variant->card_name; 1787 card->driver_name = "vc4-hdmi"; 1788 card->dev = dev; 1789 card->owner = THIS_MODULE; 1790 1791 /* 1792 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and 1793 * stores a pointer to the snd card object in dev->driver_data. This 1794 * means we cannot use it for something else. The hdmi back-pointer is 1795 * now stored in card->drvdata and should be retrieved with 1796 * snd_soc_card_get_drvdata() if needed. 1797 */ 1798 snd_soc_card_set_drvdata(card, vc4_hdmi); 1799 ret = devm_snd_soc_register_card(dev, card); 1800 if (ret) 1801 dev_err_probe(dev, ret, "Could not register sound card\n"); 1802 1803 return ret; 1804 1805 } 1806 1807 static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv) 1808 { 1809 struct vc4_hdmi *vc4_hdmi = priv; 1810 struct drm_connector *connector = &vc4_hdmi->connector; 1811 struct drm_device *dev = connector->dev; 1812 1813 if (dev && dev->registered) 1814 drm_connector_helper_hpd_irq_event(connector); 1815 1816 return IRQ_HANDLED; 1817 } 1818 1819 static int vc4_hdmi_hotplug_init(struct vc4_hdmi *vc4_hdmi) 1820 { 1821 struct drm_connector *connector = &vc4_hdmi->connector; 1822 struct platform_device *pdev = vc4_hdmi->pdev; 1823 int ret; 1824 1825 if (vc4_hdmi->variant->external_irq_controller) { 1826 unsigned int hpd_con = platform_get_irq_byname(pdev, "hpd-connected"); 1827 unsigned int hpd_rm = platform_get_irq_byname(pdev, "hpd-removed"); 1828 1829 ret = request_threaded_irq(hpd_con, 1830 NULL, 1831 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT, 1832 "vc4 hdmi hpd connected", vc4_hdmi); 1833 if (ret) 1834 return ret; 1835 1836 ret = request_threaded_irq(hpd_rm, 1837 NULL, 1838 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT, 1839 "vc4 hdmi hpd disconnected", vc4_hdmi); 1840 if (ret) { 1841 free_irq(hpd_con, vc4_hdmi); 1842 return ret; 1843 } 1844 1845 connector->polled = DRM_CONNECTOR_POLL_HPD; 1846 } 1847 1848 return 0; 1849 } 1850 1851 static void vc4_hdmi_hotplug_exit(struct vc4_hdmi *vc4_hdmi) 1852 { 1853 struct platform_device *pdev = vc4_hdmi->pdev; 1854 1855 if (vc4_hdmi->variant->external_irq_controller) { 1856 free_irq(platform_get_irq_byname(pdev, "hpd-connected"), vc4_hdmi); 1857 free_irq(platform_get_irq_byname(pdev, "hpd-removed"), vc4_hdmi); 1858 } 1859 } 1860 1861 #ifdef CONFIG_DRM_VC4_HDMI_CEC 1862 static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv) 1863 { 1864 struct vc4_hdmi *vc4_hdmi = priv; 1865 1866 if (vc4_hdmi->cec_rx_msg.len) 1867 cec_received_msg(vc4_hdmi->cec_adap, 1868 &vc4_hdmi->cec_rx_msg); 1869 1870 return IRQ_HANDLED; 1871 } 1872 1873 static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv) 1874 { 1875 struct vc4_hdmi *vc4_hdmi = priv; 1876 1877 if (vc4_hdmi->cec_tx_ok) { 1878 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK, 1879 0, 0, 0, 0); 1880 } else { 1881 /* 1882 * This CEC implementation makes 1 retry, so if we 1883 * get a NACK, then that means it made 2 attempts. 1884 */ 1885 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK, 1886 0, 2, 0, 0); 1887 } 1888 return IRQ_HANDLED; 1889 } 1890 1891 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv) 1892 { 1893 struct vc4_hdmi *vc4_hdmi = priv; 1894 irqreturn_t ret; 1895 1896 if (vc4_hdmi->cec_irq_was_rx) 1897 ret = vc4_cec_irq_handler_rx_thread(irq, priv); 1898 else 1899 ret = vc4_cec_irq_handler_tx_thread(irq, priv); 1900 1901 return ret; 1902 } 1903 1904 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1) 1905 { 1906 struct drm_device *dev = vc4_hdmi->connector.dev; 1907 struct cec_msg *msg = &vc4_hdmi->cec_rx_msg; 1908 unsigned int i; 1909 1910 lockdep_assert_held(&vc4_hdmi->hw_lock); 1911 1912 msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >> 1913 VC4_HDMI_CEC_REC_WRD_CNT_SHIFT); 1914 1915 if (msg->len > 16) { 1916 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len); 1917 return; 1918 } 1919 1920 for (i = 0; i < msg->len; i += 4) { 1921 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2)); 1922 1923 msg->msg[i] = val & 0xff; 1924 msg->msg[i + 1] = (val >> 8) & 0xff; 1925 msg->msg[i + 2] = (val >> 16) & 0xff; 1926 msg->msg[i + 3] = (val >> 24) & 0xff; 1927 } 1928 } 1929 1930 static irqreturn_t vc4_cec_irq_handler_tx_bare_locked(struct vc4_hdmi *vc4_hdmi) 1931 { 1932 u32 cntrl1; 1933 1934 lockdep_assert_held(&vc4_hdmi->hw_lock); 1935 1936 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1); 1937 vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD; 1938 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 1939 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 1940 1941 return IRQ_WAKE_THREAD; 1942 } 1943 1944 static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv) 1945 { 1946 struct vc4_hdmi *vc4_hdmi = priv; 1947 irqreturn_t ret; 1948 1949 spin_lock(&vc4_hdmi->hw_lock); 1950 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi); 1951 spin_unlock(&vc4_hdmi->hw_lock); 1952 1953 return ret; 1954 } 1955 1956 static irqreturn_t vc4_cec_irq_handler_rx_bare_locked(struct vc4_hdmi *vc4_hdmi) 1957 { 1958 u32 cntrl1; 1959 1960 lockdep_assert_held(&vc4_hdmi->hw_lock); 1961 1962 vc4_hdmi->cec_rx_msg.len = 0; 1963 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1); 1964 vc4_cec_read_msg(vc4_hdmi, cntrl1); 1965 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 1966 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 1967 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 1968 1969 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 1970 1971 return IRQ_WAKE_THREAD; 1972 } 1973 1974 static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv) 1975 { 1976 struct vc4_hdmi *vc4_hdmi = priv; 1977 irqreturn_t ret; 1978 1979 spin_lock(&vc4_hdmi->hw_lock); 1980 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi); 1981 spin_unlock(&vc4_hdmi->hw_lock); 1982 1983 return ret; 1984 } 1985 1986 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv) 1987 { 1988 struct vc4_hdmi *vc4_hdmi = priv; 1989 u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS); 1990 irqreturn_t ret; 1991 u32 cntrl5; 1992 1993 if (!(stat & VC4_HDMI_CPU_CEC)) 1994 return IRQ_NONE; 1995 1996 spin_lock(&vc4_hdmi->hw_lock); 1997 cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5); 1998 vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT; 1999 if (vc4_hdmi->cec_irq_was_rx) 2000 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi); 2001 else 2002 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi); 2003 2004 HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC); 2005 spin_unlock(&vc4_hdmi->hw_lock); 2006 2007 return ret; 2008 } 2009 2010 static int vc4_hdmi_cec_enable(struct cec_adapter *adap) 2011 { 2012 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 2013 /* clock period in microseconds */ 2014 const u32 usecs = 1000000 / CEC_CLOCK_FREQ; 2015 unsigned long flags; 2016 u32 val; 2017 int ret; 2018 2019 /* 2020 * NOTE: This function should really take vc4_hdmi->mutex, but doing so 2021 * results in a reentrancy since cec_s_phys_addr_from_edid() called in 2022 * .detect or .get_modes might call .adap_enable, which leads to this 2023 * function being called with that mutex held. 2024 * 2025 * Concurrency is not an issue for the moment since we don't share any 2026 * state with KMS, so we can ignore the lock for now, but we need to 2027 * keep it in mind if we were to change that assumption. 2028 */ 2029 2030 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev); 2031 if (ret) 2032 return ret; 2033 2034 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2035 2036 val = HDMI_READ(HDMI_CEC_CNTRL_5); 2037 val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET | 2038 VC4_HDMI_CEC_CNT_TO_4700_US_MASK | 2039 VC4_HDMI_CEC_CNT_TO_4500_US_MASK); 2040 val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) | 2041 ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT); 2042 2043 HDMI_WRITE(HDMI_CEC_CNTRL_5, val | 2044 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 2045 HDMI_WRITE(HDMI_CEC_CNTRL_5, val); 2046 HDMI_WRITE(HDMI_CEC_CNTRL_2, 2047 ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) | 2048 ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) | 2049 ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) | 2050 ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) | 2051 ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT)); 2052 HDMI_WRITE(HDMI_CEC_CNTRL_3, 2053 ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) | 2054 ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) | 2055 ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) | 2056 ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT)); 2057 HDMI_WRITE(HDMI_CEC_CNTRL_4, 2058 ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) | 2059 ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) | 2060 ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) | 2061 ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT)); 2062 2063 if (!vc4_hdmi->variant->external_irq_controller) 2064 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC); 2065 2066 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2067 2068 return 0; 2069 } 2070 2071 static int vc4_hdmi_cec_disable(struct cec_adapter *adap) 2072 { 2073 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 2074 unsigned long flags; 2075 2076 /* 2077 * NOTE: This function should really take vc4_hdmi->mutex, but doing so 2078 * results in a reentrancy since cec_s_phys_addr_from_edid() called in 2079 * .detect or .get_modes might call .adap_enable, which leads to this 2080 * function being called with that mutex held. 2081 * 2082 * Concurrency is not an issue for the moment since we don't share any 2083 * state with KMS, so we can ignore the lock for now, but we need to 2084 * keep it in mind if we were to change that assumption. 2085 */ 2086 2087 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2088 2089 if (!vc4_hdmi->variant->external_irq_controller) 2090 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC); 2091 2092 HDMI_WRITE(HDMI_CEC_CNTRL_5, HDMI_READ(HDMI_CEC_CNTRL_5) | 2093 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 2094 2095 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2096 2097 pm_runtime_put(&vc4_hdmi->pdev->dev); 2098 2099 return 0; 2100 } 2101 2102 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable) 2103 { 2104 if (enable) 2105 return vc4_hdmi_cec_enable(adap); 2106 else 2107 return vc4_hdmi_cec_disable(adap); 2108 } 2109 2110 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr) 2111 { 2112 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 2113 unsigned long flags; 2114 2115 /* 2116 * NOTE: This function should really take vc4_hdmi->mutex, but doing so 2117 * results in a reentrancy since cec_s_phys_addr_from_edid() called in 2118 * .detect or .get_modes might call .adap_enable, which leads to this 2119 * function being called with that mutex held. 2120 * 2121 * Concurrency is not an issue for the moment since we don't share any 2122 * state with KMS, so we can ignore the lock for now, but we need to 2123 * keep it in mind if we were to change that assumption. 2124 */ 2125 2126 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2127 HDMI_WRITE(HDMI_CEC_CNTRL_1, 2128 (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) | 2129 (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT); 2130 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2131 2132 return 0; 2133 } 2134 2135 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts, 2136 u32 signal_free_time, struct cec_msg *msg) 2137 { 2138 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 2139 struct drm_device *dev = vc4_hdmi->connector.dev; 2140 unsigned long flags; 2141 u32 val; 2142 unsigned int i; 2143 2144 /* 2145 * NOTE: This function should really take vc4_hdmi->mutex, but doing so 2146 * results in a reentrancy since cec_s_phys_addr_from_edid() called in 2147 * .detect or .get_modes might call .adap_enable, which leads to this 2148 * function being called with that mutex held. 2149 * 2150 * Concurrency is not an issue for the moment since we don't share any 2151 * state with KMS, so we can ignore the lock for now, but we need to 2152 * keep it in mind if we were to change that assumption. 2153 */ 2154 2155 if (msg->len > 16) { 2156 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len); 2157 return -ENOMEM; 2158 } 2159 2160 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2161 2162 for (i = 0; i < msg->len; i += 4) 2163 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2), 2164 (msg->msg[i]) | 2165 (msg->msg[i + 1] << 8) | 2166 (msg->msg[i + 2] << 16) | 2167 (msg->msg[i + 3] << 24)); 2168 2169 val = HDMI_READ(HDMI_CEC_CNTRL_1); 2170 val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 2171 HDMI_WRITE(HDMI_CEC_CNTRL_1, val); 2172 val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK; 2173 val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT; 2174 val |= VC4_HDMI_CEC_START_XMIT_BEGIN; 2175 2176 HDMI_WRITE(HDMI_CEC_CNTRL_1, val); 2177 2178 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2179 2180 return 0; 2181 } 2182 2183 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = { 2184 .adap_enable = vc4_hdmi_cec_adap_enable, 2185 .adap_log_addr = vc4_hdmi_cec_adap_log_addr, 2186 .adap_transmit = vc4_hdmi_cec_adap_transmit, 2187 }; 2188 2189 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi) 2190 { 2191 struct cec_connector_info conn_info; 2192 struct platform_device *pdev = vc4_hdmi->pdev; 2193 struct device *dev = &pdev->dev; 2194 unsigned long flags; 2195 u32 value; 2196 int ret; 2197 2198 if (!of_find_property(dev->of_node, "interrupts", NULL)) { 2199 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n"); 2200 return 0; 2201 } 2202 2203 vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops, 2204 vc4_hdmi, "vc4", 2205 CEC_CAP_DEFAULTS | 2206 CEC_CAP_CONNECTOR_INFO, 1); 2207 ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap); 2208 if (ret < 0) 2209 return ret; 2210 2211 cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector); 2212 cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info); 2213 2214 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2215 value = HDMI_READ(HDMI_CEC_CNTRL_1); 2216 /* Set the logical address to Unregistered */ 2217 value |= VC4_HDMI_CEC_ADDR_MASK; 2218 HDMI_WRITE(HDMI_CEC_CNTRL_1, value); 2219 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2220 2221 vc4_hdmi_cec_update_clk_div(vc4_hdmi); 2222 2223 if (vc4_hdmi->variant->external_irq_controller) { 2224 ret = request_threaded_irq(platform_get_irq_byname(pdev, "cec-rx"), 2225 vc4_cec_irq_handler_rx_bare, 2226 vc4_cec_irq_handler_rx_thread, 0, 2227 "vc4 hdmi cec rx", vc4_hdmi); 2228 if (ret) 2229 goto err_delete_cec_adap; 2230 2231 ret = request_threaded_irq(platform_get_irq_byname(pdev, "cec-tx"), 2232 vc4_cec_irq_handler_tx_bare, 2233 vc4_cec_irq_handler_tx_thread, 0, 2234 "vc4 hdmi cec tx", vc4_hdmi); 2235 if (ret) 2236 goto err_remove_cec_rx_handler; 2237 } else { 2238 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2239 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff); 2240 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2241 2242 ret = request_threaded_irq(platform_get_irq(pdev, 0), 2243 vc4_cec_irq_handler, 2244 vc4_cec_irq_handler_thread, 0, 2245 "vc4 hdmi cec", vc4_hdmi); 2246 if (ret) 2247 goto err_delete_cec_adap; 2248 } 2249 2250 ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev); 2251 if (ret < 0) 2252 goto err_remove_handlers; 2253 2254 return 0; 2255 2256 err_remove_handlers: 2257 if (vc4_hdmi->variant->external_irq_controller) 2258 free_irq(platform_get_irq_byname(pdev, "cec-tx"), vc4_hdmi); 2259 else 2260 free_irq(platform_get_irq(pdev, 0), vc4_hdmi); 2261 2262 err_remove_cec_rx_handler: 2263 if (vc4_hdmi->variant->external_irq_controller) 2264 free_irq(platform_get_irq_byname(pdev, "cec-rx"), vc4_hdmi); 2265 2266 err_delete_cec_adap: 2267 cec_delete_adapter(vc4_hdmi->cec_adap); 2268 2269 return ret; 2270 } 2271 2272 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi) 2273 { 2274 struct platform_device *pdev = vc4_hdmi->pdev; 2275 2276 if (vc4_hdmi->variant->external_irq_controller) { 2277 free_irq(platform_get_irq_byname(pdev, "cec-rx"), vc4_hdmi); 2278 free_irq(platform_get_irq_byname(pdev, "cec-tx"), vc4_hdmi); 2279 } else { 2280 free_irq(platform_get_irq(pdev, 0), vc4_hdmi); 2281 } 2282 2283 cec_unregister_adapter(vc4_hdmi->cec_adap); 2284 } 2285 #else 2286 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi) 2287 { 2288 return 0; 2289 } 2290 2291 static void vc4_hdmi_cec_exit(struct vc4_hdmi *vc4_hdmi) {}; 2292 2293 #endif 2294 2295 static int vc4_hdmi_build_regset(struct vc4_hdmi *vc4_hdmi, 2296 struct debugfs_regset32 *regset, 2297 enum vc4_hdmi_regs reg) 2298 { 2299 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant; 2300 struct debugfs_reg32 *regs, *new_regs; 2301 unsigned int count = 0; 2302 unsigned int i; 2303 2304 regs = kcalloc(variant->num_registers, sizeof(*regs), 2305 GFP_KERNEL); 2306 if (!regs) 2307 return -ENOMEM; 2308 2309 for (i = 0; i < variant->num_registers; i++) { 2310 const struct vc4_hdmi_register *field = &variant->registers[i]; 2311 2312 if (field->reg != reg) 2313 continue; 2314 2315 regs[count].name = field->name; 2316 regs[count].offset = field->offset; 2317 count++; 2318 } 2319 2320 new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL); 2321 if (!new_regs) 2322 return -ENOMEM; 2323 2324 regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg); 2325 regset->regs = new_regs; 2326 regset->nregs = count; 2327 2328 return 0; 2329 } 2330 2331 static int vc4_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi) 2332 { 2333 struct platform_device *pdev = vc4_hdmi->pdev; 2334 struct device *dev = &pdev->dev; 2335 int ret; 2336 2337 vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0); 2338 if (IS_ERR(vc4_hdmi->hdmicore_regs)) 2339 return PTR_ERR(vc4_hdmi->hdmicore_regs); 2340 2341 vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1); 2342 if (IS_ERR(vc4_hdmi->hd_regs)) 2343 return PTR_ERR(vc4_hdmi->hd_regs); 2344 2345 ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD); 2346 if (ret) 2347 return ret; 2348 2349 ret = vc4_hdmi_build_regset(vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI); 2350 if (ret) 2351 return ret; 2352 2353 vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel"); 2354 if (IS_ERR(vc4_hdmi->pixel_clock)) { 2355 ret = PTR_ERR(vc4_hdmi->pixel_clock); 2356 if (ret != -EPROBE_DEFER) 2357 DRM_ERROR("Failed to get pixel clock\n"); 2358 return ret; 2359 } 2360 2361 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); 2362 if (IS_ERR(vc4_hdmi->hsm_clock)) { 2363 DRM_ERROR("Failed to get HDMI state machine clock\n"); 2364 return PTR_ERR(vc4_hdmi->hsm_clock); 2365 } 2366 vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock; 2367 vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock; 2368 2369 return 0; 2370 } 2371 2372 static int vc5_hdmi_init_resources(struct vc4_hdmi *vc4_hdmi) 2373 { 2374 struct platform_device *pdev = vc4_hdmi->pdev; 2375 struct device *dev = &pdev->dev; 2376 struct resource *res; 2377 2378 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi"); 2379 if (!res) 2380 return -ENODEV; 2381 2382 vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start, 2383 resource_size(res)); 2384 if (!vc4_hdmi->hdmicore_regs) 2385 return -ENOMEM; 2386 2387 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd"); 2388 if (!res) 2389 return -ENODEV; 2390 2391 vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res)); 2392 if (!vc4_hdmi->hd_regs) 2393 return -ENOMEM; 2394 2395 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec"); 2396 if (!res) 2397 return -ENODEV; 2398 2399 vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res)); 2400 if (!vc4_hdmi->cec_regs) 2401 return -ENOMEM; 2402 2403 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc"); 2404 if (!res) 2405 return -ENODEV; 2406 2407 vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res)); 2408 if (!vc4_hdmi->csc_regs) 2409 return -ENOMEM; 2410 2411 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp"); 2412 if (!res) 2413 return -ENODEV; 2414 2415 vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res)); 2416 if (!vc4_hdmi->dvp_regs) 2417 return -ENOMEM; 2418 2419 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy"); 2420 if (!res) 2421 return -ENODEV; 2422 2423 vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res)); 2424 if (!vc4_hdmi->phy_regs) 2425 return -ENOMEM; 2426 2427 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet"); 2428 if (!res) 2429 return -ENODEV; 2430 2431 vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res)); 2432 if (!vc4_hdmi->ram_regs) 2433 return -ENOMEM; 2434 2435 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm"); 2436 if (!res) 2437 return -ENODEV; 2438 2439 vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res)); 2440 if (!vc4_hdmi->rm_regs) 2441 return -ENOMEM; 2442 2443 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); 2444 if (IS_ERR(vc4_hdmi->hsm_clock)) { 2445 DRM_ERROR("Failed to get HDMI state machine clock\n"); 2446 return PTR_ERR(vc4_hdmi->hsm_clock); 2447 } 2448 2449 vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb"); 2450 if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) { 2451 DRM_ERROR("Failed to get pixel bvb clock\n"); 2452 return PTR_ERR(vc4_hdmi->pixel_bvb_clock); 2453 } 2454 2455 vc4_hdmi->audio_clock = devm_clk_get(dev, "audio"); 2456 if (IS_ERR(vc4_hdmi->audio_clock)) { 2457 DRM_ERROR("Failed to get audio clock\n"); 2458 return PTR_ERR(vc4_hdmi->audio_clock); 2459 } 2460 2461 vc4_hdmi->cec_clock = devm_clk_get(dev, "cec"); 2462 if (IS_ERR(vc4_hdmi->cec_clock)) { 2463 DRM_ERROR("Failed to get CEC clock\n"); 2464 return PTR_ERR(vc4_hdmi->cec_clock); 2465 } 2466 2467 vc4_hdmi->reset = devm_reset_control_get(dev, NULL); 2468 if (IS_ERR(vc4_hdmi->reset)) { 2469 DRM_ERROR("Failed to get HDMI reset line\n"); 2470 return PTR_ERR(vc4_hdmi->reset); 2471 } 2472 2473 return 0; 2474 } 2475 2476 static int __maybe_unused vc4_hdmi_runtime_suspend(struct device *dev) 2477 { 2478 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 2479 2480 clk_disable_unprepare(vc4_hdmi->hsm_clock); 2481 2482 return 0; 2483 } 2484 2485 static int vc4_hdmi_runtime_resume(struct device *dev) 2486 { 2487 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 2488 int ret; 2489 2490 ret = clk_prepare_enable(vc4_hdmi->hsm_clock); 2491 if (ret) 2492 return ret; 2493 2494 return 0; 2495 } 2496 2497 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data) 2498 { 2499 const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev); 2500 struct platform_device *pdev = to_platform_device(dev); 2501 struct drm_device *drm = dev_get_drvdata(master); 2502 struct vc4_hdmi *vc4_hdmi; 2503 struct drm_encoder *encoder; 2504 struct device_node *ddc_node; 2505 int ret; 2506 2507 vc4_hdmi = devm_kzalloc(dev, sizeof(*vc4_hdmi), GFP_KERNEL); 2508 if (!vc4_hdmi) 2509 return -ENOMEM; 2510 mutex_init(&vc4_hdmi->mutex); 2511 spin_lock_init(&vc4_hdmi->hw_lock); 2512 INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq); 2513 2514 dev_set_drvdata(dev, vc4_hdmi); 2515 encoder = &vc4_hdmi->encoder.base.base; 2516 vc4_hdmi->encoder.base.type = variant->encoder_type; 2517 vc4_hdmi->encoder.base.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure; 2518 vc4_hdmi->encoder.base.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable; 2519 vc4_hdmi->encoder.base.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable; 2520 vc4_hdmi->encoder.base.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable; 2521 vc4_hdmi->encoder.base.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown; 2522 vc4_hdmi->pdev = pdev; 2523 vc4_hdmi->variant = variant; 2524 2525 /* 2526 * Since we don't know the state of the controller and its 2527 * display (if any), let's assume it's always enabled. 2528 * vc4_hdmi_disable_scrambling() will thus run at boot, make 2529 * sure it's disabled, and avoid any inconsistency. 2530 */ 2531 vc4_hdmi->scdc_enabled = true; 2532 2533 ret = variant->init_resources(vc4_hdmi); 2534 if (ret) 2535 return ret; 2536 2537 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0); 2538 if (!ddc_node) { 2539 DRM_ERROR("Failed to find ddc node in device tree\n"); 2540 return -ENODEV; 2541 } 2542 2543 vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node); 2544 of_node_put(ddc_node); 2545 if (!vc4_hdmi->ddc) { 2546 DRM_DEBUG("Failed to get ddc i2c adapter by node\n"); 2547 return -EPROBE_DEFER; 2548 } 2549 2550 /* Only use the GPIO HPD pin if present in the DT, otherwise 2551 * we'll use the HDMI core's register. 2552 */ 2553 vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN); 2554 if (IS_ERR(vc4_hdmi->hpd_gpio)) { 2555 ret = PTR_ERR(vc4_hdmi->hpd_gpio); 2556 goto err_put_ddc; 2557 } 2558 2559 vc4_hdmi->disable_wifi_frequencies = 2560 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence"); 2561 2562 if (variant->max_pixel_clock == 600000000) { 2563 struct vc4_dev *vc4 = to_vc4_dev(drm); 2564 long max_rate = clk_round_rate(vc4->hvs->core_clk, 550000000); 2565 2566 if (max_rate < 550000000) 2567 vc4_hdmi->disable_4kp60 = true; 2568 } 2569 2570 /* 2571 * If we boot without any cable connected to the HDMI connector, 2572 * the firmware will skip the HSM initialization and leave it 2573 * with a rate of 0, resulting in a bus lockup when we're 2574 * accessing the registers even if it's enabled. 2575 * 2576 * Let's put a sensible default at runtime_resume so that we 2577 * don't end up in this situation. 2578 */ 2579 ret = clk_set_min_rate(vc4_hdmi->hsm_clock, HSM_MIN_CLOCK_FREQ); 2580 if (ret) 2581 goto err_put_ddc; 2582 2583 /* 2584 * We need to have the device powered up at this point to call 2585 * our reset hook and for the CEC init. 2586 */ 2587 ret = vc4_hdmi_runtime_resume(dev); 2588 if (ret) 2589 goto err_put_ddc; 2590 2591 pm_runtime_get_noresume(dev); 2592 pm_runtime_set_active(dev); 2593 pm_runtime_enable(dev); 2594 2595 if (vc4_hdmi->variant->reset) 2596 vc4_hdmi->variant->reset(vc4_hdmi); 2597 2598 if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") || 2599 of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1")) && 2600 HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) { 2601 clk_prepare_enable(vc4_hdmi->pixel_clock); 2602 clk_prepare_enable(vc4_hdmi->hsm_clock); 2603 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock); 2604 } 2605 2606 drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS); 2607 drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs); 2608 2609 ret = vc4_hdmi_connector_init(drm, vc4_hdmi); 2610 if (ret) 2611 goto err_destroy_encoder; 2612 2613 ret = vc4_hdmi_hotplug_init(vc4_hdmi); 2614 if (ret) 2615 goto err_destroy_conn; 2616 2617 ret = vc4_hdmi_cec_init(vc4_hdmi); 2618 if (ret) 2619 goto err_free_hotplug; 2620 2621 ret = vc4_hdmi_audio_init(vc4_hdmi); 2622 if (ret) 2623 goto err_free_cec; 2624 2625 vc4_debugfs_add_file(drm, variant->debugfs_name, 2626 vc4_hdmi_debugfs_regs, 2627 vc4_hdmi); 2628 2629 pm_runtime_put_sync(dev); 2630 2631 return 0; 2632 2633 err_free_cec: 2634 vc4_hdmi_cec_exit(vc4_hdmi); 2635 err_free_hotplug: 2636 vc4_hdmi_hotplug_exit(vc4_hdmi); 2637 err_destroy_conn: 2638 vc4_hdmi_connector_destroy(&vc4_hdmi->connector); 2639 err_destroy_encoder: 2640 drm_encoder_cleanup(encoder); 2641 pm_runtime_put_sync(dev); 2642 pm_runtime_disable(dev); 2643 err_put_ddc: 2644 put_device(&vc4_hdmi->ddc->dev); 2645 2646 return ret; 2647 } 2648 2649 static void vc4_hdmi_unbind(struct device *dev, struct device *master, 2650 void *data) 2651 { 2652 struct vc4_hdmi *vc4_hdmi; 2653 2654 /* 2655 * ASoC makes it a bit hard to retrieve a pointer to the 2656 * vc4_hdmi structure. Registering the card will overwrite our 2657 * device drvdata with a pointer to the snd_soc_card structure, 2658 * which can then be used to retrieve whatever drvdata we want 2659 * to associate. 2660 * 2661 * However, that doesn't fly in the case where we wouldn't 2662 * register an ASoC card (because of an old DT that is missing 2663 * the dmas properties for example), then the card isn't 2664 * registered and the device drvdata wouldn't be set. 2665 * 2666 * We can deal with both cases by making sure a snd_soc_card 2667 * pointer and a vc4_hdmi structure are pointing to the same 2668 * memory address, so we can treat them indistinctly without any 2669 * issue. 2670 */ 2671 BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0); 2672 BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0); 2673 vc4_hdmi = dev_get_drvdata(dev); 2674 2675 kfree(vc4_hdmi->hdmi_regset.regs); 2676 kfree(vc4_hdmi->hd_regset.regs); 2677 2678 vc4_hdmi_cec_exit(vc4_hdmi); 2679 vc4_hdmi_hotplug_exit(vc4_hdmi); 2680 vc4_hdmi_connector_destroy(&vc4_hdmi->connector); 2681 drm_encoder_cleanup(&vc4_hdmi->encoder.base.base); 2682 2683 pm_runtime_disable(dev); 2684 2685 put_device(&vc4_hdmi->ddc->dev); 2686 } 2687 2688 static const struct component_ops vc4_hdmi_ops = { 2689 .bind = vc4_hdmi_bind, 2690 .unbind = vc4_hdmi_unbind, 2691 }; 2692 2693 static int vc4_hdmi_dev_probe(struct platform_device *pdev) 2694 { 2695 return component_add(&pdev->dev, &vc4_hdmi_ops); 2696 } 2697 2698 static int vc4_hdmi_dev_remove(struct platform_device *pdev) 2699 { 2700 component_del(&pdev->dev, &vc4_hdmi_ops); 2701 return 0; 2702 } 2703 2704 static const struct vc4_hdmi_variant bcm2835_variant = { 2705 .encoder_type = VC4_ENCODER_TYPE_HDMI0, 2706 .debugfs_name = "hdmi_regs", 2707 .card_name = "vc4-hdmi", 2708 .max_pixel_clock = 162000000, 2709 .registers = vc4_hdmi_fields, 2710 .num_registers = ARRAY_SIZE(vc4_hdmi_fields), 2711 2712 .init_resources = vc4_hdmi_init_resources, 2713 .csc_setup = vc4_hdmi_csc_setup, 2714 .reset = vc4_hdmi_reset, 2715 .set_timings = vc4_hdmi_set_timings, 2716 .phy_init = vc4_hdmi_phy_init, 2717 .phy_disable = vc4_hdmi_phy_disable, 2718 .phy_rng_enable = vc4_hdmi_phy_rng_enable, 2719 .phy_rng_disable = vc4_hdmi_phy_rng_disable, 2720 .channel_map = vc4_hdmi_channel_map, 2721 .supports_hdr = false, 2722 }; 2723 2724 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = { 2725 .encoder_type = VC4_ENCODER_TYPE_HDMI0, 2726 .debugfs_name = "hdmi0_regs", 2727 .card_name = "vc4-hdmi-0", 2728 .max_pixel_clock = 600000000, 2729 .registers = vc5_hdmi_hdmi0_fields, 2730 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi0_fields), 2731 .phy_lane_mapping = { 2732 PHY_LANE_0, 2733 PHY_LANE_1, 2734 PHY_LANE_2, 2735 PHY_LANE_CK, 2736 }, 2737 .unsupported_odd_h_timings = true, 2738 .external_irq_controller = true, 2739 2740 .init_resources = vc5_hdmi_init_resources, 2741 .csc_setup = vc5_hdmi_csc_setup, 2742 .reset = vc5_hdmi_reset, 2743 .set_timings = vc5_hdmi_set_timings, 2744 .phy_init = vc5_hdmi_phy_init, 2745 .phy_disable = vc5_hdmi_phy_disable, 2746 .phy_rng_enable = vc5_hdmi_phy_rng_enable, 2747 .phy_rng_disable = vc5_hdmi_phy_rng_disable, 2748 .channel_map = vc5_hdmi_channel_map, 2749 .supports_hdr = true, 2750 }; 2751 2752 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = { 2753 .encoder_type = VC4_ENCODER_TYPE_HDMI1, 2754 .debugfs_name = "hdmi1_regs", 2755 .card_name = "vc4-hdmi-1", 2756 .max_pixel_clock = HDMI_14_MAX_TMDS_CLK, 2757 .registers = vc5_hdmi_hdmi1_fields, 2758 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi1_fields), 2759 .phy_lane_mapping = { 2760 PHY_LANE_1, 2761 PHY_LANE_0, 2762 PHY_LANE_CK, 2763 PHY_LANE_2, 2764 }, 2765 .unsupported_odd_h_timings = true, 2766 .external_irq_controller = true, 2767 2768 .init_resources = vc5_hdmi_init_resources, 2769 .csc_setup = vc5_hdmi_csc_setup, 2770 .reset = vc5_hdmi_reset, 2771 .set_timings = vc5_hdmi_set_timings, 2772 .phy_init = vc5_hdmi_phy_init, 2773 .phy_disable = vc5_hdmi_phy_disable, 2774 .phy_rng_enable = vc5_hdmi_phy_rng_enable, 2775 .phy_rng_disable = vc5_hdmi_phy_rng_disable, 2776 .channel_map = vc5_hdmi_channel_map, 2777 .supports_hdr = true, 2778 }; 2779 2780 static const struct of_device_id vc4_hdmi_dt_match[] = { 2781 { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant }, 2782 { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant }, 2783 { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant }, 2784 {} 2785 }; 2786 2787 static const struct dev_pm_ops vc4_hdmi_pm_ops = { 2788 SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend, 2789 vc4_hdmi_runtime_resume, 2790 NULL) 2791 }; 2792 2793 struct platform_driver vc4_hdmi_driver = { 2794 .probe = vc4_hdmi_dev_probe, 2795 .remove = vc4_hdmi_dev_remove, 2796 .driver = { 2797 .name = "vc4_hdmi", 2798 .of_match_table = vc4_hdmi_dt_match, 2799 .pm = &vc4_hdmi_pm_ops, 2800 }, 2801 }; 2802