1 /* 2 * Copyright (C) 2015 Broadcom 3 * Copyright (c) 2014 The Linux Foundation. All rights reserved. 4 * Copyright (C) 2013 Red Hat 5 * Author: Rob Clark <robdclark@gmail.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License version 2 as published by 9 * the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 /** 21 * DOC: VC4 Falcon HDMI module 22 * 23 * The HDMI core has a state machine and a PHY. On BCM2835, most of 24 * the unit operates off of the HSM clock from CPRMAN. It also 25 * internally uses the PLLH_PIX clock for the PHY. 26 * 27 * HDMI infoframes are kept within a small packet ram, where each 28 * packet can be individually enabled for including in a frame. 29 * 30 * HDMI audio is implemented entirely within the HDMI IP block. A 31 * register in the HDMI encoder takes SPDIF frames from the DMA engine 32 * and transfers them over an internal MAI (multi-channel audio 33 * interconnect) bus to the encoder side for insertion into the video 34 * blank regions. 35 * 36 * The driver's HDMI encoder does not yet support power management. 37 * The HDMI encoder's power domain and the HSM/pixel clocks are kept 38 * continuously running, and only the HDMI logic and packet ram are 39 * powered off/on at disable/enable time. 40 * 41 * The driver does not yet support CEC control, though the HDMI 42 * encoder block has CEC support. 43 */ 44 45 #include <drm/drm_atomic_helper.h> 46 #include <drm/drm_crtc_helper.h> 47 #include <drm/drm_edid.h> 48 #include <linux/clk.h> 49 #include <linux/component.h> 50 #include <linux/i2c.h> 51 #include <linux/of_address.h> 52 #include <linux/of_gpio.h> 53 #include <linux/of_platform.h> 54 #include <linux/pm_runtime.h> 55 #include <linux/rational.h> 56 #include <sound/dmaengine_pcm.h> 57 #include <sound/pcm_drm_eld.h> 58 #include <sound/pcm_params.h> 59 #include <sound/soc.h> 60 #include "media/cec.h" 61 #include "vc4_drv.h" 62 #include "vc4_regs.h" 63 64 #define HSM_CLOCK_FREQ 163682864 65 #define CEC_CLOCK_FREQ 40000 66 #define CEC_CLOCK_DIV (HSM_CLOCK_FREQ / CEC_CLOCK_FREQ) 67 68 /* HDMI audio information */ 69 struct vc4_hdmi_audio { 70 struct snd_soc_card card; 71 struct snd_soc_dai_link link; 72 int samplerate; 73 int channels; 74 struct snd_dmaengine_dai_dma_data dma_data; 75 struct snd_pcm_substream *substream; 76 }; 77 78 /* General HDMI hardware state. */ 79 struct vc4_hdmi { 80 struct platform_device *pdev; 81 82 struct drm_encoder *encoder; 83 struct drm_connector *connector; 84 85 struct vc4_hdmi_audio audio; 86 87 struct i2c_adapter *ddc; 88 void __iomem *hdmicore_regs; 89 void __iomem *hd_regs; 90 int hpd_gpio; 91 bool hpd_active_low; 92 93 struct cec_adapter *cec_adap; 94 struct cec_msg cec_rx_msg; 95 bool cec_tx_ok; 96 bool cec_irq_was_rx; 97 98 struct clk *pixel_clock; 99 struct clk *hsm_clock; 100 }; 101 102 #define HDMI_READ(offset) readl(vc4->hdmi->hdmicore_regs + offset) 103 #define HDMI_WRITE(offset, val) writel(val, vc4->hdmi->hdmicore_regs + offset) 104 #define HD_READ(offset) readl(vc4->hdmi->hd_regs + offset) 105 #define HD_WRITE(offset, val) writel(val, vc4->hdmi->hd_regs + offset) 106 107 /* VC4 HDMI encoder KMS struct */ 108 struct vc4_hdmi_encoder { 109 struct vc4_encoder base; 110 bool hdmi_monitor; 111 bool limited_rgb_range; 112 bool rgb_range_selectable; 113 }; 114 115 static inline struct vc4_hdmi_encoder * 116 to_vc4_hdmi_encoder(struct drm_encoder *encoder) 117 { 118 return container_of(encoder, struct vc4_hdmi_encoder, base.base); 119 } 120 121 /* VC4 HDMI connector KMS struct */ 122 struct vc4_hdmi_connector { 123 struct drm_connector base; 124 125 /* Since the connector is attached to just the one encoder, 126 * this is the reference to it so we can do the best_encoder() 127 * hook. 128 */ 129 struct drm_encoder *encoder; 130 }; 131 132 static inline struct vc4_hdmi_connector * 133 to_vc4_hdmi_connector(struct drm_connector *connector) 134 { 135 return container_of(connector, struct vc4_hdmi_connector, base); 136 } 137 138 #define HDMI_REG(reg) { reg, #reg } 139 static const struct { 140 u32 reg; 141 const char *name; 142 } hdmi_regs[] = { 143 HDMI_REG(VC4_HDMI_CORE_REV), 144 HDMI_REG(VC4_HDMI_SW_RESET_CONTROL), 145 HDMI_REG(VC4_HDMI_HOTPLUG_INT), 146 HDMI_REG(VC4_HDMI_HOTPLUG), 147 HDMI_REG(VC4_HDMI_MAI_CHANNEL_MAP), 148 HDMI_REG(VC4_HDMI_MAI_CONFIG), 149 HDMI_REG(VC4_HDMI_MAI_FORMAT), 150 HDMI_REG(VC4_HDMI_AUDIO_PACKET_CONFIG), 151 HDMI_REG(VC4_HDMI_RAM_PACKET_CONFIG), 152 HDMI_REG(VC4_HDMI_HORZA), 153 HDMI_REG(VC4_HDMI_HORZB), 154 HDMI_REG(VC4_HDMI_FIFO_CTL), 155 HDMI_REG(VC4_HDMI_SCHEDULER_CONTROL), 156 HDMI_REG(VC4_HDMI_VERTA0), 157 HDMI_REG(VC4_HDMI_VERTA1), 158 HDMI_REG(VC4_HDMI_VERTB0), 159 HDMI_REG(VC4_HDMI_VERTB1), 160 HDMI_REG(VC4_HDMI_TX_PHY_RESET_CTL), 161 HDMI_REG(VC4_HDMI_TX_PHY_CTL0), 162 163 HDMI_REG(VC4_HDMI_CEC_CNTRL_1), 164 HDMI_REG(VC4_HDMI_CEC_CNTRL_2), 165 HDMI_REG(VC4_HDMI_CEC_CNTRL_3), 166 HDMI_REG(VC4_HDMI_CEC_CNTRL_4), 167 HDMI_REG(VC4_HDMI_CEC_CNTRL_5), 168 HDMI_REG(VC4_HDMI_CPU_STATUS), 169 HDMI_REG(VC4_HDMI_CPU_MASK_STATUS), 170 171 HDMI_REG(VC4_HDMI_CEC_RX_DATA_1), 172 HDMI_REG(VC4_HDMI_CEC_RX_DATA_2), 173 HDMI_REG(VC4_HDMI_CEC_RX_DATA_3), 174 HDMI_REG(VC4_HDMI_CEC_RX_DATA_4), 175 HDMI_REG(VC4_HDMI_CEC_TX_DATA_1), 176 HDMI_REG(VC4_HDMI_CEC_TX_DATA_2), 177 HDMI_REG(VC4_HDMI_CEC_TX_DATA_3), 178 HDMI_REG(VC4_HDMI_CEC_TX_DATA_4), 179 }; 180 181 static const struct { 182 u32 reg; 183 const char *name; 184 } hd_regs[] = { 185 HDMI_REG(VC4_HD_M_CTL), 186 HDMI_REG(VC4_HD_MAI_CTL), 187 HDMI_REG(VC4_HD_MAI_THR), 188 HDMI_REG(VC4_HD_MAI_FMT), 189 HDMI_REG(VC4_HD_MAI_SMP), 190 HDMI_REG(VC4_HD_VID_CTL), 191 HDMI_REG(VC4_HD_CSC_CTL), 192 HDMI_REG(VC4_HD_FRAME_COUNT), 193 }; 194 195 #ifdef CONFIG_DEBUG_FS 196 int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused) 197 { 198 struct drm_info_node *node = (struct drm_info_node *)m->private; 199 struct drm_device *dev = node->minor->dev; 200 struct vc4_dev *vc4 = to_vc4_dev(dev); 201 int i; 202 203 for (i = 0; i < ARRAY_SIZE(hdmi_regs); i++) { 204 seq_printf(m, "%s (0x%04x): 0x%08x\n", 205 hdmi_regs[i].name, hdmi_regs[i].reg, 206 HDMI_READ(hdmi_regs[i].reg)); 207 } 208 209 for (i = 0; i < ARRAY_SIZE(hd_regs); i++) { 210 seq_printf(m, "%s (0x%04x): 0x%08x\n", 211 hd_regs[i].name, hd_regs[i].reg, 212 HD_READ(hd_regs[i].reg)); 213 } 214 215 return 0; 216 } 217 #endif /* CONFIG_DEBUG_FS */ 218 219 static void vc4_hdmi_dump_regs(struct drm_device *dev) 220 { 221 struct vc4_dev *vc4 = to_vc4_dev(dev); 222 int i; 223 224 for (i = 0; i < ARRAY_SIZE(hdmi_regs); i++) { 225 DRM_INFO("0x%04x (%s): 0x%08x\n", 226 hdmi_regs[i].reg, hdmi_regs[i].name, 227 HDMI_READ(hdmi_regs[i].reg)); 228 } 229 for (i = 0; i < ARRAY_SIZE(hd_regs); i++) { 230 DRM_INFO("0x%04x (%s): 0x%08x\n", 231 hd_regs[i].reg, hd_regs[i].name, 232 HD_READ(hd_regs[i].reg)); 233 } 234 } 235 236 static enum drm_connector_status 237 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force) 238 { 239 struct drm_device *dev = connector->dev; 240 struct vc4_dev *vc4 = to_vc4_dev(dev); 241 242 if (vc4->hdmi->hpd_gpio) { 243 if (gpio_get_value_cansleep(vc4->hdmi->hpd_gpio) ^ 244 vc4->hdmi->hpd_active_low) 245 return connector_status_connected; 246 cec_phys_addr_invalidate(vc4->hdmi->cec_adap); 247 return connector_status_disconnected; 248 } 249 250 if (drm_probe_ddc(vc4->hdmi->ddc)) 251 return connector_status_connected; 252 253 if (HDMI_READ(VC4_HDMI_HOTPLUG) & VC4_HDMI_HOTPLUG_CONNECTED) 254 return connector_status_connected; 255 cec_phys_addr_invalidate(vc4->hdmi->cec_adap); 256 return connector_status_disconnected; 257 } 258 259 static void vc4_hdmi_connector_destroy(struct drm_connector *connector) 260 { 261 drm_connector_unregister(connector); 262 drm_connector_cleanup(connector); 263 } 264 265 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector) 266 { 267 struct vc4_hdmi_connector *vc4_connector = 268 to_vc4_hdmi_connector(connector); 269 struct drm_encoder *encoder = vc4_connector->encoder; 270 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 271 struct drm_device *dev = connector->dev; 272 struct vc4_dev *vc4 = to_vc4_dev(dev); 273 int ret = 0; 274 struct edid *edid; 275 276 edid = drm_get_edid(connector, vc4->hdmi->ddc); 277 cec_s_phys_addr_from_edid(vc4->hdmi->cec_adap, edid); 278 if (!edid) 279 return -ENODEV; 280 281 vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid); 282 283 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) { 284 vc4_encoder->rgb_range_selectable = 285 drm_rgb_quant_range_selectable(edid); 286 } 287 288 drm_mode_connector_update_edid_property(connector, edid); 289 ret = drm_add_edid_modes(connector, edid); 290 kfree(edid); 291 292 return ret; 293 } 294 295 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = { 296 .detect = vc4_hdmi_connector_detect, 297 .fill_modes = drm_helper_probe_single_connector_modes, 298 .destroy = vc4_hdmi_connector_destroy, 299 .reset = drm_atomic_helper_connector_reset, 300 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 301 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 302 }; 303 304 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = { 305 .get_modes = vc4_hdmi_connector_get_modes, 306 }; 307 308 static struct drm_connector *vc4_hdmi_connector_init(struct drm_device *dev, 309 struct drm_encoder *encoder) 310 { 311 struct drm_connector *connector; 312 struct vc4_hdmi_connector *hdmi_connector; 313 314 hdmi_connector = devm_kzalloc(dev->dev, sizeof(*hdmi_connector), 315 GFP_KERNEL); 316 if (!hdmi_connector) 317 return ERR_PTR(-ENOMEM); 318 connector = &hdmi_connector->base; 319 320 hdmi_connector->encoder = encoder; 321 322 drm_connector_init(dev, connector, &vc4_hdmi_connector_funcs, 323 DRM_MODE_CONNECTOR_HDMIA); 324 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs); 325 326 connector->polled = (DRM_CONNECTOR_POLL_CONNECT | 327 DRM_CONNECTOR_POLL_DISCONNECT); 328 329 connector->interlace_allowed = 1; 330 connector->doublescan_allowed = 0; 331 332 drm_mode_connector_attach_encoder(connector, encoder); 333 334 return connector; 335 } 336 337 static void vc4_hdmi_encoder_destroy(struct drm_encoder *encoder) 338 { 339 drm_encoder_cleanup(encoder); 340 } 341 342 static const struct drm_encoder_funcs vc4_hdmi_encoder_funcs = { 343 .destroy = vc4_hdmi_encoder_destroy, 344 }; 345 346 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder, 347 enum hdmi_infoframe_type type) 348 { 349 struct drm_device *dev = encoder->dev; 350 struct vc4_dev *vc4 = to_vc4_dev(dev); 351 u32 packet_id = type - 0x80; 352 353 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, 354 HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id)); 355 356 return wait_for(!(HDMI_READ(VC4_HDMI_RAM_PACKET_STATUS) & 357 BIT(packet_id)), 100); 358 } 359 360 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder, 361 union hdmi_infoframe *frame) 362 { 363 struct drm_device *dev = encoder->dev; 364 struct vc4_dev *vc4 = to_vc4_dev(dev); 365 u32 packet_id = frame->any.type - 0x80; 366 u32 packet_reg = VC4_HDMI_RAM_PACKET(packet_id); 367 uint8_t buffer[VC4_HDMI_PACKET_STRIDE]; 368 ssize_t len, i; 369 int ret; 370 371 WARN_ONCE(!(HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) & 372 VC4_HDMI_RAM_PACKET_ENABLE), 373 "Packet RAM has to be on to store the packet."); 374 375 len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer)); 376 if (len < 0) 377 return; 378 379 ret = vc4_hdmi_stop_packet(encoder, frame->any.type); 380 if (ret) { 381 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret); 382 return; 383 } 384 385 for (i = 0; i < len; i += 7) { 386 HDMI_WRITE(packet_reg, 387 buffer[i + 0] << 0 | 388 buffer[i + 1] << 8 | 389 buffer[i + 2] << 16); 390 packet_reg += 4; 391 392 HDMI_WRITE(packet_reg, 393 buffer[i + 3] << 0 | 394 buffer[i + 4] << 8 | 395 buffer[i + 5] << 16 | 396 buffer[i + 6] << 24); 397 packet_reg += 4; 398 } 399 400 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, 401 HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) | BIT(packet_id)); 402 ret = wait_for((HDMI_READ(VC4_HDMI_RAM_PACKET_STATUS) & 403 BIT(packet_id)), 100); 404 if (ret) 405 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret); 406 } 407 408 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder) 409 { 410 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 411 struct drm_crtc *crtc = encoder->crtc; 412 const struct drm_display_mode *mode = &crtc->state->adjusted_mode; 413 union hdmi_infoframe frame; 414 int ret; 415 416 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, mode, false); 417 if (ret < 0) { 418 DRM_ERROR("couldn't fill AVI infoframe\n"); 419 return; 420 } 421 422 drm_hdmi_avi_infoframe_quant_range(&frame.avi, mode, 423 vc4_encoder->limited_rgb_range ? 424 HDMI_QUANTIZATION_RANGE_LIMITED : 425 HDMI_QUANTIZATION_RANGE_FULL, 426 vc4_encoder->rgb_range_selectable, 427 false); 428 429 vc4_hdmi_write_infoframe(encoder, &frame); 430 } 431 432 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder) 433 { 434 union hdmi_infoframe frame; 435 int ret; 436 437 ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore"); 438 if (ret < 0) { 439 DRM_ERROR("couldn't fill SPD infoframe\n"); 440 return; 441 } 442 443 frame.spd.sdi = HDMI_SPD_SDI_PC; 444 445 vc4_hdmi_write_infoframe(encoder, &frame); 446 } 447 448 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder) 449 { 450 struct drm_device *drm = encoder->dev; 451 struct vc4_dev *vc4 = drm->dev_private; 452 struct vc4_hdmi *hdmi = vc4->hdmi; 453 union hdmi_infoframe frame; 454 int ret; 455 456 ret = hdmi_audio_infoframe_init(&frame.audio); 457 458 frame.audio.coding_type = HDMI_AUDIO_CODING_TYPE_STREAM; 459 frame.audio.sample_frequency = HDMI_AUDIO_SAMPLE_FREQUENCY_STREAM; 460 frame.audio.sample_size = HDMI_AUDIO_SAMPLE_SIZE_STREAM; 461 frame.audio.channels = hdmi->audio.channels; 462 463 vc4_hdmi_write_infoframe(encoder, &frame); 464 } 465 466 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder) 467 { 468 vc4_hdmi_set_avi_infoframe(encoder); 469 vc4_hdmi_set_spd_infoframe(encoder); 470 } 471 472 static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder) 473 { 474 struct drm_device *dev = encoder->dev; 475 struct vc4_dev *vc4 = to_vc4_dev(dev); 476 struct vc4_hdmi *hdmi = vc4->hdmi; 477 int ret; 478 479 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, 0); 480 481 HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16); 482 HD_WRITE(VC4_HD_VID_CTL, 483 HD_READ(VC4_HD_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE); 484 485 clk_disable_unprepare(hdmi->pixel_clock); 486 487 ret = pm_runtime_put(&hdmi->pdev->dev); 488 if (ret < 0) 489 DRM_ERROR("Failed to release power domain: %d\n", ret); 490 } 491 492 static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder) 493 { 494 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; 495 struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder); 496 struct drm_device *dev = encoder->dev; 497 struct vc4_dev *vc4 = to_vc4_dev(dev); 498 struct vc4_hdmi *hdmi = vc4->hdmi; 499 bool debug_dump_regs = false; 500 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 501 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 502 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 503 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 504 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 505 VC4_HDMI_VERTA_VSP) | 506 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 507 VC4_HDMI_VERTA_VFP) | 508 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL)); 509 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 510 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end, 511 VC4_HDMI_VERTB_VBP)); 512 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 513 VC4_SET_FIELD(mode->crtc_vtotal - 514 mode->crtc_vsync_end - 515 interlaced, 516 VC4_HDMI_VERTB_VBP)); 517 u32 csc_ctl; 518 int ret; 519 520 ret = pm_runtime_get_sync(&hdmi->pdev->dev); 521 if (ret < 0) { 522 DRM_ERROR("Failed to retain power domain: %d\n", ret); 523 return; 524 } 525 526 ret = clk_set_rate(hdmi->pixel_clock, 527 mode->clock * 1000 * 528 ((mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1)); 529 if (ret) { 530 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret); 531 return; 532 } 533 534 ret = clk_prepare_enable(hdmi->pixel_clock); 535 if (ret) { 536 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret); 537 return; 538 } 539 540 HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL, 541 VC4_HDMI_SW_RESET_HDMI | 542 VC4_HDMI_SW_RESET_FORMAT_DETECT); 543 544 HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL, 0); 545 546 /* PHY should be in reset, like 547 * vc4_hdmi_encoder_disable() does. 548 */ 549 HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16); 550 551 HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0); 552 553 if (debug_dump_regs) { 554 DRM_INFO("HDMI regs before:\n"); 555 vc4_hdmi_dump_regs(dev); 556 } 557 558 HD_WRITE(VC4_HD_VID_CTL, 0); 559 560 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL, 561 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) | 562 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT | 563 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS); 564 565 HDMI_WRITE(VC4_HDMI_HORZA, 566 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) | 567 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) | 568 VC4_SET_FIELD(mode->hdisplay * pixel_rep, 569 VC4_HDMI_HORZA_HAP)); 570 571 HDMI_WRITE(VC4_HDMI_HORZB, 572 VC4_SET_FIELD((mode->htotal - 573 mode->hsync_end) * pixel_rep, 574 VC4_HDMI_HORZB_HBP) | 575 VC4_SET_FIELD((mode->hsync_end - 576 mode->hsync_start) * pixel_rep, 577 VC4_HDMI_HORZB_HSP) | 578 VC4_SET_FIELD((mode->hsync_start - 579 mode->hdisplay) * pixel_rep, 580 VC4_HDMI_HORZB_HFP)); 581 582 HDMI_WRITE(VC4_HDMI_VERTA0, verta); 583 HDMI_WRITE(VC4_HDMI_VERTA1, verta); 584 585 HDMI_WRITE(VC4_HDMI_VERTB0, vertb_even); 586 HDMI_WRITE(VC4_HDMI_VERTB1, vertb); 587 588 HD_WRITE(VC4_HD_VID_CTL, 589 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) | 590 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW)); 591 592 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR, 593 VC4_HD_CSC_CTL_ORDER); 594 595 if (vc4_encoder->hdmi_monitor && 596 drm_default_rgb_quant_range(mode) == 597 HDMI_QUANTIZATION_RANGE_LIMITED) { 598 /* CEA VICs other than #1 requre limited range RGB 599 * output unless overridden by an AVI infoframe. 600 * Apply a colorspace conversion to squash 0-255 down 601 * to 16-235. The matrix here is: 602 * 603 * [ 0 0 0.8594 16] 604 * [ 0 0.8594 0 16] 605 * [ 0.8594 0 0 16] 606 * [ 0 0 0 1] 607 */ 608 csc_ctl |= VC4_HD_CSC_CTL_ENABLE; 609 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC; 610 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM, 611 VC4_HD_CSC_CTL_MODE); 612 613 HD_WRITE(VC4_HD_CSC_12_11, (0x000 << 16) | 0x000); 614 HD_WRITE(VC4_HD_CSC_14_13, (0x100 << 16) | 0x6e0); 615 HD_WRITE(VC4_HD_CSC_22_21, (0x6e0 << 16) | 0x000); 616 HD_WRITE(VC4_HD_CSC_24_23, (0x100 << 16) | 0x000); 617 HD_WRITE(VC4_HD_CSC_32_31, (0x000 << 16) | 0x6e0); 618 HD_WRITE(VC4_HD_CSC_34_33, (0x100 << 16) | 0x000); 619 vc4_encoder->limited_rgb_range = true; 620 } else { 621 vc4_encoder->limited_rgb_range = false; 622 } 623 624 /* The RGB order applies even when CSC is disabled. */ 625 HD_WRITE(VC4_HD_CSC_CTL, csc_ctl); 626 627 HDMI_WRITE(VC4_HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N); 628 629 if (debug_dump_regs) { 630 DRM_INFO("HDMI regs after:\n"); 631 vc4_hdmi_dump_regs(dev); 632 } 633 634 HD_WRITE(VC4_HD_VID_CTL, 635 HD_READ(VC4_HD_VID_CTL) | 636 VC4_HD_VID_CTL_ENABLE | 637 VC4_HD_VID_CTL_UNDERFLOW_ENABLE | 638 VC4_HD_VID_CTL_FRAME_COUNTER_RESET); 639 640 if (vc4_encoder->hdmi_monitor) { 641 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL, 642 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) | 643 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 644 645 ret = wait_for(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) & 646 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000); 647 WARN_ONCE(ret, "Timeout waiting for " 648 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 649 } else { 650 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, 651 HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) & 652 ~(VC4_HDMI_RAM_PACKET_ENABLE)); 653 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL, 654 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) & 655 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 656 657 ret = wait_for(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) & 658 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000); 659 WARN_ONCE(ret, "Timeout waiting for " 660 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 661 } 662 663 if (vc4_encoder->hdmi_monitor) { 664 u32 drift; 665 666 WARN_ON(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) & 667 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE)); 668 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL, 669 HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) | 670 VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT); 671 672 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG, 673 VC4_HDMI_RAM_PACKET_ENABLE); 674 675 vc4_hdmi_set_infoframes(encoder); 676 677 drift = HDMI_READ(VC4_HDMI_FIFO_CTL); 678 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK; 679 680 HDMI_WRITE(VC4_HDMI_FIFO_CTL, 681 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 682 HDMI_WRITE(VC4_HDMI_FIFO_CTL, 683 drift | VC4_HDMI_FIFO_CTL_RECENTER); 684 usleep_range(1000, 1100); 685 HDMI_WRITE(VC4_HDMI_FIFO_CTL, 686 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 687 HDMI_WRITE(VC4_HDMI_FIFO_CTL, 688 drift | VC4_HDMI_FIFO_CTL_RECENTER); 689 690 ret = wait_for(HDMI_READ(VC4_HDMI_FIFO_CTL) & 691 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1); 692 WARN_ONCE(ret, "Timeout waiting for " 693 "VC4_HDMI_FIFO_CTL_RECENTER_DONE"); 694 } 695 } 696 697 static enum drm_mode_status 698 vc4_hdmi_encoder_mode_valid(struct drm_encoder *crtc, 699 const struct drm_display_mode *mode) 700 { 701 /* HSM clock must be 108% of the pixel clock. Additionally, 702 * the AXI clock needs to be at least 25% of pixel clock, but 703 * HSM ends up being the limiting factor. 704 */ 705 if (mode->clock > HSM_CLOCK_FREQ / (1000 * 108 / 100)) 706 return MODE_CLOCK_HIGH; 707 708 return MODE_OK; 709 } 710 711 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = { 712 .mode_valid = vc4_hdmi_encoder_mode_valid, 713 .disable = vc4_hdmi_encoder_disable, 714 .enable = vc4_hdmi_encoder_enable, 715 }; 716 717 /* HDMI audio codec callbacks */ 718 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *hdmi) 719 { 720 struct drm_device *drm = hdmi->encoder->dev; 721 struct vc4_dev *vc4 = to_vc4_dev(drm); 722 u32 hsm_clock = clk_get_rate(hdmi->hsm_clock); 723 unsigned long n, m; 724 725 rational_best_approximation(hsm_clock, hdmi->audio.samplerate, 726 VC4_HD_MAI_SMP_N_MASK >> 727 VC4_HD_MAI_SMP_N_SHIFT, 728 (VC4_HD_MAI_SMP_M_MASK >> 729 VC4_HD_MAI_SMP_M_SHIFT) + 1, 730 &n, &m); 731 732 HD_WRITE(VC4_HD_MAI_SMP, 733 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) | 734 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M)); 735 } 736 737 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *hdmi) 738 { 739 struct drm_encoder *encoder = hdmi->encoder; 740 struct drm_crtc *crtc = encoder->crtc; 741 struct drm_device *drm = encoder->dev; 742 struct vc4_dev *vc4 = to_vc4_dev(drm); 743 const struct drm_display_mode *mode = &crtc->state->adjusted_mode; 744 u32 samplerate = hdmi->audio.samplerate; 745 u32 n, cts; 746 u64 tmp; 747 748 n = 128 * samplerate / 1000; 749 tmp = (u64)(mode->clock * 1000) * n; 750 do_div(tmp, 128 * samplerate); 751 cts = tmp; 752 753 HDMI_WRITE(VC4_HDMI_CRP_CFG, 754 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN | 755 VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N)); 756 757 /* 758 * We could get slightly more accurate clocks in some cases by 759 * providing a CTS_1 value. The two CTS values are alternated 760 * between based on the period fields 761 */ 762 HDMI_WRITE(VC4_HDMI_CTS_0, cts); 763 HDMI_WRITE(VC4_HDMI_CTS_1, cts); 764 } 765 766 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai) 767 { 768 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai); 769 770 return snd_soc_card_get_drvdata(card); 771 } 772 773 static int vc4_hdmi_audio_startup(struct snd_pcm_substream *substream, 774 struct snd_soc_dai *dai) 775 { 776 struct vc4_hdmi *hdmi = dai_to_hdmi(dai); 777 struct drm_encoder *encoder = hdmi->encoder; 778 struct vc4_dev *vc4 = to_vc4_dev(encoder->dev); 779 int ret; 780 781 if (hdmi->audio.substream && hdmi->audio.substream != substream) 782 return -EINVAL; 783 784 hdmi->audio.substream = substream; 785 786 /* 787 * If the HDMI encoder hasn't probed, or the encoder is 788 * currently in DVI mode, treat the codec dai as missing. 789 */ 790 if (!encoder->crtc || !(HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) & 791 VC4_HDMI_RAM_PACKET_ENABLE)) 792 return -ENODEV; 793 794 ret = snd_pcm_hw_constraint_eld(substream->runtime, 795 hdmi->connector->eld); 796 if (ret) 797 return ret; 798 799 return 0; 800 } 801 802 static int vc4_hdmi_audio_set_fmt(struct snd_soc_dai *dai, unsigned int fmt) 803 { 804 return 0; 805 } 806 807 static void vc4_hdmi_audio_reset(struct vc4_hdmi *hdmi) 808 { 809 struct drm_encoder *encoder = hdmi->encoder; 810 struct drm_device *drm = encoder->dev; 811 struct device *dev = &hdmi->pdev->dev; 812 struct vc4_dev *vc4 = to_vc4_dev(drm); 813 int ret; 814 815 ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO); 816 if (ret) 817 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret); 818 819 HD_WRITE(VC4_HD_MAI_CTL, VC4_HD_MAI_CTL_RESET); 820 HD_WRITE(VC4_HD_MAI_CTL, VC4_HD_MAI_CTL_ERRORF); 821 HD_WRITE(VC4_HD_MAI_CTL, VC4_HD_MAI_CTL_FLUSH); 822 } 823 824 static void vc4_hdmi_audio_shutdown(struct snd_pcm_substream *substream, 825 struct snd_soc_dai *dai) 826 { 827 struct vc4_hdmi *hdmi = dai_to_hdmi(dai); 828 829 if (substream != hdmi->audio.substream) 830 return; 831 832 vc4_hdmi_audio_reset(hdmi); 833 834 hdmi->audio.substream = NULL; 835 } 836 837 /* HDMI audio codec callbacks */ 838 static int vc4_hdmi_audio_hw_params(struct snd_pcm_substream *substream, 839 struct snd_pcm_hw_params *params, 840 struct snd_soc_dai *dai) 841 { 842 struct vc4_hdmi *hdmi = dai_to_hdmi(dai); 843 struct drm_encoder *encoder = hdmi->encoder; 844 struct drm_device *drm = encoder->dev; 845 struct device *dev = &hdmi->pdev->dev; 846 struct vc4_dev *vc4 = to_vc4_dev(drm); 847 u32 audio_packet_config, channel_mask; 848 u32 channel_map, i; 849 850 if (substream != hdmi->audio.substream) 851 return -EINVAL; 852 853 dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__, 854 params_rate(params), params_width(params), 855 params_channels(params)); 856 857 hdmi->audio.channels = params_channels(params); 858 hdmi->audio.samplerate = params_rate(params); 859 860 HD_WRITE(VC4_HD_MAI_CTL, 861 VC4_HD_MAI_CTL_RESET | 862 VC4_HD_MAI_CTL_FLUSH | 863 VC4_HD_MAI_CTL_DLATE | 864 VC4_HD_MAI_CTL_ERRORE | 865 VC4_HD_MAI_CTL_ERRORF); 866 867 vc4_hdmi_audio_set_mai_clock(hdmi); 868 869 audio_packet_config = 870 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT | 871 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS | 872 VC4_SET_FIELD(0xf, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER); 873 874 channel_mask = GENMASK(hdmi->audio.channels - 1, 0); 875 audio_packet_config |= VC4_SET_FIELD(channel_mask, 876 VC4_HDMI_AUDIO_PACKET_CEA_MASK); 877 878 /* Set the MAI threshold. This logic mimics the firmware's. */ 879 if (hdmi->audio.samplerate > 96000) { 880 HD_WRITE(VC4_HD_MAI_THR, 881 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQHIGH) | 882 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW)); 883 } else if (hdmi->audio.samplerate > 48000) { 884 HD_WRITE(VC4_HD_MAI_THR, 885 VC4_SET_FIELD(0x14, VC4_HD_MAI_THR_DREQHIGH) | 886 VC4_SET_FIELD(0x12, VC4_HD_MAI_THR_DREQLOW)); 887 } else { 888 HD_WRITE(VC4_HD_MAI_THR, 889 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICHIGH) | 890 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_PANICLOW) | 891 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQHIGH) | 892 VC4_SET_FIELD(0x10, VC4_HD_MAI_THR_DREQLOW)); 893 } 894 895 HDMI_WRITE(VC4_HDMI_MAI_CONFIG, 896 VC4_HDMI_MAI_CONFIG_BIT_REVERSE | 897 VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK)); 898 899 channel_map = 0; 900 for (i = 0; i < 8; i++) { 901 if (channel_mask & BIT(i)) 902 channel_map |= i << (3 * i); 903 } 904 905 HDMI_WRITE(VC4_HDMI_MAI_CHANNEL_MAP, channel_map); 906 HDMI_WRITE(VC4_HDMI_AUDIO_PACKET_CONFIG, audio_packet_config); 907 vc4_hdmi_set_n_cts(hdmi); 908 909 return 0; 910 } 911 912 static int vc4_hdmi_audio_trigger(struct snd_pcm_substream *substream, int cmd, 913 struct snd_soc_dai *dai) 914 { 915 struct vc4_hdmi *hdmi = dai_to_hdmi(dai); 916 struct drm_encoder *encoder = hdmi->encoder; 917 struct drm_device *drm = encoder->dev; 918 struct vc4_dev *vc4 = to_vc4_dev(drm); 919 920 switch (cmd) { 921 case SNDRV_PCM_TRIGGER_START: 922 vc4_hdmi_set_audio_infoframe(encoder); 923 HDMI_WRITE(VC4_HDMI_TX_PHY_CTL0, 924 HDMI_READ(VC4_HDMI_TX_PHY_CTL0) & 925 ~VC4_HDMI_TX_PHY_RNG_PWRDN); 926 HD_WRITE(VC4_HD_MAI_CTL, 927 VC4_SET_FIELD(hdmi->audio.channels, 928 VC4_HD_MAI_CTL_CHNUM) | 929 VC4_HD_MAI_CTL_ENABLE); 930 break; 931 case SNDRV_PCM_TRIGGER_STOP: 932 HD_WRITE(VC4_HD_MAI_CTL, 933 VC4_HD_MAI_CTL_DLATE | 934 VC4_HD_MAI_CTL_ERRORE | 935 VC4_HD_MAI_CTL_ERRORF); 936 HDMI_WRITE(VC4_HDMI_TX_PHY_CTL0, 937 HDMI_READ(VC4_HDMI_TX_PHY_CTL0) | 938 VC4_HDMI_TX_PHY_RNG_PWRDN); 939 break; 940 default: 941 break; 942 } 943 944 return 0; 945 } 946 947 static inline struct vc4_hdmi * 948 snd_component_to_hdmi(struct snd_soc_component *component) 949 { 950 struct snd_soc_card *card = snd_soc_component_get_drvdata(component); 951 952 return snd_soc_card_get_drvdata(card); 953 } 954 955 static int vc4_hdmi_audio_eld_ctl_info(struct snd_kcontrol *kcontrol, 956 struct snd_ctl_elem_info *uinfo) 957 { 958 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 959 struct vc4_hdmi *hdmi = snd_component_to_hdmi(component); 960 961 uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES; 962 uinfo->count = sizeof(hdmi->connector->eld); 963 964 return 0; 965 } 966 967 static int vc4_hdmi_audio_eld_ctl_get(struct snd_kcontrol *kcontrol, 968 struct snd_ctl_elem_value *ucontrol) 969 { 970 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol); 971 struct vc4_hdmi *hdmi = snd_component_to_hdmi(component); 972 973 memcpy(ucontrol->value.bytes.data, hdmi->connector->eld, 974 sizeof(hdmi->connector->eld)); 975 976 return 0; 977 } 978 979 static const struct snd_kcontrol_new vc4_hdmi_audio_controls[] = { 980 { 981 .access = SNDRV_CTL_ELEM_ACCESS_READ | 982 SNDRV_CTL_ELEM_ACCESS_VOLATILE, 983 .iface = SNDRV_CTL_ELEM_IFACE_PCM, 984 .name = "ELD", 985 .info = vc4_hdmi_audio_eld_ctl_info, 986 .get = vc4_hdmi_audio_eld_ctl_get, 987 }, 988 }; 989 990 static const struct snd_soc_dapm_widget vc4_hdmi_audio_widgets[] = { 991 SND_SOC_DAPM_OUTPUT("TX"), 992 }; 993 994 static const struct snd_soc_dapm_route vc4_hdmi_audio_routes[] = { 995 { "TX", NULL, "Playback" }, 996 }; 997 998 static const struct snd_soc_codec_driver vc4_hdmi_audio_codec_drv = { 999 .component_driver = { 1000 .controls = vc4_hdmi_audio_controls, 1001 .num_controls = ARRAY_SIZE(vc4_hdmi_audio_controls), 1002 .dapm_widgets = vc4_hdmi_audio_widgets, 1003 .num_dapm_widgets = ARRAY_SIZE(vc4_hdmi_audio_widgets), 1004 .dapm_routes = vc4_hdmi_audio_routes, 1005 .num_dapm_routes = ARRAY_SIZE(vc4_hdmi_audio_routes), 1006 }, 1007 }; 1008 1009 static const struct snd_soc_dai_ops vc4_hdmi_audio_dai_ops = { 1010 .startup = vc4_hdmi_audio_startup, 1011 .shutdown = vc4_hdmi_audio_shutdown, 1012 .hw_params = vc4_hdmi_audio_hw_params, 1013 .set_fmt = vc4_hdmi_audio_set_fmt, 1014 .trigger = vc4_hdmi_audio_trigger, 1015 }; 1016 1017 static struct snd_soc_dai_driver vc4_hdmi_audio_codec_dai_drv = { 1018 .name = "vc4-hdmi-hifi", 1019 .playback = { 1020 .stream_name = "Playback", 1021 .channels_min = 2, 1022 .channels_max = 8, 1023 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 1024 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 1025 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 1026 SNDRV_PCM_RATE_192000, 1027 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 1028 }, 1029 }; 1030 1031 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = { 1032 .name = "vc4-hdmi-cpu-dai-component", 1033 }; 1034 1035 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai) 1036 { 1037 struct vc4_hdmi *hdmi = dai_to_hdmi(dai); 1038 1039 snd_soc_dai_init_dma_data(dai, &hdmi->audio.dma_data, NULL); 1040 1041 return 0; 1042 } 1043 1044 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = { 1045 .name = "vc4-hdmi-cpu-dai", 1046 .probe = vc4_hdmi_audio_cpu_dai_probe, 1047 .playback = { 1048 .stream_name = "Playback", 1049 .channels_min = 1, 1050 .channels_max = 8, 1051 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 1052 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 1053 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 1054 SNDRV_PCM_RATE_192000, 1055 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 1056 }, 1057 .ops = &vc4_hdmi_audio_dai_ops, 1058 }; 1059 1060 static const struct snd_dmaengine_pcm_config pcm_conf = { 1061 .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx", 1062 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 1063 }; 1064 1065 static int vc4_hdmi_audio_init(struct vc4_hdmi *hdmi) 1066 { 1067 struct snd_soc_dai_link *dai_link = &hdmi->audio.link; 1068 struct snd_soc_card *card = &hdmi->audio.card; 1069 struct device *dev = &hdmi->pdev->dev; 1070 const __be32 *addr; 1071 int ret; 1072 1073 if (!of_find_property(dev->of_node, "dmas", NULL)) { 1074 dev_warn(dev, 1075 "'dmas' DT property is missing, no HDMI audio\n"); 1076 return 0; 1077 } 1078 1079 /* 1080 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve 1081 * the bus address specified in the DT, because the physical address 1082 * (the one returned by platform_get_resource()) is not appropriate 1083 * for DMA transfers. 1084 * This VC/MMU should probably be exposed to avoid this kind of hacks. 1085 */ 1086 addr = of_get_address(dev->of_node, 1, NULL, NULL); 1087 hdmi->audio.dma_data.addr = be32_to_cpup(addr) + VC4_HD_MAI_DATA; 1088 hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1089 hdmi->audio.dma_data.maxburst = 2; 1090 1091 ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0); 1092 if (ret) { 1093 dev_err(dev, "Could not register PCM component: %d\n", ret); 1094 return ret; 1095 } 1096 1097 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp, 1098 &vc4_hdmi_audio_cpu_dai_drv, 1); 1099 if (ret) { 1100 dev_err(dev, "Could not register CPU DAI: %d\n", ret); 1101 return ret; 1102 } 1103 1104 /* register codec and codec dai */ 1105 ret = snd_soc_register_codec(dev, &vc4_hdmi_audio_codec_drv, 1106 &vc4_hdmi_audio_codec_dai_drv, 1); 1107 if (ret) { 1108 dev_err(dev, "Could not register codec: %d\n", ret); 1109 return ret; 1110 } 1111 1112 dai_link->name = "MAI"; 1113 dai_link->stream_name = "MAI PCM"; 1114 dai_link->codec_dai_name = vc4_hdmi_audio_codec_dai_drv.name; 1115 dai_link->cpu_dai_name = dev_name(dev); 1116 dai_link->codec_name = dev_name(dev); 1117 dai_link->platform_name = dev_name(dev); 1118 1119 card->dai_link = dai_link; 1120 card->num_links = 1; 1121 card->name = "vc4-hdmi"; 1122 card->dev = dev; 1123 1124 /* 1125 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and 1126 * stores a pointer to the snd card object in dev->driver_data. This 1127 * means we cannot use it for something else. The hdmi back-pointer is 1128 * now stored in card->drvdata and should be retrieved with 1129 * snd_soc_card_get_drvdata() if needed. 1130 */ 1131 snd_soc_card_set_drvdata(card, hdmi); 1132 ret = devm_snd_soc_register_card(dev, card); 1133 if (ret) { 1134 dev_err(dev, "Could not register sound card: %d\n", ret); 1135 goto unregister_codec; 1136 } 1137 1138 return 0; 1139 1140 unregister_codec: 1141 snd_soc_unregister_codec(dev); 1142 1143 return ret; 1144 } 1145 1146 static void vc4_hdmi_audio_cleanup(struct vc4_hdmi *hdmi) 1147 { 1148 struct device *dev = &hdmi->pdev->dev; 1149 1150 /* 1151 * If drvdata is not set this means the audio card was not 1152 * registered, just skip codec unregistration in this case. 1153 */ 1154 if (dev_get_drvdata(dev)) 1155 snd_soc_unregister_codec(dev); 1156 } 1157 1158 #ifdef CONFIG_DRM_VC4_HDMI_CEC 1159 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv) 1160 { 1161 struct vc4_dev *vc4 = priv; 1162 struct vc4_hdmi *hdmi = vc4->hdmi; 1163 1164 if (hdmi->cec_irq_was_rx) { 1165 if (hdmi->cec_rx_msg.len) 1166 cec_received_msg(hdmi->cec_adap, &hdmi->cec_rx_msg); 1167 } else if (hdmi->cec_tx_ok) { 1168 cec_transmit_done(hdmi->cec_adap, CEC_TX_STATUS_OK, 1169 0, 0, 0, 0); 1170 } else { 1171 /* 1172 * This CEC implementation makes 1 retry, so if we 1173 * get a NACK, then that means it made 2 attempts. 1174 */ 1175 cec_transmit_done(hdmi->cec_adap, CEC_TX_STATUS_NACK, 1176 0, 2, 0, 0); 1177 } 1178 return IRQ_HANDLED; 1179 } 1180 1181 static void vc4_cec_read_msg(struct vc4_dev *vc4, u32 cntrl1) 1182 { 1183 struct cec_msg *msg = &vc4->hdmi->cec_rx_msg; 1184 unsigned int i; 1185 1186 msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >> 1187 VC4_HDMI_CEC_REC_WRD_CNT_SHIFT); 1188 for (i = 0; i < msg->len; i += 4) { 1189 u32 val = HDMI_READ(VC4_HDMI_CEC_RX_DATA_1 + i); 1190 1191 msg->msg[i] = val & 0xff; 1192 msg->msg[i + 1] = (val >> 8) & 0xff; 1193 msg->msg[i + 2] = (val >> 16) & 0xff; 1194 msg->msg[i + 3] = (val >> 24) & 0xff; 1195 } 1196 } 1197 1198 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv) 1199 { 1200 struct vc4_dev *vc4 = priv; 1201 struct vc4_hdmi *hdmi = vc4->hdmi; 1202 u32 stat = HDMI_READ(VC4_HDMI_CPU_STATUS); 1203 u32 cntrl1, cntrl5; 1204 1205 if (!(stat & VC4_HDMI_CPU_CEC)) 1206 return IRQ_NONE; 1207 hdmi->cec_rx_msg.len = 0; 1208 cntrl1 = HDMI_READ(VC4_HDMI_CEC_CNTRL_1); 1209 cntrl5 = HDMI_READ(VC4_HDMI_CEC_CNTRL_5); 1210 hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT; 1211 if (hdmi->cec_irq_was_rx) { 1212 vc4_cec_read_msg(vc4, cntrl1); 1213 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 1214 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, cntrl1); 1215 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 1216 } else { 1217 hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD; 1218 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 1219 } 1220 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, cntrl1); 1221 HDMI_WRITE(VC4_HDMI_CPU_CLEAR, VC4_HDMI_CPU_CEC); 1222 1223 return IRQ_WAKE_THREAD; 1224 } 1225 1226 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable) 1227 { 1228 struct vc4_dev *vc4 = cec_get_drvdata(adap); 1229 /* clock period in microseconds */ 1230 const u32 usecs = 1000000 / CEC_CLOCK_FREQ; 1231 u32 val = HDMI_READ(VC4_HDMI_CEC_CNTRL_5); 1232 1233 val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET | 1234 VC4_HDMI_CEC_CNT_TO_4700_US_MASK | 1235 VC4_HDMI_CEC_CNT_TO_4500_US_MASK); 1236 val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) | 1237 ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT); 1238 1239 if (enable) { 1240 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_5, val | 1241 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 1242 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_5, val); 1243 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_2, 1244 ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) | 1245 ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) | 1246 ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) | 1247 ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) | 1248 ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT)); 1249 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_3, 1250 ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) | 1251 ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) | 1252 ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) | 1253 ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT)); 1254 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_4, 1255 ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) | 1256 ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) | 1257 ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) | 1258 ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT)); 1259 1260 HDMI_WRITE(VC4_HDMI_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC); 1261 } else { 1262 HDMI_WRITE(VC4_HDMI_CPU_MASK_SET, VC4_HDMI_CPU_CEC); 1263 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_5, val | 1264 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 1265 } 1266 return 0; 1267 } 1268 1269 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr) 1270 { 1271 struct vc4_dev *vc4 = cec_get_drvdata(adap); 1272 1273 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, 1274 (HDMI_READ(VC4_HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) | 1275 (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT); 1276 return 0; 1277 } 1278 1279 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts, 1280 u32 signal_free_time, struct cec_msg *msg) 1281 { 1282 struct vc4_dev *vc4 = cec_get_drvdata(adap); 1283 u32 val; 1284 unsigned int i; 1285 1286 for (i = 0; i < msg->len; i += 4) 1287 HDMI_WRITE(VC4_HDMI_CEC_TX_DATA_1 + i, 1288 (msg->msg[i]) | 1289 (msg->msg[i + 1] << 8) | 1290 (msg->msg[i + 2] << 16) | 1291 (msg->msg[i + 3] << 24)); 1292 1293 val = HDMI_READ(VC4_HDMI_CEC_CNTRL_1); 1294 val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 1295 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, val); 1296 val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK; 1297 val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT; 1298 val |= VC4_HDMI_CEC_START_XMIT_BEGIN; 1299 1300 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, val); 1301 return 0; 1302 } 1303 1304 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = { 1305 .adap_enable = vc4_hdmi_cec_adap_enable, 1306 .adap_log_addr = vc4_hdmi_cec_adap_log_addr, 1307 .adap_transmit = vc4_hdmi_cec_adap_transmit, 1308 }; 1309 #endif 1310 1311 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data) 1312 { 1313 struct platform_device *pdev = to_platform_device(dev); 1314 struct drm_device *drm = dev_get_drvdata(master); 1315 struct vc4_dev *vc4 = drm->dev_private; 1316 struct vc4_hdmi *hdmi; 1317 struct vc4_hdmi_encoder *vc4_hdmi_encoder; 1318 struct device_node *ddc_node; 1319 u32 value; 1320 int ret; 1321 1322 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); 1323 if (!hdmi) 1324 return -ENOMEM; 1325 1326 vc4_hdmi_encoder = devm_kzalloc(dev, sizeof(*vc4_hdmi_encoder), 1327 GFP_KERNEL); 1328 if (!vc4_hdmi_encoder) 1329 return -ENOMEM; 1330 vc4_hdmi_encoder->base.type = VC4_ENCODER_TYPE_HDMI; 1331 hdmi->encoder = &vc4_hdmi_encoder->base.base; 1332 1333 hdmi->pdev = pdev; 1334 hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0); 1335 if (IS_ERR(hdmi->hdmicore_regs)) 1336 return PTR_ERR(hdmi->hdmicore_regs); 1337 1338 hdmi->hd_regs = vc4_ioremap_regs(pdev, 1); 1339 if (IS_ERR(hdmi->hd_regs)) 1340 return PTR_ERR(hdmi->hd_regs); 1341 1342 hdmi->pixel_clock = devm_clk_get(dev, "pixel"); 1343 if (IS_ERR(hdmi->pixel_clock)) { 1344 DRM_ERROR("Failed to get pixel clock\n"); 1345 return PTR_ERR(hdmi->pixel_clock); 1346 } 1347 hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); 1348 if (IS_ERR(hdmi->hsm_clock)) { 1349 DRM_ERROR("Failed to get HDMI state machine clock\n"); 1350 return PTR_ERR(hdmi->hsm_clock); 1351 } 1352 1353 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0); 1354 if (!ddc_node) { 1355 DRM_ERROR("Failed to find ddc node in device tree\n"); 1356 return -ENODEV; 1357 } 1358 1359 hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node); 1360 of_node_put(ddc_node); 1361 if (!hdmi->ddc) { 1362 DRM_DEBUG("Failed to get ddc i2c adapter by node\n"); 1363 return -EPROBE_DEFER; 1364 } 1365 1366 /* This is the rate that is set by the firmware. The number 1367 * needs to be a bit higher than the pixel clock rate 1368 * (generally 148.5Mhz). 1369 */ 1370 ret = clk_set_rate(hdmi->hsm_clock, HSM_CLOCK_FREQ); 1371 if (ret) { 1372 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret); 1373 goto err_put_i2c; 1374 } 1375 1376 ret = clk_prepare_enable(hdmi->hsm_clock); 1377 if (ret) { 1378 DRM_ERROR("Failed to turn on HDMI state machine clock: %d\n", 1379 ret); 1380 goto err_put_i2c; 1381 } 1382 1383 /* Only use the GPIO HPD pin if present in the DT, otherwise 1384 * we'll use the HDMI core's register. 1385 */ 1386 if (of_find_property(dev->of_node, "hpd-gpios", &value)) { 1387 enum of_gpio_flags hpd_gpio_flags; 1388 1389 hdmi->hpd_gpio = of_get_named_gpio_flags(dev->of_node, 1390 "hpd-gpios", 0, 1391 &hpd_gpio_flags); 1392 if (hdmi->hpd_gpio < 0) { 1393 ret = hdmi->hpd_gpio; 1394 goto err_unprepare_hsm; 1395 } 1396 1397 hdmi->hpd_active_low = hpd_gpio_flags & OF_GPIO_ACTIVE_LOW; 1398 } 1399 1400 vc4->hdmi = hdmi; 1401 1402 /* HDMI core must be enabled. */ 1403 if (!(HD_READ(VC4_HD_M_CTL) & VC4_HD_M_ENABLE)) { 1404 HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_SW_RST); 1405 udelay(1); 1406 HD_WRITE(VC4_HD_M_CTL, 0); 1407 1408 HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_ENABLE); 1409 } 1410 pm_runtime_enable(dev); 1411 1412 drm_encoder_init(drm, hdmi->encoder, &vc4_hdmi_encoder_funcs, 1413 DRM_MODE_ENCODER_TMDS, NULL); 1414 drm_encoder_helper_add(hdmi->encoder, &vc4_hdmi_encoder_helper_funcs); 1415 1416 hdmi->connector = vc4_hdmi_connector_init(drm, hdmi->encoder); 1417 if (IS_ERR(hdmi->connector)) { 1418 ret = PTR_ERR(hdmi->connector); 1419 goto err_destroy_encoder; 1420 } 1421 #ifdef CONFIG_DRM_VC4_HDMI_CEC 1422 hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops, 1423 vc4, "vc4", 1424 CEC_CAP_TRANSMIT | 1425 CEC_CAP_LOG_ADDRS | 1426 CEC_CAP_PASSTHROUGH | 1427 CEC_CAP_RC, 1); 1428 ret = PTR_ERR_OR_ZERO(hdmi->cec_adap); 1429 if (ret < 0) 1430 goto err_destroy_conn; 1431 HDMI_WRITE(VC4_HDMI_CPU_MASK_SET, 0xffffffff); 1432 value = HDMI_READ(VC4_HDMI_CEC_CNTRL_1); 1433 value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK; 1434 /* 1435 * Set the logical address to Unregistered and set the clock 1436 * divider: the hsm_clock rate and this divider setting will 1437 * give a 40 kHz CEC clock. 1438 */ 1439 value |= VC4_HDMI_CEC_ADDR_MASK | 1440 (4091 << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT); 1441 HDMI_WRITE(VC4_HDMI_CEC_CNTRL_1, value); 1442 ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0), 1443 vc4_cec_irq_handler, 1444 vc4_cec_irq_handler_thread, 0, 1445 "vc4 hdmi cec", vc4); 1446 if (ret) 1447 goto err_delete_cec_adap; 1448 ret = cec_register_adapter(hdmi->cec_adap, dev); 1449 if (ret < 0) 1450 goto err_delete_cec_adap; 1451 #endif 1452 1453 ret = vc4_hdmi_audio_init(hdmi); 1454 if (ret) 1455 goto err_destroy_encoder; 1456 1457 return 0; 1458 1459 #ifdef CONFIG_DRM_VC4_HDMI_CEC 1460 err_delete_cec_adap: 1461 cec_delete_adapter(hdmi->cec_adap); 1462 err_destroy_conn: 1463 vc4_hdmi_connector_destroy(hdmi->connector); 1464 #endif 1465 err_destroy_encoder: 1466 vc4_hdmi_encoder_destroy(hdmi->encoder); 1467 err_unprepare_hsm: 1468 clk_disable_unprepare(hdmi->hsm_clock); 1469 pm_runtime_disable(dev); 1470 err_put_i2c: 1471 put_device(&hdmi->ddc->dev); 1472 1473 return ret; 1474 } 1475 1476 static void vc4_hdmi_unbind(struct device *dev, struct device *master, 1477 void *data) 1478 { 1479 struct drm_device *drm = dev_get_drvdata(master); 1480 struct vc4_dev *vc4 = drm->dev_private; 1481 struct vc4_hdmi *hdmi = vc4->hdmi; 1482 1483 vc4_hdmi_audio_cleanup(hdmi); 1484 cec_unregister_adapter(hdmi->cec_adap); 1485 vc4_hdmi_connector_destroy(hdmi->connector); 1486 vc4_hdmi_encoder_destroy(hdmi->encoder); 1487 1488 clk_disable_unprepare(hdmi->hsm_clock); 1489 pm_runtime_disable(dev); 1490 1491 put_device(&hdmi->ddc->dev); 1492 1493 vc4->hdmi = NULL; 1494 } 1495 1496 static const struct component_ops vc4_hdmi_ops = { 1497 .bind = vc4_hdmi_bind, 1498 .unbind = vc4_hdmi_unbind, 1499 }; 1500 1501 static int vc4_hdmi_dev_probe(struct platform_device *pdev) 1502 { 1503 return component_add(&pdev->dev, &vc4_hdmi_ops); 1504 } 1505 1506 static int vc4_hdmi_dev_remove(struct platform_device *pdev) 1507 { 1508 component_del(&pdev->dev, &vc4_hdmi_ops); 1509 return 0; 1510 } 1511 1512 static const struct of_device_id vc4_hdmi_dt_match[] = { 1513 { .compatible = "brcm,bcm2835-hdmi" }, 1514 {} 1515 }; 1516 1517 struct platform_driver vc4_hdmi_driver = { 1518 .probe = vc4_hdmi_dev_probe, 1519 .remove = vc4_hdmi_dev_remove, 1520 .driver = { 1521 .name = "vc4_hdmi", 1522 .of_match_table = vc4_hdmi_dt_match, 1523 }, 1524 }; 1525