1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2015 Broadcom 4 * Copyright (c) 2014 The Linux Foundation. All rights reserved. 5 * Copyright (C) 2013 Red Hat 6 * Author: Rob Clark <robdclark@gmail.com> 7 */ 8 9 /** 10 * DOC: VC4 Falcon HDMI module 11 * 12 * The HDMI core has a state machine and a PHY. On BCM2835, most of 13 * the unit operates off of the HSM clock from CPRMAN. It also 14 * internally uses the PLLH_PIX clock for the PHY. 15 * 16 * HDMI infoframes are kept within a small packet ram, where each 17 * packet can be individually enabled for including in a frame. 18 * 19 * HDMI audio is implemented entirely within the HDMI IP block. A 20 * register in the HDMI encoder takes SPDIF frames from the DMA engine 21 * and transfers them over an internal MAI (multi-channel audio 22 * interconnect) bus to the encoder side for insertion into the video 23 * blank regions. 24 * 25 * The driver's HDMI encoder does not yet support power management. 26 * The HDMI encoder's power domain and the HSM/pixel clocks are kept 27 * continuously running, and only the HDMI logic and packet ram are 28 * powered off/on at disable/enable time. 29 * 30 * The driver does not yet support CEC control, though the HDMI 31 * encoder block has CEC support. 32 */ 33 34 #include <drm/display/drm_hdmi_helper.h> 35 #include <drm/display/drm_scdc_helper.h> 36 #include <drm/drm_atomic_helper.h> 37 #include <drm/drm_drv.h> 38 #include <drm/drm_probe_helper.h> 39 #include <drm/drm_simple_kms_helper.h> 40 #include <linux/clk.h> 41 #include <linux/component.h> 42 #include <linux/gpio/consumer.h> 43 #include <linux/i2c.h> 44 #include <linux/of.h> 45 #include <linux/of_address.h> 46 #include <linux/pm_runtime.h> 47 #include <linux/rational.h> 48 #include <linux/reset.h> 49 #include <sound/dmaengine_pcm.h> 50 #include <sound/hdmi-codec.h> 51 #include <sound/pcm_drm_eld.h> 52 #include <sound/pcm_params.h> 53 #include <sound/soc.h> 54 #include "media/cec.h" 55 #include "vc4_drv.h" 56 #include "vc4_hdmi.h" 57 #include "vc4_hdmi_regs.h" 58 #include "vc4_regs.h" 59 60 #define VC5_HDMI_HORZA_HFP_SHIFT 16 61 #define VC5_HDMI_HORZA_HFP_MASK VC4_MASK(28, 16) 62 #define VC5_HDMI_HORZA_VPOS BIT(15) 63 #define VC5_HDMI_HORZA_HPOS BIT(14) 64 #define VC5_HDMI_HORZA_HAP_SHIFT 0 65 #define VC5_HDMI_HORZA_HAP_MASK VC4_MASK(13, 0) 66 67 #define VC5_HDMI_HORZB_HBP_SHIFT 16 68 #define VC5_HDMI_HORZB_HBP_MASK VC4_MASK(26, 16) 69 #define VC5_HDMI_HORZB_HSP_SHIFT 0 70 #define VC5_HDMI_HORZB_HSP_MASK VC4_MASK(10, 0) 71 72 #define VC5_HDMI_VERTA_VSP_SHIFT 24 73 #define VC5_HDMI_VERTA_VSP_MASK VC4_MASK(28, 24) 74 #define VC5_HDMI_VERTA_VFP_SHIFT 16 75 #define VC5_HDMI_VERTA_VFP_MASK VC4_MASK(22, 16) 76 #define VC5_HDMI_VERTA_VAL_SHIFT 0 77 #define VC5_HDMI_VERTA_VAL_MASK VC4_MASK(12, 0) 78 79 #define VC5_HDMI_VERTB_VSPO_SHIFT 16 80 #define VC5_HDMI_VERTB_VSPO_MASK VC4_MASK(29, 16) 81 82 #define VC4_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT 0 83 #define VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK VC4_MASK(3, 0) 84 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_SHIFT 0 85 #define VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK VC4_MASK(3, 0) 86 87 #define VC5_HDMI_SCRAMBLER_CTL_ENABLE BIT(0) 88 89 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_SHIFT 8 90 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK VC4_MASK(10, 8) 91 92 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_SHIFT 0 93 #define VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK VC4_MASK(3, 0) 94 95 #define VC5_HDMI_GCP_CONFIG_GCP_ENABLE BIT(31) 96 97 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_SHIFT 8 98 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK VC4_MASK(15, 8) 99 100 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_MASK VC4_MASK(7, 0) 101 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_SET_AVMUTE BIT(0) 102 #define VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_CLEAR_AVMUTE BIT(4) 103 104 # define VC4_HD_M_SW_RST BIT(2) 105 # define VC4_HD_M_ENABLE BIT(0) 106 107 #define HSM_MIN_CLOCK_FREQ 120000000 108 #define CEC_CLOCK_FREQ 40000 109 110 #define HDMI_14_MAX_TMDS_CLK (340 * 1000 * 1000) 111 112 static const char * const output_format_str[] = { 113 [VC4_HDMI_OUTPUT_RGB] = "RGB", 114 [VC4_HDMI_OUTPUT_YUV420] = "YUV 4:2:0", 115 [VC4_HDMI_OUTPUT_YUV422] = "YUV 4:2:2", 116 [VC4_HDMI_OUTPUT_YUV444] = "YUV 4:4:4", 117 }; 118 119 static const char *vc4_hdmi_output_fmt_str(enum vc4_hdmi_output_format fmt) 120 { 121 if (fmt >= ARRAY_SIZE(output_format_str)) 122 return "invalid"; 123 124 return output_format_str[fmt]; 125 } 126 127 static unsigned long long 128 vc4_hdmi_encoder_compute_mode_clock(const struct drm_display_mode *mode, 129 unsigned int bpc, enum vc4_hdmi_output_format fmt); 130 131 static bool vc4_hdmi_supports_scrambling(struct vc4_hdmi *vc4_hdmi) 132 { 133 struct drm_display_info *display = &vc4_hdmi->connector.display_info; 134 135 lockdep_assert_held(&vc4_hdmi->mutex); 136 137 if (!display->is_hdmi) 138 return false; 139 140 if (!display->hdmi.scdc.supported || 141 !display->hdmi.scdc.scrambling.supported) 142 return false; 143 144 return true; 145 } 146 147 static bool vc4_hdmi_mode_needs_scrambling(const struct drm_display_mode *mode, 148 unsigned int bpc, 149 enum vc4_hdmi_output_format fmt) 150 { 151 unsigned long long clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc, fmt); 152 153 return clock > HDMI_14_MAX_TMDS_CLK; 154 } 155 156 static bool vc4_hdmi_is_full_range(struct vc4_hdmi *vc4_hdmi, 157 struct vc4_hdmi_connector_state *vc4_state) 158 { 159 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 160 struct drm_display_info *display = &vc4_hdmi->connector.display_info; 161 162 if (vc4_state->broadcast_rgb == VC4_HDMI_BROADCAST_RGB_LIMITED) 163 return false; 164 else if (vc4_state->broadcast_rgb == VC4_HDMI_BROADCAST_RGB_FULL) 165 return true; 166 167 return !display->is_hdmi || 168 drm_default_rgb_quant_range(mode) == HDMI_QUANTIZATION_RANGE_FULL; 169 } 170 171 static int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused) 172 { 173 struct drm_debugfs_entry *entry = m->private; 174 struct vc4_hdmi *vc4_hdmi = entry->file.data; 175 struct drm_device *drm = vc4_hdmi->connector.dev; 176 struct drm_printer p = drm_seq_file_printer(m); 177 int idx; 178 179 if (!drm_dev_enter(drm, &idx)) 180 return -ENODEV; 181 182 drm_print_regset32(&p, &vc4_hdmi->hdmi_regset); 183 drm_print_regset32(&p, &vc4_hdmi->hd_regset); 184 drm_print_regset32(&p, &vc4_hdmi->cec_regset); 185 drm_print_regset32(&p, &vc4_hdmi->csc_regset); 186 drm_print_regset32(&p, &vc4_hdmi->dvp_regset); 187 drm_print_regset32(&p, &vc4_hdmi->phy_regset); 188 drm_print_regset32(&p, &vc4_hdmi->ram_regset); 189 drm_print_regset32(&p, &vc4_hdmi->rm_regset); 190 191 drm_dev_exit(idx); 192 193 return 0; 194 } 195 196 static void vc4_hdmi_reset(struct vc4_hdmi *vc4_hdmi) 197 { 198 struct drm_device *drm = vc4_hdmi->connector.dev; 199 unsigned long flags; 200 int idx; 201 202 /* 203 * We can be called by our bind callback, when the 204 * connector->dev pointer might not be initialised yet. 205 */ 206 if (drm && !drm_dev_enter(drm, &idx)) 207 return; 208 209 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 210 211 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_SW_RST); 212 udelay(1); 213 HDMI_WRITE(HDMI_M_CTL, 0); 214 215 HDMI_WRITE(HDMI_M_CTL, VC4_HD_M_ENABLE); 216 217 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 218 VC4_HDMI_SW_RESET_HDMI | 219 VC4_HDMI_SW_RESET_FORMAT_DETECT); 220 221 HDMI_WRITE(HDMI_SW_RESET_CONTROL, 0); 222 223 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 224 225 if (drm) 226 drm_dev_exit(idx); 227 } 228 229 static void vc5_hdmi_reset(struct vc4_hdmi *vc4_hdmi) 230 { 231 struct drm_device *drm = vc4_hdmi->connector.dev; 232 unsigned long flags; 233 int idx; 234 235 /* 236 * We can be called by our bind callback, when the 237 * connector->dev pointer might not be initialised yet. 238 */ 239 if (drm && !drm_dev_enter(drm, &idx)) 240 return; 241 242 reset_control_reset(vc4_hdmi->reset); 243 244 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 245 246 HDMI_WRITE(HDMI_DVP_CTL, 0); 247 248 HDMI_WRITE(HDMI_CLOCK_STOP, 249 HDMI_READ(HDMI_CLOCK_STOP) | VC4_DVP_HT_CLOCK_STOP_PIXEL); 250 251 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 252 253 if (drm) 254 drm_dev_exit(idx); 255 } 256 257 #ifdef CONFIG_DRM_VC4_HDMI_CEC 258 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) 259 { 260 struct drm_device *drm = vc4_hdmi->connector.dev; 261 unsigned long cec_rate; 262 unsigned long flags; 263 u16 clk_cnt; 264 u32 value; 265 int idx; 266 267 /* 268 * This function is called by our runtime_resume implementation 269 * and thus at bind time, when we haven't registered our 270 * connector yet and thus don't have a pointer to the DRM 271 * device. 272 */ 273 if (drm && !drm_dev_enter(drm, &idx)) 274 return; 275 276 cec_rate = clk_get_rate(vc4_hdmi->cec_clock); 277 278 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 279 280 value = HDMI_READ(HDMI_CEC_CNTRL_1); 281 value &= ~VC4_HDMI_CEC_DIV_CLK_CNT_MASK; 282 283 /* 284 * Set the clock divider: the hsm_clock rate and this divider 285 * setting will give a 40 kHz CEC clock. 286 */ 287 clk_cnt = cec_rate / CEC_CLOCK_FREQ; 288 value |= clk_cnt << VC4_HDMI_CEC_DIV_CLK_CNT_SHIFT; 289 HDMI_WRITE(HDMI_CEC_CNTRL_1, value); 290 291 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 292 293 if (drm) 294 drm_dev_exit(idx); 295 } 296 #else 297 static void vc4_hdmi_cec_update_clk_div(struct vc4_hdmi *vc4_hdmi) {} 298 #endif 299 300 static int reset_pipe(struct drm_crtc *crtc, 301 struct drm_modeset_acquire_ctx *ctx) 302 { 303 struct drm_atomic_state *state; 304 struct drm_crtc_state *crtc_state; 305 int ret; 306 307 state = drm_atomic_state_alloc(crtc->dev); 308 if (!state) 309 return -ENOMEM; 310 311 state->acquire_ctx = ctx; 312 313 crtc_state = drm_atomic_get_crtc_state(state, crtc); 314 if (IS_ERR(crtc_state)) { 315 ret = PTR_ERR(crtc_state); 316 goto out; 317 } 318 319 crtc_state->connectors_changed = true; 320 321 ret = drm_atomic_commit(state); 322 out: 323 drm_atomic_state_put(state); 324 325 return ret; 326 } 327 328 static int vc4_hdmi_reset_link(struct drm_connector *connector, 329 struct drm_modeset_acquire_ctx *ctx) 330 { 331 struct drm_device *drm; 332 struct vc4_hdmi *vc4_hdmi; 333 struct drm_connector_state *conn_state; 334 struct drm_crtc_state *crtc_state; 335 struct drm_crtc *crtc; 336 bool scrambling_needed; 337 u8 config; 338 int ret; 339 340 if (!connector) 341 return 0; 342 343 drm = connector->dev; 344 ret = drm_modeset_lock(&drm->mode_config.connection_mutex, ctx); 345 if (ret) 346 return ret; 347 348 conn_state = connector->state; 349 crtc = conn_state->crtc; 350 if (!crtc) 351 return 0; 352 353 ret = drm_modeset_lock(&crtc->mutex, ctx); 354 if (ret) 355 return ret; 356 357 crtc_state = crtc->state; 358 if (!crtc_state->active) 359 return 0; 360 361 vc4_hdmi = connector_to_vc4_hdmi(connector); 362 mutex_lock(&vc4_hdmi->mutex); 363 364 if (!vc4_hdmi_supports_scrambling(vc4_hdmi)) { 365 mutex_unlock(&vc4_hdmi->mutex); 366 return 0; 367 } 368 369 scrambling_needed = vc4_hdmi_mode_needs_scrambling(&vc4_hdmi->saved_adjusted_mode, 370 vc4_hdmi->output_bpc, 371 vc4_hdmi->output_format); 372 if (!scrambling_needed) { 373 mutex_unlock(&vc4_hdmi->mutex); 374 return 0; 375 } 376 377 if (conn_state->commit && 378 !try_wait_for_completion(&conn_state->commit->hw_done)) { 379 mutex_unlock(&vc4_hdmi->mutex); 380 return 0; 381 } 382 383 ret = drm_scdc_readb(connector->ddc, SCDC_TMDS_CONFIG, &config); 384 if (ret < 0) { 385 drm_err(drm, "Failed to read TMDS config: %d\n", ret); 386 mutex_unlock(&vc4_hdmi->mutex); 387 return 0; 388 } 389 390 if (!!(config & SCDC_SCRAMBLING_ENABLE) == scrambling_needed) { 391 mutex_unlock(&vc4_hdmi->mutex); 392 return 0; 393 } 394 395 mutex_unlock(&vc4_hdmi->mutex); 396 397 /* 398 * HDMI 2.0 says that one should not send scrambled data 399 * prior to configuring the sink scrambling, and that 400 * TMDS clock/data transmission should be suspended when 401 * changing the TMDS clock rate in the sink. So let's 402 * just do a full modeset here, even though some sinks 403 * would be perfectly happy if were to just reconfigure 404 * the SCDC settings on the fly. 405 */ 406 return reset_pipe(crtc, ctx); 407 } 408 409 static void vc4_hdmi_handle_hotplug(struct vc4_hdmi *vc4_hdmi, 410 struct drm_modeset_acquire_ctx *ctx, 411 enum drm_connector_status status) 412 { 413 struct drm_connector *connector = &vc4_hdmi->connector; 414 struct edid *edid; 415 int ret; 416 417 /* 418 * NOTE: This function should really be called with 419 * vc4_hdmi->mutex held, but doing so results in reentrancy 420 * issues since cec_s_phys_addr_from_edid might call 421 * .adap_enable, which leads to that funtion being called with 422 * our mutex held. 423 * 424 * A similar situation occurs with vc4_hdmi_reset_link() that 425 * will call into our KMS hooks if the scrambling was enabled. 426 * 427 * Concurrency isn't an issue at the moment since we don't share 428 * any state with any of the other frameworks so we can ignore 429 * the lock for now. 430 */ 431 432 if (status == connector_status_disconnected) { 433 cec_phys_addr_invalidate(vc4_hdmi->cec_adap); 434 return; 435 } 436 437 edid = drm_get_edid(connector, vc4_hdmi->ddc); 438 if (!edid) 439 return; 440 441 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid); 442 kfree(edid); 443 444 for (;;) { 445 ret = vc4_hdmi_reset_link(connector, ctx); 446 if (ret == -EDEADLK) { 447 drm_modeset_backoff(ctx); 448 continue; 449 } 450 451 break; 452 } 453 } 454 455 static int vc4_hdmi_connector_detect_ctx(struct drm_connector *connector, 456 struct drm_modeset_acquire_ctx *ctx, 457 bool force) 458 { 459 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 460 enum drm_connector_status status = connector_status_disconnected; 461 int ret; 462 463 /* 464 * NOTE: This function should really take vc4_hdmi->mutex, but 465 * doing so results in reentrancy issues since 466 * vc4_hdmi_handle_hotplug() can call into other functions that 467 * would take the mutex while it's held here. 468 * 469 * Concurrency isn't an issue at the moment since we don't share 470 * any state with any of the other frameworks so we can ignore 471 * the lock for now. 472 */ 473 474 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev); 475 if (ret) { 476 drm_err_once(connector->dev, "Failed to retain HDMI power domain: %d\n", 477 ret); 478 return connector_status_unknown; 479 } 480 481 if (vc4_hdmi->hpd_gpio) { 482 if (gpiod_get_value_cansleep(vc4_hdmi->hpd_gpio)) 483 status = connector_status_connected; 484 } else { 485 if (vc4_hdmi->variant->hp_detect && 486 vc4_hdmi->variant->hp_detect(vc4_hdmi)) 487 status = connector_status_connected; 488 } 489 490 vc4_hdmi_handle_hotplug(vc4_hdmi, ctx, status); 491 pm_runtime_put(&vc4_hdmi->pdev->dev); 492 493 return status; 494 } 495 496 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector) 497 { 498 struct vc4_hdmi *vc4_hdmi = connector_to_vc4_hdmi(connector); 499 struct vc4_dev *vc4 = to_vc4_dev(connector->dev); 500 int ret = 0; 501 struct edid *edid; 502 503 /* 504 * NOTE: This function should really take vc4_hdmi->mutex, but 505 * doing so results in reentrancy issues since 506 * cec_s_phys_addr_from_edid might call .adap_enable, which 507 * leads to that funtion being called with our mutex held. 508 * 509 * Concurrency isn't an issue at the moment since we don't share 510 * any state with any of the other frameworks so we can ignore 511 * the lock for now. 512 */ 513 514 edid = drm_get_edid(connector, vc4_hdmi->ddc); 515 cec_s_phys_addr_from_edid(vc4_hdmi->cec_adap, edid); 516 if (!edid) 517 return 0; 518 519 drm_connector_update_edid_property(connector, edid); 520 ret = drm_add_edid_modes(connector, edid); 521 kfree(edid); 522 523 if (!vc4->hvs->vc5_hdmi_enable_hdmi_20) { 524 struct drm_device *drm = connector->dev; 525 const struct drm_display_mode *mode; 526 527 list_for_each_entry(mode, &connector->probed_modes, head) { 528 if (vc4_hdmi_mode_needs_scrambling(mode, 8, VC4_HDMI_OUTPUT_RGB)) { 529 drm_warn_once(drm, "The core clock cannot reach frequencies high enough to support 4k @ 60Hz."); 530 drm_warn_once(drm, "Please change your config.txt file to add hdmi_enable_4kp60."); 531 } 532 } 533 } 534 535 return ret; 536 } 537 538 static int vc4_hdmi_connector_atomic_check(struct drm_connector *connector, 539 struct drm_atomic_state *state) 540 { 541 struct drm_connector_state *old_state = 542 drm_atomic_get_old_connector_state(state, connector); 543 struct vc4_hdmi_connector_state *old_vc4_state = 544 conn_state_to_vc4_hdmi_conn_state(old_state); 545 struct drm_connector_state *new_state = 546 drm_atomic_get_new_connector_state(state, connector); 547 struct vc4_hdmi_connector_state *new_vc4_state = 548 conn_state_to_vc4_hdmi_conn_state(new_state); 549 struct drm_crtc *crtc = new_state->crtc; 550 551 if (!crtc) 552 return 0; 553 554 if (old_state->tv.margins.left != new_state->tv.margins.left || 555 old_state->tv.margins.right != new_state->tv.margins.right || 556 old_state->tv.margins.top != new_state->tv.margins.top || 557 old_state->tv.margins.bottom != new_state->tv.margins.bottom) { 558 struct drm_crtc_state *crtc_state; 559 int ret; 560 561 crtc_state = drm_atomic_get_crtc_state(state, crtc); 562 if (IS_ERR(crtc_state)) 563 return PTR_ERR(crtc_state); 564 565 /* 566 * Strictly speaking, we should be calling 567 * drm_atomic_helper_check_planes() after our call to 568 * drm_atomic_add_affected_planes(). However, the 569 * connector atomic_check is called as part of 570 * drm_atomic_helper_check_modeset() that already 571 * happens before a call to 572 * drm_atomic_helper_check_planes() in 573 * drm_atomic_helper_check(). 574 */ 575 ret = drm_atomic_add_affected_planes(state, crtc); 576 if (ret) 577 return ret; 578 } 579 580 if (old_state->colorspace != new_state->colorspace || 581 old_vc4_state->broadcast_rgb != new_vc4_state->broadcast_rgb || 582 !drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) { 583 struct drm_crtc_state *crtc_state; 584 585 crtc_state = drm_atomic_get_crtc_state(state, crtc); 586 if (IS_ERR(crtc_state)) 587 return PTR_ERR(crtc_state); 588 589 crtc_state->mode_changed = true; 590 } 591 592 return 0; 593 } 594 595 static int vc4_hdmi_connector_get_property(struct drm_connector *connector, 596 const struct drm_connector_state *state, 597 struct drm_property *property, 598 uint64_t *val) 599 { 600 struct drm_device *drm = connector->dev; 601 struct vc4_hdmi *vc4_hdmi = 602 connector_to_vc4_hdmi(connector); 603 const struct vc4_hdmi_connector_state *vc4_conn_state = 604 conn_state_to_vc4_hdmi_conn_state(state); 605 606 if (property == vc4_hdmi->broadcast_rgb_property) { 607 *val = vc4_conn_state->broadcast_rgb; 608 } else { 609 drm_dbg(drm, "Unknown property [PROP:%d:%s]\n", 610 property->base.id, property->name); 611 return -EINVAL; 612 } 613 614 return 0; 615 } 616 617 static int vc4_hdmi_connector_set_property(struct drm_connector *connector, 618 struct drm_connector_state *state, 619 struct drm_property *property, 620 uint64_t val) 621 { 622 struct drm_device *drm = connector->dev; 623 struct vc4_hdmi *vc4_hdmi = 624 connector_to_vc4_hdmi(connector); 625 struct vc4_hdmi_connector_state *vc4_conn_state = 626 conn_state_to_vc4_hdmi_conn_state(state); 627 628 if (property == vc4_hdmi->broadcast_rgb_property) { 629 vc4_conn_state->broadcast_rgb = val; 630 return 0; 631 } 632 633 drm_dbg(drm, "Unknown property [PROP:%d:%s]\n", 634 property->base.id, property->name); 635 return -EINVAL; 636 } 637 638 static void vc4_hdmi_connector_reset(struct drm_connector *connector) 639 { 640 struct vc4_hdmi_connector_state *old_state = 641 conn_state_to_vc4_hdmi_conn_state(connector->state); 642 struct vc4_hdmi_connector_state *new_state = 643 kzalloc(sizeof(*new_state), GFP_KERNEL); 644 645 if (connector->state) 646 __drm_atomic_helper_connector_destroy_state(connector->state); 647 648 kfree(old_state); 649 __drm_atomic_helper_connector_reset(connector, &new_state->base); 650 651 if (!new_state) 652 return; 653 654 new_state->base.max_bpc = 8; 655 new_state->base.max_requested_bpc = 8; 656 new_state->output_format = VC4_HDMI_OUTPUT_RGB; 657 new_state->broadcast_rgb = VC4_HDMI_BROADCAST_RGB_AUTO; 658 drm_atomic_helper_connector_tv_margins_reset(connector); 659 } 660 661 static struct drm_connector_state * 662 vc4_hdmi_connector_duplicate_state(struct drm_connector *connector) 663 { 664 struct drm_connector_state *conn_state = connector->state; 665 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state); 666 struct vc4_hdmi_connector_state *new_state; 667 668 new_state = kzalloc(sizeof(*new_state), GFP_KERNEL); 669 if (!new_state) 670 return NULL; 671 672 new_state->tmds_char_rate = vc4_state->tmds_char_rate; 673 new_state->output_bpc = vc4_state->output_bpc; 674 new_state->output_format = vc4_state->output_format; 675 new_state->broadcast_rgb = vc4_state->broadcast_rgb; 676 __drm_atomic_helper_connector_duplicate_state(connector, &new_state->base); 677 678 return &new_state->base; 679 } 680 681 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = { 682 .fill_modes = drm_helper_probe_single_connector_modes, 683 .reset = vc4_hdmi_connector_reset, 684 .atomic_duplicate_state = vc4_hdmi_connector_duplicate_state, 685 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 686 .atomic_get_property = vc4_hdmi_connector_get_property, 687 .atomic_set_property = vc4_hdmi_connector_set_property, 688 }; 689 690 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = { 691 .detect_ctx = vc4_hdmi_connector_detect_ctx, 692 .get_modes = vc4_hdmi_connector_get_modes, 693 .atomic_check = vc4_hdmi_connector_atomic_check, 694 }; 695 696 static const struct drm_prop_enum_list broadcast_rgb_names[] = { 697 { VC4_HDMI_BROADCAST_RGB_AUTO, "Automatic" }, 698 { VC4_HDMI_BROADCAST_RGB_FULL, "Full" }, 699 { VC4_HDMI_BROADCAST_RGB_LIMITED, "Limited 16:235" }, 700 }; 701 702 static void 703 vc4_hdmi_attach_broadcast_rgb_property(struct drm_device *dev, 704 struct vc4_hdmi *vc4_hdmi) 705 { 706 struct drm_property *prop = vc4_hdmi->broadcast_rgb_property; 707 708 if (!prop) { 709 prop = drm_property_create_enum(dev, DRM_MODE_PROP_ENUM, 710 "Broadcast RGB", 711 broadcast_rgb_names, 712 ARRAY_SIZE(broadcast_rgb_names)); 713 if (!prop) 714 return; 715 716 vc4_hdmi->broadcast_rgb_property = prop; 717 } 718 719 drm_object_attach_property(&vc4_hdmi->connector.base, prop, 720 VC4_HDMI_BROADCAST_RGB_AUTO); 721 } 722 723 static int vc4_hdmi_connector_init(struct drm_device *dev, 724 struct vc4_hdmi *vc4_hdmi) 725 { 726 struct drm_connector *connector = &vc4_hdmi->connector; 727 struct drm_encoder *encoder = &vc4_hdmi->encoder.base; 728 int ret; 729 730 ret = drmm_connector_init(dev, connector, 731 &vc4_hdmi_connector_funcs, 732 DRM_MODE_CONNECTOR_HDMIA, 733 vc4_hdmi->ddc); 734 if (ret) 735 return ret; 736 737 drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs); 738 739 /* 740 * Some of the properties below require access to state, like bpc. 741 * Allocate some default initial connector state with our reset helper. 742 */ 743 if (connector->funcs->reset) 744 connector->funcs->reset(connector); 745 746 /* Create and attach TV margin props to this connector. */ 747 ret = drm_mode_create_tv_margin_properties(dev); 748 if (ret) 749 return ret; 750 751 ret = drm_mode_create_hdmi_colorspace_property(connector, 0); 752 if (ret) 753 return ret; 754 755 drm_connector_attach_colorspace_property(connector); 756 drm_connector_attach_tv_margin_properties(connector); 757 drm_connector_attach_max_bpc_property(connector, 8, 12); 758 759 connector->polled = (DRM_CONNECTOR_POLL_CONNECT | 760 DRM_CONNECTOR_POLL_DISCONNECT); 761 762 connector->interlace_allowed = 1; 763 connector->doublescan_allowed = 0; 764 connector->stereo_allowed = 1; 765 766 if (vc4_hdmi->variant->supports_hdr) 767 drm_connector_attach_hdr_output_metadata_property(connector); 768 769 vc4_hdmi_attach_broadcast_rgb_property(dev, vc4_hdmi); 770 771 drm_connector_attach_encoder(connector, encoder); 772 773 return 0; 774 } 775 776 static int vc4_hdmi_stop_packet(struct drm_encoder *encoder, 777 enum hdmi_infoframe_type type, 778 bool poll) 779 { 780 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 781 struct drm_device *drm = vc4_hdmi->connector.dev; 782 u32 packet_id = type - 0x80; 783 unsigned long flags; 784 int ret = 0; 785 int idx; 786 787 if (!drm_dev_enter(drm, &idx)) 788 return -ENODEV; 789 790 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 791 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 792 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & ~BIT(packet_id)); 793 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 794 795 if (poll) { 796 ret = wait_for(!(HDMI_READ(HDMI_RAM_PACKET_STATUS) & 797 BIT(packet_id)), 100); 798 } 799 800 drm_dev_exit(idx); 801 return ret; 802 } 803 804 static void vc4_hdmi_write_infoframe(struct drm_encoder *encoder, 805 union hdmi_infoframe *frame) 806 { 807 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 808 struct drm_device *drm = vc4_hdmi->connector.dev; 809 u32 packet_id = frame->any.type - 0x80; 810 const struct vc4_hdmi_register *ram_packet_start = 811 &vc4_hdmi->variant->registers[HDMI_RAM_PACKET_START]; 812 u32 packet_reg = ram_packet_start->offset + VC4_HDMI_PACKET_STRIDE * packet_id; 813 u32 packet_reg_next = ram_packet_start->offset + 814 VC4_HDMI_PACKET_STRIDE * (packet_id + 1); 815 void __iomem *base = __vc4_hdmi_get_field_base(vc4_hdmi, 816 ram_packet_start->reg); 817 uint8_t buffer[VC4_HDMI_PACKET_STRIDE] = {}; 818 unsigned long flags; 819 ssize_t len, i; 820 int ret; 821 int idx; 822 823 if (!drm_dev_enter(drm, &idx)) 824 return; 825 826 WARN_ONCE(!(HDMI_READ(HDMI_RAM_PACKET_CONFIG) & 827 VC4_HDMI_RAM_PACKET_ENABLE), 828 "Packet RAM has to be on to store the packet."); 829 830 len = hdmi_infoframe_pack(frame, buffer, sizeof(buffer)); 831 if (len < 0) 832 goto out; 833 834 ret = vc4_hdmi_stop_packet(encoder, frame->any.type, true); 835 if (ret) { 836 DRM_ERROR("Failed to wait for infoframe to go idle: %d\n", ret); 837 goto out; 838 } 839 840 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 841 842 for (i = 0; i < len; i += 7) { 843 writel(buffer[i + 0] << 0 | 844 buffer[i + 1] << 8 | 845 buffer[i + 2] << 16, 846 base + packet_reg); 847 packet_reg += 4; 848 849 writel(buffer[i + 3] << 0 | 850 buffer[i + 4] << 8 | 851 buffer[i + 5] << 16 | 852 buffer[i + 6] << 24, 853 base + packet_reg); 854 packet_reg += 4; 855 } 856 857 /* 858 * clear remainder of packet ram as it's included in the 859 * infoframe and triggers a checksum error on hdmi analyser 860 */ 861 for (; packet_reg < packet_reg_next; packet_reg += 4) 862 writel(0, base + packet_reg); 863 864 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 865 HDMI_READ(HDMI_RAM_PACKET_CONFIG) | BIT(packet_id)); 866 867 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 868 869 ret = wait_for((HDMI_READ(HDMI_RAM_PACKET_STATUS) & 870 BIT(packet_id)), 100); 871 if (ret) 872 DRM_ERROR("Failed to wait for infoframe to start: %d\n", ret); 873 874 out: 875 drm_dev_exit(idx); 876 } 877 878 static void vc4_hdmi_avi_infoframe_colorspace(struct hdmi_avi_infoframe *frame, 879 enum vc4_hdmi_output_format fmt) 880 { 881 switch (fmt) { 882 case VC4_HDMI_OUTPUT_RGB: 883 frame->colorspace = HDMI_COLORSPACE_RGB; 884 break; 885 886 case VC4_HDMI_OUTPUT_YUV420: 887 frame->colorspace = HDMI_COLORSPACE_YUV420; 888 break; 889 890 case VC4_HDMI_OUTPUT_YUV422: 891 frame->colorspace = HDMI_COLORSPACE_YUV422; 892 break; 893 894 case VC4_HDMI_OUTPUT_YUV444: 895 frame->colorspace = HDMI_COLORSPACE_YUV444; 896 break; 897 898 default: 899 break; 900 } 901 } 902 903 static void vc4_hdmi_set_avi_infoframe(struct drm_encoder *encoder) 904 { 905 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 906 struct drm_connector *connector = &vc4_hdmi->connector; 907 struct drm_connector_state *cstate = connector->state; 908 struct vc4_hdmi_connector_state *vc4_state = 909 conn_state_to_vc4_hdmi_conn_state(cstate); 910 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 911 union hdmi_infoframe frame; 912 int ret; 913 914 lockdep_assert_held(&vc4_hdmi->mutex); 915 916 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, 917 connector, mode); 918 if (ret < 0) { 919 DRM_ERROR("couldn't fill AVI infoframe\n"); 920 return; 921 } 922 923 drm_hdmi_avi_infoframe_quant_range(&frame.avi, 924 connector, mode, 925 vc4_hdmi_is_full_range(vc4_hdmi, vc4_state) ? 926 HDMI_QUANTIZATION_RANGE_FULL : 927 HDMI_QUANTIZATION_RANGE_LIMITED); 928 drm_hdmi_avi_infoframe_colorimetry(&frame.avi, cstate); 929 vc4_hdmi_avi_infoframe_colorspace(&frame.avi, vc4_state->output_format); 930 drm_hdmi_avi_infoframe_bars(&frame.avi, cstate); 931 932 vc4_hdmi_write_infoframe(encoder, &frame); 933 } 934 935 static void vc4_hdmi_set_spd_infoframe(struct drm_encoder *encoder) 936 { 937 union hdmi_infoframe frame; 938 int ret; 939 940 ret = hdmi_spd_infoframe_init(&frame.spd, "Broadcom", "Videocore"); 941 if (ret < 0) { 942 DRM_ERROR("couldn't fill SPD infoframe\n"); 943 return; 944 } 945 946 frame.spd.sdi = HDMI_SPD_SDI_PC; 947 948 vc4_hdmi_write_infoframe(encoder, &frame); 949 } 950 951 static void vc4_hdmi_set_audio_infoframe(struct drm_encoder *encoder) 952 { 953 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 954 struct hdmi_audio_infoframe *audio = &vc4_hdmi->audio.infoframe; 955 union hdmi_infoframe frame; 956 957 memcpy(&frame.audio, audio, sizeof(*audio)); 958 959 if (vc4_hdmi->packet_ram_enabled) 960 vc4_hdmi_write_infoframe(encoder, &frame); 961 } 962 963 static void vc4_hdmi_set_hdr_infoframe(struct drm_encoder *encoder) 964 { 965 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 966 struct drm_connector *connector = &vc4_hdmi->connector; 967 struct drm_connector_state *conn_state = connector->state; 968 union hdmi_infoframe frame; 969 970 lockdep_assert_held(&vc4_hdmi->mutex); 971 972 if (!vc4_hdmi->variant->supports_hdr) 973 return; 974 975 if (!conn_state->hdr_output_metadata) 976 return; 977 978 if (drm_hdmi_infoframe_set_hdr_metadata(&frame.drm, conn_state)) 979 return; 980 981 vc4_hdmi_write_infoframe(encoder, &frame); 982 } 983 984 static void vc4_hdmi_set_infoframes(struct drm_encoder *encoder) 985 { 986 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 987 988 lockdep_assert_held(&vc4_hdmi->mutex); 989 990 vc4_hdmi_set_avi_infoframe(encoder); 991 vc4_hdmi_set_spd_infoframe(encoder); 992 /* 993 * If audio was streaming, then we need to reenabled the audio 994 * infoframe here during encoder_enable. 995 */ 996 if (vc4_hdmi->audio.streaming) 997 vc4_hdmi_set_audio_infoframe(encoder); 998 999 vc4_hdmi_set_hdr_infoframe(encoder); 1000 } 1001 1002 #define SCRAMBLING_POLLING_DELAY_MS 1000 1003 1004 static void vc4_hdmi_enable_scrambling(struct drm_encoder *encoder) 1005 { 1006 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1007 struct drm_connector *connector = &vc4_hdmi->connector; 1008 struct drm_device *drm = connector->dev; 1009 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1010 unsigned long flags; 1011 int idx; 1012 1013 lockdep_assert_held(&vc4_hdmi->mutex); 1014 1015 if (!vc4_hdmi_supports_scrambling(vc4_hdmi)) 1016 return; 1017 1018 if (!vc4_hdmi_mode_needs_scrambling(mode, 1019 vc4_hdmi->output_bpc, 1020 vc4_hdmi->output_format)) 1021 return; 1022 1023 if (!drm_dev_enter(drm, &idx)) 1024 return; 1025 1026 drm_scdc_set_high_tmds_clock_ratio(connector, true); 1027 drm_scdc_set_scrambling(connector, true); 1028 1029 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1030 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) | 1031 VC5_HDMI_SCRAMBLER_CTL_ENABLE); 1032 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1033 1034 drm_dev_exit(idx); 1035 1036 vc4_hdmi->scdc_enabled = true; 1037 1038 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work, 1039 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS)); 1040 } 1041 1042 static void vc4_hdmi_disable_scrambling(struct drm_encoder *encoder) 1043 { 1044 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1045 struct drm_connector *connector = &vc4_hdmi->connector; 1046 struct drm_device *drm = connector->dev; 1047 unsigned long flags; 1048 int idx; 1049 1050 lockdep_assert_held(&vc4_hdmi->mutex); 1051 1052 if (!vc4_hdmi->scdc_enabled) 1053 return; 1054 1055 vc4_hdmi->scdc_enabled = false; 1056 1057 if (delayed_work_pending(&vc4_hdmi->scrambling_work)) 1058 cancel_delayed_work_sync(&vc4_hdmi->scrambling_work); 1059 1060 if (!drm_dev_enter(drm, &idx)) 1061 return; 1062 1063 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1064 HDMI_WRITE(HDMI_SCRAMBLER_CTL, HDMI_READ(HDMI_SCRAMBLER_CTL) & 1065 ~VC5_HDMI_SCRAMBLER_CTL_ENABLE); 1066 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1067 1068 drm_scdc_set_scrambling(connector, false); 1069 drm_scdc_set_high_tmds_clock_ratio(connector, false); 1070 1071 drm_dev_exit(idx); 1072 } 1073 1074 static void vc4_hdmi_scrambling_wq(struct work_struct *work) 1075 { 1076 struct vc4_hdmi *vc4_hdmi = container_of(to_delayed_work(work), 1077 struct vc4_hdmi, 1078 scrambling_work); 1079 struct drm_connector *connector = &vc4_hdmi->connector; 1080 1081 if (drm_scdc_get_scrambling_status(connector)) 1082 return; 1083 1084 drm_scdc_set_high_tmds_clock_ratio(connector, true); 1085 drm_scdc_set_scrambling(connector, true); 1086 1087 queue_delayed_work(system_wq, &vc4_hdmi->scrambling_work, 1088 msecs_to_jiffies(SCRAMBLING_POLLING_DELAY_MS)); 1089 } 1090 1091 static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder, 1092 struct drm_atomic_state *state) 1093 { 1094 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1095 struct drm_device *drm = vc4_hdmi->connector.dev; 1096 unsigned long flags; 1097 int idx; 1098 1099 mutex_lock(&vc4_hdmi->mutex); 1100 1101 vc4_hdmi->packet_ram_enabled = false; 1102 1103 if (!drm_dev_enter(drm, &idx)) 1104 goto out; 1105 1106 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1107 1108 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0); 1109 1110 HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_CLRRGB); 1111 1112 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1113 1114 mdelay(1); 1115 1116 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1117 HDMI_WRITE(HDMI_VID_CTL, 1118 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE); 1119 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1120 1121 vc4_hdmi_disable_scrambling(encoder); 1122 1123 drm_dev_exit(idx); 1124 1125 out: 1126 mutex_unlock(&vc4_hdmi->mutex); 1127 } 1128 1129 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder, 1130 struct drm_atomic_state *state) 1131 { 1132 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1133 struct drm_device *drm = vc4_hdmi->connector.dev; 1134 unsigned long flags; 1135 int ret; 1136 int idx; 1137 1138 mutex_lock(&vc4_hdmi->mutex); 1139 1140 if (!drm_dev_enter(drm, &idx)) 1141 goto out; 1142 1143 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1144 HDMI_WRITE(HDMI_VID_CTL, 1145 HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX); 1146 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1147 1148 if (vc4_hdmi->variant->phy_disable) 1149 vc4_hdmi->variant->phy_disable(vc4_hdmi); 1150 1151 clk_disable_unprepare(vc4_hdmi->pixel_bvb_clock); 1152 clk_disable_unprepare(vc4_hdmi->pixel_clock); 1153 1154 ret = pm_runtime_put(&vc4_hdmi->pdev->dev); 1155 if (ret < 0) 1156 DRM_ERROR("Failed to release power domain: %d\n", ret); 1157 1158 drm_dev_exit(idx); 1159 1160 out: 1161 mutex_unlock(&vc4_hdmi->mutex); 1162 } 1163 1164 static void vc4_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, 1165 struct drm_connector_state *state, 1166 const struct drm_display_mode *mode) 1167 { 1168 struct vc4_hdmi_connector_state *vc4_state = 1169 conn_state_to_vc4_hdmi_conn_state(state); 1170 struct drm_device *drm = vc4_hdmi->connector.dev; 1171 unsigned long flags; 1172 u32 csc_ctl; 1173 int idx; 1174 1175 if (!drm_dev_enter(drm, &idx)) 1176 return; 1177 1178 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1179 1180 csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR, 1181 VC4_HD_CSC_CTL_ORDER); 1182 1183 if (!vc4_hdmi_is_full_range(vc4_hdmi, vc4_state)) { 1184 /* CEA VICs other than #1 requre limited range RGB 1185 * output unless overridden by an AVI infoframe. 1186 * Apply a colorspace conversion to squash 0-255 down 1187 * to 16-235. The matrix here is: 1188 * 1189 * [ 0 0 0.8594 16] 1190 * [ 0 0.8594 0 16] 1191 * [ 0.8594 0 0 16] 1192 * [ 0 0 0 1] 1193 */ 1194 csc_ctl |= VC4_HD_CSC_CTL_ENABLE; 1195 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC; 1196 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM, 1197 VC4_HD_CSC_CTL_MODE); 1198 1199 HDMI_WRITE(HDMI_CSC_12_11, (0x000 << 16) | 0x000); 1200 HDMI_WRITE(HDMI_CSC_14_13, (0x100 << 16) | 0x6e0); 1201 HDMI_WRITE(HDMI_CSC_22_21, (0x6e0 << 16) | 0x000); 1202 HDMI_WRITE(HDMI_CSC_24_23, (0x100 << 16) | 0x000); 1203 HDMI_WRITE(HDMI_CSC_32_31, (0x000 << 16) | 0x6e0); 1204 HDMI_WRITE(HDMI_CSC_34_33, (0x100 << 16) | 0x000); 1205 } 1206 1207 /* The RGB order applies even when CSC is disabled. */ 1208 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl); 1209 1210 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1211 1212 drm_dev_exit(idx); 1213 } 1214 1215 /* 1216 * Matrices for (internal) RGB to RGB output. 1217 * 1218 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets 1219 */ 1220 static const u16 vc5_hdmi_csc_full_rgb_to_rgb[2][3][4] = { 1221 { 1222 /* 1223 * Full range - unity 1224 * 1225 * [ 1 0 0 0] 1226 * [ 0 1 0 0] 1227 * [ 0 0 1 0] 1228 */ 1229 { 0x2000, 0x0000, 0x0000, 0x0000 }, 1230 { 0x0000, 0x2000, 0x0000, 0x0000 }, 1231 { 0x0000, 0x0000, 0x2000, 0x0000 }, 1232 }, 1233 { 1234 /* 1235 * Limited range 1236 * 1237 * CEA VICs other than #1 require limited range RGB 1238 * output unless overridden by an AVI infoframe. Apply a 1239 * colorspace conversion to squash 0-255 down to 16-235. 1240 * The matrix here is: 1241 * 1242 * [ 0.8594 0 0 16] 1243 * [ 0 0.8594 0 16] 1244 * [ 0 0 0.8594 16] 1245 */ 1246 { 0x1b80, 0x0000, 0x0000, 0x0400 }, 1247 { 0x0000, 0x1b80, 0x0000, 0x0400 }, 1248 { 0x0000, 0x0000, 0x1b80, 0x0400 }, 1249 }, 1250 }; 1251 1252 /* 1253 * Conversion between Full Range RGB and YUV using the BT.601 Colorspace 1254 * 1255 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets 1256 */ 1257 static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt601[2][3][4] = { 1258 { 1259 /* 1260 * Full Range 1261 * 1262 * [ 0.299000 0.587000 0.114000 0 ] 1263 * [ -0.168736 -0.331264 0.500000 128 ] 1264 * [ 0.500000 -0.418688 -0.081312 128 ] 1265 */ 1266 { 0x0991, 0x12c9, 0x03a6, 0x0000 }, 1267 { 0xfa9b, 0xf567, 0x1000, 0x2000 }, 1268 { 0x1000, 0xf29b, 0xfd67, 0x2000 }, 1269 }, 1270 { 1271 /* Limited Range 1272 * 1273 * [ 0.255785 0.502160 0.097523 16 ] 1274 * [ -0.147644 -0.289856 0.437500 128 ] 1275 * [ 0.437500 -0.366352 -0.071148 128 ] 1276 */ 1277 { 0x082f, 0x1012, 0x031f, 0x0400 }, 1278 { 0xfb48, 0xf6ba, 0x0e00, 0x2000 }, 1279 { 0x0e00, 0xf448, 0xfdba, 0x2000 }, 1280 }, 1281 }; 1282 1283 /* 1284 * Conversion between Full Range RGB and YUV using the BT.709 Colorspace 1285 * 1286 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets 1287 */ 1288 static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt709[2][3][4] = { 1289 { 1290 /* 1291 * Full Range 1292 * 1293 * [ 0.212600 0.715200 0.072200 0 ] 1294 * [ -0.114572 -0.385428 0.500000 128 ] 1295 * [ 0.500000 -0.454153 -0.045847 128 ] 1296 */ 1297 { 0x06ce, 0x16e3, 0x024f, 0x0000 }, 1298 { 0xfc56, 0xf3ac, 0x1000, 0x2000 }, 1299 { 0x1000, 0xf179, 0xfe89, 0x2000 }, 1300 }, 1301 { 1302 /* 1303 * Limited Range 1304 * 1305 * [ 0.181906 0.611804 0.061758 16 ] 1306 * [ -0.100268 -0.337232 0.437500 128 ] 1307 * [ 0.437500 -0.397386 -0.040114 128 ] 1308 */ 1309 { 0x05d2, 0x1394, 0x01fa, 0x0400 }, 1310 { 0xfccc, 0xf536, 0x0e00, 0x2000 }, 1311 { 0x0e00, 0xf34a, 0xfeb8, 0x2000 }, 1312 }, 1313 }; 1314 1315 /* 1316 * Conversion between Full Range RGB and YUV using the BT.2020 Colorspace 1317 * 1318 * Matrices are signed 2p13 fixed point, with signed 9p6 offsets 1319 */ 1320 static const u16 vc5_hdmi_csc_full_rgb_to_yuv_bt2020[2][3][4] = { 1321 { 1322 /* 1323 * Full Range 1324 * 1325 * [ 0.262700 0.678000 0.059300 0 ] 1326 * [ -0.139630 -0.360370 0.500000 128 ] 1327 * [ 0.500000 -0.459786 -0.040214 128 ] 1328 */ 1329 { 0x0868, 0x15b2, 0x01e6, 0x0000 }, 1330 { 0xfb89, 0xf479, 0x1000, 0x2000 }, 1331 { 0x1000, 0xf14a, 0xfeb8, 0x2000 }, 1332 }, 1333 { 1334 /* Limited Range 1335 * 1336 * [ 0.224732 0.580008 0.050729 16 ] 1337 * [ -0.122176 -0.315324 0.437500 128 ] 1338 * [ 0.437500 -0.402312 -0.035188 128 ] 1339 */ 1340 { 0x082f, 0x1012, 0x031f, 0x0400 }, 1341 { 0xfb48, 0xf6ba, 0x0e00, 0x2000 }, 1342 { 0x0e00, 0xf448, 0xfdba, 0x2000 }, 1343 }, 1344 }; 1345 1346 static void vc5_hdmi_set_csc_coeffs(struct vc4_hdmi *vc4_hdmi, 1347 const u16 coeffs[3][4]) 1348 { 1349 lockdep_assert_held(&vc4_hdmi->hw_lock); 1350 1351 HDMI_WRITE(HDMI_CSC_12_11, (coeffs[0][1] << 16) | coeffs[0][0]); 1352 HDMI_WRITE(HDMI_CSC_14_13, (coeffs[0][3] << 16) | coeffs[0][2]); 1353 HDMI_WRITE(HDMI_CSC_22_21, (coeffs[1][1] << 16) | coeffs[1][0]); 1354 HDMI_WRITE(HDMI_CSC_24_23, (coeffs[1][3] << 16) | coeffs[1][2]); 1355 HDMI_WRITE(HDMI_CSC_32_31, (coeffs[2][1] << 16) | coeffs[2][0]); 1356 HDMI_WRITE(HDMI_CSC_34_33, (coeffs[2][3] << 16) | coeffs[2][2]); 1357 } 1358 1359 static void vc5_hdmi_set_csc_coeffs_swap(struct vc4_hdmi *vc4_hdmi, 1360 const u16 coeffs[3][4]) 1361 { 1362 lockdep_assert_held(&vc4_hdmi->hw_lock); 1363 1364 /* YUV444 needs the CSC matrices using the channels in a different order */ 1365 HDMI_WRITE(HDMI_CSC_12_11, (coeffs[1][1] << 16) | coeffs[1][0]); 1366 HDMI_WRITE(HDMI_CSC_14_13, (coeffs[1][3] << 16) | coeffs[1][2]); 1367 HDMI_WRITE(HDMI_CSC_22_21, (coeffs[2][1] << 16) | coeffs[2][0]); 1368 HDMI_WRITE(HDMI_CSC_24_23, (coeffs[2][3] << 16) | coeffs[2][2]); 1369 HDMI_WRITE(HDMI_CSC_32_31, (coeffs[0][1] << 16) | coeffs[0][0]); 1370 HDMI_WRITE(HDMI_CSC_34_33, (coeffs[0][3] << 16) | coeffs[0][2]); 1371 } 1372 1373 static const u16 1374 (*vc5_hdmi_find_yuv_csc_coeffs(struct vc4_hdmi *vc4_hdmi, u32 colorspace, bool limited))[4] 1375 { 1376 switch (colorspace) { 1377 case DRM_MODE_COLORIMETRY_SMPTE_170M_YCC: 1378 case DRM_MODE_COLORIMETRY_XVYCC_601: 1379 case DRM_MODE_COLORIMETRY_SYCC_601: 1380 case DRM_MODE_COLORIMETRY_OPYCC_601: 1381 case DRM_MODE_COLORIMETRY_BT601_YCC: 1382 return vc5_hdmi_csc_full_rgb_to_yuv_bt601[limited]; 1383 1384 default: 1385 case DRM_MODE_COLORIMETRY_NO_DATA: 1386 case DRM_MODE_COLORIMETRY_BT709_YCC: 1387 case DRM_MODE_COLORIMETRY_XVYCC_709: 1388 case DRM_MODE_COLORIMETRY_RGB_WIDE_FIXED: 1389 case DRM_MODE_COLORIMETRY_RGB_WIDE_FLOAT: 1390 return vc5_hdmi_csc_full_rgb_to_yuv_bt709[limited]; 1391 1392 case DRM_MODE_COLORIMETRY_BT2020_CYCC: 1393 case DRM_MODE_COLORIMETRY_BT2020_YCC: 1394 case DRM_MODE_COLORIMETRY_BT2020_RGB: 1395 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65: 1396 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER: 1397 return vc5_hdmi_csc_full_rgb_to_yuv_bt2020[limited]; 1398 } 1399 } 1400 1401 static void vc5_hdmi_csc_setup(struct vc4_hdmi *vc4_hdmi, 1402 struct drm_connector_state *state, 1403 const struct drm_display_mode *mode) 1404 { 1405 struct drm_device *drm = vc4_hdmi->connector.dev; 1406 struct vc4_hdmi_connector_state *vc4_state = 1407 conn_state_to_vc4_hdmi_conn_state(state); 1408 unsigned int lim_range = vc4_hdmi_is_full_range(vc4_hdmi, vc4_state) ? 0 : 1; 1409 unsigned long flags; 1410 const u16 (*csc)[4]; 1411 u32 if_cfg = 0; 1412 u32 if_xbar = 0x543210; 1413 u32 csc_chan_ctl = 0; 1414 u32 csc_ctl = VC5_MT_CP_CSC_CTL_ENABLE | VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM, 1415 VC5_MT_CP_CSC_CTL_MODE); 1416 int idx; 1417 1418 if (!drm_dev_enter(drm, &idx)) 1419 return; 1420 1421 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1422 1423 switch (vc4_state->output_format) { 1424 case VC4_HDMI_OUTPUT_YUV444: 1425 csc = vc5_hdmi_find_yuv_csc_coeffs(vc4_hdmi, state->colorspace, !!lim_range); 1426 1427 vc5_hdmi_set_csc_coeffs_swap(vc4_hdmi, csc); 1428 break; 1429 1430 case VC4_HDMI_OUTPUT_YUV422: 1431 csc = vc5_hdmi_find_yuv_csc_coeffs(vc4_hdmi, state->colorspace, !!lim_range); 1432 1433 csc_ctl |= VC4_SET_FIELD(VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422_STANDARD, 1434 VC5_MT_CP_CSC_CTL_FILTER_MODE_444_TO_422) | 1435 VC5_MT_CP_CSC_CTL_USE_444_TO_422 | 1436 VC5_MT_CP_CSC_CTL_USE_RNG_SUPPRESSION; 1437 1438 csc_chan_ctl |= VC4_SET_FIELD(VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP_LEGACY_STYLE, 1439 VC5_MT_CP_CHANNEL_CTL_OUTPUT_REMAP); 1440 1441 if_cfg |= VC4_SET_FIELD(VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422_FORMAT_422_LEGACY, 1442 VC5_DVP_HT_VEC_INTERFACE_CFG_SEL_422); 1443 1444 vc5_hdmi_set_csc_coeffs(vc4_hdmi, csc); 1445 break; 1446 1447 case VC4_HDMI_OUTPUT_RGB: 1448 if_xbar = 0x354021; 1449 1450 vc5_hdmi_set_csc_coeffs(vc4_hdmi, vc5_hdmi_csc_full_rgb_to_rgb[lim_range]); 1451 break; 1452 1453 default: 1454 break; 1455 } 1456 1457 HDMI_WRITE(HDMI_VEC_INTERFACE_CFG, if_cfg); 1458 HDMI_WRITE(HDMI_VEC_INTERFACE_XBAR, if_xbar); 1459 HDMI_WRITE(HDMI_CSC_CHANNEL_CTL, csc_chan_ctl); 1460 HDMI_WRITE(HDMI_CSC_CTL, csc_ctl); 1461 1462 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1463 1464 drm_dev_exit(idx); 1465 } 1466 1467 static void vc4_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi, 1468 struct drm_connector_state *state, 1469 const struct drm_display_mode *mode) 1470 { 1471 struct drm_device *drm = vc4_hdmi->connector.dev; 1472 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 1473 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 1474 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 1475 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 1476 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 1477 VC4_HDMI_VERTA_VSP) | 1478 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 1479 VC4_HDMI_VERTA_VFP) | 1480 VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL)); 1481 u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 1482 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end + 1483 interlaced, 1484 VC4_HDMI_VERTB_VBP)); 1485 u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) | 1486 VC4_SET_FIELD(mode->crtc_vtotal - 1487 mode->crtc_vsync_end, 1488 VC4_HDMI_VERTB_VBP)); 1489 unsigned long flags; 1490 u32 reg; 1491 int idx; 1492 1493 if (!drm_dev_enter(drm, &idx)) 1494 return; 1495 1496 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1497 1498 HDMI_WRITE(HDMI_HORZA, 1499 (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) | 1500 (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) | 1501 VC4_SET_FIELD(mode->hdisplay * pixel_rep, 1502 VC4_HDMI_HORZA_HAP)); 1503 1504 HDMI_WRITE(HDMI_HORZB, 1505 VC4_SET_FIELD((mode->htotal - 1506 mode->hsync_end) * pixel_rep, 1507 VC4_HDMI_HORZB_HBP) | 1508 VC4_SET_FIELD((mode->hsync_end - 1509 mode->hsync_start) * pixel_rep, 1510 VC4_HDMI_HORZB_HSP) | 1511 VC4_SET_FIELD((mode->hsync_start - 1512 mode->hdisplay) * pixel_rep, 1513 VC4_HDMI_HORZB_HFP)); 1514 1515 HDMI_WRITE(HDMI_VERTA0, verta); 1516 HDMI_WRITE(HDMI_VERTA1, verta); 1517 1518 HDMI_WRITE(HDMI_VERTB0, vertb_even); 1519 HDMI_WRITE(HDMI_VERTB1, vertb); 1520 1521 reg = HDMI_READ(HDMI_MISC_CONTROL); 1522 reg &= ~VC4_HDMI_MISC_CONTROL_PIXEL_REP_MASK; 1523 reg |= VC4_SET_FIELD(pixel_rep - 1, VC4_HDMI_MISC_CONTROL_PIXEL_REP); 1524 HDMI_WRITE(HDMI_MISC_CONTROL, reg); 1525 1526 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1527 1528 drm_dev_exit(idx); 1529 } 1530 1531 static void vc5_hdmi_set_timings(struct vc4_hdmi *vc4_hdmi, 1532 struct drm_connector_state *state, 1533 const struct drm_display_mode *mode) 1534 { 1535 struct drm_device *drm = vc4_hdmi->connector.dev; 1536 const struct vc4_hdmi_connector_state *vc4_state = 1537 conn_state_to_vc4_hdmi_conn_state(state); 1538 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 1539 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 1540 bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 1541 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 1542 u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 1543 VC5_HDMI_VERTA_VSP) | 1544 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 1545 VC5_HDMI_VERTA_VFP) | 1546 VC4_SET_FIELD(mode->crtc_vdisplay, VC5_HDMI_VERTA_VAL)); 1547 u32 vertb = (VC4_SET_FIELD(mode->htotal >> (2 - pixel_rep), 1548 VC5_HDMI_VERTB_VSPO) | 1549 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end + 1550 interlaced, 1551 VC4_HDMI_VERTB_VBP)); 1552 u32 vertb_even = (VC4_SET_FIELD(0, VC5_HDMI_VERTB_VSPO) | 1553 VC4_SET_FIELD(mode->crtc_vtotal - 1554 mode->crtc_vsync_end, 1555 VC4_HDMI_VERTB_VBP)); 1556 unsigned long flags; 1557 unsigned char gcp; 1558 u32 reg; 1559 int idx; 1560 1561 if (!drm_dev_enter(drm, &idx)) 1562 return; 1563 1564 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1565 1566 HDMI_WRITE(HDMI_HORZA, 1567 (vsync_pos ? VC5_HDMI_HORZA_VPOS : 0) | 1568 (hsync_pos ? VC5_HDMI_HORZA_HPOS : 0) | 1569 VC4_SET_FIELD(mode->hdisplay * pixel_rep, 1570 VC5_HDMI_HORZA_HAP) | 1571 VC4_SET_FIELD((mode->hsync_start - 1572 mode->hdisplay) * pixel_rep, 1573 VC5_HDMI_HORZA_HFP)); 1574 1575 HDMI_WRITE(HDMI_HORZB, 1576 VC4_SET_FIELD((mode->htotal - 1577 mode->hsync_end) * pixel_rep, 1578 VC5_HDMI_HORZB_HBP) | 1579 VC4_SET_FIELD((mode->hsync_end - 1580 mode->hsync_start) * pixel_rep, 1581 VC5_HDMI_HORZB_HSP)); 1582 1583 HDMI_WRITE(HDMI_VERTA0, verta); 1584 HDMI_WRITE(HDMI_VERTA1, verta); 1585 1586 HDMI_WRITE(HDMI_VERTB0, vertb_even); 1587 HDMI_WRITE(HDMI_VERTB1, vertb); 1588 1589 switch (vc4_state->output_bpc) { 1590 case 12: 1591 gcp = 6; 1592 break; 1593 case 10: 1594 gcp = 5; 1595 break; 1596 case 8: 1597 default: 1598 gcp = 0; 1599 break; 1600 } 1601 1602 /* 1603 * YCC422 is always 36-bit and not considered deep colour so 1604 * doesn't signal in GCP. 1605 */ 1606 if (vc4_state->output_format == VC4_HDMI_OUTPUT_YUV422) { 1607 gcp = 0; 1608 } 1609 1610 reg = HDMI_READ(HDMI_DEEP_COLOR_CONFIG_1); 1611 reg &= ~(VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE_MASK | 1612 VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH_MASK); 1613 reg |= VC4_SET_FIELD(2, VC5_HDMI_DEEP_COLOR_CONFIG_1_INIT_PACK_PHASE) | 1614 VC4_SET_FIELD(gcp, VC5_HDMI_DEEP_COLOR_CONFIG_1_COLOR_DEPTH); 1615 HDMI_WRITE(HDMI_DEEP_COLOR_CONFIG_1, reg); 1616 1617 reg = HDMI_READ(HDMI_GCP_WORD_1); 1618 reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1_MASK; 1619 reg |= VC4_SET_FIELD(gcp, VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_1); 1620 reg &= ~VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_MASK; 1621 reg |= VC5_HDMI_GCP_WORD_1_GCP_SUBPACKET_BYTE_0_CLEAR_AVMUTE; 1622 HDMI_WRITE(HDMI_GCP_WORD_1, reg); 1623 1624 reg = HDMI_READ(HDMI_GCP_CONFIG); 1625 reg |= VC5_HDMI_GCP_CONFIG_GCP_ENABLE; 1626 HDMI_WRITE(HDMI_GCP_CONFIG, reg); 1627 1628 reg = HDMI_READ(HDMI_MISC_CONTROL); 1629 reg &= ~VC5_HDMI_MISC_CONTROL_PIXEL_REP_MASK; 1630 reg |= VC4_SET_FIELD(pixel_rep - 1, VC5_HDMI_MISC_CONTROL_PIXEL_REP); 1631 HDMI_WRITE(HDMI_MISC_CONTROL, reg); 1632 1633 HDMI_WRITE(HDMI_CLOCK_STOP, 0); 1634 1635 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1636 1637 drm_dev_exit(idx); 1638 } 1639 1640 static void vc4_hdmi_recenter_fifo(struct vc4_hdmi *vc4_hdmi) 1641 { 1642 struct drm_device *drm = vc4_hdmi->connector.dev; 1643 unsigned long flags; 1644 u32 drift; 1645 int ret; 1646 int idx; 1647 1648 if (!drm_dev_enter(drm, &idx)) 1649 return; 1650 1651 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1652 1653 drift = HDMI_READ(HDMI_FIFO_CTL); 1654 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK; 1655 1656 HDMI_WRITE(HDMI_FIFO_CTL, 1657 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 1658 HDMI_WRITE(HDMI_FIFO_CTL, 1659 drift | VC4_HDMI_FIFO_CTL_RECENTER); 1660 1661 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1662 1663 usleep_range(1000, 1100); 1664 1665 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1666 1667 HDMI_WRITE(HDMI_FIFO_CTL, 1668 drift & ~VC4_HDMI_FIFO_CTL_RECENTER); 1669 HDMI_WRITE(HDMI_FIFO_CTL, 1670 drift | VC4_HDMI_FIFO_CTL_RECENTER); 1671 1672 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1673 1674 ret = wait_for(HDMI_READ(HDMI_FIFO_CTL) & 1675 VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1); 1676 WARN_ONCE(ret, "Timeout waiting for " 1677 "VC4_HDMI_FIFO_CTL_RECENTER_DONE"); 1678 1679 drm_dev_exit(idx); 1680 } 1681 1682 static void vc4_hdmi_encoder_pre_crtc_configure(struct drm_encoder *encoder, 1683 struct drm_atomic_state *state) 1684 { 1685 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1686 struct drm_device *drm = vc4_hdmi->connector.dev; 1687 struct drm_connector *connector = &vc4_hdmi->connector; 1688 struct drm_connector_state *conn_state = 1689 drm_atomic_get_new_connector_state(state, connector); 1690 struct vc4_hdmi_connector_state *vc4_conn_state = 1691 conn_state_to_vc4_hdmi_conn_state(conn_state); 1692 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1693 unsigned long tmds_char_rate = vc4_conn_state->tmds_char_rate; 1694 unsigned long bvb_rate, hsm_rate; 1695 unsigned long flags; 1696 int ret; 1697 int idx; 1698 1699 mutex_lock(&vc4_hdmi->mutex); 1700 1701 if (!drm_dev_enter(drm, &idx)) 1702 goto out; 1703 1704 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev); 1705 if (ret < 0) { 1706 DRM_ERROR("Failed to retain power domain: %d\n", ret); 1707 goto err_dev_exit; 1708 } 1709 1710 /* 1711 * As stated in RPi's vc4 firmware "HDMI state machine (HSM) clock must 1712 * be faster than pixel clock, infinitesimally faster, tested in 1713 * simulation. Otherwise, exact value is unimportant for HDMI 1714 * operation." This conflicts with bcm2835's vc4 documentation, which 1715 * states HSM's clock has to be at least 108% of the pixel clock. 1716 * 1717 * Real life tests reveal that vc4's firmware statement holds up, and 1718 * users are able to use pixel clocks closer to HSM's, namely for 1719 * 1920x1200@60Hz. So it was decided to have leave a 1% margin between 1720 * both clocks. Which, for RPi0-3 implies a maximum pixel clock of 1721 * 162MHz. 1722 * 1723 * Additionally, the AXI clock needs to be at least 25% of 1724 * pixel clock, but HSM ends up being the limiting factor. 1725 */ 1726 hsm_rate = max_t(unsigned long, 1727 HSM_MIN_CLOCK_FREQ, 1728 (tmds_char_rate / 100) * 101); 1729 ret = clk_set_min_rate(vc4_hdmi->hsm_clock, hsm_rate); 1730 if (ret) { 1731 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret); 1732 goto err_put_runtime_pm; 1733 } 1734 1735 ret = clk_set_rate(vc4_hdmi->pixel_clock, tmds_char_rate); 1736 if (ret) { 1737 DRM_ERROR("Failed to set pixel clock rate: %d\n", ret); 1738 goto err_put_runtime_pm; 1739 } 1740 1741 ret = clk_prepare_enable(vc4_hdmi->pixel_clock); 1742 if (ret) { 1743 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret); 1744 goto err_put_runtime_pm; 1745 } 1746 1747 1748 vc4_hdmi_cec_update_clk_div(vc4_hdmi); 1749 1750 if (tmds_char_rate > 297000000) 1751 bvb_rate = 300000000; 1752 else if (tmds_char_rate > 148500000) 1753 bvb_rate = 150000000; 1754 else 1755 bvb_rate = 75000000; 1756 1757 ret = clk_set_min_rate(vc4_hdmi->pixel_bvb_clock, bvb_rate); 1758 if (ret) { 1759 DRM_ERROR("Failed to set pixel bvb clock rate: %d\n", ret); 1760 goto err_disable_pixel_clock; 1761 } 1762 1763 ret = clk_prepare_enable(vc4_hdmi->pixel_bvb_clock); 1764 if (ret) { 1765 DRM_ERROR("Failed to turn on pixel bvb clock: %d\n", ret); 1766 goto err_disable_pixel_clock; 1767 } 1768 1769 if (vc4_hdmi->variant->phy_init) 1770 vc4_hdmi->variant->phy_init(vc4_hdmi, vc4_conn_state); 1771 1772 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1773 1774 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1775 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 1776 VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT | 1777 VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS); 1778 1779 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1780 1781 if (vc4_hdmi->variant->set_timings) 1782 vc4_hdmi->variant->set_timings(vc4_hdmi, conn_state, mode); 1783 1784 drm_dev_exit(idx); 1785 1786 mutex_unlock(&vc4_hdmi->mutex); 1787 1788 return; 1789 1790 err_disable_pixel_clock: 1791 clk_disable_unprepare(vc4_hdmi->pixel_clock); 1792 err_put_runtime_pm: 1793 pm_runtime_put(&vc4_hdmi->pdev->dev); 1794 err_dev_exit: 1795 drm_dev_exit(idx); 1796 out: 1797 mutex_unlock(&vc4_hdmi->mutex); 1798 return; 1799 } 1800 1801 static void vc4_hdmi_encoder_pre_crtc_enable(struct drm_encoder *encoder, 1802 struct drm_atomic_state *state) 1803 { 1804 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1805 struct drm_device *drm = vc4_hdmi->connector.dev; 1806 struct drm_connector *connector = &vc4_hdmi->connector; 1807 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1808 struct drm_connector_state *conn_state = 1809 drm_atomic_get_new_connector_state(state, connector); 1810 unsigned long flags; 1811 int idx; 1812 1813 mutex_lock(&vc4_hdmi->mutex); 1814 1815 if (!drm_dev_enter(drm, &idx)) 1816 goto out; 1817 1818 if (vc4_hdmi->variant->csc_setup) 1819 vc4_hdmi->variant->csc_setup(vc4_hdmi, conn_state, mode); 1820 1821 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1822 HDMI_WRITE(HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N); 1823 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1824 1825 drm_dev_exit(idx); 1826 1827 out: 1828 mutex_unlock(&vc4_hdmi->mutex); 1829 } 1830 1831 static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder, 1832 struct drm_atomic_state *state) 1833 { 1834 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1835 struct drm_device *drm = vc4_hdmi->connector.dev; 1836 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 1837 struct drm_display_info *display = &vc4_hdmi->connector.display_info; 1838 bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC; 1839 bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC; 1840 unsigned long flags; 1841 int ret; 1842 int idx; 1843 1844 mutex_lock(&vc4_hdmi->mutex); 1845 1846 if (!drm_dev_enter(drm, &idx)) 1847 goto out; 1848 1849 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1850 1851 HDMI_WRITE(HDMI_VID_CTL, 1852 VC4_HD_VID_CTL_ENABLE | 1853 VC4_HD_VID_CTL_CLRRGB | 1854 VC4_HD_VID_CTL_UNDERFLOW_ENABLE | 1855 VC4_HD_VID_CTL_FRAME_COUNTER_RESET | 1856 (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) | 1857 (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW)); 1858 1859 HDMI_WRITE(HDMI_VID_CTL, 1860 HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX); 1861 1862 if (display->is_hdmi) { 1863 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1864 HDMI_READ(HDMI_SCHEDULER_CONTROL) | 1865 VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 1866 1867 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1868 1869 ret = wait_for(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1870 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1000); 1871 WARN_ONCE(ret, "Timeout waiting for " 1872 "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 1873 } else { 1874 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 1875 HDMI_READ(HDMI_RAM_PACKET_CONFIG) & 1876 ~(VC4_HDMI_RAM_PACKET_ENABLE)); 1877 HDMI_WRITE(HDMI_SCHEDULER_CONTROL, 1878 HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1879 ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI); 1880 1881 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1882 1883 ret = wait_for(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1884 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1000); 1885 WARN_ONCE(ret, "Timeout waiting for " 1886 "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n"); 1887 } 1888 1889 if (display->is_hdmi) { 1890 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 1891 1892 WARN_ON(!(HDMI_READ(HDMI_SCHEDULER_CONTROL) & 1893 VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE)); 1894 1895 HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 1896 VC4_HDMI_RAM_PACKET_ENABLE); 1897 1898 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 1899 vc4_hdmi->packet_ram_enabled = true; 1900 1901 vc4_hdmi_set_infoframes(encoder); 1902 } 1903 1904 vc4_hdmi_recenter_fifo(vc4_hdmi); 1905 vc4_hdmi_enable_scrambling(encoder); 1906 1907 drm_dev_exit(idx); 1908 1909 out: 1910 mutex_unlock(&vc4_hdmi->mutex); 1911 } 1912 1913 static void vc4_hdmi_encoder_atomic_mode_set(struct drm_encoder *encoder, 1914 struct drm_crtc_state *crtc_state, 1915 struct drm_connector_state *conn_state) 1916 { 1917 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 1918 struct vc4_hdmi_connector_state *vc4_state = 1919 conn_state_to_vc4_hdmi_conn_state(conn_state); 1920 1921 mutex_lock(&vc4_hdmi->mutex); 1922 drm_mode_copy(&vc4_hdmi->saved_adjusted_mode, 1923 &crtc_state->adjusted_mode); 1924 vc4_hdmi->output_bpc = vc4_state->output_bpc; 1925 vc4_hdmi->output_format = vc4_state->output_format; 1926 mutex_unlock(&vc4_hdmi->mutex); 1927 } 1928 1929 static bool 1930 vc4_hdmi_sink_supports_format_bpc(const struct vc4_hdmi *vc4_hdmi, 1931 const struct drm_display_info *info, 1932 const struct drm_display_mode *mode, 1933 unsigned int format, unsigned int bpc) 1934 { 1935 struct drm_device *dev = vc4_hdmi->connector.dev; 1936 u8 vic = drm_match_cea_mode(mode); 1937 1938 if (vic == 1 && bpc != 8) { 1939 drm_dbg(dev, "VIC1 requires a bpc of 8, got %u\n", bpc); 1940 return false; 1941 } 1942 1943 if (!info->is_hdmi && 1944 (format != VC4_HDMI_OUTPUT_RGB || bpc != 8)) { 1945 drm_dbg(dev, "DVI Monitors require an RGB output at 8 bpc\n"); 1946 return false; 1947 } 1948 1949 switch (format) { 1950 case VC4_HDMI_OUTPUT_RGB: 1951 drm_dbg(dev, "RGB Format, checking the constraints.\n"); 1952 1953 if (!(info->color_formats & DRM_COLOR_FORMAT_RGB444)) 1954 return false; 1955 1956 if (bpc == 10 && !(info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30)) { 1957 drm_dbg(dev, "10 BPC but sink doesn't support Deep Color 30.\n"); 1958 return false; 1959 } 1960 1961 if (bpc == 12 && !(info->edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_36)) { 1962 drm_dbg(dev, "12 BPC but sink doesn't support Deep Color 36.\n"); 1963 return false; 1964 } 1965 1966 drm_dbg(dev, "RGB format supported in that configuration.\n"); 1967 1968 return true; 1969 1970 case VC4_HDMI_OUTPUT_YUV422: 1971 drm_dbg(dev, "YUV422 format, checking the constraints.\n"); 1972 1973 if (!(info->color_formats & DRM_COLOR_FORMAT_YCBCR422)) { 1974 drm_dbg(dev, "Sink doesn't support YUV422.\n"); 1975 return false; 1976 } 1977 1978 if (bpc != 12) { 1979 drm_dbg(dev, "YUV422 only supports 12 bpc.\n"); 1980 return false; 1981 } 1982 1983 drm_dbg(dev, "YUV422 format supported in that configuration.\n"); 1984 1985 return true; 1986 1987 case VC4_HDMI_OUTPUT_YUV444: 1988 drm_dbg(dev, "YUV444 format, checking the constraints.\n"); 1989 1990 if (!(info->color_formats & DRM_COLOR_FORMAT_YCBCR444)) { 1991 drm_dbg(dev, "Sink doesn't support YUV444.\n"); 1992 return false; 1993 } 1994 1995 if (bpc == 10 && !(info->edid_hdmi_ycbcr444_dc_modes & DRM_EDID_HDMI_DC_30)) { 1996 drm_dbg(dev, "10 BPC but sink doesn't support Deep Color 30.\n"); 1997 return false; 1998 } 1999 2000 if (bpc == 12 && !(info->edid_hdmi_ycbcr444_dc_modes & DRM_EDID_HDMI_DC_36)) { 2001 drm_dbg(dev, "12 BPC but sink doesn't support Deep Color 36.\n"); 2002 return false; 2003 } 2004 2005 drm_dbg(dev, "YUV444 format supported in that configuration.\n"); 2006 2007 return true; 2008 } 2009 2010 return false; 2011 } 2012 2013 static enum drm_mode_status 2014 vc4_hdmi_encoder_clock_valid(const struct vc4_hdmi *vc4_hdmi, 2015 const struct drm_display_mode *mode, 2016 unsigned long long clock) 2017 { 2018 const struct drm_connector *connector = &vc4_hdmi->connector; 2019 const struct drm_display_info *info = &connector->display_info; 2020 struct vc4_dev *vc4 = to_vc4_dev(connector->dev); 2021 2022 if (clock > vc4_hdmi->variant->max_pixel_clock) 2023 return MODE_CLOCK_HIGH; 2024 2025 if (!vc4->hvs->vc5_hdmi_enable_hdmi_20 && clock > HDMI_14_MAX_TMDS_CLK) 2026 return MODE_CLOCK_HIGH; 2027 2028 /* 4096x2160@60 is not reliable without overclocking core */ 2029 if (!vc4->hvs->vc5_hdmi_enable_4096by2160 && 2030 mode->hdisplay > 3840 && mode->vdisplay >= 2160 && 2031 drm_mode_vrefresh(mode) >= 50) 2032 return MODE_CLOCK_HIGH; 2033 2034 if (info->max_tmds_clock && clock > (info->max_tmds_clock * 1000)) 2035 return MODE_CLOCK_HIGH; 2036 2037 return MODE_OK; 2038 } 2039 2040 static unsigned long long 2041 vc4_hdmi_encoder_compute_mode_clock(const struct drm_display_mode *mode, 2042 unsigned int bpc, 2043 enum vc4_hdmi_output_format fmt) 2044 { 2045 unsigned long long clock = mode->clock * 1000ULL; 2046 2047 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 2048 clock = clock * 2; 2049 2050 if (fmt == VC4_HDMI_OUTPUT_YUV422) 2051 bpc = 8; 2052 2053 clock = clock * bpc; 2054 do_div(clock, 8); 2055 2056 return clock; 2057 } 2058 2059 static int 2060 vc4_hdmi_encoder_compute_clock(const struct vc4_hdmi *vc4_hdmi, 2061 struct vc4_hdmi_connector_state *vc4_state, 2062 const struct drm_display_mode *mode, 2063 unsigned int bpc, unsigned int fmt) 2064 { 2065 unsigned long long clock; 2066 2067 clock = vc4_hdmi_encoder_compute_mode_clock(mode, bpc, fmt); 2068 if (vc4_hdmi_encoder_clock_valid(vc4_hdmi, mode, clock) != MODE_OK) 2069 return -EINVAL; 2070 2071 vc4_state->tmds_char_rate = clock; 2072 2073 return 0; 2074 } 2075 2076 static int 2077 vc4_hdmi_encoder_compute_format(const struct vc4_hdmi *vc4_hdmi, 2078 struct vc4_hdmi_connector_state *vc4_state, 2079 const struct drm_display_mode *mode, 2080 unsigned int bpc) 2081 { 2082 struct drm_device *dev = vc4_hdmi->connector.dev; 2083 const struct drm_connector *connector = &vc4_hdmi->connector; 2084 const struct drm_display_info *info = &connector->display_info; 2085 unsigned int format; 2086 2087 drm_dbg(dev, "Trying with an RGB output\n"); 2088 2089 format = VC4_HDMI_OUTPUT_RGB; 2090 if (vc4_hdmi_sink_supports_format_bpc(vc4_hdmi, info, mode, format, bpc)) { 2091 int ret; 2092 2093 ret = vc4_hdmi_encoder_compute_clock(vc4_hdmi, vc4_state, 2094 mode, bpc, format); 2095 if (!ret) { 2096 vc4_state->output_format = format; 2097 return 0; 2098 } 2099 } 2100 2101 drm_dbg(dev, "Failed, Trying with an YUV422 output\n"); 2102 2103 format = VC4_HDMI_OUTPUT_YUV422; 2104 if (vc4_hdmi_sink_supports_format_bpc(vc4_hdmi, info, mode, format, bpc)) { 2105 int ret; 2106 2107 ret = vc4_hdmi_encoder_compute_clock(vc4_hdmi, vc4_state, 2108 mode, bpc, format); 2109 if (!ret) { 2110 vc4_state->output_format = format; 2111 return 0; 2112 } 2113 } 2114 2115 drm_dbg(dev, "Failed. No Format Supported for that bpc count.\n"); 2116 2117 return -EINVAL; 2118 } 2119 2120 static int 2121 vc4_hdmi_encoder_compute_config(const struct vc4_hdmi *vc4_hdmi, 2122 struct vc4_hdmi_connector_state *vc4_state, 2123 const struct drm_display_mode *mode) 2124 { 2125 struct drm_device *dev = vc4_hdmi->connector.dev; 2126 struct drm_connector_state *conn_state = &vc4_state->base; 2127 unsigned int max_bpc = clamp_t(unsigned int, conn_state->max_bpc, 8, 12); 2128 unsigned int bpc; 2129 int ret; 2130 2131 for (bpc = max_bpc; bpc >= 8; bpc -= 2) { 2132 drm_dbg(dev, "Trying with a %d bpc output\n", bpc); 2133 2134 ret = vc4_hdmi_encoder_compute_format(vc4_hdmi, vc4_state, 2135 mode, bpc); 2136 if (ret) 2137 continue; 2138 2139 vc4_state->output_bpc = bpc; 2140 2141 drm_dbg(dev, 2142 "Mode %ux%u @ %uHz: Found configuration: bpc: %u, fmt: %s, clock: %llu\n", 2143 mode->hdisplay, mode->vdisplay, drm_mode_vrefresh(mode), 2144 vc4_state->output_bpc, 2145 vc4_hdmi_output_fmt_str(vc4_state->output_format), 2146 vc4_state->tmds_char_rate); 2147 2148 break; 2149 } 2150 2151 return ret; 2152 } 2153 2154 #define WIFI_2_4GHz_CH1_MIN_FREQ 2400000000ULL 2155 #define WIFI_2_4GHz_CH1_MAX_FREQ 2422000000ULL 2156 2157 static int vc4_hdmi_encoder_atomic_check(struct drm_encoder *encoder, 2158 struct drm_crtc_state *crtc_state, 2159 struct drm_connector_state *conn_state) 2160 { 2161 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 2162 struct drm_connector *connector = &vc4_hdmi->connector; 2163 struct drm_connector_state *old_conn_state = 2164 drm_atomic_get_old_connector_state(conn_state->state, connector); 2165 struct vc4_hdmi_connector_state *old_vc4_state = 2166 conn_state_to_vc4_hdmi_conn_state(old_conn_state); 2167 struct vc4_hdmi_connector_state *vc4_state = conn_state_to_vc4_hdmi_conn_state(conn_state); 2168 struct drm_display_mode *mode = &crtc_state->adjusted_mode; 2169 unsigned long long tmds_char_rate = mode->clock * 1000; 2170 unsigned long long tmds_bit_rate; 2171 int ret; 2172 2173 if (vc4_hdmi->variant->unsupported_odd_h_timings) { 2174 if (mode->flags & DRM_MODE_FLAG_DBLCLK) { 2175 /* Only try to fixup DBLCLK modes to get 480i and 576i 2176 * working. 2177 * A generic solution for all modes with odd horizontal 2178 * timing values seems impossible based on trying to 2179 * solve it for 1366x768 monitors. 2180 */ 2181 if ((mode->hsync_start - mode->hdisplay) & 1) 2182 mode->hsync_start--; 2183 if ((mode->hsync_end - mode->hsync_start) & 1) 2184 mode->hsync_end--; 2185 } 2186 2187 /* Now check whether we still have odd values remaining */ 2188 if ((mode->hdisplay % 2) || (mode->hsync_start % 2) || 2189 (mode->hsync_end % 2) || (mode->htotal % 2)) 2190 return -EINVAL; 2191 } 2192 2193 /* 2194 * The 1440p@60 pixel rate is in the same range than the first 2195 * WiFi channel (between 2.4GHz and 2.422GHz with 22MHz 2196 * bandwidth). Slightly lower the frequency to bring it out of 2197 * the WiFi range. 2198 */ 2199 tmds_bit_rate = tmds_char_rate * 10; 2200 if (vc4_hdmi->disable_wifi_frequencies && 2201 (tmds_bit_rate >= WIFI_2_4GHz_CH1_MIN_FREQ && 2202 tmds_bit_rate <= WIFI_2_4GHz_CH1_MAX_FREQ)) { 2203 mode->clock = 238560; 2204 tmds_char_rate = mode->clock * 1000; 2205 } 2206 2207 ret = vc4_hdmi_encoder_compute_config(vc4_hdmi, vc4_state, mode); 2208 if (ret) 2209 return ret; 2210 2211 /* vc4_hdmi_encoder_compute_config may have changed output_bpc and/or output_format */ 2212 if (vc4_state->output_bpc != old_vc4_state->output_bpc || 2213 vc4_state->output_format != old_vc4_state->output_format) 2214 crtc_state->mode_changed = true; 2215 2216 return 0; 2217 } 2218 2219 static enum drm_mode_status 2220 vc4_hdmi_encoder_mode_valid(struct drm_encoder *encoder, 2221 const struct drm_display_mode *mode) 2222 { 2223 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 2224 2225 if (vc4_hdmi->variant->unsupported_odd_h_timings && 2226 !(mode->flags & DRM_MODE_FLAG_DBLCLK) && 2227 ((mode->hdisplay % 2) || (mode->hsync_start % 2) || 2228 (mode->hsync_end % 2) || (mode->htotal % 2))) 2229 return MODE_H_ILLEGAL; 2230 2231 return vc4_hdmi_encoder_clock_valid(vc4_hdmi, mode, mode->clock * 1000); 2232 } 2233 2234 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = { 2235 .atomic_check = vc4_hdmi_encoder_atomic_check, 2236 .atomic_mode_set = vc4_hdmi_encoder_atomic_mode_set, 2237 .mode_valid = vc4_hdmi_encoder_mode_valid, 2238 }; 2239 2240 static int vc4_hdmi_late_register(struct drm_encoder *encoder) 2241 { 2242 struct drm_device *drm = encoder->dev; 2243 struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder); 2244 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant; 2245 2246 drm_debugfs_add_file(drm, variant->debugfs_name, 2247 vc4_hdmi_debugfs_regs, vc4_hdmi); 2248 2249 return 0; 2250 } 2251 2252 static const struct drm_encoder_funcs vc4_hdmi_encoder_funcs = { 2253 .late_register = vc4_hdmi_late_register, 2254 }; 2255 2256 static u32 vc4_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask) 2257 { 2258 int i; 2259 u32 channel_map = 0; 2260 2261 for (i = 0; i < 8; i++) { 2262 if (channel_mask & BIT(i)) 2263 channel_map |= i << (3 * i); 2264 } 2265 return channel_map; 2266 } 2267 2268 static u32 vc5_hdmi_channel_map(struct vc4_hdmi *vc4_hdmi, u32 channel_mask) 2269 { 2270 int i; 2271 u32 channel_map = 0; 2272 2273 for (i = 0; i < 8; i++) { 2274 if (channel_mask & BIT(i)) 2275 channel_map |= i << (4 * i); 2276 } 2277 return channel_map; 2278 } 2279 2280 static bool vc5_hdmi_hp_detect(struct vc4_hdmi *vc4_hdmi) 2281 { 2282 struct drm_device *drm = vc4_hdmi->connector.dev; 2283 unsigned long flags; 2284 u32 hotplug; 2285 int idx; 2286 2287 if (!drm_dev_enter(drm, &idx)) 2288 return false; 2289 2290 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2291 hotplug = HDMI_READ(HDMI_HOTPLUG); 2292 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2293 2294 drm_dev_exit(idx); 2295 2296 return !!(hotplug & VC4_HDMI_HOTPLUG_CONNECTED); 2297 } 2298 2299 /* HDMI audio codec callbacks */ 2300 static void vc4_hdmi_audio_set_mai_clock(struct vc4_hdmi *vc4_hdmi, 2301 unsigned int samplerate) 2302 { 2303 struct drm_device *drm = vc4_hdmi->connector.dev; 2304 u32 hsm_clock; 2305 unsigned long flags; 2306 unsigned long n, m; 2307 int idx; 2308 2309 if (!drm_dev_enter(drm, &idx)) 2310 return; 2311 2312 hsm_clock = clk_get_rate(vc4_hdmi->audio_clock); 2313 rational_best_approximation(hsm_clock, samplerate, 2314 VC4_HD_MAI_SMP_N_MASK >> 2315 VC4_HD_MAI_SMP_N_SHIFT, 2316 (VC4_HD_MAI_SMP_M_MASK >> 2317 VC4_HD_MAI_SMP_M_SHIFT) + 1, 2318 &n, &m); 2319 2320 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2321 HDMI_WRITE(HDMI_MAI_SMP, 2322 VC4_SET_FIELD(n, VC4_HD_MAI_SMP_N) | 2323 VC4_SET_FIELD(m - 1, VC4_HD_MAI_SMP_M)); 2324 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2325 2326 drm_dev_exit(idx); 2327 } 2328 2329 static void vc4_hdmi_set_n_cts(struct vc4_hdmi *vc4_hdmi, unsigned int samplerate) 2330 { 2331 const struct drm_display_mode *mode = &vc4_hdmi->saved_adjusted_mode; 2332 u32 n, cts; 2333 u64 tmp; 2334 2335 lockdep_assert_held(&vc4_hdmi->mutex); 2336 lockdep_assert_held(&vc4_hdmi->hw_lock); 2337 2338 n = 128 * samplerate / 1000; 2339 tmp = (u64)(mode->clock * 1000) * n; 2340 do_div(tmp, 128 * samplerate); 2341 cts = tmp; 2342 2343 HDMI_WRITE(HDMI_CRP_CFG, 2344 VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN | 2345 VC4_SET_FIELD(n, VC4_HDMI_CRP_CFG_N)); 2346 2347 /* 2348 * We could get slightly more accurate clocks in some cases by 2349 * providing a CTS_1 value. The two CTS values are alternated 2350 * between based on the period fields 2351 */ 2352 HDMI_WRITE(HDMI_CTS_0, cts); 2353 HDMI_WRITE(HDMI_CTS_1, cts); 2354 } 2355 2356 static inline struct vc4_hdmi *dai_to_hdmi(struct snd_soc_dai *dai) 2357 { 2358 struct snd_soc_card *card = snd_soc_dai_get_drvdata(dai); 2359 2360 return snd_soc_card_get_drvdata(card); 2361 } 2362 2363 static bool vc4_hdmi_audio_can_stream(struct vc4_hdmi *vc4_hdmi) 2364 { 2365 struct drm_display_info *display = &vc4_hdmi->connector.display_info; 2366 2367 lockdep_assert_held(&vc4_hdmi->mutex); 2368 2369 /* 2370 * If the encoder is currently in DVI mode, treat the codec DAI 2371 * as missing. 2372 */ 2373 if (!display->is_hdmi) 2374 return false; 2375 2376 return true; 2377 } 2378 2379 static int vc4_hdmi_audio_startup(struct device *dev, void *data) 2380 { 2381 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 2382 struct drm_device *drm = vc4_hdmi->connector.dev; 2383 unsigned long flags; 2384 int ret = 0; 2385 int idx; 2386 2387 mutex_lock(&vc4_hdmi->mutex); 2388 2389 if (!drm_dev_enter(drm, &idx)) { 2390 ret = -ENODEV; 2391 goto out; 2392 } 2393 2394 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) { 2395 ret = -ENODEV; 2396 goto out_dev_exit; 2397 } 2398 2399 vc4_hdmi->audio.streaming = true; 2400 2401 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2402 HDMI_WRITE(HDMI_MAI_CTL, 2403 VC4_HD_MAI_CTL_RESET | 2404 VC4_HD_MAI_CTL_FLUSH | 2405 VC4_HD_MAI_CTL_DLATE | 2406 VC4_HD_MAI_CTL_ERRORE | 2407 VC4_HD_MAI_CTL_ERRORF); 2408 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2409 2410 if (vc4_hdmi->variant->phy_rng_enable) 2411 vc4_hdmi->variant->phy_rng_enable(vc4_hdmi); 2412 2413 out_dev_exit: 2414 drm_dev_exit(idx); 2415 out: 2416 mutex_unlock(&vc4_hdmi->mutex); 2417 2418 return ret; 2419 } 2420 2421 static void vc4_hdmi_audio_reset(struct vc4_hdmi *vc4_hdmi) 2422 { 2423 struct drm_encoder *encoder = &vc4_hdmi->encoder.base; 2424 struct device *dev = &vc4_hdmi->pdev->dev; 2425 unsigned long flags; 2426 int ret; 2427 2428 lockdep_assert_held(&vc4_hdmi->mutex); 2429 2430 vc4_hdmi->audio.streaming = false; 2431 ret = vc4_hdmi_stop_packet(encoder, HDMI_INFOFRAME_TYPE_AUDIO, false); 2432 if (ret) 2433 dev_err(dev, "Failed to stop audio infoframe: %d\n", ret); 2434 2435 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2436 2437 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_RESET); 2438 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_ERRORF); 2439 HDMI_WRITE(HDMI_MAI_CTL, VC4_HD_MAI_CTL_FLUSH); 2440 2441 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2442 } 2443 2444 static void vc4_hdmi_audio_shutdown(struct device *dev, void *data) 2445 { 2446 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 2447 struct drm_device *drm = vc4_hdmi->connector.dev; 2448 unsigned long flags; 2449 int idx; 2450 2451 mutex_lock(&vc4_hdmi->mutex); 2452 2453 if (!drm_dev_enter(drm, &idx)) 2454 goto out; 2455 2456 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2457 2458 HDMI_WRITE(HDMI_MAI_CTL, 2459 VC4_HD_MAI_CTL_DLATE | 2460 VC4_HD_MAI_CTL_ERRORE | 2461 VC4_HD_MAI_CTL_ERRORF); 2462 2463 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2464 2465 if (vc4_hdmi->variant->phy_rng_disable) 2466 vc4_hdmi->variant->phy_rng_disable(vc4_hdmi); 2467 2468 vc4_hdmi->audio.streaming = false; 2469 vc4_hdmi_audio_reset(vc4_hdmi); 2470 2471 drm_dev_exit(idx); 2472 2473 out: 2474 mutex_unlock(&vc4_hdmi->mutex); 2475 } 2476 2477 static int sample_rate_to_mai_fmt(int samplerate) 2478 { 2479 switch (samplerate) { 2480 case 8000: 2481 return VC4_HDMI_MAI_SAMPLE_RATE_8000; 2482 case 11025: 2483 return VC4_HDMI_MAI_SAMPLE_RATE_11025; 2484 case 12000: 2485 return VC4_HDMI_MAI_SAMPLE_RATE_12000; 2486 case 16000: 2487 return VC4_HDMI_MAI_SAMPLE_RATE_16000; 2488 case 22050: 2489 return VC4_HDMI_MAI_SAMPLE_RATE_22050; 2490 case 24000: 2491 return VC4_HDMI_MAI_SAMPLE_RATE_24000; 2492 case 32000: 2493 return VC4_HDMI_MAI_SAMPLE_RATE_32000; 2494 case 44100: 2495 return VC4_HDMI_MAI_SAMPLE_RATE_44100; 2496 case 48000: 2497 return VC4_HDMI_MAI_SAMPLE_RATE_48000; 2498 case 64000: 2499 return VC4_HDMI_MAI_SAMPLE_RATE_64000; 2500 case 88200: 2501 return VC4_HDMI_MAI_SAMPLE_RATE_88200; 2502 case 96000: 2503 return VC4_HDMI_MAI_SAMPLE_RATE_96000; 2504 case 128000: 2505 return VC4_HDMI_MAI_SAMPLE_RATE_128000; 2506 case 176400: 2507 return VC4_HDMI_MAI_SAMPLE_RATE_176400; 2508 case 192000: 2509 return VC4_HDMI_MAI_SAMPLE_RATE_192000; 2510 default: 2511 return VC4_HDMI_MAI_SAMPLE_RATE_NOT_INDICATED; 2512 } 2513 } 2514 2515 /* HDMI audio codec callbacks */ 2516 static int vc4_hdmi_audio_prepare(struct device *dev, void *data, 2517 struct hdmi_codec_daifmt *daifmt, 2518 struct hdmi_codec_params *params) 2519 { 2520 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 2521 struct drm_device *drm = vc4_hdmi->connector.dev; 2522 struct drm_encoder *encoder = &vc4_hdmi->encoder.base; 2523 unsigned int sample_rate = params->sample_rate; 2524 unsigned int channels = params->channels; 2525 unsigned long flags; 2526 u32 audio_packet_config, channel_mask; 2527 u32 channel_map; 2528 u32 mai_audio_format; 2529 u32 mai_sample_rate; 2530 int ret = 0; 2531 int idx; 2532 2533 dev_dbg(dev, "%s: %u Hz, %d bit, %d channels\n", __func__, 2534 sample_rate, params->sample_width, channels); 2535 2536 mutex_lock(&vc4_hdmi->mutex); 2537 2538 if (!drm_dev_enter(drm, &idx)) { 2539 ret = -ENODEV; 2540 goto out; 2541 } 2542 2543 if (!vc4_hdmi_audio_can_stream(vc4_hdmi)) { 2544 ret = -EINVAL; 2545 goto out_dev_exit; 2546 } 2547 2548 vc4_hdmi_audio_set_mai_clock(vc4_hdmi, sample_rate); 2549 2550 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 2551 HDMI_WRITE(HDMI_MAI_CTL, 2552 VC4_SET_FIELD(channels, VC4_HD_MAI_CTL_CHNUM) | 2553 VC4_HD_MAI_CTL_WHOLSMP | 2554 VC4_HD_MAI_CTL_CHALIGN | 2555 VC4_HD_MAI_CTL_ENABLE); 2556 2557 mai_sample_rate = sample_rate_to_mai_fmt(sample_rate); 2558 if (params->iec.status[0] & IEC958_AES0_NONAUDIO && 2559 params->channels == 8) 2560 mai_audio_format = VC4_HDMI_MAI_FORMAT_HBR; 2561 else 2562 mai_audio_format = VC4_HDMI_MAI_FORMAT_PCM; 2563 HDMI_WRITE(HDMI_MAI_FMT, 2564 VC4_SET_FIELD(mai_sample_rate, 2565 VC4_HDMI_MAI_FORMAT_SAMPLE_RATE) | 2566 VC4_SET_FIELD(mai_audio_format, 2567 VC4_HDMI_MAI_FORMAT_AUDIO_FORMAT)); 2568 2569 /* The B frame identifier should match the value used by alsa-lib (8) */ 2570 audio_packet_config = 2571 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT | 2572 VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS | 2573 VC4_SET_FIELD(0x8, VC4_HDMI_AUDIO_PACKET_B_FRAME_IDENTIFIER); 2574 2575 channel_mask = GENMASK(channels - 1, 0); 2576 audio_packet_config |= VC4_SET_FIELD(channel_mask, 2577 VC4_HDMI_AUDIO_PACKET_CEA_MASK); 2578 2579 /* Set the MAI threshold */ 2580 HDMI_WRITE(HDMI_MAI_THR, 2581 VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICHIGH) | 2582 VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_PANICLOW) | 2583 VC4_SET_FIELD(0x06, VC4_HD_MAI_THR_DREQHIGH) | 2584 VC4_SET_FIELD(0x08, VC4_HD_MAI_THR_DREQLOW)); 2585 2586 HDMI_WRITE(HDMI_MAI_CONFIG, 2587 VC4_HDMI_MAI_CONFIG_BIT_REVERSE | 2588 VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE | 2589 VC4_SET_FIELD(channel_mask, VC4_HDMI_MAI_CHANNEL_MASK)); 2590 2591 channel_map = vc4_hdmi->variant->channel_map(vc4_hdmi, channel_mask); 2592 HDMI_WRITE(HDMI_MAI_CHANNEL_MAP, channel_map); 2593 HDMI_WRITE(HDMI_AUDIO_PACKET_CONFIG, audio_packet_config); 2594 2595 vc4_hdmi_set_n_cts(vc4_hdmi, sample_rate); 2596 2597 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 2598 2599 memcpy(&vc4_hdmi->audio.infoframe, ¶ms->cea, sizeof(params->cea)); 2600 vc4_hdmi_set_audio_infoframe(encoder); 2601 2602 out_dev_exit: 2603 drm_dev_exit(idx); 2604 out: 2605 mutex_unlock(&vc4_hdmi->mutex); 2606 2607 return ret; 2608 } 2609 2610 static const struct snd_soc_component_driver vc4_hdmi_audio_cpu_dai_comp = { 2611 .name = "vc4-hdmi-cpu-dai-component", 2612 .legacy_dai_naming = 1, 2613 }; 2614 2615 static int vc4_hdmi_audio_cpu_dai_probe(struct snd_soc_dai *dai) 2616 { 2617 struct vc4_hdmi *vc4_hdmi = dai_to_hdmi(dai); 2618 2619 snd_soc_dai_init_dma_data(dai, &vc4_hdmi->audio.dma_data, NULL); 2620 2621 return 0; 2622 } 2623 2624 static const struct snd_soc_dai_ops vc4_snd_dai_ops = { 2625 .probe = vc4_hdmi_audio_cpu_dai_probe, 2626 }; 2627 2628 static struct snd_soc_dai_driver vc4_hdmi_audio_cpu_dai_drv = { 2629 .name = "vc4-hdmi-cpu-dai", 2630 .ops = &vc4_snd_dai_ops, 2631 .playback = { 2632 .stream_name = "Playback", 2633 .channels_min = 1, 2634 .channels_max = 8, 2635 .rates = SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_44100 | 2636 SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_88200 | 2637 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_176400 | 2638 SNDRV_PCM_RATE_192000, 2639 .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE, 2640 }, 2641 }; 2642 2643 static const struct snd_dmaengine_pcm_config pcm_conf = { 2644 .chan_names[SNDRV_PCM_STREAM_PLAYBACK] = "audio-rx", 2645 .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config, 2646 }; 2647 2648 static int vc4_hdmi_audio_get_eld(struct device *dev, void *data, 2649 uint8_t *buf, size_t len) 2650 { 2651 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 2652 struct drm_connector *connector = &vc4_hdmi->connector; 2653 2654 mutex_lock(&vc4_hdmi->mutex); 2655 memcpy(buf, connector->eld, min(sizeof(connector->eld), len)); 2656 mutex_unlock(&vc4_hdmi->mutex); 2657 2658 return 0; 2659 } 2660 2661 static const struct hdmi_codec_ops vc4_hdmi_codec_ops = { 2662 .get_eld = vc4_hdmi_audio_get_eld, 2663 .prepare = vc4_hdmi_audio_prepare, 2664 .audio_shutdown = vc4_hdmi_audio_shutdown, 2665 .audio_startup = vc4_hdmi_audio_startup, 2666 }; 2667 2668 static struct hdmi_codec_pdata vc4_hdmi_codec_pdata = { 2669 .ops = &vc4_hdmi_codec_ops, 2670 .max_i2s_channels = 8, 2671 .i2s = 1, 2672 }; 2673 2674 static void vc4_hdmi_audio_codec_release(void *ptr) 2675 { 2676 struct vc4_hdmi *vc4_hdmi = ptr; 2677 2678 platform_device_unregister(vc4_hdmi->audio.codec_pdev); 2679 vc4_hdmi->audio.codec_pdev = NULL; 2680 } 2681 2682 static int vc4_hdmi_audio_init(struct vc4_hdmi *vc4_hdmi) 2683 { 2684 const struct vc4_hdmi_register *mai_data = 2685 &vc4_hdmi->variant->registers[HDMI_MAI_DATA]; 2686 struct snd_soc_dai_link *dai_link = &vc4_hdmi->audio.link; 2687 struct snd_soc_card *card = &vc4_hdmi->audio.card; 2688 struct device *dev = &vc4_hdmi->pdev->dev; 2689 struct platform_device *codec_pdev; 2690 const __be32 *addr; 2691 int index, len; 2692 int ret; 2693 2694 /* 2695 * ASoC makes it a bit hard to retrieve a pointer to the 2696 * vc4_hdmi structure. Registering the card will overwrite our 2697 * device drvdata with a pointer to the snd_soc_card structure, 2698 * which can then be used to retrieve whatever drvdata we want 2699 * to associate. 2700 * 2701 * However, that doesn't fly in the case where we wouldn't 2702 * register an ASoC card (because of an old DT that is missing 2703 * the dmas properties for example), then the card isn't 2704 * registered and the device drvdata wouldn't be set. 2705 * 2706 * We can deal with both cases by making sure a snd_soc_card 2707 * pointer and a vc4_hdmi structure are pointing to the same 2708 * memory address, so we can treat them indistinctly without any 2709 * issue. 2710 */ 2711 BUILD_BUG_ON(offsetof(struct vc4_hdmi_audio, card) != 0); 2712 BUILD_BUG_ON(offsetof(struct vc4_hdmi, audio) != 0); 2713 2714 if (!of_find_property(dev->of_node, "dmas", &len) || !len) { 2715 dev_warn(dev, 2716 "'dmas' DT property is missing or empty, no HDMI audio\n"); 2717 return 0; 2718 } 2719 2720 if (mai_data->reg != VC4_HD) { 2721 WARN_ONCE(true, "MAI isn't in the HD block\n"); 2722 return -EINVAL; 2723 } 2724 2725 /* 2726 * Get the physical address of VC4_HD_MAI_DATA. We need to retrieve 2727 * the bus address specified in the DT, because the physical address 2728 * (the one returned by platform_get_resource()) is not appropriate 2729 * for DMA transfers. 2730 * This VC/MMU should probably be exposed to avoid this kind of hacks. 2731 */ 2732 index = of_property_match_string(dev->of_node, "reg-names", "hd"); 2733 /* Before BCM2711, we don't have a named register range */ 2734 if (index < 0) 2735 index = 1; 2736 2737 addr = of_get_address(dev->of_node, index, NULL, NULL); 2738 if (!addr) 2739 return -EINVAL; 2740 2741 vc4_hdmi->audio.dma_data.addr = be32_to_cpup(addr) + mai_data->offset; 2742 vc4_hdmi->audio.dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 2743 vc4_hdmi->audio.dma_data.maxburst = 2; 2744 2745 /* 2746 * NOTE: Strictly speaking, we should probably use a DRM-managed 2747 * registration there to avoid removing all the audio components 2748 * by the time the driver doesn't have any user anymore. 2749 * 2750 * However, the ASoC core uses a number of devm_kzalloc calls 2751 * when registering, even when using non-device-managed 2752 * functions (such as in snd_soc_register_component()). 2753 * 2754 * If we call snd_soc_unregister_component() in a DRM-managed 2755 * action, the device-managed actions have already been executed 2756 * and thus we would access memory that has been freed. 2757 * 2758 * Using device-managed hooks here probably leaves us open to a 2759 * bunch of issues if userspace still has a handle on the ALSA 2760 * device when the device is removed. However, this is mitigated 2761 * by the use of drm_dev_enter()/drm_dev_exit() in the audio 2762 * path to prevent the access to the device resources if it 2763 * isn't there anymore. 2764 * 2765 * Then, the vc4_hdmi structure is DRM-managed and thus only 2766 * freed whenever the last user has closed the DRM device file. 2767 * It should thus outlive ALSA in most situations. 2768 */ 2769 ret = devm_snd_dmaengine_pcm_register(dev, &pcm_conf, 0); 2770 if (ret) { 2771 dev_err(dev, "Could not register PCM component: %d\n", ret); 2772 return ret; 2773 } 2774 2775 ret = devm_snd_soc_register_component(dev, &vc4_hdmi_audio_cpu_dai_comp, 2776 &vc4_hdmi_audio_cpu_dai_drv, 1); 2777 if (ret) { 2778 dev_err(dev, "Could not register CPU DAI: %d\n", ret); 2779 return ret; 2780 } 2781 2782 codec_pdev = platform_device_register_data(dev, HDMI_CODEC_DRV_NAME, 2783 PLATFORM_DEVID_AUTO, 2784 &vc4_hdmi_codec_pdata, 2785 sizeof(vc4_hdmi_codec_pdata)); 2786 if (IS_ERR(codec_pdev)) { 2787 dev_err(dev, "Couldn't register the HDMI codec: %ld\n", PTR_ERR(codec_pdev)); 2788 return PTR_ERR(codec_pdev); 2789 } 2790 vc4_hdmi->audio.codec_pdev = codec_pdev; 2791 2792 ret = devm_add_action_or_reset(dev, vc4_hdmi_audio_codec_release, vc4_hdmi); 2793 if (ret) 2794 return ret; 2795 2796 dai_link->cpus = &vc4_hdmi->audio.cpu; 2797 dai_link->codecs = &vc4_hdmi->audio.codec; 2798 dai_link->platforms = &vc4_hdmi->audio.platform; 2799 2800 dai_link->num_cpus = 1; 2801 dai_link->num_codecs = 1; 2802 dai_link->num_platforms = 1; 2803 2804 dai_link->name = "MAI"; 2805 dai_link->stream_name = "MAI PCM"; 2806 dai_link->codecs->dai_name = "i2s-hifi"; 2807 dai_link->cpus->dai_name = dev_name(dev); 2808 dai_link->codecs->name = dev_name(&codec_pdev->dev); 2809 dai_link->platforms->name = dev_name(dev); 2810 2811 card->dai_link = dai_link; 2812 card->num_links = 1; 2813 card->name = vc4_hdmi->variant->card_name; 2814 card->driver_name = "vc4-hdmi"; 2815 card->dev = dev; 2816 card->owner = THIS_MODULE; 2817 2818 /* 2819 * Be careful, snd_soc_register_card() calls dev_set_drvdata() and 2820 * stores a pointer to the snd card object in dev->driver_data. This 2821 * means we cannot use it for something else. The hdmi back-pointer is 2822 * now stored in card->drvdata and should be retrieved with 2823 * snd_soc_card_get_drvdata() if needed. 2824 */ 2825 snd_soc_card_set_drvdata(card, vc4_hdmi); 2826 ret = devm_snd_soc_register_card(dev, card); 2827 if (ret) 2828 dev_err_probe(dev, ret, "Could not register sound card\n"); 2829 2830 return ret; 2831 2832 } 2833 2834 static irqreturn_t vc4_hdmi_hpd_irq_thread(int irq, void *priv) 2835 { 2836 struct vc4_hdmi *vc4_hdmi = priv; 2837 struct drm_connector *connector = &vc4_hdmi->connector; 2838 struct drm_device *dev = connector->dev; 2839 2840 if (dev && dev->registered) 2841 drm_connector_helper_hpd_irq_event(connector); 2842 2843 return IRQ_HANDLED; 2844 } 2845 2846 static int vc4_hdmi_hotplug_init(struct vc4_hdmi *vc4_hdmi) 2847 { 2848 struct drm_connector *connector = &vc4_hdmi->connector; 2849 struct platform_device *pdev = vc4_hdmi->pdev; 2850 int ret; 2851 2852 if (vc4_hdmi->variant->external_irq_controller) { 2853 unsigned int hpd_con = platform_get_irq_byname(pdev, "hpd-connected"); 2854 unsigned int hpd_rm = platform_get_irq_byname(pdev, "hpd-removed"); 2855 2856 ret = devm_request_threaded_irq(&pdev->dev, hpd_con, 2857 NULL, 2858 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT, 2859 "vc4 hdmi hpd connected", vc4_hdmi); 2860 if (ret) 2861 return ret; 2862 2863 ret = devm_request_threaded_irq(&pdev->dev, hpd_rm, 2864 NULL, 2865 vc4_hdmi_hpd_irq_thread, IRQF_ONESHOT, 2866 "vc4 hdmi hpd disconnected", vc4_hdmi); 2867 if (ret) 2868 return ret; 2869 2870 connector->polled = DRM_CONNECTOR_POLL_HPD; 2871 } 2872 2873 return 0; 2874 } 2875 2876 #ifdef CONFIG_DRM_VC4_HDMI_CEC 2877 static irqreturn_t vc4_cec_irq_handler_rx_thread(int irq, void *priv) 2878 { 2879 struct vc4_hdmi *vc4_hdmi = priv; 2880 2881 if (vc4_hdmi->cec_rx_msg.len) 2882 cec_received_msg(vc4_hdmi->cec_adap, 2883 &vc4_hdmi->cec_rx_msg); 2884 2885 return IRQ_HANDLED; 2886 } 2887 2888 static irqreturn_t vc4_cec_irq_handler_tx_thread(int irq, void *priv) 2889 { 2890 struct vc4_hdmi *vc4_hdmi = priv; 2891 2892 if (vc4_hdmi->cec_tx_ok) { 2893 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_OK, 2894 0, 0, 0, 0); 2895 } else { 2896 /* 2897 * This CEC implementation makes 1 retry, so if we 2898 * get a NACK, then that means it made 2 attempts. 2899 */ 2900 cec_transmit_done(vc4_hdmi->cec_adap, CEC_TX_STATUS_NACK, 2901 0, 2, 0, 0); 2902 } 2903 return IRQ_HANDLED; 2904 } 2905 2906 static irqreturn_t vc4_cec_irq_handler_thread(int irq, void *priv) 2907 { 2908 struct vc4_hdmi *vc4_hdmi = priv; 2909 irqreturn_t ret; 2910 2911 if (vc4_hdmi->cec_irq_was_rx) 2912 ret = vc4_cec_irq_handler_rx_thread(irq, priv); 2913 else 2914 ret = vc4_cec_irq_handler_tx_thread(irq, priv); 2915 2916 return ret; 2917 } 2918 2919 static void vc4_cec_read_msg(struct vc4_hdmi *vc4_hdmi, u32 cntrl1) 2920 { 2921 struct drm_device *dev = vc4_hdmi->connector.dev; 2922 struct cec_msg *msg = &vc4_hdmi->cec_rx_msg; 2923 unsigned int i; 2924 2925 lockdep_assert_held(&vc4_hdmi->hw_lock); 2926 2927 msg->len = 1 + ((cntrl1 & VC4_HDMI_CEC_REC_WRD_CNT_MASK) >> 2928 VC4_HDMI_CEC_REC_WRD_CNT_SHIFT); 2929 2930 if (msg->len > 16) { 2931 drm_err(dev, "Attempting to read too much data (%d)\n", msg->len); 2932 return; 2933 } 2934 2935 for (i = 0; i < msg->len; i += 4) { 2936 u32 val = HDMI_READ(HDMI_CEC_RX_DATA_1 + (i >> 2)); 2937 2938 msg->msg[i] = val & 0xff; 2939 msg->msg[i + 1] = (val >> 8) & 0xff; 2940 msg->msg[i + 2] = (val >> 16) & 0xff; 2941 msg->msg[i + 3] = (val >> 24) & 0xff; 2942 } 2943 } 2944 2945 static irqreturn_t vc4_cec_irq_handler_tx_bare_locked(struct vc4_hdmi *vc4_hdmi) 2946 { 2947 u32 cntrl1; 2948 2949 /* 2950 * We don't need to protect the register access using 2951 * drm_dev_enter() there because the interrupt handler lifetime 2952 * is tied to the device itself, and not to the DRM device. 2953 * 2954 * So when the device will be gone, one of the first thing we 2955 * will be doing will be to unregister the interrupt handler, 2956 * and then unregister the DRM device. drm_dev_enter() would 2957 * thus always succeed if we are here. 2958 */ 2959 2960 lockdep_assert_held(&vc4_hdmi->hw_lock); 2961 2962 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1); 2963 vc4_hdmi->cec_tx_ok = cntrl1 & VC4_HDMI_CEC_TX_STATUS_GOOD; 2964 cntrl1 &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 2965 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 2966 2967 return IRQ_WAKE_THREAD; 2968 } 2969 2970 static irqreturn_t vc4_cec_irq_handler_tx_bare(int irq, void *priv) 2971 { 2972 struct vc4_hdmi *vc4_hdmi = priv; 2973 irqreturn_t ret; 2974 2975 spin_lock(&vc4_hdmi->hw_lock); 2976 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi); 2977 spin_unlock(&vc4_hdmi->hw_lock); 2978 2979 return ret; 2980 } 2981 2982 static irqreturn_t vc4_cec_irq_handler_rx_bare_locked(struct vc4_hdmi *vc4_hdmi) 2983 { 2984 u32 cntrl1; 2985 2986 lockdep_assert_held(&vc4_hdmi->hw_lock); 2987 2988 /* 2989 * We don't need to protect the register access using 2990 * drm_dev_enter() there because the interrupt handler lifetime 2991 * is tied to the device itself, and not to the DRM device. 2992 * 2993 * So when the device will be gone, one of the first thing we 2994 * will be doing will be to unregister the interrupt handler, 2995 * and then unregister the DRM device. drm_dev_enter() would 2996 * thus always succeed if we are here. 2997 */ 2998 2999 vc4_hdmi->cec_rx_msg.len = 0; 3000 cntrl1 = HDMI_READ(HDMI_CEC_CNTRL_1); 3001 vc4_cec_read_msg(vc4_hdmi, cntrl1); 3002 cntrl1 |= VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 3003 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 3004 cntrl1 &= ~VC4_HDMI_CEC_CLEAR_RECEIVE_OFF; 3005 3006 HDMI_WRITE(HDMI_CEC_CNTRL_1, cntrl1); 3007 3008 return IRQ_WAKE_THREAD; 3009 } 3010 3011 static irqreturn_t vc4_cec_irq_handler_rx_bare(int irq, void *priv) 3012 { 3013 struct vc4_hdmi *vc4_hdmi = priv; 3014 irqreturn_t ret; 3015 3016 spin_lock(&vc4_hdmi->hw_lock); 3017 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi); 3018 spin_unlock(&vc4_hdmi->hw_lock); 3019 3020 return ret; 3021 } 3022 3023 static irqreturn_t vc4_cec_irq_handler(int irq, void *priv) 3024 { 3025 struct vc4_hdmi *vc4_hdmi = priv; 3026 u32 stat = HDMI_READ(HDMI_CEC_CPU_STATUS); 3027 irqreturn_t ret; 3028 u32 cntrl5; 3029 3030 /* 3031 * We don't need to protect the register access using 3032 * drm_dev_enter() there because the interrupt handler lifetime 3033 * is tied to the device itself, and not to the DRM device. 3034 * 3035 * So when the device will be gone, one of the first thing we 3036 * will be doing will be to unregister the interrupt handler, 3037 * and then unregister the DRM device. drm_dev_enter() would 3038 * thus always succeed if we are here. 3039 */ 3040 3041 if (!(stat & VC4_HDMI_CPU_CEC)) 3042 return IRQ_NONE; 3043 3044 spin_lock(&vc4_hdmi->hw_lock); 3045 cntrl5 = HDMI_READ(HDMI_CEC_CNTRL_5); 3046 vc4_hdmi->cec_irq_was_rx = cntrl5 & VC4_HDMI_CEC_RX_CEC_INT; 3047 if (vc4_hdmi->cec_irq_was_rx) 3048 ret = vc4_cec_irq_handler_rx_bare_locked(vc4_hdmi); 3049 else 3050 ret = vc4_cec_irq_handler_tx_bare_locked(vc4_hdmi); 3051 3052 HDMI_WRITE(HDMI_CEC_CPU_CLEAR, VC4_HDMI_CPU_CEC); 3053 spin_unlock(&vc4_hdmi->hw_lock); 3054 3055 return ret; 3056 } 3057 3058 static int vc4_hdmi_cec_enable(struct cec_adapter *adap) 3059 { 3060 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 3061 struct drm_device *drm = vc4_hdmi->connector.dev; 3062 /* clock period in microseconds */ 3063 const u32 usecs = 1000000 / CEC_CLOCK_FREQ; 3064 unsigned long flags; 3065 u32 val; 3066 int ret; 3067 int idx; 3068 3069 if (!drm_dev_enter(drm, &idx)) 3070 /* 3071 * We can't return an error code, because the CEC 3072 * framework will emit WARN_ON messages at unbind 3073 * otherwise. 3074 */ 3075 return 0; 3076 3077 ret = pm_runtime_resume_and_get(&vc4_hdmi->pdev->dev); 3078 if (ret) { 3079 drm_dev_exit(idx); 3080 return ret; 3081 } 3082 3083 mutex_lock(&vc4_hdmi->mutex); 3084 3085 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 3086 3087 val = HDMI_READ(HDMI_CEC_CNTRL_5); 3088 val &= ~(VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET | 3089 VC4_HDMI_CEC_CNT_TO_4700_US_MASK | 3090 VC4_HDMI_CEC_CNT_TO_4500_US_MASK); 3091 val |= ((4700 / usecs) << VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT) | 3092 ((4500 / usecs) << VC4_HDMI_CEC_CNT_TO_4500_US_SHIFT); 3093 3094 HDMI_WRITE(HDMI_CEC_CNTRL_5, val | 3095 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 3096 HDMI_WRITE(HDMI_CEC_CNTRL_5, val); 3097 HDMI_WRITE(HDMI_CEC_CNTRL_2, 3098 ((1500 / usecs) << VC4_HDMI_CEC_CNT_TO_1500_US_SHIFT) | 3099 ((1300 / usecs) << VC4_HDMI_CEC_CNT_TO_1300_US_SHIFT) | 3100 ((800 / usecs) << VC4_HDMI_CEC_CNT_TO_800_US_SHIFT) | 3101 ((600 / usecs) << VC4_HDMI_CEC_CNT_TO_600_US_SHIFT) | 3102 ((400 / usecs) << VC4_HDMI_CEC_CNT_TO_400_US_SHIFT)); 3103 HDMI_WRITE(HDMI_CEC_CNTRL_3, 3104 ((2750 / usecs) << VC4_HDMI_CEC_CNT_TO_2750_US_SHIFT) | 3105 ((2400 / usecs) << VC4_HDMI_CEC_CNT_TO_2400_US_SHIFT) | 3106 ((2050 / usecs) << VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT) | 3107 ((1700 / usecs) << VC4_HDMI_CEC_CNT_TO_1700_US_SHIFT)); 3108 HDMI_WRITE(HDMI_CEC_CNTRL_4, 3109 ((4300 / usecs) << VC4_HDMI_CEC_CNT_TO_4300_US_SHIFT) | 3110 ((3900 / usecs) << VC4_HDMI_CEC_CNT_TO_3900_US_SHIFT) | 3111 ((3600 / usecs) << VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT) | 3112 ((3500 / usecs) << VC4_HDMI_CEC_CNT_TO_3500_US_SHIFT)); 3113 3114 if (!vc4_hdmi->variant->external_irq_controller) 3115 HDMI_WRITE(HDMI_CEC_CPU_MASK_CLEAR, VC4_HDMI_CPU_CEC); 3116 3117 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 3118 3119 mutex_unlock(&vc4_hdmi->mutex); 3120 drm_dev_exit(idx); 3121 3122 return 0; 3123 } 3124 3125 static int vc4_hdmi_cec_disable(struct cec_adapter *adap) 3126 { 3127 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 3128 struct drm_device *drm = vc4_hdmi->connector.dev; 3129 unsigned long flags; 3130 int idx; 3131 3132 if (!drm_dev_enter(drm, &idx)) 3133 /* 3134 * We can't return an error code, because the CEC 3135 * framework will emit WARN_ON messages at unbind 3136 * otherwise. 3137 */ 3138 return 0; 3139 3140 mutex_lock(&vc4_hdmi->mutex); 3141 3142 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 3143 3144 if (!vc4_hdmi->variant->external_irq_controller) 3145 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, VC4_HDMI_CPU_CEC); 3146 3147 HDMI_WRITE(HDMI_CEC_CNTRL_5, HDMI_READ(HDMI_CEC_CNTRL_5) | 3148 VC4_HDMI_CEC_TX_SW_RESET | VC4_HDMI_CEC_RX_SW_RESET); 3149 3150 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 3151 3152 mutex_unlock(&vc4_hdmi->mutex); 3153 3154 pm_runtime_put(&vc4_hdmi->pdev->dev); 3155 3156 drm_dev_exit(idx); 3157 3158 return 0; 3159 } 3160 3161 static int vc4_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable) 3162 { 3163 if (enable) 3164 return vc4_hdmi_cec_enable(adap); 3165 else 3166 return vc4_hdmi_cec_disable(adap); 3167 } 3168 3169 static int vc4_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr) 3170 { 3171 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 3172 struct drm_device *drm = vc4_hdmi->connector.dev; 3173 unsigned long flags; 3174 int idx; 3175 3176 if (!drm_dev_enter(drm, &idx)) 3177 /* 3178 * We can't return an error code, because the CEC 3179 * framework will emit WARN_ON messages at unbind 3180 * otherwise. 3181 */ 3182 return 0; 3183 3184 mutex_lock(&vc4_hdmi->mutex); 3185 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 3186 HDMI_WRITE(HDMI_CEC_CNTRL_1, 3187 (HDMI_READ(HDMI_CEC_CNTRL_1) & ~VC4_HDMI_CEC_ADDR_MASK) | 3188 (log_addr & 0xf) << VC4_HDMI_CEC_ADDR_SHIFT); 3189 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 3190 mutex_unlock(&vc4_hdmi->mutex); 3191 3192 drm_dev_exit(idx); 3193 3194 return 0; 3195 } 3196 3197 static int vc4_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts, 3198 u32 signal_free_time, struct cec_msg *msg) 3199 { 3200 struct vc4_hdmi *vc4_hdmi = cec_get_drvdata(adap); 3201 struct drm_device *dev = vc4_hdmi->connector.dev; 3202 unsigned long flags; 3203 u32 val; 3204 unsigned int i; 3205 int idx; 3206 3207 if (!drm_dev_enter(dev, &idx)) 3208 return -ENODEV; 3209 3210 if (msg->len > 16) { 3211 drm_err(dev, "Attempting to transmit too much data (%d)\n", msg->len); 3212 drm_dev_exit(idx); 3213 return -ENOMEM; 3214 } 3215 3216 mutex_lock(&vc4_hdmi->mutex); 3217 3218 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 3219 3220 for (i = 0; i < msg->len; i += 4) 3221 HDMI_WRITE(HDMI_CEC_TX_DATA_1 + (i >> 2), 3222 (msg->msg[i]) | 3223 (msg->msg[i + 1] << 8) | 3224 (msg->msg[i + 2] << 16) | 3225 (msg->msg[i + 3] << 24)); 3226 3227 val = HDMI_READ(HDMI_CEC_CNTRL_1); 3228 val &= ~VC4_HDMI_CEC_START_XMIT_BEGIN; 3229 HDMI_WRITE(HDMI_CEC_CNTRL_1, val); 3230 val &= ~VC4_HDMI_CEC_MESSAGE_LENGTH_MASK; 3231 val |= (msg->len - 1) << VC4_HDMI_CEC_MESSAGE_LENGTH_SHIFT; 3232 val |= VC4_HDMI_CEC_START_XMIT_BEGIN; 3233 3234 HDMI_WRITE(HDMI_CEC_CNTRL_1, val); 3235 3236 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 3237 mutex_unlock(&vc4_hdmi->mutex); 3238 drm_dev_exit(idx); 3239 3240 return 0; 3241 } 3242 3243 static const struct cec_adap_ops vc4_hdmi_cec_adap_ops = { 3244 .adap_enable = vc4_hdmi_cec_adap_enable, 3245 .adap_log_addr = vc4_hdmi_cec_adap_log_addr, 3246 .adap_transmit = vc4_hdmi_cec_adap_transmit, 3247 }; 3248 3249 static void vc4_hdmi_cec_release(void *ptr) 3250 { 3251 struct vc4_hdmi *vc4_hdmi = ptr; 3252 3253 cec_unregister_adapter(vc4_hdmi->cec_adap); 3254 vc4_hdmi->cec_adap = NULL; 3255 } 3256 3257 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi) 3258 { 3259 struct cec_connector_info conn_info; 3260 struct platform_device *pdev = vc4_hdmi->pdev; 3261 struct device *dev = &pdev->dev; 3262 int ret; 3263 3264 if (!of_property_present(dev->of_node, "interrupts")) { 3265 dev_warn(dev, "'interrupts' DT property is missing, no CEC\n"); 3266 return 0; 3267 } 3268 3269 vc4_hdmi->cec_adap = cec_allocate_adapter(&vc4_hdmi_cec_adap_ops, 3270 vc4_hdmi, 3271 vc4_hdmi->variant->card_name, 3272 CEC_CAP_DEFAULTS | 3273 CEC_CAP_CONNECTOR_INFO, 1); 3274 ret = PTR_ERR_OR_ZERO(vc4_hdmi->cec_adap); 3275 if (ret < 0) 3276 return ret; 3277 3278 cec_fill_conn_info_from_drm(&conn_info, &vc4_hdmi->connector); 3279 cec_s_conn_info(vc4_hdmi->cec_adap, &conn_info); 3280 3281 if (vc4_hdmi->variant->external_irq_controller) { 3282 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-rx"), 3283 vc4_cec_irq_handler_rx_bare, 3284 vc4_cec_irq_handler_rx_thread, 0, 3285 "vc4 hdmi cec rx", vc4_hdmi); 3286 if (ret) 3287 goto err_delete_cec_adap; 3288 3289 ret = devm_request_threaded_irq(dev, platform_get_irq_byname(pdev, "cec-tx"), 3290 vc4_cec_irq_handler_tx_bare, 3291 vc4_cec_irq_handler_tx_thread, 0, 3292 "vc4 hdmi cec tx", vc4_hdmi); 3293 if (ret) 3294 goto err_delete_cec_adap; 3295 } else { 3296 ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0), 3297 vc4_cec_irq_handler, 3298 vc4_cec_irq_handler_thread, 0, 3299 "vc4 hdmi cec", vc4_hdmi); 3300 if (ret) 3301 goto err_delete_cec_adap; 3302 } 3303 3304 ret = cec_register_adapter(vc4_hdmi->cec_adap, &pdev->dev); 3305 if (ret < 0) 3306 goto err_delete_cec_adap; 3307 3308 /* 3309 * NOTE: Strictly speaking, we should probably use a DRM-managed 3310 * registration there to avoid removing the CEC adapter by the 3311 * time the DRM driver doesn't have any user anymore. 3312 * 3313 * However, the CEC framework already cleans up the CEC adapter 3314 * only when the last user has closed its file descriptor, so we 3315 * don't need to handle it in DRM. 3316 * 3317 * By the time the device-managed hook is executed, we will give 3318 * up our reference to the CEC adapter and therefore don't 3319 * really care when it's actually freed. 3320 * 3321 * There's still a problematic sequence: if we unregister our 3322 * CEC adapter, but the userspace keeps a handle on the CEC 3323 * adapter but not the DRM device for some reason. In such a 3324 * case, our vc4_hdmi structure will be freed, but the 3325 * cec_adapter structure will have a dangling pointer to what 3326 * used to be our HDMI controller. If we get a CEC call at that 3327 * moment, we could end up with a use-after-free. Fortunately, 3328 * the CEC framework already handles this too, by calling 3329 * cec_is_registered() in cec_ioctl() and cec_poll(). 3330 */ 3331 ret = devm_add_action_or_reset(dev, vc4_hdmi_cec_release, vc4_hdmi); 3332 if (ret) 3333 return ret; 3334 3335 return 0; 3336 3337 err_delete_cec_adap: 3338 cec_delete_adapter(vc4_hdmi->cec_adap); 3339 3340 return ret; 3341 } 3342 #else 3343 static int vc4_hdmi_cec_init(struct vc4_hdmi *vc4_hdmi) 3344 { 3345 return 0; 3346 } 3347 #endif 3348 3349 static void vc4_hdmi_free_regset(struct drm_device *drm, void *ptr) 3350 { 3351 struct debugfs_reg32 *regs = ptr; 3352 3353 kfree(regs); 3354 } 3355 3356 static int vc4_hdmi_build_regset(struct drm_device *drm, 3357 struct vc4_hdmi *vc4_hdmi, 3358 struct debugfs_regset32 *regset, 3359 enum vc4_hdmi_regs reg) 3360 { 3361 const struct vc4_hdmi_variant *variant = vc4_hdmi->variant; 3362 struct debugfs_reg32 *regs, *new_regs; 3363 unsigned int count = 0; 3364 unsigned int i; 3365 int ret; 3366 3367 regs = kcalloc(variant->num_registers, sizeof(*regs), 3368 GFP_KERNEL); 3369 if (!regs) 3370 return -ENOMEM; 3371 3372 for (i = 0; i < variant->num_registers; i++) { 3373 const struct vc4_hdmi_register *field = &variant->registers[i]; 3374 3375 if (field->reg != reg) 3376 continue; 3377 3378 regs[count].name = field->name; 3379 regs[count].offset = field->offset; 3380 count++; 3381 } 3382 3383 new_regs = krealloc(regs, count * sizeof(*regs), GFP_KERNEL); 3384 if (!new_regs) 3385 return -ENOMEM; 3386 3387 regset->base = __vc4_hdmi_get_field_base(vc4_hdmi, reg); 3388 regset->regs = new_regs; 3389 regset->nregs = count; 3390 3391 ret = drmm_add_action_or_reset(drm, vc4_hdmi_free_regset, new_regs); 3392 if (ret) 3393 return ret; 3394 3395 return 0; 3396 } 3397 3398 static int vc4_hdmi_init_resources(struct drm_device *drm, 3399 struct vc4_hdmi *vc4_hdmi) 3400 { 3401 struct platform_device *pdev = vc4_hdmi->pdev; 3402 struct device *dev = &pdev->dev; 3403 int ret; 3404 3405 vc4_hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0); 3406 if (IS_ERR(vc4_hdmi->hdmicore_regs)) 3407 return PTR_ERR(vc4_hdmi->hdmicore_regs); 3408 3409 vc4_hdmi->hd_regs = vc4_ioremap_regs(pdev, 1); 3410 if (IS_ERR(vc4_hdmi->hd_regs)) 3411 return PTR_ERR(vc4_hdmi->hd_regs); 3412 3413 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD); 3414 if (ret) 3415 return ret; 3416 3417 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI); 3418 if (ret) 3419 return ret; 3420 3421 vc4_hdmi->pixel_clock = devm_clk_get(dev, "pixel"); 3422 if (IS_ERR(vc4_hdmi->pixel_clock)) { 3423 ret = PTR_ERR(vc4_hdmi->pixel_clock); 3424 if (ret != -EPROBE_DEFER) 3425 DRM_ERROR("Failed to get pixel clock\n"); 3426 return ret; 3427 } 3428 3429 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); 3430 if (IS_ERR(vc4_hdmi->hsm_clock)) { 3431 DRM_ERROR("Failed to get HDMI state machine clock\n"); 3432 return PTR_ERR(vc4_hdmi->hsm_clock); 3433 } 3434 vc4_hdmi->audio_clock = vc4_hdmi->hsm_clock; 3435 vc4_hdmi->cec_clock = vc4_hdmi->hsm_clock; 3436 3437 return 0; 3438 } 3439 3440 static int vc5_hdmi_init_resources(struct drm_device *drm, 3441 struct vc4_hdmi *vc4_hdmi) 3442 { 3443 struct platform_device *pdev = vc4_hdmi->pdev; 3444 struct device *dev = &pdev->dev; 3445 struct resource *res; 3446 int ret; 3447 3448 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi"); 3449 if (!res) 3450 return -ENODEV; 3451 3452 vc4_hdmi->hdmicore_regs = devm_ioremap(dev, res->start, 3453 resource_size(res)); 3454 if (!vc4_hdmi->hdmicore_regs) 3455 return -ENOMEM; 3456 3457 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hd"); 3458 if (!res) 3459 return -ENODEV; 3460 3461 vc4_hdmi->hd_regs = devm_ioremap(dev, res->start, resource_size(res)); 3462 if (!vc4_hdmi->hd_regs) 3463 return -ENOMEM; 3464 3465 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cec"); 3466 if (!res) 3467 return -ENODEV; 3468 3469 vc4_hdmi->cec_regs = devm_ioremap(dev, res->start, resource_size(res)); 3470 if (!vc4_hdmi->cec_regs) 3471 return -ENOMEM; 3472 3473 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csc"); 3474 if (!res) 3475 return -ENODEV; 3476 3477 vc4_hdmi->csc_regs = devm_ioremap(dev, res->start, resource_size(res)); 3478 if (!vc4_hdmi->csc_regs) 3479 return -ENOMEM; 3480 3481 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dvp"); 3482 if (!res) 3483 return -ENODEV; 3484 3485 vc4_hdmi->dvp_regs = devm_ioremap(dev, res->start, resource_size(res)); 3486 if (!vc4_hdmi->dvp_regs) 3487 return -ENOMEM; 3488 3489 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy"); 3490 if (!res) 3491 return -ENODEV; 3492 3493 vc4_hdmi->phy_regs = devm_ioremap(dev, res->start, resource_size(res)); 3494 if (!vc4_hdmi->phy_regs) 3495 return -ENOMEM; 3496 3497 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "packet"); 3498 if (!res) 3499 return -ENODEV; 3500 3501 vc4_hdmi->ram_regs = devm_ioremap(dev, res->start, resource_size(res)); 3502 if (!vc4_hdmi->ram_regs) 3503 return -ENOMEM; 3504 3505 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rm"); 3506 if (!res) 3507 return -ENODEV; 3508 3509 vc4_hdmi->rm_regs = devm_ioremap(dev, res->start, resource_size(res)); 3510 if (!vc4_hdmi->rm_regs) 3511 return -ENOMEM; 3512 3513 vc4_hdmi->hsm_clock = devm_clk_get(dev, "hdmi"); 3514 if (IS_ERR(vc4_hdmi->hsm_clock)) { 3515 DRM_ERROR("Failed to get HDMI state machine clock\n"); 3516 return PTR_ERR(vc4_hdmi->hsm_clock); 3517 } 3518 3519 vc4_hdmi->pixel_bvb_clock = devm_clk_get(dev, "bvb"); 3520 if (IS_ERR(vc4_hdmi->pixel_bvb_clock)) { 3521 DRM_ERROR("Failed to get pixel bvb clock\n"); 3522 return PTR_ERR(vc4_hdmi->pixel_bvb_clock); 3523 } 3524 3525 vc4_hdmi->audio_clock = devm_clk_get(dev, "audio"); 3526 if (IS_ERR(vc4_hdmi->audio_clock)) { 3527 DRM_ERROR("Failed to get audio clock\n"); 3528 return PTR_ERR(vc4_hdmi->audio_clock); 3529 } 3530 3531 vc4_hdmi->cec_clock = devm_clk_get(dev, "cec"); 3532 if (IS_ERR(vc4_hdmi->cec_clock)) { 3533 DRM_ERROR("Failed to get CEC clock\n"); 3534 return PTR_ERR(vc4_hdmi->cec_clock); 3535 } 3536 3537 vc4_hdmi->reset = devm_reset_control_get(dev, NULL); 3538 if (IS_ERR(vc4_hdmi->reset)) { 3539 DRM_ERROR("Failed to get HDMI reset line\n"); 3540 return PTR_ERR(vc4_hdmi->reset); 3541 } 3542 3543 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hdmi_regset, VC4_HDMI); 3544 if (ret) 3545 return ret; 3546 3547 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->hd_regset, VC4_HD); 3548 if (ret) 3549 return ret; 3550 3551 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->cec_regset, VC5_CEC); 3552 if (ret) 3553 return ret; 3554 3555 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->csc_regset, VC5_CSC); 3556 if (ret) 3557 return ret; 3558 3559 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->dvp_regset, VC5_DVP); 3560 if (ret) 3561 return ret; 3562 3563 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->phy_regset, VC5_PHY); 3564 if (ret) 3565 return ret; 3566 3567 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->ram_regset, VC5_RAM); 3568 if (ret) 3569 return ret; 3570 3571 ret = vc4_hdmi_build_regset(drm, vc4_hdmi, &vc4_hdmi->rm_regset, VC5_RM); 3572 if (ret) 3573 return ret; 3574 3575 return 0; 3576 } 3577 3578 static int vc4_hdmi_runtime_suspend(struct device *dev) 3579 { 3580 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 3581 3582 clk_disable_unprepare(vc4_hdmi->hsm_clock); 3583 3584 return 0; 3585 } 3586 3587 static int vc4_hdmi_runtime_resume(struct device *dev) 3588 { 3589 struct vc4_hdmi *vc4_hdmi = dev_get_drvdata(dev); 3590 unsigned long __maybe_unused flags; 3591 u32 __maybe_unused value; 3592 unsigned long rate; 3593 int ret; 3594 3595 ret = clk_prepare_enable(vc4_hdmi->hsm_clock); 3596 if (ret) 3597 return ret; 3598 3599 /* 3600 * Whenever the RaspberryPi boots without an HDMI monitor 3601 * plugged in, the firmware won't have initialized the HSM clock 3602 * rate and it will be reported as 0. 3603 * 3604 * If we try to access a register of the controller in such a 3605 * case, it will lead to a silent CPU stall. Let's make sure we 3606 * prevent such a case. 3607 */ 3608 rate = clk_get_rate(vc4_hdmi->hsm_clock); 3609 if (!rate) { 3610 ret = -EINVAL; 3611 goto err_disable_clk; 3612 } 3613 3614 if (vc4_hdmi->variant->reset) 3615 vc4_hdmi->variant->reset(vc4_hdmi); 3616 3617 #ifdef CONFIG_DRM_VC4_HDMI_CEC 3618 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 3619 value = HDMI_READ(HDMI_CEC_CNTRL_1); 3620 /* Set the logical address to Unregistered */ 3621 value |= VC4_HDMI_CEC_ADDR_MASK; 3622 HDMI_WRITE(HDMI_CEC_CNTRL_1, value); 3623 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 3624 3625 vc4_hdmi_cec_update_clk_div(vc4_hdmi); 3626 3627 if (!vc4_hdmi->variant->external_irq_controller) { 3628 spin_lock_irqsave(&vc4_hdmi->hw_lock, flags); 3629 HDMI_WRITE(HDMI_CEC_CPU_MASK_SET, 0xffffffff); 3630 spin_unlock_irqrestore(&vc4_hdmi->hw_lock, flags); 3631 } 3632 #endif 3633 3634 return 0; 3635 3636 err_disable_clk: 3637 clk_disable_unprepare(vc4_hdmi->hsm_clock); 3638 return ret; 3639 } 3640 3641 static void vc4_hdmi_put_ddc_device(void *ptr) 3642 { 3643 struct vc4_hdmi *vc4_hdmi = ptr; 3644 3645 put_device(&vc4_hdmi->ddc->dev); 3646 } 3647 3648 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data) 3649 { 3650 const struct vc4_hdmi_variant *variant = of_device_get_match_data(dev); 3651 struct platform_device *pdev = to_platform_device(dev); 3652 struct drm_device *drm = dev_get_drvdata(master); 3653 struct vc4_hdmi *vc4_hdmi; 3654 struct drm_encoder *encoder; 3655 struct device_node *ddc_node; 3656 int ret; 3657 3658 vc4_hdmi = drmm_kzalloc(drm, sizeof(*vc4_hdmi), GFP_KERNEL); 3659 if (!vc4_hdmi) 3660 return -ENOMEM; 3661 3662 ret = drmm_mutex_init(drm, &vc4_hdmi->mutex); 3663 if (ret) 3664 return ret; 3665 3666 spin_lock_init(&vc4_hdmi->hw_lock); 3667 INIT_DELAYED_WORK(&vc4_hdmi->scrambling_work, vc4_hdmi_scrambling_wq); 3668 3669 dev_set_drvdata(dev, vc4_hdmi); 3670 encoder = &vc4_hdmi->encoder.base; 3671 vc4_hdmi->encoder.type = variant->encoder_type; 3672 vc4_hdmi->encoder.pre_crtc_configure = vc4_hdmi_encoder_pre_crtc_configure; 3673 vc4_hdmi->encoder.pre_crtc_enable = vc4_hdmi_encoder_pre_crtc_enable; 3674 vc4_hdmi->encoder.post_crtc_enable = vc4_hdmi_encoder_post_crtc_enable; 3675 vc4_hdmi->encoder.post_crtc_disable = vc4_hdmi_encoder_post_crtc_disable; 3676 vc4_hdmi->encoder.post_crtc_powerdown = vc4_hdmi_encoder_post_crtc_powerdown; 3677 vc4_hdmi->pdev = pdev; 3678 vc4_hdmi->variant = variant; 3679 3680 /* 3681 * Since we don't know the state of the controller and its 3682 * display (if any), let's assume it's always enabled. 3683 * vc4_hdmi_disable_scrambling() will thus run at boot, make 3684 * sure it's disabled, and avoid any inconsistency. 3685 */ 3686 if (variant->max_pixel_clock > HDMI_14_MAX_TMDS_CLK) 3687 vc4_hdmi->scdc_enabled = true; 3688 3689 ret = variant->init_resources(drm, vc4_hdmi); 3690 if (ret) 3691 return ret; 3692 3693 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0); 3694 if (!ddc_node) { 3695 DRM_ERROR("Failed to find ddc node in device tree\n"); 3696 return -ENODEV; 3697 } 3698 3699 vc4_hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node); 3700 of_node_put(ddc_node); 3701 if (!vc4_hdmi->ddc) { 3702 DRM_DEBUG("Failed to get ddc i2c adapter by node\n"); 3703 return -EPROBE_DEFER; 3704 } 3705 3706 ret = devm_add_action_or_reset(dev, vc4_hdmi_put_ddc_device, vc4_hdmi); 3707 if (ret) 3708 return ret; 3709 3710 /* Only use the GPIO HPD pin if present in the DT, otherwise 3711 * we'll use the HDMI core's register. 3712 */ 3713 vc4_hdmi->hpd_gpio = devm_gpiod_get_optional(dev, "hpd", GPIOD_IN); 3714 if (IS_ERR(vc4_hdmi->hpd_gpio)) { 3715 return PTR_ERR(vc4_hdmi->hpd_gpio); 3716 } 3717 3718 vc4_hdmi->disable_wifi_frequencies = 3719 of_property_read_bool(dev->of_node, "wifi-2.4ghz-coexistence"); 3720 3721 ret = devm_pm_runtime_enable(dev); 3722 if (ret) 3723 return ret; 3724 3725 /* 3726 * We need to have the device powered up at this point to call 3727 * our reset hook and for the CEC init. 3728 */ 3729 ret = pm_runtime_resume_and_get(dev); 3730 if (ret) 3731 return ret; 3732 3733 if ((of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi0") || 3734 of_device_is_compatible(dev->of_node, "brcm,bcm2711-hdmi1")) && 3735 HDMI_READ(HDMI_VID_CTL) & VC4_HD_VID_CTL_ENABLE) { 3736 clk_prepare_enable(vc4_hdmi->pixel_clock); 3737 clk_prepare_enable(vc4_hdmi->hsm_clock); 3738 clk_prepare_enable(vc4_hdmi->pixel_bvb_clock); 3739 } 3740 3741 ret = drmm_encoder_init(drm, encoder, 3742 &vc4_hdmi_encoder_funcs, 3743 DRM_MODE_ENCODER_TMDS, 3744 NULL); 3745 if (ret) 3746 goto err_put_runtime_pm; 3747 3748 drm_encoder_helper_add(encoder, &vc4_hdmi_encoder_helper_funcs); 3749 3750 ret = vc4_hdmi_connector_init(drm, vc4_hdmi); 3751 if (ret) 3752 goto err_put_runtime_pm; 3753 3754 ret = vc4_hdmi_hotplug_init(vc4_hdmi); 3755 if (ret) 3756 goto err_put_runtime_pm; 3757 3758 ret = vc4_hdmi_cec_init(vc4_hdmi); 3759 if (ret) 3760 goto err_put_runtime_pm; 3761 3762 ret = vc4_hdmi_audio_init(vc4_hdmi); 3763 if (ret) 3764 goto err_put_runtime_pm; 3765 3766 pm_runtime_put_sync(dev); 3767 3768 return 0; 3769 3770 err_put_runtime_pm: 3771 pm_runtime_put_sync(dev); 3772 3773 return ret; 3774 } 3775 3776 static const struct component_ops vc4_hdmi_ops = { 3777 .bind = vc4_hdmi_bind, 3778 }; 3779 3780 static int vc4_hdmi_dev_probe(struct platform_device *pdev) 3781 { 3782 return component_add(&pdev->dev, &vc4_hdmi_ops); 3783 } 3784 3785 static void vc4_hdmi_dev_remove(struct platform_device *pdev) 3786 { 3787 component_del(&pdev->dev, &vc4_hdmi_ops); 3788 } 3789 3790 static const struct vc4_hdmi_variant bcm2835_variant = { 3791 .encoder_type = VC4_ENCODER_TYPE_HDMI0, 3792 .debugfs_name = "hdmi_regs", 3793 .card_name = "vc4-hdmi", 3794 .max_pixel_clock = 162000000, 3795 .registers = vc4_hdmi_fields, 3796 .num_registers = ARRAY_SIZE(vc4_hdmi_fields), 3797 3798 .init_resources = vc4_hdmi_init_resources, 3799 .csc_setup = vc4_hdmi_csc_setup, 3800 .reset = vc4_hdmi_reset, 3801 .set_timings = vc4_hdmi_set_timings, 3802 .phy_init = vc4_hdmi_phy_init, 3803 .phy_disable = vc4_hdmi_phy_disable, 3804 .phy_rng_enable = vc4_hdmi_phy_rng_enable, 3805 .phy_rng_disable = vc4_hdmi_phy_rng_disable, 3806 .channel_map = vc4_hdmi_channel_map, 3807 .supports_hdr = false, 3808 }; 3809 3810 static const struct vc4_hdmi_variant bcm2711_hdmi0_variant = { 3811 .encoder_type = VC4_ENCODER_TYPE_HDMI0, 3812 .debugfs_name = "hdmi0_regs", 3813 .card_name = "vc4-hdmi-0", 3814 .max_pixel_clock = 600000000, 3815 .registers = vc5_hdmi_hdmi0_fields, 3816 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi0_fields), 3817 .phy_lane_mapping = { 3818 PHY_LANE_0, 3819 PHY_LANE_1, 3820 PHY_LANE_2, 3821 PHY_LANE_CK, 3822 }, 3823 .unsupported_odd_h_timings = true, 3824 .external_irq_controller = true, 3825 3826 .init_resources = vc5_hdmi_init_resources, 3827 .csc_setup = vc5_hdmi_csc_setup, 3828 .reset = vc5_hdmi_reset, 3829 .set_timings = vc5_hdmi_set_timings, 3830 .phy_init = vc5_hdmi_phy_init, 3831 .phy_disable = vc5_hdmi_phy_disable, 3832 .phy_rng_enable = vc5_hdmi_phy_rng_enable, 3833 .phy_rng_disable = vc5_hdmi_phy_rng_disable, 3834 .channel_map = vc5_hdmi_channel_map, 3835 .supports_hdr = true, 3836 .hp_detect = vc5_hdmi_hp_detect, 3837 }; 3838 3839 static const struct vc4_hdmi_variant bcm2711_hdmi1_variant = { 3840 .encoder_type = VC4_ENCODER_TYPE_HDMI1, 3841 .debugfs_name = "hdmi1_regs", 3842 .card_name = "vc4-hdmi-1", 3843 .max_pixel_clock = HDMI_14_MAX_TMDS_CLK, 3844 .registers = vc5_hdmi_hdmi1_fields, 3845 .num_registers = ARRAY_SIZE(vc5_hdmi_hdmi1_fields), 3846 .phy_lane_mapping = { 3847 PHY_LANE_1, 3848 PHY_LANE_0, 3849 PHY_LANE_CK, 3850 PHY_LANE_2, 3851 }, 3852 .unsupported_odd_h_timings = true, 3853 .external_irq_controller = true, 3854 3855 .init_resources = vc5_hdmi_init_resources, 3856 .csc_setup = vc5_hdmi_csc_setup, 3857 .reset = vc5_hdmi_reset, 3858 .set_timings = vc5_hdmi_set_timings, 3859 .phy_init = vc5_hdmi_phy_init, 3860 .phy_disable = vc5_hdmi_phy_disable, 3861 .phy_rng_enable = vc5_hdmi_phy_rng_enable, 3862 .phy_rng_disable = vc5_hdmi_phy_rng_disable, 3863 .channel_map = vc5_hdmi_channel_map, 3864 .supports_hdr = true, 3865 .hp_detect = vc5_hdmi_hp_detect, 3866 }; 3867 3868 static const struct of_device_id vc4_hdmi_dt_match[] = { 3869 { .compatible = "brcm,bcm2835-hdmi", .data = &bcm2835_variant }, 3870 { .compatible = "brcm,bcm2711-hdmi0", .data = &bcm2711_hdmi0_variant }, 3871 { .compatible = "brcm,bcm2711-hdmi1", .data = &bcm2711_hdmi1_variant }, 3872 {} 3873 }; 3874 3875 static const struct dev_pm_ops vc4_hdmi_pm_ops = { 3876 SET_RUNTIME_PM_OPS(vc4_hdmi_runtime_suspend, 3877 vc4_hdmi_runtime_resume, 3878 NULL) 3879 }; 3880 3881 struct platform_driver vc4_hdmi_driver = { 3882 .probe = vc4_hdmi_dev_probe, 3883 .remove_new = vc4_hdmi_dev_remove, 3884 .driver = { 3885 .name = "vc4_hdmi", 3886 .of_match_table = vc4_hdmi_dt_match, 3887 .pm = &vc4_hdmi_pm_ops, 3888 }, 3889 }; 3890