1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2016 Broadcom 4 */ 5 6 /** 7 * DOC: VC4 DSI0/DSI1 module 8 * 9 * BCM2835 contains two DSI modules, DSI0 and DSI1. DSI0 is a 10 * single-lane DSI controller, while DSI1 is a more modern 4-lane DSI 11 * controller. 12 * 13 * Most Raspberry Pi boards expose DSI1 as their "DISPLAY" connector, 14 * while the compute module brings both DSI0 and DSI1 out. 15 * 16 * This driver has been tested for DSI1 video-mode display only 17 * currently, with most of the information necessary for DSI0 18 * hopefully present. 19 */ 20 21 #include <linux/clk-provider.h> 22 #include <linux/clk.h> 23 #include <linux/completion.h> 24 #include <linux/component.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/dmaengine.h> 27 #include <linux/io.h> 28 #include <linux/of_address.h> 29 #include <linux/of_platform.h> 30 #include <linux/pm_runtime.h> 31 32 #include <drm/drm_atomic_helper.h> 33 #include <drm/drm_bridge.h> 34 #include <drm/drm_edid.h> 35 #include <drm/drm_mipi_dsi.h> 36 #include <drm/drm_of.h> 37 #include <drm/drm_panel.h> 38 #include <drm/drm_probe_helper.h> 39 #include <drm/drm_simple_kms_helper.h> 40 41 #include "vc4_drv.h" 42 #include "vc4_regs.h" 43 44 #define DSI_CMD_FIFO_DEPTH 16 45 #define DSI_PIX_FIFO_DEPTH 256 46 #define DSI_PIX_FIFO_WIDTH 4 47 48 #define DSI0_CTRL 0x00 49 50 /* Command packet control. */ 51 #define DSI0_TXPKT1C 0x04 /* AKA PKTC */ 52 #define DSI1_TXPKT1C 0x04 53 # define DSI_TXPKT1C_TRIG_CMD_MASK VC4_MASK(31, 24) 54 # define DSI_TXPKT1C_TRIG_CMD_SHIFT 24 55 # define DSI_TXPKT1C_CMD_REPEAT_MASK VC4_MASK(23, 10) 56 # define DSI_TXPKT1C_CMD_REPEAT_SHIFT 10 57 58 # define DSI_TXPKT1C_DISPLAY_NO_MASK VC4_MASK(9, 8) 59 # define DSI_TXPKT1C_DISPLAY_NO_SHIFT 8 60 /* Short, trigger, BTA, or a long packet that fits all in CMDFIFO. */ 61 # define DSI_TXPKT1C_DISPLAY_NO_SHORT 0 62 /* Primary display where cmdfifo provides part of the payload and 63 * pixelvalve the rest. 64 */ 65 # define DSI_TXPKT1C_DISPLAY_NO_PRIMARY 1 66 /* Secondary display where cmdfifo provides part of the payload and 67 * pixfifo the rest. 68 */ 69 # define DSI_TXPKT1C_DISPLAY_NO_SECONDARY 2 70 71 # define DSI_TXPKT1C_CMD_TX_TIME_MASK VC4_MASK(7, 6) 72 # define DSI_TXPKT1C_CMD_TX_TIME_SHIFT 6 73 74 # define DSI_TXPKT1C_CMD_CTRL_MASK VC4_MASK(5, 4) 75 # define DSI_TXPKT1C_CMD_CTRL_SHIFT 4 76 /* Command only. Uses TXPKT1H and DISPLAY_NO */ 77 # define DSI_TXPKT1C_CMD_CTRL_TX 0 78 /* Command with BTA for either ack or read data. */ 79 # define DSI_TXPKT1C_CMD_CTRL_RX 1 80 /* Trigger according to TRIG_CMD */ 81 # define DSI_TXPKT1C_CMD_CTRL_TRIG 2 82 /* BTA alone for getting error status after a command, or a TE trigger 83 * without a previous command. 84 */ 85 # define DSI_TXPKT1C_CMD_CTRL_BTA 3 86 87 # define DSI_TXPKT1C_CMD_MODE_LP BIT(3) 88 # define DSI_TXPKT1C_CMD_TYPE_LONG BIT(2) 89 # define DSI_TXPKT1C_CMD_TE_EN BIT(1) 90 # define DSI_TXPKT1C_CMD_EN BIT(0) 91 92 /* Command packet header. */ 93 #define DSI0_TXPKT1H 0x08 /* AKA PKTH */ 94 #define DSI1_TXPKT1H 0x08 95 # define DSI_TXPKT1H_BC_CMDFIFO_MASK VC4_MASK(31, 24) 96 # define DSI_TXPKT1H_BC_CMDFIFO_SHIFT 24 97 # define DSI_TXPKT1H_BC_PARAM_MASK VC4_MASK(23, 8) 98 # define DSI_TXPKT1H_BC_PARAM_SHIFT 8 99 # define DSI_TXPKT1H_BC_DT_MASK VC4_MASK(7, 0) 100 # define DSI_TXPKT1H_BC_DT_SHIFT 0 101 102 #define DSI0_RXPKT1H 0x0c /* AKA RX1_PKTH */ 103 #define DSI1_RXPKT1H 0x14 104 # define DSI_RXPKT1H_CRC_ERR BIT(31) 105 # define DSI_RXPKT1H_DET_ERR BIT(30) 106 # define DSI_RXPKT1H_ECC_ERR BIT(29) 107 # define DSI_RXPKT1H_COR_ERR BIT(28) 108 # define DSI_RXPKT1H_INCOMP_PKT BIT(25) 109 # define DSI_RXPKT1H_PKT_TYPE_LONG BIT(24) 110 /* Byte count if DSI_RXPKT1H_PKT_TYPE_LONG */ 111 # define DSI_RXPKT1H_BC_PARAM_MASK VC4_MASK(23, 8) 112 # define DSI_RXPKT1H_BC_PARAM_SHIFT 8 113 /* Short return bytes if !DSI_RXPKT1H_PKT_TYPE_LONG */ 114 # define DSI_RXPKT1H_SHORT_1_MASK VC4_MASK(23, 16) 115 # define DSI_RXPKT1H_SHORT_1_SHIFT 16 116 # define DSI_RXPKT1H_SHORT_0_MASK VC4_MASK(15, 8) 117 # define DSI_RXPKT1H_SHORT_0_SHIFT 8 118 # define DSI_RXPKT1H_DT_LP_CMD_MASK VC4_MASK(7, 0) 119 # define DSI_RXPKT1H_DT_LP_CMD_SHIFT 0 120 121 #define DSI0_RXPKT2H 0x10 /* AKA RX2_PKTH */ 122 #define DSI1_RXPKT2H 0x18 123 # define DSI_RXPKT1H_DET_ERR BIT(30) 124 # define DSI_RXPKT1H_ECC_ERR BIT(29) 125 # define DSI_RXPKT1H_COR_ERR BIT(28) 126 # define DSI_RXPKT1H_INCOMP_PKT BIT(25) 127 # define DSI_RXPKT1H_BC_PARAM_MASK VC4_MASK(23, 8) 128 # define DSI_RXPKT1H_BC_PARAM_SHIFT 8 129 # define DSI_RXPKT1H_DT_MASK VC4_MASK(7, 0) 130 # define DSI_RXPKT1H_DT_SHIFT 0 131 132 #define DSI0_TXPKT_CMD_FIFO 0x14 /* AKA CMD_DATAF */ 133 #define DSI1_TXPKT_CMD_FIFO 0x1c 134 135 #define DSI0_DISP0_CTRL 0x18 136 # define DSI_DISP0_PIX_CLK_DIV_MASK VC4_MASK(21, 13) 137 # define DSI_DISP0_PIX_CLK_DIV_SHIFT 13 138 # define DSI_DISP0_LP_STOP_CTRL_MASK VC4_MASK(12, 11) 139 # define DSI_DISP0_LP_STOP_CTRL_SHIFT 11 140 # define DSI_DISP0_LP_STOP_DISABLE 0 141 # define DSI_DISP0_LP_STOP_PERLINE 1 142 # define DSI_DISP0_LP_STOP_PERFRAME 2 143 144 /* Transmit RGB pixels and null packets only during HACTIVE, instead 145 * of going to LP-STOP. 146 */ 147 # define DSI_DISP_HACTIVE_NULL BIT(10) 148 /* Transmit blanking packet only during vblank, instead of allowing LP-STOP. */ 149 # define DSI_DISP_VBLP_CTRL BIT(9) 150 /* Transmit blanking packet only during HFP, instead of allowing LP-STOP. */ 151 # define DSI_DISP_HFP_CTRL BIT(8) 152 /* Transmit blanking packet only during HBP, instead of allowing LP-STOP. */ 153 # define DSI_DISP_HBP_CTRL BIT(7) 154 # define DSI_DISP0_CHANNEL_MASK VC4_MASK(6, 5) 155 # define DSI_DISP0_CHANNEL_SHIFT 5 156 /* Enables end events for HSYNC/VSYNC, not just start events. */ 157 # define DSI_DISP0_ST_END BIT(4) 158 # define DSI_DISP0_PFORMAT_MASK VC4_MASK(3, 2) 159 # define DSI_DISP0_PFORMAT_SHIFT 2 160 # define DSI_PFORMAT_RGB565 0 161 # define DSI_PFORMAT_RGB666_PACKED 1 162 # define DSI_PFORMAT_RGB666 2 163 # define DSI_PFORMAT_RGB888 3 164 /* Default is VIDEO mode. */ 165 # define DSI_DISP0_COMMAND_MODE BIT(1) 166 # define DSI_DISP0_ENABLE BIT(0) 167 168 #define DSI0_DISP1_CTRL 0x1c 169 #define DSI1_DISP1_CTRL 0x2c 170 /* Format of the data written to TXPKT_PIX_FIFO. */ 171 # define DSI_DISP1_PFORMAT_MASK VC4_MASK(2, 1) 172 # define DSI_DISP1_PFORMAT_SHIFT 1 173 # define DSI_DISP1_PFORMAT_16BIT 0 174 # define DSI_DISP1_PFORMAT_24BIT 1 175 # define DSI_DISP1_PFORMAT_32BIT_LE 2 176 # define DSI_DISP1_PFORMAT_32BIT_BE 3 177 178 /* DISP1 is always command mode. */ 179 # define DSI_DISP1_ENABLE BIT(0) 180 181 #define DSI0_TXPKT_PIX_FIFO 0x20 /* AKA PIX_FIFO */ 182 183 #define DSI0_INT_STAT 0x24 184 #define DSI0_INT_EN 0x28 185 # define DSI0_INT_FIFO_ERR BIT(25) 186 # define DSI0_INT_CMDC_DONE_MASK VC4_MASK(24, 23) 187 # define DSI0_INT_CMDC_DONE_SHIFT 23 188 # define DSI0_INT_CMDC_DONE_NO_REPEAT 1 189 # define DSI0_INT_CMDC_DONE_REPEAT 3 190 # define DSI0_INT_PHY_DIR_RTF BIT(22) 191 # define DSI0_INT_PHY_D1_ULPS BIT(21) 192 # define DSI0_INT_PHY_D1_STOP BIT(20) 193 # define DSI0_INT_PHY_RXLPDT BIT(19) 194 # define DSI0_INT_PHY_RXTRIG BIT(18) 195 # define DSI0_INT_PHY_D0_ULPS BIT(17) 196 # define DSI0_INT_PHY_D0_LPDT BIT(16) 197 # define DSI0_INT_PHY_D0_FTR BIT(15) 198 # define DSI0_INT_PHY_D0_STOP BIT(14) 199 /* Signaled when the clock lane enters the given state. */ 200 # define DSI0_INT_PHY_CLK_ULPS BIT(13) 201 # define DSI0_INT_PHY_CLK_HS BIT(12) 202 # define DSI0_INT_PHY_CLK_FTR BIT(11) 203 /* Signaled on timeouts */ 204 # define DSI0_INT_PR_TO BIT(10) 205 # define DSI0_INT_TA_TO BIT(9) 206 # define DSI0_INT_LPRX_TO BIT(8) 207 # define DSI0_INT_HSTX_TO BIT(7) 208 /* Contention on a line when trying to drive the line low */ 209 # define DSI0_INT_ERR_CONT_LP1 BIT(6) 210 # define DSI0_INT_ERR_CONT_LP0 BIT(5) 211 /* Control error: incorrect line state sequence on data lane 0. */ 212 # define DSI0_INT_ERR_CONTROL BIT(4) 213 # define DSI0_INT_ERR_SYNC_ESC BIT(3) 214 # define DSI0_INT_RX2_PKT BIT(2) 215 # define DSI0_INT_RX1_PKT BIT(1) 216 # define DSI0_INT_CMD_PKT BIT(0) 217 218 #define DSI0_INTERRUPTS_ALWAYS_ENABLED (DSI0_INT_ERR_SYNC_ESC | \ 219 DSI0_INT_ERR_CONTROL | \ 220 DSI0_INT_ERR_CONT_LP0 | \ 221 DSI0_INT_ERR_CONT_LP1 | \ 222 DSI0_INT_HSTX_TO | \ 223 DSI0_INT_LPRX_TO | \ 224 DSI0_INT_TA_TO | \ 225 DSI0_INT_PR_TO) 226 227 # define DSI1_INT_PHY_D3_ULPS BIT(30) 228 # define DSI1_INT_PHY_D3_STOP BIT(29) 229 # define DSI1_INT_PHY_D2_ULPS BIT(28) 230 # define DSI1_INT_PHY_D2_STOP BIT(27) 231 # define DSI1_INT_PHY_D1_ULPS BIT(26) 232 # define DSI1_INT_PHY_D1_STOP BIT(25) 233 # define DSI1_INT_PHY_D0_ULPS BIT(24) 234 # define DSI1_INT_PHY_D0_STOP BIT(23) 235 # define DSI1_INT_FIFO_ERR BIT(22) 236 # define DSI1_INT_PHY_DIR_RTF BIT(21) 237 # define DSI1_INT_PHY_RXLPDT BIT(20) 238 # define DSI1_INT_PHY_RXTRIG BIT(19) 239 # define DSI1_INT_PHY_D0_LPDT BIT(18) 240 # define DSI1_INT_PHY_DIR_FTR BIT(17) 241 242 /* Signaled when the clock lane enters the given state. */ 243 # define DSI1_INT_PHY_CLOCK_ULPS BIT(16) 244 # define DSI1_INT_PHY_CLOCK_HS BIT(15) 245 # define DSI1_INT_PHY_CLOCK_STOP BIT(14) 246 247 /* Signaled on timeouts */ 248 # define DSI1_INT_PR_TO BIT(13) 249 # define DSI1_INT_TA_TO BIT(12) 250 # define DSI1_INT_LPRX_TO BIT(11) 251 # define DSI1_INT_HSTX_TO BIT(10) 252 253 /* Contention on a line when trying to drive the line low */ 254 # define DSI1_INT_ERR_CONT_LP1 BIT(9) 255 # define DSI1_INT_ERR_CONT_LP0 BIT(8) 256 257 /* Control error: incorrect line state sequence on data lane 0. */ 258 # define DSI1_INT_ERR_CONTROL BIT(7) 259 /* LPDT synchronization error (bits received not a multiple of 8. */ 260 261 # define DSI1_INT_ERR_SYNC_ESC BIT(6) 262 /* Signaled after receiving an error packet from the display in 263 * response to a read. 264 */ 265 # define DSI1_INT_RXPKT2 BIT(5) 266 /* Signaled after receiving a packet. The header and optional short 267 * response will be in RXPKT1H, and a long response will be in the 268 * RXPKT_FIFO. 269 */ 270 # define DSI1_INT_RXPKT1 BIT(4) 271 # define DSI1_INT_TXPKT2_DONE BIT(3) 272 # define DSI1_INT_TXPKT2_END BIT(2) 273 /* Signaled after all repeats of TXPKT1 are transferred. */ 274 # define DSI1_INT_TXPKT1_DONE BIT(1) 275 /* Signaled after each TXPKT1 repeat is scheduled. */ 276 # define DSI1_INT_TXPKT1_END BIT(0) 277 278 #define DSI1_INTERRUPTS_ALWAYS_ENABLED (DSI1_INT_ERR_SYNC_ESC | \ 279 DSI1_INT_ERR_CONTROL | \ 280 DSI1_INT_ERR_CONT_LP0 | \ 281 DSI1_INT_ERR_CONT_LP1 | \ 282 DSI1_INT_HSTX_TO | \ 283 DSI1_INT_LPRX_TO | \ 284 DSI1_INT_TA_TO | \ 285 DSI1_INT_PR_TO) 286 287 #define DSI0_STAT 0x2c 288 #define DSI0_HSTX_TO_CNT 0x30 289 #define DSI0_LPRX_TO_CNT 0x34 290 #define DSI0_TA_TO_CNT 0x38 291 #define DSI0_PR_TO_CNT 0x3c 292 #define DSI0_PHYC 0x40 293 # define DSI1_PHYC_ESC_CLK_LPDT_MASK VC4_MASK(25, 20) 294 # define DSI1_PHYC_ESC_CLK_LPDT_SHIFT 20 295 # define DSI1_PHYC_HS_CLK_CONTINUOUS BIT(18) 296 # define DSI0_PHYC_ESC_CLK_LPDT_MASK VC4_MASK(17, 12) 297 # define DSI0_PHYC_ESC_CLK_LPDT_SHIFT 12 298 # define DSI1_PHYC_CLANE_ULPS BIT(17) 299 # define DSI1_PHYC_CLANE_ENABLE BIT(16) 300 # define DSI_PHYC_DLANE3_ULPS BIT(13) 301 # define DSI_PHYC_DLANE3_ENABLE BIT(12) 302 # define DSI0_PHYC_HS_CLK_CONTINUOUS BIT(10) 303 # define DSI0_PHYC_CLANE_ULPS BIT(9) 304 # define DSI_PHYC_DLANE2_ULPS BIT(9) 305 # define DSI0_PHYC_CLANE_ENABLE BIT(8) 306 # define DSI_PHYC_DLANE2_ENABLE BIT(8) 307 # define DSI_PHYC_DLANE1_ULPS BIT(5) 308 # define DSI_PHYC_DLANE1_ENABLE BIT(4) 309 # define DSI_PHYC_DLANE0_FORCE_STOP BIT(2) 310 # define DSI_PHYC_DLANE0_ULPS BIT(1) 311 # define DSI_PHYC_DLANE0_ENABLE BIT(0) 312 313 #define DSI0_HS_CLT0 0x44 314 #define DSI0_HS_CLT1 0x48 315 #define DSI0_HS_CLT2 0x4c 316 #define DSI0_HS_DLT3 0x50 317 #define DSI0_HS_DLT4 0x54 318 #define DSI0_HS_DLT5 0x58 319 #define DSI0_HS_DLT6 0x5c 320 #define DSI0_HS_DLT7 0x60 321 322 #define DSI0_PHY_AFEC0 0x64 323 # define DSI0_PHY_AFEC0_DDR2CLK_EN BIT(26) 324 # define DSI0_PHY_AFEC0_DDRCLK_EN BIT(25) 325 # define DSI0_PHY_AFEC0_LATCH_ULPS BIT(24) 326 # define DSI1_PHY_AFEC0_IDR_DLANE3_MASK VC4_MASK(31, 29) 327 # define DSI1_PHY_AFEC0_IDR_DLANE3_SHIFT 29 328 # define DSI1_PHY_AFEC0_IDR_DLANE2_MASK VC4_MASK(28, 26) 329 # define DSI1_PHY_AFEC0_IDR_DLANE2_SHIFT 26 330 # define DSI1_PHY_AFEC0_IDR_DLANE1_MASK VC4_MASK(27, 23) 331 # define DSI1_PHY_AFEC0_IDR_DLANE1_SHIFT 23 332 # define DSI1_PHY_AFEC0_IDR_DLANE0_MASK VC4_MASK(22, 20) 333 # define DSI1_PHY_AFEC0_IDR_DLANE0_SHIFT 20 334 # define DSI1_PHY_AFEC0_IDR_CLANE_MASK VC4_MASK(19, 17) 335 # define DSI1_PHY_AFEC0_IDR_CLANE_SHIFT 17 336 # define DSI0_PHY_AFEC0_ACTRL_DLANE1_MASK VC4_MASK(23, 20) 337 # define DSI0_PHY_AFEC0_ACTRL_DLANE1_SHIFT 20 338 # define DSI0_PHY_AFEC0_ACTRL_DLANE0_MASK VC4_MASK(19, 16) 339 # define DSI0_PHY_AFEC0_ACTRL_DLANE0_SHIFT 16 340 # define DSI0_PHY_AFEC0_ACTRL_CLANE_MASK VC4_MASK(15, 12) 341 # define DSI0_PHY_AFEC0_ACTRL_CLANE_SHIFT 12 342 # define DSI1_PHY_AFEC0_DDR2CLK_EN BIT(16) 343 # define DSI1_PHY_AFEC0_DDRCLK_EN BIT(15) 344 # define DSI1_PHY_AFEC0_LATCH_ULPS BIT(14) 345 # define DSI1_PHY_AFEC0_RESET BIT(13) 346 # define DSI1_PHY_AFEC0_PD BIT(12) 347 # define DSI0_PHY_AFEC0_RESET BIT(11) 348 # define DSI1_PHY_AFEC0_PD_BG BIT(11) 349 # define DSI0_PHY_AFEC0_PD BIT(10) 350 # define DSI1_PHY_AFEC0_PD_DLANE1 BIT(10) 351 # define DSI0_PHY_AFEC0_PD_BG BIT(9) 352 # define DSI1_PHY_AFEC0_PD_DLANE2 BIT(9) 353 # define DSI0_PHY_AFEC0_PD_DLANE1 BIT(8) 354 # define DSI1_PHY_AFEC0_PD_DLANE3 BIT(8) 355 # define DSI_PHY_AFEC0_PTATADJ_MASK VC4_MASK(7, 4) 356 # define DSI_PHY_AFEC0_PTATADJ_SHIFT 4 357 # define DSI_PHY_AFEC0_CTATADJ_MASK VC4_MASK(3, 0) 358 # define DSI_PHY_AFEC0_CTATADJ_SHIFT 0 359 360 #define DSI0_PHY_AFEC1 0x68 361 # define DSI0_PHY_AFEC1_IDR_DLANE1_MASK VC4_MASK(10, 8) 362 # define DSI0_PHY_AFEC1_IDR_DLANE1_SHIFT 8 363 # define DSI0_PHY_AFEC1_IDR_DLANE0_MASK VC4_MASK(6, 4) 364 # define DSI0_PHY_AFEC1_IDR_DLANE0_SHIFT 4 365 # define DSI0_PHY_AFEC1_IDR_CLANE_MASK VC4_MASK(2, 0) 366 # define DSI0_PHY_AFEC1_IDR_CLANE_SHIFT 0 367 368 #define DSI0_TST_SEL 0x6c 369 #define DSI0_TST_MON 0x70 370 #define DSI0_ID 0x74 371 # define DSI_ID_VALUE 0x00647369 372 373 #define DSI1_CTRL 0x00 374 # define DSI_CTRL_HS_CLKC_MASK VC4_MASK(15, 14) 375 # define DSI_CTRL_HS_CLKC_SHIFT 14 376 # define DSI_CTRL_HS_CLKC_BYTE 0 377 # define DSI_CTRL_HS_CLKC_DDR2 1 378 # define DSI_CTRL_HS_CLKC_DDR 2 379 380 # define DSI_CTRL_RX_LPDT_EOT_DISABLE BIT(13) 381 # define DSI_CTRL_LPDT_EOT_DISABLE BIT(12) 382 # define DSI_CTRL_HSDT_EOT_DISABLE BIT(11) 383 # define DSI_CTRL_SOFT_RESET_CFG BIT(10) 384 # define DSI_CTRL_CAL_BYTE BIT(9) 385 # define DSI_CTRL_INV_BYTE BIT(8) 386 # define DSI_CTRL_CLR_LDF BIT(7) 387 # define DSI0_CTRL_CLR_PBCF BIT(6) 388 # define DSI1_CTRL_CLR_RXF BIT(6) 389 # define DSI0_CTRL_CLR_CPBCF BIT(5) 390 # define DSI1_CTRL_CLR_PDF BIT(5) 391 # define DSI0_CTRL_CLR_PDF BIT(4) 392 # define DSI1_CTRL_CLR_CDF BIT(4) 393 # define DSI0_CTRL_CLR_CDF BIT(3) 394 # define DSI0_CTRL_CTRL2 BIT(2) 395 # define DSI1_CTRL_DISABLE_DISP_CRCC BIT(2) 396 # define DSI0_CTRL_CTRL1 BIT(1) 397 # define DSI1_CTRL_DISABLE_DISP_ECCC BIT(1) 398 # define DSI0_CTRL_CTRL0 BIT(0) 399 # define DSI1_CTRL_EN BIT(0) 400 # define DSI0_CTRL_RESET_FIFOS (DSI_CTRL_CLR_LDF | \ 401 DSI0_CTRL_CLR_PBCF | \ 402 DSI0_CTRL_CLR_CPBCF | \ 403 DSI0_CTRL_CLR_PDF | \ 404 DSI0_CTRL_CLR_CDF) 405 # define DSI1_CTRL_RESET_FIFOS (DSI_CTRL_CLR_LDF | \ 406 DSI1_CTRL_CLR_RXF | \ 407 DSI1_CTRL_CLR_PDF | \ 408 DSI1_CTRL_CLR_CDF) 409 410 #define DSI1_TXPKT2C 0x0c 411 #define DSI1_TXPKT2H 0x10 412 #define DSI1_TXPKT_PIX_FIFO 0x20 413 #define DSI1_RXPKT_FIFO 0x24 414 #define DSI1_DISP0_CTRL 0x28 415 #define DSI1_INT_STAT 0x30 416 #define DSI1_INT_EN 0x34 417 /* State reporting bits. These mostly behave like INT_STAT, where 418 * writing a 1 clears the bit. 419 */ 420 #define DSI1_STAT 0x38 421 # define DSI1_STAT_PHY_D3_ULPS BIT(31) 422 # define DSI1_STAT_PHY_D3_STOP BIT(30) 423 # define DSI1_STAT_PHY_D2_ULPS BIT(29) 424 # define DSI1_STAT_PHY_D2_STOP BIT(28) 425 # define DSI1_STAT_PHY_D1_ULPS BIT(27) 426 # define DSI1_STAT_PHY_D1_STOP BIT(26) 427 # define DSI1_STAT_PHY_D0_ULPS BIT(25) 428 # define DSI1_STAT_PHY_D0_STOP BIT(24) 429 # define DSI1_STAT_FIFO_ERR BIT(23) 430 # define DSI1_STAT_PHY_RXLPDT BIT(22) 431 # define DSI1_STAT_PHY_RXTRIG BIT(21) 432 # define DSI1_STAT_PHY_D0_LPDT BIT(20) 433 /* Set when in forward direction */ 434 # define DSI1_STAT_PHY_DIR BIT(19) 435 # define DSI1_STAT_PHY_CLOCK_ULPS BIT(18) 436 # define DSI1_STAT_PHY_CLOCK_HS BIT(17) 437 # define DSI1_STAT_PHY_CLOCK_STOP BIT(16) 438 # define DSI1_STAT_PR_TO BIT(15) 439 # define DSI1_STAT_TA_TO BIT(14) 440 # define DSI1_STAT_LPRX_TO BIT(13) 441 # define DSI1_STAT_HSTX_TO BIT(12) 442 # define DSI1_STAT_ERR_CONT_LP1 BIT(11) 443 # define DSI1_STAT_ERR_CONT_LP0 BIT(10) 444 # define DSI1_STAT_ERR_CONTROL BIT(9) 445 # define DSI1_STAT_ERR_SYNC_ESC BIT(8) 446 # define DSI1_STAT_RXPKT2 BIT(7) 447 # define DSI1_STAT_RXPKT1 BIT(6) 448 # define DSI1_STAT_TXPKT2_BUSY BIT(5) 449 # define DSI1_STAT_TXPKT2_DONE BIT(4) 450 # define DSI1_STAT_TXPKT2_END BIT(3) 451 # define DSI1_STAT_TXPKT1_BUSY BIT(2) 452 # define DSI1_STAT_TXPKT1_DONE BIT(1) 453 # define DSI1_STAT_TXPKT1_END BIT(0) 454 455 #define DSI1_HSTX_TO_CNT 0x3c 456 #define DSI1_LPRX_TO_CNT 0x40 457 #define DSI1_TA_TO_CNT 0x44 458 #define DSI1_PR_TO_CNT 0x48 459 #define DSI1_PHYC 0x4c 460 461 #define DSI1_HS_CLT0 0x50 462 # define DSI_HS_CLT0_CZERO_MASK VC4_MASK(26, 18) 463 # define DSI_HS_CLT0_CZERO_SHIFT 18 464 # define DSI_HS_CLT0_CPRE_MASK VC4_MASK(17, 9) 465 # define DSI_HS_CLT0_CPRE_SHIFT 9 466 # define DSI_HS_CLT0_CPREP_MASK VC4_MASK(8, 0) 467 # define DSI_HS_CLT0_CPREP_SHIFT 0 468 469 #define DSI1_HS_CLT1 0x54 470 # define DSI_HS_CLT1_CTRAIL_MASK VC4_MASK(17, 9) 471 # define DSI_HS_CLT1_CTRAIL_SHIFT 9 472 # define DSI_HS_CLT1_CPOST_MASK VC4_MASK(8, 0) 473 # define DSI_HS_CLT1_CPOST_SHIFT 0 474 475 #define DSI1_HS_CLT2 0x58 476 # define DSI_HS_CLT2_WUP_MASK VC4_MASK(23, 0) 477 # define DSI_HS_CLT2_WUP_SHIFT 0 478 479 #define DSI1_HS_DLT3 0x5c 480 # define DSI_HS_DLT3_EXIT_MASK VC4_MASK(26, 18) 481 # define DSI_HS_DLT3_EXIT_SHIFT 18 482 # define DSI_HS_DLT3_ZERO_MASK VC4_MASK(17, 9) 483 # define DSI_HS_DLT3_ZERO_SHIFT 9 484 # define DSI_HS_DLT3_PRE_MASK VC4_MASK(8, 0) 485 # define DSI_HS_DLT3_PRE_SHIFT 0 486 487 #define DSI1_HS_DLT4 0x60 488 # define DSI_HS_DLT4_ANLAT_MASK VC4_MASK(22, 18) 489 # define DSI_HS_DLT4_ANLAT_SHIFT 18 490 # define DSI_HS_DLT4_TRAIL_MASK VC4_MASK(17, 9) 491 # define DSI_HS_DLT4_TRAIL_SHIFT 9 492 # define DSI_HS_DLT4_LPX_MASK VC4_MASK(8, 0) 493 # define DSI_HS_DLT4_LPX_SHIFT 0 494 495 #define DSI1_HS_DLT5 0x64 496 # define DSI_HS_DLT5_INIT_MASK VC4_MASK(23, 0) 497 # define DSI_HS_DLT5_INIT_SHIFT 0 498 499 #define DSI1_HS_DLT6 0x68 500 # define DSI_HS_DLT6_TA_GET_MASK VC4_MASK(31, 24) 501 # define DSI_HS_DLT6_TA_GET_SHIFT 24 502 # define DSI_HS_DLT6_TA_SURE_MASK VC4_MASK(23, 16) 503 # define DSI_HS_DLT6_TA_SURE_SHIFT 16 504 # define DSI_HS_DLT6_TA_GO_MASK VC4_MASK(15, 8) 505 # define DSI_HS_DLT6_TA_GO_SHIFT 8 506 # define DSI_HS_DLT6_LP_LPX_MASK VC4_MASK(7, 0) 507 # define DSI_HS_DLT6_LP_LPX_SHIFT 0 508 509 #define DSI1_HS_DLT7 0x6c 510 # define DSI_HS_DLT7_LP_WUP_MASK VC4_MASK(23, 0) 511 # define DSI_HS_DLT7_LP_WUP_SHIFT 0 512 513 #define DSI1_PHY_AFEC0 0x70 514 515 #define DSI1_PHY_AFEC1 0x74 516 # define DSI1_PHY_AFEC1_ACTRL_DLANE3_MASK VC4_MASK(19, 16) 517 # define DSI1_PHY_AFEC1_ACTRL_DLANE3_SHIFT 16 518 # define DSI1_PHY_AFEC1_ACTRL_DLANE2_MASK VC4_MASK(15, 12) 519 # define DSI1_PHY_AFEC1_ACTRL_DLANE2_SHIFT 12 520 # define DSI1_PHY_AFEC1_ACTRL_DLANE1_MASK VC4_MASK(11, 8) 521 # define DSI1_PHY_AFEC1_ACTRL_DLANE1_SHIFT 8 522 # define DSI1_PHY_AFEC1_ACTRL_DLANE0_MASK VC4_MASK(7, 4) 523 # define DSI1_PHY_AFEC1_ACTRL_DLANE0_SHIFT 4 524 # define DSI1_PHY_AFEC1_ACTRL_CLANE_MASK VC4_MASK(3, 0) 525 # define DSI1_PHY_AFEC1_ACTRL_CLANE_SHIFT 0 526 527 #define DSI1_TST_SEL 0x78 528 #define DSI1_TST_MON 0x7c 529 #define DSI1_PHY_TST1 0x80 530 #define DSI1_PHY_TST2 0x84 531 #define DSI1_PHY_FIFO_STAT 0x88 532 /* Actually, all registers in the range that aren't otherwise claimed 533 * will return the ID. 534 */ 535 #define DSI1_ID 0x8c 536 537 struct vc4_dsi_variant { 538 /* Whether we're on bcm2835's DSI0 or DSI1. */ 539 unsigned int port; 540 541 bool broken_axi_workaround; 542 543 const char *debugfs_name; 544 const struct debugfs_reg32 *regs; 545 size_t nregs; 546 547 }; 548 549 /* General DSI hardware state. */ 550 struct vc4_dsi { 551 struct vc4_encoder encoder; 552 struct mipi_dsi_host dsi_host; 553 554 struct kref kref; 555 556 struct platform_device *pdev; 557 558 struct drm_bridge *out_bridge; 559 struct drm_bridge bridge; 560 561 void __iomem *regs; 562 563 struct dma_chan *reg_dma_chan; 564 dma_addr_t reg_dma_paddr; 565 u32 *reg_dma_mem; 566 dma_addr_t reg_paddr; 567 568 const struct vc4_dsi_variant *variant; 569 570 /* DSI channel for the panel we're connected to. */ 571 u32 channel; 572 u32 lanes; 573 u32 format; 574 u32 divider; 575 u32 mode_flags; 576 577 /* Input clock from CPRMAN to the digital PHY, for the DSI 578 * escape clock. 579 */ 580 struct clk *escape_clock; 581 582 /* Input clock to the analog PHY, used to generate the DSI bit 583 * clock. 584 */ 585 struct clk *pll_phy_clock; 586 587 /* HS Clocks generated within the DSI analog PHY. */ 588 struct clk_fixed_factor phy_clocks[3]; 589 590 struct clk_hw_onecell_data *clk_onecell; 591 592 /* Pixel clock output to the pixelvalve, generated from the HS 593 * clock. 594 */ 595 struct clk *pixel_clock; 596 597 struct completion xfer_completion; 598 int xfer_result; 599 600 struct debugfs_regset32 regset; 601 }; 602 603 #define host_to_dsi(host) container_of(host, struct vc4_dsi, dsi_host) 604 605 static inline struct vc4_dsi * 606 to_vc4_dsi(struct drm_encoder *encoder) 607 { 608 return container_of(encoder, struct vc4_dsi, encoder.base); 609 } 610 611 static inline struct vc4_dsi * 612 bridge_to_vc4_dsi(struct drm_bridge *bridge) 613 { 614 return container_of(bridge, struct vc4_dsi, bridge); 615 } 616 617 static inline void 618 dsi_dma_workaround_write(struct vc4_dsi *dsi, u32 offset, u32 val) 619 { 620 struct dma_chan *chan = dsi->reg_dma_chan; 621 struct dma_async_tx_descriptor *tx; 622 dma_cookie_t cookie; 623 int ret; 624 625 kunit_fail_current_test("Accessing a register in a unit test!\n"); 626 627 /* DSI0 should be able to write normally. */ 628 if (!chan) { 629 writel(val, dsi->regs + offset); 630 return; 631 } 632 633 *dsi->reg_dma_mem = val; 634 635 tx = chan->device->device_prep_dma_memcpy(chan, 636 dsi->reg_paddr + offset, 637 dsi->reg_dma_paddr, 638 4, 0); 639 if (!tx) { 640 DRM_ERROR("Failed to set up DMA register write\n"); 641 return; 642 } 643 644 cookie = tx->tx_submit(tx); 645 ret = dma_submit_error(cookie); 646 if (ret) { 647 DRM_ERROR("Failed to submit DMA: %d\n", ret); 648 return; 649 } 650 ret = dma_sync_wait(chan, cookie); 651 if (ret) 652 DRM_ERROR("Failed to wait for DMA: %d\n", ret); 653 } 654 655 #define DSI_READ(offset) \ 656 ({ \ 657 kunit_fail_current_test("Accessing a register in a unit test!\n"); \ 658 readl(dsi->regs + (offset)); \ 659 }) 660 661 #define DSI_WRITE(offset, val) dsi_dma_workaround_write(dsi, offset, val) 662 #define DSI_PORT_READ(offset) \ 663 DSI_READ(dsi->variant->port ? DSI1_##offset : DSI0_##offset) 664 #define DSI_PORT_WRITE(offset, val) \ 665 DSI_WRITE(dsi->variant->port ? DSI1_##offset : DSI0_##offset, val) 666 #define DSI_PORT_BIT(bit) (dsi->variant->port ? DSI1_##bit : DSI0_##bit) 667 668 static const struct debugfs_reg32 dsi0_regs[] = { 669 VC4_REG32(DSI0_CTRL), 670 VC4_REG32(DSI0_STAT), 671 VC4_REG32(DSI0_HSTX_TO_CNT), 672 VC4_REG32(DSI0_LPRX_TO_CNT), 673 VC4_REG32(DSI0_TA_TO_CNT), 674 VC4_REG32(DSI0_PR_TO_CNT), 675 VC4_REG32(DSI0_DISP0_CTRL), 676 VC4_REG32(DSI0_DISP1_CTRL), 677 VC4_REG32(DSI0_INT_STAT), 678 VC4_REG32(DSI0_INT_EN), 679 VC4_REG32(DSI0_PHYC), 680 VC4_REG32(DSI0_HS_CLT0), 681 VC4_REG32(DSI0_HS_CLT1), 682 VC4_REG32(DSI0_HS_CLT2), 683 VC4_REG32(DSI0_HS_DLT3), 684 VC4_REG32(DSI0_HS_DLT4), 685 VC4_REG32(DSI0_HS_DLT5), 686 VC4_REG32(DSI0_HS_DLT6), 687 VC4_REG32(DSI0_HS_DLT7), 688 VC4_REG32(DSI0_PHY_AFEC0), 689 VC4_REG32(DSI0_PHY_AFEC1), 690 VC4_REG32(DSI0_ID), 691 }; 692 693 static const struct debugfs_reg32 dsi1_regs[] = { 694 VC4_REG32(DSI1_CTRL), 695 VC4_REG32(DSI1_STAT), 696 VC4_REG32(DSI1_HSTX_TO_CNT), 697 VC4_REG32(DSI1_LPRX_TO_CNT), 698 VC4_REG32(DSI1_TA_TO_CNT), 699 VC4_REG32(DSI1_PR_TO_CNT), 700 VC4_REG32(DSI1_DISP0_CTRL), 701 VC4_REG32(DSI1_DISP1_CTRL), 702 VC4_REG32(DSI1_INT_STAT), 703 VC4_REG32(DSI1_INT_EN), 704 VC4_REG32(DSI1_PHYC), 705 VC4_REG32(DSI1_HS_CLT0), 706 VC4_REG32(DSI1_HS_CLT1), 707 VC4_REG32(DSI1_HS_CLT2), 708 VC4_REG32(DSI1_HS_DLT3), 709 VC4_REG32(DSI1_HS_DLT4), 710 VC4_REG32(DSI1_HS_DLT5), 711 VC4_REG32(DSI1_HS_DLT6), 712 VC4_REG32(DSI1_HS_DLT7), 713 VC4_REG32(DSI1_PHY_AFEC0), 714 VC4_REG32(DSI1_PHY_AFEC1), 715 VC4_REG32(DSI1_ID), 716 }; 717 718 static void vc4_dsi_latch_ulps(struct vc4_dsi *dsi, bool latch) 719 { 720 u32 afec0 = DSI_PORT_READ(PHY_AFEC0); 721 722 if (latch) 723 afec0 |= DSI_PORT_BIT(PHY_AFEC0_LATCH_ULPS); 724 else 725 afec0 &= ~DSI_PORT_BIT(PHY_AFEC0_LATCH_ULPS); 726 727 DSI_PORT_WRITE(PHY_AFEC0, afec0); 728 } 729 730 /* Enters or exits Ultra Low Power State. */ 731 static void vc4_dsi_ulps(struct vc4_dsi *dsi, bool ulps) 732 { 733 bool non_continuous = dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS; 734 u32 phyc_ulps = ((non_continuous ? DSI_PORT_BIT(PHYC_CLANE_ULPS) : 0) | 735 DSI_PHYC_DLANE0_ULPS | 736 (dsi->lanes > 1 ? DSI_PHYC_DLANE1_ULPS : 0) | 737 (dsi->lanes > 2 ? DSI_PHYC_DLANE2_ULPS : 0) | 738 (dsi->lanes > 3 ? DSI_PHYC_DLANE3_ULPS : 0)); 739 u32 stat_ulps = ((non_continuous ? DSI1_STAT_PHY_CLOCK_ULPS : 0) | 740 DSI1_STAT_PHY_D0_ULPS | 741 (dsi->lanes > 1 ? DSI1_STAT_PHY_D1_ULPS : 0) | 742 (dsi->lanes > 2 ? DSI1_STAT_PHY_D2_ULPS : 0) | 743 (dsi->lanes > 3 ? DSI1_STAT_PHY_D3_ULPS : 0)); 744 u32 stat_stop = ((non_continuous ? DSI1_STAT_PHY_CLOCK_STOP : 0) | 745 DSI1_STAT_PHY_D0_STOP | 746 (dsi->lanes > 1 ? DSI1_STAT_PHY_D1_STOP : 0) | 747 (dsi->lanes > 2 ? DSI1_STAT_PHY_D2_STOP : 0) | 748 (dsi->lanes > 3 ? DSI1_STAT_PHY_D3_STOP : 0)); 749 int ret; 750 bool ulps_currently_enabled = (DSI_PORT_READ(PHY_AFEC0) & 751 DSI_PORT_BIT(PHY_AFEC0_LATCH_ULPS)); 752 753 if (ulps == ulps_currently_enabled) 754 return; 755 756 DSI_PORT_WRITE(STAT, stat_ulps); 757 DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) | phyc_ulps); 758 ret = wait_for((DSI_PORT_READ(STAT) & stat_ulps) == stat_ulps, 200); 759 if (ret) { 760 dev_warn(&dsi->pdev->dev, 761 "Timeout waiting for DSI ULPS entry: STAT 0x%08x", 762 DSI_PORT_READ(STAT)); 763 DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) & ~phyc_ulps); 764 vc4_dsi_latch_ulps(dsi, false); 765 return; 766 } 767 768 /* The DSI module can't be disabled while the module is 769 * generating ULPS state. So, to be able to disable the 770 * module, we have the AFE latch the ULPS state and continue 771 * on to having the module enter STOP. 772 */ 773 vc4_dsi_latch_ulps(dsi, ulps); 774 775 DSI_PORT_WRITE(STAT, stat_stop); 776 DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) & ~phyc_ulps); 777 ret = wait_for((DSI_PORT_READ(STAT) & stat_stop) == stat_stop, 200); 778 if (ret) { 779 dev_warn(&dsi->pdev->dev, 780 "Timeout waiting for DSI STOP entry: STAT 0x%08x", 781 DSI_PORT_READ(STAT)); 782 DSI_PORT_WRITE(PHYC, DSI_PORT_READ(PHYC) & ~phyc_ulps); 783 return; 784 } 785 } 786 787 static u32 788 dsi_hs_timing(u32 ui_ns, u32 ns, u32 ui) 789 { 790 /* The HS timings have to be rounded up to a multiple of 8 791 * because we're using the byte clock. 792 */ 793 return roundup(ui + DIV_ROUND_UP(ns, ui_ns), 8); 794 } 795 796 /* ESC always runs at 100Mhz. */ 797 #define ESC_TIME_NS 10 798 799 static u32 800 dsi_esc_timing(u32 ns) 801 { 802 return DIV_ROUND_UP(ns, ESC_TIME_NS); 803 } 804 805 static void vc4_dsi_bridge_disable(struct drm_bridge *bridge, 806 struct drm_bridge_state *state) 807 { 808 struct vc4_dsi *dsi = bridge_to_vc4_dsi(bridge); 809 u32 disp0_ctrl; 810 811 disp0_ctrl = DSI_PORT_READ(DISP0_CTRL); 812 disp0_ctrl &= ~DSI_DISP0_ENABLE; 813 DSI_PORT_WRITE(DISP0_CTRL, disp0_ctrl); 814 } 815 816 static void vc4_dsi_bridge_post_disable(struct drm_bridge *bridge, 817 struct drm_bridge_state *state) 818 { 819 struct vc4_dsi *dsi = bridge_to_vc4_dsi(bridge); 820 struct device *dev = &dsi->pdev->dev; 821 822 clk_disable_unprepare(dsi->pll_phy_clock); 823 clk_disable_unprepare(dsi->escape_clock); 824 clk_disable_unprepare(dsi->pixel_clock); 825 826 pm_runtime_put(dev); 827 } 828 829 /* Extends the mode's blank intervals to handle BCM2835's integer-only 830 * DSI PLL divider. 831 * 832 * On 2835, PLLD is set to 2Ghz, and may not be changed by the display 833 * driver since most peripherals are hanging off of the PLLD_PER 834 * divider. PLLD_DSI1, which drives our DSI bit clock (and therefore 835 * the pixel clock), only has an integer divider off of DSI. 836 * 837 * To get our panel mode to refresh at the expected 60Hz, we need to 838 * extend the horizontal blank time. This means we drive a 839 * higher-than-expected clock rate to the panel, but that's what the 840 * firmware does too. 841 */ 842 static bool vc4_dsi_bridge_mode_fixup(struct drm_bridge *bridge, 843 const struct drm_display_mode *mode, 844 struct drm_display_mode *adjusted_mode) 845 { 846 struct vc4_dsi *dsi = bridge_to_vc4_dsi(bridge); 847 struct clk *phy_parent = clk_get_parent(dsi->pll_phy_clock); 848 unsigned long parent_rate = clk_get_rate(phy_parent); 849 unsigned long pixel_clock_hz = mode->clock * 1000; 850 unsigned long pll_clock = pixel_clock_hz * dsi->divider; 851 int divider; 852 853 /* Find what divider gets us a faster clock than the requested 854 * pixel clock. 855 */ 856 for (divider = 1; divider < 255; divider++) { 857 if (parent_rate / (divider + 1) < pll_clock) 858 break; 859 } 860 861 /* Now that we've picked a PLL divider, calculate back to its 862 * pixel clock. 863 */ 864 pll_clock = parent_rate / divider; 865 pixel_clock_hz = pll_clock / dsi->divider; 866 867 adjusted_mode->clock = pixel_clock_hz / 1000; 868 869 /* Given the new pixel clock, adjust HFP to keep vrefresh the same. */ 870 adjusted_mode->htotal = adjusted_mode->clock * mode->htotal / 871 mode->clock; 872 adjusted_mode->hsync_end += adjusted_mode->htotal - mode->htotal; 873 adjusted_mode->hsync_start += adjusted_mode->htotal - mode->htotal; 874 875 return true; 876 } 877 878 static void vc4_dsi_bridge_pre_enable(struct drm_bridge *bridge, 879 struct drm_bridge_state *old_state) 880 { 881 struct drm_atomic_state *state = old_state->base.state; 882 struct vc4_dsi *dsi = bridge_to_vc4_dsi(bridge); 883 const struct drm_crtc_state *crtc_state; 884 struct device *dev = &dsi->pdev->dev; 885 const struct drm_display_mode *mode; 886 struct drm_connector *connector; 887 bool debug_dump_regs = false; 888 unsigned long hs_clock; 889 struct drm_crtc *crtc; 890 u32 ui_ns; 891 /* Minimum LP state duration in escape clock cycles. */ 892 u32 lpx = dsi_esc_timing(60); 893 unsigned long pixel_clock_hz; 894 unsigned long dsip_clock; 895 unsigned long phy_clock; 896 int ret; 897 898 ret = pm_runtime_resume_and_get(dev); 899 if (ret) { 900 DRM_ERROR("Failed to runtime PM enable on DSI%d\n", dsi->variant->port); 901 return; 902 } 903 904 if (debug_dump_regs) { 905 struct drm_printer p = drm_info_printer(&dsi->pdev->dev); 906 dev_info(&dsi->pdev->dev, "DSI regs before:\n"); 907 drm_print_regset32(&p, &dsi->regset); 908 } 909 910 /* 911 * Retrieve the CRTC adjusted mode. This requires a little dance to go 912 * from the bridge to the encoder, to the connector and to the CRTC. 913 */ 914 connector = drm_atomic_get_new_connector_for_encoder(state, 915 bridge->encoder); 916 crtc = drm_atomic_get_new_connector_state(state, connector)->crtc; 917 crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 918 mode = &crtc_state->adjusted_mode; 919 920 pixel_clock_hz = mode->clock * 1000; 921 922 /* Round up the clk_set_rate() request slightly, since 923 * PLLD_DSI1 is an integer divider and its rate selection will 924 * never round up. 925 */ 926 phy_clock = (pixel_clock_hz + 1000) * dsi->divider; 927 ret = clk_set_rate(dsi->pll_phy_clock, phy_clock); 928 if (ret) { 929 dev_err(&dsi->pdev->dev, 930 "Failed to set phy clock to %ld: %d\n", phy_clock, ret); 931 } 932 933 /* Reset the DSI and all its fifos. */ 934 DSI_PORT_WRITE(CTRL, 935 DSI_CTRL_SOFT_RESET_CFG | 936 DSI_PORT_BIT(CTRL_RESET_FIFOS)); 937 938 DSI_PORT_WRITE(CTRL, 939 DSI_CTRL_HSDT_EOT_DISABLE | 940 DSI_CTRL_RX_LPDT_EOT_DISABLE); 941 942 /* Clear all stat bits so we see what has happened during enable. */ 943 DSI_PORT_WRITE(STAT, DSI_PORT_READ(STAT)); 944 945 /* Set AFE CTR00/CTR1 to release powerdown of analog. */ 946 if (dsi->variant->port == 0) { 947 u32 afec0 = (VC4_SET_FIELD(7, DSI_PHY_AFEC0_PTATADJ) | 948 VC4_SET_FIELD(7, DSI_PHY_AFEC0_CTATADJ)); 949 950 if (dsi->lanes < 2) 951 afec0 |= DSI0_PHY_AFEC0_PD_DLANE1; 952 953 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO)) 954 afec0 |= DSI0_PHY_AFEC0_RESET; 955 956 DSI_PORT_WRITE(PHY_AFEC0, afec0); 957 958 /* AFEC reset hold time */ 959 mdelay(1); 960 961 DSI_PORT_WRITE(PHY_AFEC1, 962 VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_DLANE1) | 963 VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_DLANE0) | 964 VC4_SET_FIELD(6, DSI0_PHY_AFEC1_IDR_CLANE)); 965 } else { 966 u32 afec0 = (VC4_SET_FIELD(7, DSI_PHY_AFEC0_PTATADJ) | 967 VC4_SET_FIELD(7, DSI_PHY_AFEC0_CTATADJ) | 968 VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_CLANE) | 969 VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE0) | 970 VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE1) | 971 VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE2) | 972 VC4_SET_FIELD(6, DSI1_PHY_AFEC0_IDR_DLANE3)); 973 974 if (dsi->lanes < 4) 975 afec0 |= DSI1_PHY_AFEC0_PD_DLANE3; 976 if (dsi->lanes < 3) 977 afec0 |= DSI1_PHY_AFEC0_PD_DLANE2; 978 if (dsi->lanes < 2) 979 afec0 |= DSI1_PHY_AFEC0_PD_DLANE1; 980 981 afec0 |= DSI1_PHY_AFEC0_RESET; 982 983 DSI_PORT_WRITE(PHY_AFEC0, afec0); 984 985 DSI_PORT_WRITE(PHY_AFEC1, 0); 986 987 /* AFEC reset hold time */ 988 mdelay(1); 989 } 990 991 ret = clk_prepare_enable(dsi->escape_clock); 992 if (ret) { 993 DRM_ERROR("Failed to turn on DSI escape clock: %d\n", ret); 994 return; 995 } 996 997 ret = clk_prepare_enable(dsi->pll_phy_clock); 998 if (ret) { 999 DRM_ERROR("Failed to turn on DSI PLL: %d\n", ret); 1000 return; 1001 } 1002 1003 hs_clock = clk_get_rate(dsi->pll_phy_clock); 1004 1005 /* Yes, we set the DSI0P/DSI1P pixel clock to the byte rate, 1006 * not the pixel clock rate. DSIxP take from the APHY's byte, 1007 * DDR2, or DDR4 clock (we use byte) and feed into the PV at 1008 * that rate. Separately, a value derived from PIX_CLK_DIV 1009 * and HS_CLKC is fed into the PV to divide down to the actual 1010 * pixel clock for pushing pixels into DSI. 1011 */ 1012 dsip_clock = phy_clock / 8; 1013 ret = clk_set_rate(dsi->pixel_clock, dsip_clock); 1014 if (ret) { 1015 dev_err(dev, "Failed to set pixel clock to %ldHz: %d\n", 1016 dsip_clock, ret); 1017 } 1018 1019 ret = clk_prepare_enable(dsi->pixel_clock); 1020 if (ret) { 1021 DRM_ERROR("Failed to turn on DSI pixel clock: %d\n", ret); 1022 return; 1023 } 1024 1025 /* How many ns one DSI unit interval is. Note that the clock 1026 * is DDR, so there's an extra divide by 2. 1027 */ 1028 ui_ns = DIV_ROUND_UP(500000000, hs_clock); 1029 1030 DSI_PORT_WRITE(HS_CLT0, 1031 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 262, 0), 1032 DSI_HS_CLT0_CZERO) | 1033 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 0, 8), 1034 DSI_HS_CLT0_CPRE) | 1035 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 38, 0), 1036 DSI_HS_CLT0_CPREP)); 1037 1038 DSI_PORT_WRITE(HS_CLT1, 1039 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 60, 0), 1040 DSI_HS_CLT1_CTRAIL) | 1041 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 60, 52), 1042 DSI_HS_CLT1_CPOST)); 1043 1044 DSI_PORT_WRITE(HS_CLT2, 1045 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 1000000, 0), 1046 DSI_HS_CLT2_WUP)); 1047 1048 DSI_PORT_WRITE(HS_DLT3, 1049 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 100, 0), 1050 DSI_HS_DLT3_EXIT) | 1051 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 105, 6), 1052 DSI_HS_DLT3_ZERO) | 1053 VC4_SET_FIELD(dsi_hs_timing(ui_ns, 40, 4), 1054 DSI_HS_DLT3_PRE)); 1055 1056 DSI_PORT_WRITE(HS_DLT4, 1057 VC4_SET_FIELD(dsi_hs_timing(ui_ns, lpx * ESC_TIME_NS, 0), 1058 DSI_HS_DLT4_LPX) | 1059 VC4_SET_FIELD(max(dsi_hs_timing(ui_ns, 0, 8), 1060 dsi_hs_timing(ui_ns, 60, 4)), 1061 DSI_HS_DLT4_TRAIL) | 1062 VC4_SET_FIELD(0, DSI_HS_DLT4_ANLAT)); 1063 1064 /* T_INIT is how long STOP is driven after power-up to 1065 * indicate to the slave (also coming out of power-up) that 1066 * master init is complete, and should be greater than the 1067 * maximum of two value: T_INIT,MASTER and T_INIT,SLAVE. The 1068 * D-PHY spec gives a minimum 100us for T_INIT,MASTER and 1069 * T_INIT,SLAVE, while allowing protocols on top of it to give 1070 * greater minimums. The vc4 firmware uses an extremely 1071 * conservative 5ms, and we maintain that here. 1072 */ 1073 DSI_PORT_WRITE(HS_DLT5, VC4_SET_FIELD(dsi_hs_timing(ui_ns, 1074 5 * 1000 * 1000, 0), 1075 DSI_HS_DLT5_INIT)); 1076 1077 DSI_PORT_WRITE(HS_DLT6, 1078 VC4_SET_FIELD(lpx * 5, DSI_HS_DLT6_TA_GET) | 1079 VC4_SET_FIELD(lpx, DSI_HS_DLT6_TA_SURE) | 1080 VC4_SET_FIELD(lpx * 4, DSI_HS_DLT6_TA_GO) | 1081 VC4_SET_FIELD(lpx, DSI_HS_DLT6_LP_LPX)); 1082 1083 DSI_PORT_WRITE(HS_DLT7, 1084 VC4_SET_FIELD(dsi_esc_timing(1000000), 1085 DSI_HS_DLT7_LP_WUP)); 1086 1087 DSI_PORT_WRITE(PHYC, 1088 DSI_PHYC_DLANE0_ENABLE | 1089 (dsi->lanes >= 2 ? DSI_PHYC_DLANE1_ENABLE : 0) | 1090 (dsi->lanes >= 3 ? DSI_PHYC_DLANE2_ENABLE : 0) | 1091 (dsi->lanes >= 4 ? DSI_PHYC_DLANE3_ENABLE : 0) | 1092 DSI_PORT_BIT(PHYC_CLANE_ENABLE) | 1093 ((dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) ? 1094 0 : DSI_PORT_BIT(PHYC_HS_CLK_CONTINUOUS)) | 1095 (dsi->variant->port == 0 ? 1096 VC4_SET_FIELD(lpx - 1, DSI0_PHYC_ESC_CLK_LPDT) : 1097 VC4_SET_FIELD(lpx - 1, DSI1_PHYC_ESC_CLK_LPDT))); 1098 1099 DSI_PORT_WRITE(CTRL, 1100 DSI_PORT_READ(CTRL) | 1101 DSI_CTRL_CAL_BYTE); 1102 1103 /* HS timeout in HS clock cycles: disabled. */ 1104 DSI_PORT_WRITE(HSTX_TO_CNT, 0); 1105 /* LP receive timeout in HS clocks. */ 1106 DSI_PORT_WRITE(LPRX_TO_CNT, 0xffffff); 1107 /* Bus turnaround timeout */ 1108 DSI_PORT_WRITE(TA_TO_CNT, 100000); 1109 /* Display reset sequence timeout */ 1110 DSI_PORT_WRITE(PR_TO_CNT, 100000); 1111 1112 /* Set up DISP1 for transferring long command payloads through 1113 * the pixfifo. 1114 */ 1115 DSI_PORT_WRITE(DISP1_CTRL, 1116 VC4_SET_FIELD(DSI_DISP1_PFORMAT_32BIT_LE, 1117 DSI_DISP1_PFORMAT) | 1118 DSI_DISP1_ENABLE); 1119 1120 /* Ungate the block. */ 1121 if (dsi->variant->port == 0) 1122 DSI_PORT_WRITE(CTRL, DSI_PORT_READ(CTRL) | DSI0_CTRL_CTRL0); 1123 else 1124 DSI_PORT_WRITE(CTRL, DSI_PORT_READ(CTRL) | DSI1_CTRL_EN); 1125 1126 /* Bring AFE out of reset. */ 1127 DSI_PORT_WRITE(PHY_AFEC0, 1128 DSI_PORT_READ(PHY_AFEC0) & 1129 ~DSI_PORT_BIT(PHY_AFEC0_RESET)); 1130 1131 vc4_dsi_ulps(dsi, false); 1132 1133 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { 1134 DSI_PORT_WRITE(DISP0_CTRL, 1135 VC4_SET_FIELD(dsi->divider, 1136 DSI_DISP0_PIX_CLK_DIV) | 1137 VC4_SET_FIELD(dsi->format, DSI_DISP0_PFORMAT) | 1138 VC4_SET_FIELD(DSI_DISP0_LP_STOP_PERFRAME, 1139 DSI_DISP0_LP_STOP_CTRL) | 1140 DSI_DISP0_ST_END); 1141 } else { 1142 DSI_PORT_WRITE(DISP0_CTRL, 1143 DSI_DISP0_COMMAND_MODE); 1144 } 1145 } 1146 1147 static void vc4_dsi_bridge_enable(struct drm_bridge *bridge, 1148 struct drm_bridge_state *old_state) 1149 { 1150 struct vc4_dsi *dsi = bridge_to_vc4_dsi(bridge); 1151 bool debug_dump_regs = false; 1152 u32 disp0_ctrl; 1153 1154 disp0_ctrl = DSI_PORT_READ(DISP0_CTRL); 1155 disp0_ctrl |= DSI_DISP0_ENABLE; 1156 DSI_PORT_WRITE(DISP0_CTRL, disp0_ctrl); 1157 1158 if (debug_dump_regs) { 1159 struct drm_printer p = drm_info_printer(&dsi->pdev->dev); 1160 dev_info(&dsi->pdev->dev, "DSI regs after:\n"); 1161 drm_print_regset32(&p, &dsi->regset); 1162 } 1163 } 1164 1165 static int vc4_dsi_bridge_attach(struct drm_bridge *bridge, 1166 enum drm_bridge_attach_flags flags) 1167 { 1168 struct vc4_dsi *dsi = bridge_to_vc4_dsi(bridge); 1169 1170 /* Attach the panel or bridge to the dsi bridge */ 1171 return drm_bridge_attach(bridge->encoder, dsi->out_bridge, 1172 &dsi->bridge, flags); 1173 } 1174 1175 static ssize_t vc4_dsi_host_transfer(struct mipi_dsi_host *host, 1176 const struct mipi_dsi_msg *msg) 1177 { 1178 struct vc4_dsi *dsi = host_to_dsi(host); 1179 struct mipi_dsi_packet packet; 1180 u32 pkth = 0, pktc = 0; 1181 int i, ret; 1182 bool is_long = mipi_dsi_packet_format_is_long(msg->type); 1183 u32 cmd_fifo_len = 0, pix_fifo_len = 0; 1184 1185 mipi_dsi_create_packet(&packet, msg); 1186 1187 pkth |= VC4_SET_FIELD(packet.header[0], DSI_TXPKT1H_BC_DT); 1188 pkth |= VC4_SET_FIELD(packet.header[1] | 1189 (packet.header[2] << 8), 1190 DSI_TXPKT1H_BC_PARAM); 1191 if (is_long) { 1192 /* Divide data across the various FIFOs we have available. 1193 * The command FIFO takes byte-oriented data, but is of 1194 * limited size. The pixel FIFO (never actually used for 1195 * pixel data in reality) is word oriented, and substantially 1196 * larger. So, we use the pixel FIFO for most of the data, 1197 * sending the residual bytes in the command FIFO at the start. 1198 * 1199 * With this arrangement, the command FIFO will never get full. 1200 */ 1201 if (packet.payload_length <= 16) { 1202 cmd_fifo_len = packet.payload_length; 1203 pix_fifo_len = 0; 1204 } else { 1205 cmd_fifo_len = (packet.payload_length % 1206 DSI_PIX_FIFO_WIDTH); 1207 pix_fifo_len = ((packet.payload_length - cmd_fifo_len) / 1208 DSI_PIX_FIFO_WIDTH); 1209 } 1210 1211 WARN_ON_ONCE(pix_fifo_len >= DSI_PIX_FIFO_DEPTH); 1212 1213 pkth |= VC4_SET_FIELD(cmd_fifo_len, DSI_TXPKT1H_BC_CMDFIFO); 1214 } 1215 1216 if (msg->rx_len) { 1217 pktc |= VC4_SET_FIELD(DSI_TXPKT1C_CMD_CTRL_RX, 1218 DSI_TXPKT1C_CMD_CTRL); 1219 } else { 1220 pktc |= VC4_SET_FIELD(DSI_TXPKT1C_CMD_CTRL_TX, 1221 DSI_TXPKT1C_CMD_CTRL); 1222 } 1223 1224 for (i = 0; i < cmd_fifo_len; i++) 1225 DSI_PORT_WRITE(TXPKT_CMD_FIFO, packet.payload[i]); 1226 for (i = 0; i < pix_fifo_len; i++) { 1227 const u8 *pix = packet.payload + cmd_fifo_len + i * 4; 1228 1229 DSI_PORT_WRITE(TXPKT_PIX_FIFO, 1230 pix[0] | 1231 pix[1] << 8 | 1232 pix[2] << 16 | 1233 pix[3] << 24); 1234 } 1235 1236 if (msg->flags & MIPI_DSI_MSG_USE_LPM) 1237 pktc |= DSI_TXPKT1C_CMD_MODE_LP; 1238 if (is_long) 1239 pktc |= DSI_TXPKT1C_CMD_TYPE_LONG; 1240 1241 /* Send one copy of the packet. Larger repeats are used for pixel 1242 * data in command mode. 1243 */ 1244 pktc |= VC4_SET_FIELD(1, DSI_TXPKT1C_CMD_REPEAT); 1245 1246 pktc |= DSI_TXPKT1C_CMD_EN; 1247 if (pix_fifo_len) { 1248 pktc |= VC4_SET_FIELD(DSI_TXPKT1C_DISPLAY_NO_SECONDARY, 1249 DSI_TXPKT1C_DISPLAY_NO); 1250 } else { 1251 pktc |= VC4_SET_FIELD(DSI_TXPKT1C_DISPLAY_NO_SHORT, 1252 DSI_TXPKT1C_DISPLAY_NO); 1253 } 1254 1255 /* Enable the appropriate interrupt for the transfer completion. */ 1256 dsi->xfer_result = 0; 1257 reinit_completion(&dsi->xfer_completion); 1258 if (dsi->variant->port == 0) { 1259 DSI_PORT_WRITE(INT_STAT, 1260 DSI0_INT_CMDC_DONE_MASK | DSI1_INT_PHY_DIR_RTF); 1261 if (msg->rx_len) { 1262 DSI_PORT_WRITE(INT_EN, (DSI0_INTERRUPTS_ALWAYS_ENABLED | 1263 DSI0_INT_PHY_DIR_RTF)); 1264 } else { 1265 DSI_PORT_WRITE(INT_EN, 1266 (DSI0_INTERRUPTS_ALWAYS_ENABLED | 1267 VC4_SET_FIELD(DSI0_INT_CMDC_DONE_NO_REPEAT, 1268 DSI0_INT_CMDC_DONE))); 1269 } 1270 } else { 1271 DSI_PORT_WRITE(INT_STAT, 1272 DSI1_INT_TXPKT1_DONE | DSI1_INT_PHY_DIR_RTF); 1273 if (msg->rx_len) { 1274 DSI_PORT_WRITE(INT_EN, (DSI1_INTERRUPTS_ALWAYS_ENABLED | 1275 DSI1_INT_PHY_DIR_RTF)); 1276 } else { 1277 DSI_PORT_WRITE(INT_EN, (DSI1_INTERRUPTS_ALWAYS_ENABLED | 1278 DSI1_INT_TXPKT1_DONE)); 1279 } 1280 } 1281 1282 /* Send the packet. */ 1283 DSI_PORT_WRITE(TXPKT1H, pkth); 1284 DSI_PORT_WRITE(TXPKT1C, pktc); 1285 1286 if (!wait_for_completion_timeout(&dsi->xfer_completion, 1287 msecs_to_jiffies(1000))) { 1288 dev_err(&dsi->pdev->dev, "transfer interrupt wait timeout"); 1289 dev_err(&dsi->pdev->dev, "instat: 0x%08x\n", 1290 DSI_PORT_READ(INT_STAT)); 1291 ret = -ETIMEDOUT; 1292 } else { 1293 ret = dsi->xfer_result; 1294 } 1295 1296 DSI_PORT_WRITE(INT_EN, DSI_PORT_BIT(INTERRUPTS_ALWAYS_ENABLED)); 1297 1298 if (ret) 1299 goto reset_fifo_and_return; 1300 1301 if (ret == 0 && msg->rx_len) { 1302 u32 rxpkt1h = DSI_PORT_READ(RXPKT1H); 1303 u8 *msg_rx = msg->rx_buf; 1304 1305 if (rxpkt1h & DSI_RXPKT1H_PKT_TYPE_LONG) { 1306 u32 rxlen = VC4_GET_FIELD(rxpkt1h, 1307 DSI_RXPKT1H_BC_PARAM); 1308 1309 if (rxlen != msg->rx_len) { 1310 DRM_ERROR("DSI returned %db, expecting %db\n", 1311 rxlen, (int)msg->rx_len); 1312 ret = -ENXIO; 1313 goto reset_fifo_and_return; 1314 } 1315 1316 for (i = 0; i < msg->rx_len; i++) 1317 msg_rx[i] = DSI_READ(DSI1_RXPKT_FIFO); 1318 } else { 1319 /* FINISHME: Handle AWER */ 1320 1321 msg_rx[0] = VC4_GET_FIELD(rxpkt1h, 1322 DSI_RXPKT1H_SHORT_0); 1323 if (msg->rx_len > 1) { 1324 msg_rx[1] = VC4_GET_FIELD(rxpkt1h, 1325 DSI_RXPKT1H_SHORT_1); 1326 } 1327 } 1328 } 1329 1330 return ret; 1331 1332 reset_fifo_and_return: 1333 DRM_ERROR("DSI transfer failed, resetting: %d\n", ret); 1334 1335 DSI_PORT_WRITE(TXPKT1C, DSI_PORT_READ(TXPKT1C) & ~DSI_TXPKT1C_CMD_EN); 1336 udelay(1); 1337 DSI_PORT_WRITE(CTRL, 1338 DSI_PORT_READ(CTRL) | 1339 DSI_PORT_BIT(CTRL_RESET_FIFOS)); 1340 1341 DSI_PORT_WRITE(TXPKT1C, 0); 1342 DSI_PORT_WRITE(INT_EN, DSI_PORT_BIT(INTERRUPTS_ALWAYS_ENABLED)); 1343 return ret; 1344 } 1345 1346 static const struct component_ops vc4_dsi_ops; 1347 static int vc4_dsi_host_attach(struct mipi_dsi_host *host, 1348 struct mipi_dsi_device *device) 1349 { 1350 struct vc4_dsi *dsi = host_to_dsi(host); 1351 int ret; 1352 1353 dsi->lanes = device->lanes; 1354 dsi->channel = device->channel; 1355 dsi->mode_flags = device->mode_flags; 1356 1357 switch (device->format) { 1358 case MIPI_DSI_FMT_RGB888: 1359 dsi->format = DSI_PFORMAT_RGB888; 1360 dsi->divider = 24 / dsi->lanes; 1361 break; 1362 case MIPI_DSI_FMT_RGB666: 1363 dsi->format = DSI_PFORMAT_RGB666; 1364 dsi->divider = 24 / dsi->lanes; 1365 break; 1366 case MIPI_DSI_FMT_RGB666_PACKED: 1367 dsi->format = DSI_PFORMAT_RGB666_PACKED; 1368 dsi->divider = 18 / dsi->lanes; 1369 break; 1370 case MIPI_DSI_FMT_RGB565: 1371 dsi->format = DSI_PFORMAT_RGB565; 1372 dsi->divider = 16 / dsi->lanes; 1373 break; 1374 default: 1375 dev_err(&dsi->pdev->dev, "Unknown DSI format: %d.\n", 1376 dsi->format); 1377 return 0; 1378 } 1379 1380 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO)) { 1381 dev_err(&dsi->pdev->dev, 1382 "Only VIDEO mode panels supported currently.\n"); 1383 return 0; 1384 } 1385 1386 drm_bridge_add(&dsi->bridge); 1387 1388 ret = component_add(&dsi->pdev->dev, &vc4_dsi_ops); 1389 if (ret) { 1390 drm_bridge_remove(&dsi->bridge); 1391 return ret; 1392 } 1393 1394 return 0; 1395 } 1396 1397 static int vc4_dsi_host_detach(struct mipi_dsi_host *host, 1398 struct mipi_dsi_device *device) 1399 { 1400 struct vc4_dsi *dsi = host_to_dsi(host); 1401 1402 component_del(&dsi->pdev->dev, &vc4_dsi_ops); 1403 drm_bridge_remove(&dsi->bridge); 1404 return 0; 1405 } 1406 1407 static const struct mipi_dsi_host_ops vc4_dsi_host_ops = { 1408 .attach = vc4_dsi_host_attach, 1409 .detach = vc4_dsi_host_detach, 1410 .transfer = vc4_dsi_host_transfer, 1411 }; 1412 1413 static const struct drm_bridge_funcs vc4_dsi_bridge_funcs = { 1414 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 1415 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 1416 .atomic_reset = drm_atomic_helper_bridge_reset, 1417 .atomic_pre_enable = vc4_dsi_bridge_pre_enable, 1418 .atomic_enable = vc4_dsi_bridge_enable, 1419 .atomic_disable = vc4_dsi_bridge_disable, 1420 .atomic_post_disable = vc4_dsi_bridge_post_disable, 1421 .attach = vc4_dsi_bridge_attach, 1422 .mode_fixup = vc4_dsi_bridge_mode_fixup, 1423 }; 1424 1425 static int vc4_dsi_late_register(struct drm_encoder *encoder) 1426 { 1427 struct drm_device *drm = encoder->dev; 1428 struct vc4_dsi *dsi = to_vc4_dsi(encoder); 1429 1430 vc4_debugfs_add_regset32(drm, dsi->variant->debugfs_name, &dsi->regset); 1431 1432 return 0; 1433 } 1434 1435 static const struct drm_encoder_funcs vc4_dsi_encoder_funcs = { 1436 .late_register = vc4_dsi_late_register, 1437 }; 1438 1439 static const struct vc4_dsi_variant bcm2711_dsi1_variant = { 1440 .port = 1, 1441 .debugfs_name = "dsi1_regs", 1442 .regs = dsi1_regs, 1443 .nregs = ARRAY_SIZE(dsi1_regs), 1444 }; 1445 1446 static const struct vc4_dsi_variant bcm2835_dsi0_variant = { 1447 .port = 0, 1448 .debugfs_name = "dsi0_regs", 1449 .regs = dsi0_regs, 1450 .nregs = ARRAY_SIZE(dsi0_regs), 1451 }; 1452 1453 static const struct vc4_dsi_variant bcm2835_dsi1_variant = { 1454 .port = 1, 1455 .broken_axi_workaround = true, 1456 .debugfs_name = "dsi1_regs", 1457 .regs = dsi1_regs, 1458 .nregs = ARRAY_SIZE(dsi1_regs), 1459 }; 1460 1461 static const struct of_device_id vc4_dsi_dt_match[] = { 1462 { .compatible = "brcm,bcm2711-dsi1", &bcm2711_dsi1_variant }, 1463 { .compatible = "brcm,bcm2835-dsi0", &bcm2835_dsi0_variant }, 1464 { .compatible = "brcm,bcm2835-dsi1", &bcm2835_dsi1_variant }, 1465 {} 1466 }; 1467 1468 static void dsi_handle_error(struct vc4_dsi *dsi, 1469 irqreturn_t *ret, u32 stat, u32 bit, 1470 const char *type) 1471 { 1472 if (!(stat & bit)) 1473 return; 1474 1475 DRM_ERROR("DSI%d: %s error\n", dsi->variant->port, type); 1476 *ret = IRQ_HANDLED; 1477 } 1478 1479 /* 1480 * Initial handler for port 1 where we need the reg_dma workaround. 1481 * The register DMA writes sleep, so we can't do it in the top half. 1482 * Instead we use IRQF_ONESHOT so that the IRQ gets disabled in the 1483 * parent interrupt contrller until our interrupt thread is done. 1484 */ 1485 static irqreturn_t vc4_dsi_irq_defer_to_thread_handler(int irq, void *data) 1486 { 1487 struct vc4_dsi *dsi = data; 1488 u32 stat = DSI_PORT_READ(INT_STAT); 1489 1490 if (!stat) 1491 return IRQ_NONE; 1492 1493 return IRQ_WAKE_THREAD; 1494 } 1495 1496 /* 1497 * Normal IRQ handler for port 0, or the threaded IRQ handler for port 1498 * 1 where we need the reg_dma workaround. 1499 */ 1500 static irqreturn_t vc4_dsi_irq_handler(int irq, void *data) 1501 { 1502 struct vc4_dsi *dsi = data; 1503 u32 stat = DSI_PORT_READ(INT_STAT); 1504 irqreturn_t ret = IRQ_NONE; 1505 1506 DSI_PORT_WRITE(INT_STAT, stat); 1507 1508 dsi_handle_error(dsi, &ret, stat, 1509 DSI_PORT_BIT(INT_ERR_SYNC_ESC), "LPDT sync"); 1510 dsi_handle_error(dsi, &ret, stat, 1511 DSI_PORT_BIT(INT_ERR_CONTROL), "data lane 0 sequence"); 1512 dsi_handle_error(dsi, &ret, stat, 1513 DSI_PORT_BIT(INT_ERR_CONT_LP0), "LP0 contention"); 1514 dsi_handle_error(dsi, &ret, stat, 1515 DSI_PORT_BIT(INT_ERR_CONT_LP1), "LP1 contention"); 1516 dsi_handle_error(dsi, &ret, stat, 1517 DSI_PORT_BIT(INT_HSTX_TO), "HSTX timeout"); 1518 dsi_handle_error(dsi, &ret, stat, 1519 DSI_PORT_BIT(INT_LPRX_TO), "LPRX timeout"); 1520 dsi_handle_error(dsi, &ret, stat, 1521 DSI_PORT_BIT(INT_TA_TO), "turnaround timeout"); 1522 dsi_handle_error(dsi, &ret, stat, 1523 DSI_PORT_BIT(INT_PR_TO), "peripheral reset timeout"); 1524 1525 if (stat & ((dsi->variant->port ? DSI1_INT_TXPKT1_DONE : 1526 DSI0_INT_CMDC_DONE_MASK) | 1527 DSI_PORT_BIT(INT_PHY_DIR_RTF))) { 1528 complete(&dsi->xfer_completion); 1529 ret = IRQ_HANDLED; 1530 } else if (stat & DSI_PORT_BIT(INT_HSTX_TO)) { 1531 complete(&dsi->xfer_completion); 1532 dsi->xfer_result = -ETIMEDOUT; 1533 ret = IRQ_HANDLED; 1534 } 1535 1536 return ret; 1537 } 1538 1539 /** 1540 * vc4_dsi_init_phy_clocks - Exposes clocks generated by the analog 1541 * PHY that are consumed by CPRMAN (clk-bcm2835.c). 1542 * @dsi: DSI encoder 1543 */ 1544 static int 1545 vc4_dsi_init_phy_clocks(struct vc4_dsi *dsi) 1546 { 1547 struct device *dev = &dsi->pdev->dev; 1548 const char *parent_name = __clk_get_name(dsi->pll_phy_clock); 1549 static const struct { 1550 const char *name; 1551 int div; 1552 } phy_clocks[] = { 1553 { "byte", 8 }, 1554 { "ddr2", 4 }, 1555 { "ddr", 2 }, 1556 }; 1557 int i; 1558 1559 dsi->clk_onecell = devm_kzalloc(dev, 1560 sizeof(*dsi->clk_onecell) + 1561 ARRAY_SIZE(phy_clocks) * 1562 sizeof(struct clk_hw *), 1563 GFP_KERNEL); 1564 if (!dsi->clk_onecell) 1565 return -ENOMEM; 1566 dsi->clk_onecell->num = ARRAY_SIZE(phy_clocks); 1567 1568 for (i = 0; i < ARRAY_SIZE(phy_clocks); i++) { 1569 struct clk_fixed_factor *fix = &dsi->phy_clocks[i]; 1570 struct clk_init_data init; 1571 char clk_name[16]; 1572 int ret; 1573 1574 snprintf(clk_name, sizeof(clk_name), 1575 "dsi%u_%s", dsi->variant->port, phy_clocks[i].name); 1576 1577 /* We just use core fixed factor clock ops for the PHY 1578 * clocks. The clocks are actually gated by the 1579 * PHY_AFEC0_DDRCLK_EN bits, which we should be 1580 * setting if we use the DDR/DDR2 clocks. However, 1581 * vc4_dsi_encoder_enable() is setting up both AFEC0, 1582 * setting both our parent DSI PLL's rate and this 1583 * clock's rate, so it knows if DDR/DDR2 are going to 1584 * be used and could enable the gates itself. 1585 */ 1586 fix->mult = 1; 1587 fix->div = phy_clocks[i].div; 1588 fix->hw.init = &init; 1589 1590 memset(&init, 0, sizeof(init)); 1591 init.parent_names = &parent_name; 1592 init.num_parents = 1; 1593 init.name = clk_name; 1594 init.ops = &clk_fixed_factor_ops; 1595 1596 ret = devm_clk_hw_register(dev, &fix->hw); 1597 if (ret) 1598 return ret; 1599 1600 dsi->clk_onecell->hws[i] = &fix->hw; 1601 } 1602 1603 return of_clk_add_hw_provider(dev->of_node, 1604 of_clk_hw_onecell_get, 1605 dsi->clk_onecell); 1606 } 1607 1608 static void vc4_dsi_dma_mem_release(void *ptr) 1609 { 1610 struct vc4_dsi *dsi = ptr; 1611 struct device *dev = &dsi->pdev->dev; 1612 1613 dma_free_coherent(dev, 4, dsi->reg_dma_mem, dsi->reg_dma_paddr); 1614 dsi->reg_dma_mem = NULL; 1615 } 1616 1617 static void vc4_dsi_dma_chan_release(void *ptr) 1618 { 1619 struct vc4_dsi *dsi = ptr; 1620 1621 dma_release_channel(dsi->reg_dma_chan); 1622 dsi->reg_dma_chan = NULL; 1623 } 1624 1625 static void vc4_dsi_release(struct kref *kref) 1626 { 1627 struct vc4_dsi *dsi = 1628 container_of(kref, struct vc4_dsi, kref); 1629 1630 kfree(dsi); 1631 } 1632 1633 static void vc4_dsi_get(struct vc4_dsi *dsi) 1634 { 1635 kref_get(&dsi->kref); 1636 } 1637 1638 static void vc4_dsi_put(struct vc4_dsi *dsi) 1639 { 1640 kref_put(&dsi->kref, &vc4_dsi_release); 1641 } 1642 1643 static void vc4_dsi_release_action(struct drm_device *drm, void *ptr) 1644 { 1645 struct vc4_dsi *dsi = ptr; 1646 1647 vc4_dsi_put(dsi); 1648 } 1649 1650 static int vc4_dsi_bind(struct device *dev, struct device *master, void *data) 1651 { 1652 struct platform_device *pdev = to_platform_device(dev); 1653 struct drm_device *drm = dev_get_drvdata(master); 1654 struct vc4_dsi *dsi = dev_get_drvdata(dev); 1655 struct drm_encoder *encoder = &dsi->encoder.base; 1656 int ret; 1657 1658 vc4_dsi_get(dsi); 1659 1660 ret = drmm_add_action_or_reset(drm, vc4_dsi_release_action, dsi); 1661 if (ret) 1662 return ret; 1663 1664 dsi->variant = of_device_get_match_data(dev); 1665 1666 dsi->encoder.type = dsi->variant->port ? 1667 VC4_ENCODER_TYPE_DSI1 : VC4_ENCODER_TYPE_DSI0; 1668 1669 dsi->regs = vc4_ioremap_regs(pdev, 0); 1670 if (IS_ERR(dsi->regs)) 1671 return PTR_ERR(dsi->regs); 1672 1673 dsi->regset.base = dsi->regs; 1674 dsi->regset.regs = dsi->variant->regs; 1675 dsi->regset.nregs = dsi->variant->nregs; 1676 1677 if (DSI_PORT_READ(ID) != DSI_ID_VALUE) { 1678 dev_err(dev, "Port returned 0x%08x for ID instead of 0x%08x\n", 1679 DSI_PORT_READ(ID), DSI_ID_VALUE); 1680 return -ENODEV; 1681 } 1682 1683 /* DSI1 on BCM2835/6/7 has a broken AXI slave that doesn't respond to 1684 * writes from the ARM. It does handle writes from the DMA engine, 1685 * so set up a channel for talking to it. 1686 */ 1687 if (dsi->variant->broken_axi_workaround) { 1688 dma_cap_mask_t dma_mask; 1689 1690 dsi->reg_dma_mem = dma_alloc_coherent(dev, 4, 1691 &dsi->reg_dma_paddr, 1692 GFP_KERNEL); 1693 if (!dsi->reg_dma_mem) { 1694 DRM_ERROR("Failed to get DMA memory\n"); 1695 return -ENOMEM; 1696 } 1697 1698 ret = devm_add_action_or_reset(dev, vc4_dsi_dma_mem_release, dsi); 1699 if (ret) 1700 return ret; 1701 1702 dma_cap_zero(dma_mask); 1703 dma_cap_set(DMA_MEMCPY, dma_mask); 1704 1705 dsi->reg_dma_chan = dma_request_chan_by_mask(&dma_mask); 1706 if (IS_ERR(dsi->reg_dma_chan)) { 1707 ret = PTR_ERR(dsi->reg_dma_chan); 1708 if (ret != -EPROBE_DEFER) 1709 DRM_ERROR("Failed to get DMA channel: %d\n", 1710 ret); 1711 return ret; 1712 } 1713 1714 ret = devm_add_action_or_reset(dev, vc4_dsi_dma_chan_release, dsi); 1715 if (ret) 1716 return ret; 1717 1718 /* Get the physical address of the device's registers. The 1719 * struct resource for the regs gives us the bus address 1720 * instead. 1721 */ 1722 dsi->reg_paddr = be32_to_cpup(of_get_address(dev->of_node, 1723 0, NULL, NULL)); 1724 } 1725 1726 init_completion(&dsi->xfer_completion); 1727 /* At startup enable error-reporting interrupts and nothing else. */ 1728 DSI_PORT_WRITE(INT_EN, DSI1_INTERRUPTS_ALWAYS_ENABLED); 1729 /* Clear any existing interrupt state. */ 1730 DSI_PORT_WRITE(INT_STAT, DSI_PORT_READ(INT_STAT)); 1731 1732 if (dsi->reg_dma_mem) 1733 ret = devm_request_threaded_irq(dev, platform_get_irq(pdev, 0), 1734 vc4_dsi_irq_defer_to_thread_handler, 1735 vc4_dsi_irq_handler, 1736 IRQF_ONESHOT, 1737 "vc4 dsi", dsi); 1738 else 1739 ret = devm_request_irq(dev, platform_get_irq(pdev, 0), 1740 vc4_dsi_irq_handler, 0, "vc4 dsi", dsi); 1741 if (ret) { 1742 if (ret != -EPROBE_DEFER) 1743 dev_err(dev, "Failed to get interrupt: %d\n", ret); 1744 return ret; 1745 } 1746 1747 dsi->escape_clock = devm_clk_get(dev, "escape"); 1748 if (IS_ERR(dsi->escape_clock)) { 1749 ret = PTR_ERR(dsi->escape_clock); 1750 if (ret != -EPROBE_DEFER) 1751 dev_err(dev, "Failed to get escape clock: %d\n", ret); 1752 return ret; 1753 } 1754 1755 dsi->pll_phy_clock = devm_clk_get(dev, "phy"); 1756 if (IS_ERR(dsi->pll_phy_clock)) { 1757 ret = PTR_ERR(dsi->pll_phy_clock); 1758 if (ret != -EPROBE_DEFER) 1759 dev_err(dev, "Failed to get phy clock: %d\n", ret); 1760 return ret; 1761 } 1762 1763 dsi->pixel_clock = devm_clk_get(dev, "pixel"); 1764 if (IS_ERR(dsi->pixel_clock)) { 1765 ret = PTR_ERR(dsi->pixel_clock); 1766 if (ret != -EPROBE_DEFER) 1767 dev_err(dev, "Failed to get pixel clock: %d\n", ret); 1768 return ret; 1769 } 1770 1771 dsi->out_bridge = drmm_of_get_bridge(drm, dev->of_node, 0, 0); 1772 if (IS_ERR(dsi->out_bridge)) 1773 return PTR_ERR(dsi->out_bridge); 1774 1775 /* The esc clock rate is supposed to always be 100Mhz. */ 1776 ret = clk_set_rate(dsi->escape_clock, 100 * 1000000); 1777 if (ret) { 1778 dev_err(dev, "Failed to set esc clock: %d\n", ret); 1779 return ret; 1780 } 1781 1782 ret = vc4_dsi_init_phy_clocks(dsi); 1783 if (ret) 1784 return ret; 1785 1786 ret = drmm_encoder_init(drm, encoder, 1787 &vc4_dsi_encoder_funcs, 1788 DRM_MODE_ENCODER_DSI, 1789 NULL); 1790 if (ret) 1791 return ret; 1792 1793 ret = devm_pm_runtime_enable(dev); 1794 if (ret) 1795 return ret; 1796 1797 ret = drm_bridge_attach(encoder, &dsi->bridge, NULL, 0); 1798 if (ret) 1799 return ret; 1800 1801 return 0; 1802 } 1803 1804 static const struct component_ops vc4_dsi_ops = { 1805 .bind = vc4_dsi_bind, 1806 }; 1807 1808 static int vc4_dsi_dev_probe(struct platform_device *pdev) 1809 { 1810 struct device *dev = &pdev->dev; 1811 struct vc4_dsi *dsi; 1812 1813 dsi = kzalloc(sizeof(*dsi), GFP_KERNEL); 1814 if (!dsi) 1815 return -ENOMEM; 1816 dev_set_drvdata(dev, dsi); 1817 1818 kref_init(&dsi->kref); 1819 1820 dsi->pdev = pdev; 1821 dsi->bridge.funcs = &vc4_dsi_bridge_funcs; 1822 dsi->bridge.of_node = dev->of_node; 1823 dsi->bridge.type = DRM_MODE_CONNECTOR_DSI; 1824 dsi->dsi_host.ops = &vc4_dsi_host_ops; 1825 dsi->dsi_host.dev = dev; 1826 mipi_dsi_host_register(&dsi->dsi_host); 1827 1828 return 0; 1829 } 1830 1831 static int vc4_dsi_dev_remove(struct platform_device *pdev) 1832 { 1833 struct device *dev = &pdev->dev; 1834 struct vc4_dsi *dsi = dev_get_drvdata(dev); 1835 1836 mipi_dsi_host_unregister(&dsi->dsi_host); 1837 vc4_dsi_put(dsi); 1838 1839 return 0; 1840 } 1841 1842 struct platform_driver vc4_dsi_driver = { 1843 .probe = vc4_dsi_dev_probe, 1844 .remove = vc4_dsi_dev_remove, 1845 .driver = { 1846 .name = "vc4_dsi", 1847 .of_match_table = vc4_dsi_dt_match, 1848 }, 1849 }; 1850