1 /* 2 * Copyright (C) 2015 Broadcom 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 #include <linux/mm_types.h> 10 #include <linux/reservation.h> 11 #include <drm/drmP.h> 12 #include <drm/drm_encoder.h> 13 #include <drm/drm_gem_cma_helper.h> 14 #include <drm/drm_atomic.h> 15 #include <drm/drm_syncobj.h> 16 17 #include "uapi/drm/vc4_drm.h" 18 19 /* Don't forget to update vc4_bo.c: bo_type_names[] when adding to 20 * this. 21 */ 22 enum vc4_kernel_bo_type { 23 /* Any kernel allocation (gem_create_object hook) before it 24 * gets another type set. 25 */ 26 VC4_BO_TYPE_KERNEL, 27 VC4_BO_TYPE_V3D, 28 VC4_BO_TYPE_V3D_SHADER, 29 VC4_BO_TYPE_DUMB, 30 VC4_BO_TYPE_BIN, 31 VC4_BO_TYPE_RCL, 32 VC4_BO_TYPE_BCL, 33 VC4_BO_TYPE_KERNEL_CACHE, 34 VC4_BO_TYPE_COUNT 35 }; 36 37 /* Performance monitor object. The perform lifetime is controlled by userspace 38 * using perfmon related ioctls. A perfmon can be attached to a submit_cl 39 * request, and when this is the case, HW perf counters will be activated just 40 * before the submit_cl is submitted to the GPU and disabled when the job is 41 * done. This way, only events related to a specific job will be counted. 42 */ 43 struct vc4_perfmon { 44 /* Tracks the number of users of the perfmon, when this counter reaches 45 * zero the perfmon is destroyed. 46 */ 47 refcount_t refcnt; 48 49 /* Number of counters activated in this perfmon instance 50 * (should be less than DRM_VC4_MAX_PERF_COUNTERS). 51 */ 52 u8 ncounters; 53 54 /* Events counted by the HW perf counters. */ 55 u8 events[DRM_VC4_MAX_PERF_COUNTERS]; 56 57 /* Storage for counter values. Counters are incremented by the HW 58 * perf counter values every time the perfmon is attached to a GPU job. 59 * This way, perfmon users don't have to retrieve the results after 60 * each job if they want to track events covering several submissions. 61 * Note that counter values can't be reset, but you can fake a reset by 62 * destroying the perfmon and creating a new one. 63 */ 64 u64 counters[0]; 65 }; 66 67 struct vc4_dev { 68 struct drm_device *dev; 69 70 struct vc4_hdmi *hdmi; 71 struct vc4_hvs *hvs; 72 struct vc4_v3d *v3d; 73 struct vc4_dpi *dpi; 74 struct vc4_dsi *dsi1; 75 struct vc4_vec *vec; 76 struct vc4_txp *txp; 77 78 struct vc4_hang_state *hang_state; 79 80 /* The kernel-space BO cache. Tracks buffers that have been 81 * unreferenced by all other users (refcounts of 0!) but not 82 * yet freed, so we can do cheap allocations. 83 */ 84 struct vc4_bo_cache { 85 /* Array of list heads for entries in the BO cache, 86 * based on number of pages, so we can do O(1) lookups 87 * in the cache when allocating. 88 */ 89 struct list_head *size_list; 90 uint32_t size_list_size; 91 92 /* List of all BOs in the cache, ordered by age, so we 93 * can do O(1) lookups when trying to free old 94 * buffers. 95 */ 96 struct list_head time_list; 97 struct work_struct time_work; 98 struct timer_list time_timer; 99 } bo_cache; 100 101 u32 num_labels; 102 struct vc4_label { 103 const char *name; 104 u32 num_allocated; 105 u32 size_allocated; 106 } *bo_labels; 107 108 /* Protects bo_cache and bo_labels. */ 109 struct mutex bo_lock; 110 111 /* Purgeable BO pool. All BOs in this pool can have their memory 112 * reclaimed if the driver is unable to allocate new BOs. We also 113 * keep stats related to the purge mechanism here. 114 */ 115 struct { 116 struct list_head list; 117 unsigned int num; 118 size_t size; 119 unsigned int purged_num; 120 size_t purged_size; 121 struct mutex lock; 122 } purgeable; 123 124 uint64_t dma_fence_context; 125 126 /* Sequence number for the last job queued in bin_job_list. 127 * Starts at 0 (no jobs emitted). 128 */ 129 uint64_t emit_seqno; 130 131 /* Sequence number for the last completed job on the GPU. 132 * Starts at 0 (no jobs completed). 133 */ 134 uint64_t finished_seqno; 135 136 /* List of all struct vc4_exec_info for jobs to be executed in 137 * the binner. The first job in the list is the one currently 138 * programmed into ct0ca for execution. 139 */ 140 struct list_head bin_job_list; 141 142 /* List of all struct vc4_exec_info for jobs that have 143 * completed binning and are ready for rendering. The first 144 * job in the list is the one currently programmed into ct1ca 145 * for execution. 146 */ 147 struct list_head render_job_list; 148 149 /* List of the finished vc4_exec_infos waiting to be freed by 150 * job_done_work. 151 */ 152 struct list_head job_done_list; 153 /* Spinlock used to synchronize the job_list and seqno 154 * accesses between the IRQ handler and GEM ioctls. 155 */ 156 spinlock_t job_lock; 157 wait_queue_head_t job_wait_queue; 158 struct work_struct job_done_work; 159 160 /* Used to track the active perfmon if any. Access to this field is 161 * protected by job_lock. 162 */ 163 struct vc4_perfmon *active_perfmon; 164 165 /* List of struct vc4_seqno_cb for callbacks to be made from a 166 * workqueue when the given seqno is passed. 167 */ 168 struct list_head seqno_cb_list; 169 170 /* The memory used for storing binner tile alloc, tile state, 171 * and overflow memory allocations. This is freed when V3D 172 * powers down. 173 */ 174 struct vc4_bo *bin_bo; 175 176 /* Size of blocks allocated within bin_bo. */ 177 uint32_t bin_alloc_size; 178 179 /* Bitmask of the bin_alloc_size chunks in bin_bo that are 180 * used. 181 */ 182 uint32_t bin_alloc_used; 183 184 /* Bitmask of the current bin_alloc used for overflow memory. */ 185 uint32_t bin_alloc_overflow; 186 187 struct work_struct overflow_mem_work; 188 189 int power_refcount; 190 191 /* Mutex controlling the power refcount. */ 192 struct mutex power_lock; 193 194 struct { 195 struct timer_list timer; 196 struct work_struct reset_work; 197 } hangcheck; 198 199 struct semaphore async_modeset; 200 201 struct drm_modeset_lock ctm_state_lock; 202 struct drm_private_obj ctm_manager; 203 }; 204 205 static inline struct vc4_dev * 206 to_vc4_dev(struct drm_device *dev) 207 { 208 return (struct vc4_dev *)dev->dev_private; 209 } 210 211 struct vc4_bo { 212 struct drm_gem_cma_object base; 213 214 /* seqno of the last job to render using this BO. */ 215 uint64_t seqno; 216 217 /* seqno of the last job to use the RCL to write to this BO. 218 * 219 * Note that this doesn't include binner overflow memory 220 * writes. 221 */ 222 uint64_t write_seqno; 223 224 bool t_format; 225 226 /* List entry for the BO's position in either 227 * vc4_exec_info->unref_list or vc4_dev->bo_cache.time_list 228 */ 229 struct list_head unref_head; 230 231 /* Time in jiffies when the BO was put in vc4->bo_cache. */ 232 unsigned long free_time; 233 234 /* List entry for the BO's position in vc4_dev->bo_cache.size_list */ 235 struct list_head size_head; 236 237 /* Struct for shader validation state, if created by 238 * DRM_IOCTL_VC4_CREATE_SHADER_BO. 239 */ 240 struct vc4_validated_shader_info *validated_shader; 241 242 /* normally (resv == &_resv) except for imported bo's */ 243 struct reservation_object *resv; 244 struct reservation_object _resv; 245 246 /* One of enum vc4_kernel_bo_type, or VC4_BO_TYPE_COUNT + i 247 * for user-allocated labels. 248 */ 249 int label; 250 251 /* Count the number of active users. This is needed to determine 252 * whether we can move the BO to the purgeable list or not (when the BO 253 * is used by the GPU or the display engine we can't purge it). 254 */ 255 refcount_t usecnt; 256 257 /* Store purgeable/purged state here */ 258 u32 madv; 259 struct mutex madv_lock; 260 }; 261 262 static inline struct vc4_bo * 263 to_vc4_bo(struct drm_gem_object *bo) 264 { 265 return (struct vc4_bo *)bo; 266 } 267 268 struct vc4_fence { 269 struct dma_fence base; 270 struct drm_device *dev; 271 /* vc4 seqno for signaled() test */ 272 uint64_t seqno; 273 }; 274 275 static inline struct vc4_fence * 276 to_vc4_fence(struct dma_fence *fence) 277 { 278 return (struct vc4_fence *)fence; 279 } 280 281 struct vc4_seqno_cb { 282 struct work_struct work; 283 uint64_t seqno; 284 void (*func)(struct vc4_seqno_cb *cb); 285 }; 286 287 struct vc4_v3d { 288 struct vc4_dev *vc4; 289 struct platform_device *pdev; 290 void __iomem *regs; 291 struct clk *clk; 292 }; 293 294 struct vc4_hvs { 295 struct platform_device *pdev; 296 void __iomem *regs; 297 u32 __iomem *dlist; 298 299 /* Memory manager for CRTCs to allocate space in the display 300 * list. Units are dwords. 301 */ 302 struct drm_mm dlist_mm; 303 /* Memory manager for the LBM memory used by HVS scaling. */ 304 struct drm_mm lbm_mm; 305 spinlock_t mm_lock; 306 307 struct drm_mm_node mitchell_netravali_filter; 308 }; 309 310 struct vc4_plane { 311 struct drm_plane base; 312 }; 313 314 static inline struct vc4_plane * 315 to_vc4_plane(struct drm_plane *plane) 316 { 317 return (struct vc4_plane *)plane; 318 } 319 320 enum vc4_scaling_mode { 321 VC4_SCALING_NONE, 322 VC4_SCALING_TPZ, 323 VC4_SCALING_PPF, 324 }; 325 326 struct vc4_plane_state { 327 struct drm_plane_state base; 328 /* System memory copy of the display list for this element, computed 329 * at atomic_check time. 330 */ 331 u32 *dlist; 332 u32 dlist_size; /* Number of dwords allocated for the display list */ 333 u32 dlist_count; /* Number of used dwords in the display list. */ 334 335 /* Offset in the dlist to various words, for pageflip or 336 * cursor updates. 337 */ 338 u32 pos0_offset; 339 u32 pos2_offset; 340 u32 ptr0_offset; 341 u32 lbm_offset; 342 343 /* Offset where the plane's dlist was last stored in the 344 * hardware at vc4_crtc_atomic_flush() time. 345 */ 346 u32 __iomem *hw_dlist; 347 348 /* Clipped coordinates of the plane on the display. */ 349 int crtc_x, crtc_y, crtc_w, crtc_h; 350 /* Clipped area being scanned from in the FB. */ 351 u32 src_x, src_y; 352 353 u32 src_w[2], src_h[2]; 354 355 /* Scaling selection for the RGB/Y plane and the Cb/Cr planes. */ 356 enum vc4_scaling_mode x_scaling[2], y_scaling[2]; 357 bool is_unity; 358 bool is_yuv; 359 360 /* Offset to start scanning out from the start of the plane's 361 * BO. 362 */ 363 u32 offsets[3]; 364 365 /* Our allocation in LBM for temporary storage during scaling. */ 366 struct drm_mm_node lbm; 367 368 /* Set when the plane has per-pixel alpha content or does not cover 369 * the entire screen. This is a hint to the CRTC that it might need 370 * to enable background color fill. 371 */ 372 bool needs_bg_fill; 373 374 /* Mark the dlist as initialized. Useful to avoid initializing it twice 375 * when async update is not possible. 376 */ 377 bool dlist_initialized; 378 }; 379 380 static inline struct vc4_plane_state * 381 to_vc4_plane_state(struct drm_plane_state *state) 382 { 383 return (struct vc4_plane_state *)state; 384 } 385 386 enum vc4_encoder_type { 387 VC4_ENCODER_TYPE_NONE, 388 VC4_ENCODER_TYPE_HDMI, 389 VC4_ENCODER_TYPE_VEC, 390 VC4_ENCODER_TYPE_DSI0, 391 VC4_ENCODER_TYPE_DSI1, 392 VC4_ENCODER_TYPE_SMI, 393 VC4_ENCODER_TYPE_DPI, 394 }; 395 396 struct vc4_encoder { 397 struct drm_encoder base; 398 enum vc4_encoder_type type; 399 u32 clock_select; 400 }; 401 402 static inline struct vc4_encoder * 403 to_vc4_encoder(struct drm_encoder *encoder) 404 { 405 return container_of(encoder, struct vc4_encoder, base); 406 } 407 408 struct vc4_crtc_data { 409 /* Which channel of the HVS this pixelvalve sources from. */ 410 int hvs_channel; 411 412 enum vc4_encoder_type encoder_types[4]; 413 }; 414 415 struct vc4_crtc { 416 struct drm_crtc base; 417 const struct vc4_crtc_data *data; 418 void __iomem *regs; 419 420 /* Timestamp at start of vblank irq - unaffected by lock delays. */ 421 ktime_t t_vblank; 422 423 /* Which HVS channel we're using for our CRTC. */ 424 int channel; 425 426 u8 lut_r[256]; 427 u8 lut_g[256]; 428 u8 lut_b[256]; 429 /* Size in pixels of the COB memory allocated to this CRTC. */ 430 u32 cob_size; 431 432 struct drm_pending_vblank_event *event; 433 }; 434 435 static inline struct vc4_crtc * 436 to_vc4_crtc(struct drm_crtc *crtc) 437 { 438 return (struct vc4_crtc *)crtc; 439 } 440 441 #define V3D_READ(offset) readl(vc4->v3d->regs + offset) 442 #define V3D_WRITE(offset, val) writel(val, vc4->v3d->regs + offset) 443 #define HVS_READ(offset) readl(vc4->hvs->regs + offset) 444 #define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset) 445 446 struct vc4_exec_info { 447 /* Sequence number for this bin/render job. */ 448 uint64_t seqno; 449 450 /* Latest write_seqno of any BO that binning depends on. */ 451 uint64_t bin_dep_seqno; 452 453 struct dma_fence *fence; 454 455 /* Last current addresses the hardware was processing when the 456 * hangcheck timer checked on us. 457 */ 458 uint32_t last_ct0ca, last_ct1ca; 459 460 /* Kernel-space copy of the ioctl arguments */ 461 struct drm_vc4_submit_cl *args; 462 463 /* This is the array of BOs that were looked up at the start of exec. 464 * Command validation will use indices into this array. 465 */ 466 struct drm_gem_cma_object **bo; 467 uint32_t bo_count; 468 469 /* List of BOs that are being written by the RCL. Other than 470 * the binner temporary storage, this is all the BOs written 471 * by the job. 472 */ 473 struct drm_gem_cma_object *rcl_write_bo[4]; 474 uint32_t rcl_write_bo_count; 475 476 /* Pointers for our position in vc4->job_list */ 477 struct list_head head; 478 479 /* List of other BOs used in the job that need to be released 480 * once the job is complete. 481 */ 482 struct list_head unref_list; 483 484 /* Current unvalidated indices into @bo loaded by the non-hardware 485 * VC4_PACKET_GEM_HANDLES. 486 */ 487 uint32_t bo_index[2]; 488 489 /* This is the BO where we store the validated command lists, shader 490 * records, and uniforms. 491 */ 492 struct drm_gem_cma_object *exec_bo; 493 494 /** 495 * This tracks the per-shader-record state (packet 64) that 496 * determines the length of the shader record and the offset 497 * it's expected to be found at. It gets read in from the 498 * command lists. 499 */ 500 struct vc4_shader_state { 501 uint32_t addr; 502 /* Maximum vertex index referenced by any primitive using this 503 * shader state. 504 */ 505 uint32_t max_index; 506 } *shader_state; 507 508 /** How many shader states the user declared they were using. */ 509 uint32_t shader_state_size; 510 /** How many shader state records the validator has seen. */ 511 uint32_t shader_state_count; 512 513 bool found_tile_binning_mode_config_packet; 514 bool found_start_tile_binning_packet; 515 bool found_increment_semaphore_packet; 516 bool found_flush; 517 uint8_t bin_tiles_x, bin_tiles_y; 518 /* Physical address of the start of the tile alloc array 519 * (where each tile's binned CL will start) 520 */ 521 uint32_t tile_alloc_offset; 522 /* Bitmask of which binner slots are freed when this job completes. */ 523 uint32_t bin_slots; 524 525 /** 526 * Computed addresses pointing into exec_bo where we start the 527 * bin thread (ct0) and render thread (ct1). 528 */ 529 uint32_t ct0ca, ct0ea; 530 uint32_t ct1ca, ct1ea; 531 532 /* Pointer to the unvalidated bin CL (if present). */ 533 void *bin_u; 534 535 /* Pointers to the shader recs. These paddr gets incremented as CL 536 * packets are relocated in validate_gl_shader_state, and the vaddrs 537 * (u and v) get incremented and size decremented as the shader recs 538 * themselves are validated. 539 */ 540 void *shader_rec_u; 541 void *shader_rec_v; 542 uint32_t shader_rec_p; 543 uint32_t shader_rec_size; 544 545 /* Pointers to the uniform data. These pointers are incremented, and 546 * size decremented, as each batch of uniforms is uploaded. 547 */ 548 void *uniforms_u; 549 void *uniforms_v; 550 uint32_t uniforms_p; 551 uint32_t uniforms_size; 552 553 /* Pointer to a performance monitor object if the user requested it, 554 * NULL otherwise. 555 */ 556 struct vc4_perfmon *perfmon; 557 }; 558 559 /* Per-open file private data. Any driver-specific resource that has to be 560 * released when the DRM file is closed should be placed here. 561 */ 562 struct vc4_file { 563 struct { 564 struct idr idr; 565 struct mutex lock; 566 } perfmon; 567 }; 568 569 static inline struct vc4_exec_info * 570 vc4_first_bin_job(struct vc4_dev *vc4) 571 { 572 return list_first_entry_or_null(&vc4->bin_job_list, 573 struct vc4_exec_info, head); 574 } 575 576 static inline struct vc4_exec_info * 577 vc4_first_render_job(struct vc4_dev *vc4) 578 { 579 return list_first_entry_or_null(&vc4->render_job_list, 580 struct vc4_exec_info, head); 581 } 582 583 static inline struct vc4_exec_info * 584 vc4_last_render_job(struct vc4_dev *vc4) 585 { 586 if (list_empty(&vc4->render_job_list)) 587 return NULL; 588 return list_last_entry(&vc4->render_job_list, 589 struct vc4_exec_info, head); 590 } 591 592 /** 593 * struct vc4_texture_sample_info - saves the offsets into the UBO for texture 594 * setup parameters. 595 * 596 * This will be used at draw time to relocate the reference to the texture 597 * contents in p0, and validate that the offset combined with 598 * width/height/stride/etc. from p1 and p2/p3 doesn't sample outside the BO. 599 * Note that the hardware treats unprovided config parameters as 0, so not all 600 * of them need to be set up for every texure sample, and we'll store ~0 as 601 * the offset to mark the unused ones. 602 * 603 * See the VC4 3D architecture guide page 41 ("Texture and Memory Lookup Unit 604 * Setup") for definitions of the texture parameters. 605 */ 606 struct vc4_texture_sample_info { 607 bool is_direct; 608 uint32_t p_offset[4]; 609 }; 610 611 /** 612 * struct vc4_validated_shader_info - information about validated shaders that 613 * needs to be used from command list validation. 614 * 615 * For a given shader, each time a shader state record references it, we need 616 * to verify that the shader doesn't read more uniforms than the shader state 617 * record's uniform BO pointer can provide, and we need to apply relocations 618 * and validate the shader state record's uniforms that define the texture 619 * samples. 620 */ 621 struct vc4_validated_shader_info { 622 uint32_t uniforms_size; 623 uint32_t uniforms_src_size; 624 uint32_t num_texture_samples; 625 struct vc4_texture_sample_info *texture_samples; 626 627 uint32_t num_uniform_addr_offsets; 628 uint32_t *uniform_addr_offsets; 629 630 bool is_threaded; 631 }; 632 633 /** 634 * _wait_for - magic (register) wait macro 635 * 636 * Does the right thing for modeset paths when run under kdgb or similar atomic 637 * contexts. Note that it's important that we check the condition again after 638 * having timed out, since the timeout could be due to preemption or similar and 639 * we've never had a chance to check the condition before the timeout. 640 */ 641 #define _wait_for(COND, MS, W) ({ \ 642 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \ 643 int ret__ = 0; \ 644 while (!(COND)) { \ 645 if (time_after(jiffies, timeout__)) { \ 646 if (!(COND)) \ 647 ret__ = -ETIMEDOUT; \ 648 break; \ 649 } \ 650 if (W && drm_can_sleep()) { \ 651 msleep(W); \ 652 } else { \ 653 cpu_relax(); \ 654 } \ 655 } \ 656 ret__; \ 657 }) 658 659 #define wait_for(COND, MS) _wait_for(COND, MS, 1) 660 661 /* vc4_bo.c */ 662 struct drm_gem_object *vc4_create_object(struct drm_device *dev, size_t size); 663 void vc4_free_object(struct drm_gem_object *gem_obj); 664 struct vc4_bo *vc4_bo_create(struct drm_device *dev, size_t size, 665 bool from_cache, enum vc4_kernel_bo_type type); 666 int vc4_dumb_create(struct drm_file *file_priv, 667 struct drm_device *dev, 668 struct drm_mode_create_dumb *args); 669 struct dma_buf *vc4_prime_export(struct drm_device *dev, 670 struct drm_gem_object *obj, int flags); 671 int vc4_create_bo_ioctl(struct drm_device *dev, void *data, 672 struct drm_file *file_priv); 673 int vc4_create_shader_bo_ioctl(struct drm_device *dev, void *data, 674 struct drm_file *file_priv); 675 int vc4_mmap_bo_ioctl(struct drm_device *dev, void *data, 676 struct drm_file *file_priv); 677 int vc4_set_tiling_ioctl(struct drm_device *dev, void *data, 678 struct drm_file *file_priv); 679 int vc4_get_tiling_ioctl(struct drm_device *dev, void *data, 680 struct drm_file *file_priv); 681 int vc4_get_hang_state_ioctl(struct drm_device *dev, void *data, 682 struct drm_file *file_priv); 683 int vc4_label_bo_ioctl(struct drm_device *dev, void *data, 684 struct drm_file *file_priv); 685 vm_fault_t vc4_fault(struct vm_fault *vmf); 686 int vc4_mmap(struct file *filp, struct vm_area_struct *vma); 687 struct reservation_object *vc4_prime_res_obj(struct drm_gem_object *obj); 688 int vc4_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma); 689 struct drm_gem_object *vc4_prime_import_sg_table(struct drm_device *dev, 690 struct dma_buf_attachment *attach, 691 struct sg_table *sgt); 692 void *vc4_prime_vmap(struct drm_gem_object *obj); 693 int vc4_bo_cache_init(struct drm_device *dev); 694 void vc4_bo_cache_destroy(struct drm_device *dev); 695 int vc4_bo_stats_debugfs(struct seq_file *m, void *arg); 696 int vc4_bo_inc_usecnt(struct vc4_bo *bo); 697 void vc4_bo_dec_usecnt(struct vc4_bo *bo); 698 void vc4_bo_add_to_purgeable_pool(struct vc4_bo *bo); 699 void vc4_bo_remove_from_purgeable_pool(struct vc4_bo *bo); 700 701 /* vc4_crtc.c */ 702 extern struct platform_driver vc4_crtc_driver; 703 int vc4_crtc_debugfs_regs(struct seq_file *m, void *arg); 704 bool vc4_crtc_get_scanoutpos(struct drm_device *dev, unsigned int crtc_id, 705 bool in_vblank_irq, int *vpos, int *hpos, 706 ktime_t *stime, ktime_t *etime, 707 const struct drm_display_mode *mode); 708 void vc4_crtc_handle_vblank(struct vc4_crtc *crtc); 709 void vc4_crtc_txp_armed(struct drm_crtc_state *state); 710 711 /* vc4_debugfs.c */ 712 int vc4_debugfs_init(struct drm_minor *minor); 713 714 /* vc4_drv.c */ 715 void __iomem *vc4_ioremap_regs(struct platform_device *dev, int index); 716 717 /* vc4_dpi.c */ 718 extern struct platform_driver vc4_dpi_driver; 719 int vc4_dpi_debugfs_regs(struct seq_file *m, void *unused); 720 721 /* vc4_dsi.c */ 722 extern struct platform_driver vc4_dsi_driver; 723 int vc4_dsi_debugfs_regs(struct seq_file *m, void *unused); 724 725 /* vc4_fence.c */ 726 extern const struct dma_fence_ops vc4_fence_ops; 727 728 /* vc4_gem.c */ 729 void vc4_gem_init(struct drm_device *dev); 730 void vc4_gem_destroy(struct drm_device *dev); 731 int vc4_submit_cl_ioctl(struct drm_device *dev, void *data, 732 struct drm_file *file_priv); 733 int vc4_wait_seqno_ioctl(struct drm_device *dev, void *data, 734 struct drm_file *file_priv); 735 int vc4_wait_bo_ioctl(struct drm_device *dev, void *data, 736 struct drm_file *file_priv); 737 void vc4_submit_next_bin_job(struct drm_device *dev); 738 void vc4_submit_next_render_job(struct drm_device *dev); 739 void vc4_move_job_to_render(struct drm_device *dev, struct vc4_exec_info *exec); 740 int vc4_wait_for_seqno(struct drm_device *dev, uint64_t seqno, 741 uint64_t timeout_ns, bool interruptible); 742 void vc4_job_handle_completed(struct vc4_dev *vc4); 743 int vc4_queue_seqno_cb(struct drm_device *dev, 744 struct vc4_seqno_cb *cb, uint64_t seqno, 745 void (*func)(struct vc4_seqno_cb *cb)); 746 int vc4_gem_madvise_ioctl(struct drm_device *dev, void *data, 747 struct drm_file *file_priv); 748 749 /* vc4_hdmi.c */ 750 extern struct platform_driver vc4_hdmi_driver; 751 int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused); 752 753 /* vc4_vec.c */ 754 extern struct platform_driver vc4_vec_driver; 755 int vc4_vec_debugfs_regs(struct seq_file *m, void *unused); 756 757 /* vc4_txp.c */ 758 extern struct platform_driver vc4_txp_driver; 759 int vc4_txp_debugfs_regs(struct seq_file *m, void *unused); 760 761 /* vc4_irq.c */ 762 irqreturn_t vc4_irq(int irq, void *arg); 763 void vc4_irq_preinstall(struct drm_device *dev); 764 int vc4_irq_postinstall(struct drm_device *dev); 765 void vc4_irq_uninstall(struct drm_device *dev); 766 void vc4_irq_reset(struct drm_device *dev); 767 768 /* vc4_hvs.c */ 769 extern struct platform_driver vc4_hvs_driver; 770 void vc4_hvs_dump_state(struct drm_device *dev); 771 int vc4_hvs_debugfs_regs(struct seq_file *m, void *unused); 772 773 /* vc4_kms.c */ 774 int vc4_kms_load(struct drm_device *dev); 775 776 /* vc4_plane.c */ 777 struct drm_plane *vc4_plane_init(struct drm_device *dev, 778 enum drm_plane_type type); 779 u32 vc4_plane_write_dlist(struct drm_plane *plane, u32 __iomem *dlist); 780 u32 vc4_plane_dlist_size(const struct drm_plane_state *state); 781 void vc4_plane_async_set_fb(struct drm_plane *plane, 782 struct drm_framebuffer *fb); 783 784 /* vc4_v3d.c */ 785 extern struct platform_driver vc4_v3d_driver; 786 int vc4_v3d_debugfs_ident(struct seq_file *m, void *unused); 787 int vc4_v3d_debugfs_regs(struct seq_file *m, void *unused); 788 int vc4_v3d_get_bin_slot(struct vc4_dev *vc4); 789 790 /* vc4_validate.c */ 791 int 792 vc4_validate_bin_cl(struct drm_device *dev, 793 void *validated, 794 void *unvalidated, 795 struct vc4_exec_info *exec); 796 797 int 798 vc4_validate_shader_recs(struct drm_device *dev, struct vc4_exec_info *exec); 799 800 struct drm_gem_cma_object *vc4_use_bo(struct vc4_exec_info *exec, 801 uint32_t hindex); 802 803 int vc4_get_rcl(struct drm_device *dev, struct vc4_exec_info *exec); 804 805 bool vc4_check_tex_size(struct vc4_exec_info *exec, 806 struct drm_gem_cma_object *fbo, 807 uint32_t offset, uint8_t tiling_format, 808 uint32_t width, uint32_t height, uint8_t cpp); 809 810 /* vc4_validate_shader.c */ 811 struct vc4_validated_shader_info * 812 vc4_validate_shader(struct drm_gem_cma_object *shader_obj); 813 814 /* vc4_perfmon.c */ 815 void vc4_perfmon_get(struct vc4_perfmon *perfmon); 816 void vc4_perfmon_put(struct vc4_perfmon *perfmon); 817 void vc4_perfmon_start(struct vc4_dev *vc4, struct vc4_perfmon *perfmon); 818 void vc4_perfmon_stop(struct vc4_dev *vc4, struct vc4_perfmon *perfmon, 819 bool capture); 820 struct vc4_perfmon *vc4_perfmon_find(struct vc4_file *vc4file, int id); 821 void vc4_perfmon_open_file(struct vc4_file *vc4file); 822 void vc4_perfmon_close_file(struct vc4_file *vc4file); 823 int vc4_perfmon_create_ioctl(struct drm_device *dev, void *data, 824 struct drm_file *file_priv); 825 int vc4_perfmon_destroy_ioctl(struct drm_device *dev, void *data, 826 struct drm_file *file_priv); 827 int vc4_perfmon_get_values_ioctl(struct drm_device *dev, void *data, 828 struct drm_file *file_priv); 829