1 /* 2 * Copyright (C) 2015 Broadcom 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 #include <linux/reservation.h> 10 #include <drm/drmP.h> 11 #include <drm/drm_encoder.h> 12 #include <drm/drm_gem_cma_helper.h> 13 14 struct vc4_dev { 15 struct drm_device *dev; 16 17 struct vc4_hdmi *hdmi; 18 struct vc4_hvs *hvs; 19 struct vc4_v3d *v3d; 20 struct vc4_dpi *dpi; 21 struct vc4_dsi *dsi1; 22 struct vc4_vec *vec; 23 24 struct drm_fbdev_cma *fbdev; 25 26 struct vc4_hang_state *hang_state; 27 28 /* The kernel-space BO cache. Tracks buffers that have been 29 * unreferenced by all other users (refcounts of 0!) but not 30 * yet freed, so we can do cheap allocations. 31 */ 32 struct vc4_bo_cache { 33 /* Array of list heads for entries in the BO cache, 34 * based on number of pages, so we can do O(1) lookups 35 * in the cache when allocating. 36 */ 37 struct list_head *size_list; 38 uint32_t size_list_size; 39 40 /* List of all BOs in the cache, ordered by age, so we 41 * can do O(1) lookups when trying to free old 42 * buffers. 43 */ 44 struct list_head time_list; 45 struct work_struct time_work; 46 struct timer_list time_timer; 47 } bo_cache; 48 49 struct vc4_bo_stats { 50 u32 num_allocated; 51 u32 size_allocated; 52 u32 num_cached; 53 u32 size_cached; 54 } bo_stats; 55 56 /* Protects bo_cache and the BO stats. */ 57 struct mutex bo_lock; 58 59 uint64_t dma_fence_context; 60 61 /* Sequence number for the last job queued in bin_job_list. 62 * Starts at 0 (no jobs emitted). 63 */ 64 uint64_t emit_seqno; 65 66 /* Sequence number for the last completed job on the GPU. 67 * Starts at 0 (no jobs completed). 68 */ 69 uint64_t finished_seqno; 70 71 /* List of all struct vc4_exec_info for jobs to be executed in 72 * the binner. The first job in the list is the one currently 73 * programmed into ct0ca for execution. 74 */ 75 struct list_head bin_job_list; 76 77 /* List of all struct vc4_exec_info for jobs that have 78 * completed binning and are ready for rendering. The first 79 * job in the list is the one currently programmed into ct1ca 80 * for execution. 81 */ 82 struct list_head render_job_list; 83 84 /* List of the finished vc4_exec_infos waiting to be freed by 85 * job_done_work. 86 */ 87 struct list_head job_done_list; 88 /* Spinlock used to synchronize the job_list and seqno 89 * accesses between the IRQ handler and GEM ioctls. 90 */ 91 spinlock_t job_lock; 92 wait_queue_head_t job_wait_queue; 93 struct work_struct job_done_work; 94 95 /* List of struct vc4_seqno_cb for callbacks to be made from a 96 * workqueue when the given seqno is passed. 97 */ 98 struct list_head seqno_cb_list; 99 100 /* The memory used for storing binner tile alloc, tile state, 101 * and overflow memory allocations. This is freed when V3D 102 * powers down. 103 */ 104 struct vc4_bo *bin_bo; 105 106 /* Size of blocks allocated within bin_bo. */ 107 uint32_t bin_alloc_size; 108 109 /* Bitmask of the bin_alloc_size chunks in bin_bo that are 110 * used. 111 */ 112 uint32_t bin_alloc_used; 113 114 /* Bitmask of the current bin_alloc used for overflow memory. */ 115 uint32_t bin_alloc_overflow; 116 117 struct work_struct overflow_mem_work; 118 119 int power_refcount; 120 121 /* Mutex controlling the power refcount. */ 122 struct mutex power_lock; 123 124 struct { 125 struct timer_list timer; 126 struct work_struct reset_work; 127 } hangcheck; 128 129 struct semaphore async_modeset; 130 }; 131 132 static inline struct vc4_dev * 133 to_vc4_dev(struct drm_device *dev) 134 { 135 return (struct vc4_dev *)dev->dev_private; 136 } 137 138 struct vc4_bo { 139 struct drm_gem_cma_object base; 140 141 /* seqno of the last job to render using this BO. */ 142 uint64_t seqno; 143 144 /* seqno of the last job to use the RCL to write to this BO. 145 * 146 * Note that this doesn't include binner overflow memory 147 * writes. 148 */ 149 uint64_t write_seqno; 150 151 bool t_format; 152 153 /* List entry for the BO's position in either 154 * vc4_exec_info->unref_list or vc4_dev->bo_cache.time_list 155 */ 156 struct list_head unref_head; 157 158 /* Time in jiffies when the BO was put in vc4->bo_cache. */ 159 unsigned long free_time; 160 161 /* List entry for the BO's position in vc4_dev->bo_cache.size_list */ 162 struct list_head size_head; 163 164 /* Struct for shader validation state, if created by 165 * DRM_IOCTL_VC4_CREATE_SHADER_BO. 166 */ 167 struct vc4_validated_shader_info *validated_shader; 168 169 /* normally (resv == &_resv) except for imported bo's */ 170 struct reservation_object *resv; 171 struct reservation_object _resv; 172 }; 173 174 static inline struct vc4_bo * 175 to_vc4_bo(struct drm_gem_object *bo) 176 { 177 return (struct vc4_bo *)bo; 178 } 179 180 struct vc4_fence { 181 struct dma_fence base; 182 struct drm_device *dev; 183 /* vc4 seqno for signaled() test */ 184 uint64_t seqno; 185 }; 186 187 static inline struct vc4_fence * 188 to_vc4_fence(struct dma_fence *fence) 189 { 190 return (struct vc4_fence *)fence; 191 } 192 193 struct vc4_seqno_cb { 194 struct work_struct work; 195 uint64_t seqno; 196 void (*func)(struct vc4_seqno_cb *cb); 197 }; 198 199 struct vc4_v3d { 200 struct vc4_dev *vc4; 201 struct platform_device *pdev; 202 void __iomem *regs; 203 struct clk *clk; 204 }; 205 206 struct vc4_hvs { 207 struct platform_device *pdev; 208 void __iomem *regs; 209 u32 __iomem *dlist; 210 211 /* Memory manager for CRTCs to allocate space in the display 212 * list. Units are dwords. 213 */ 214 struct drm_mm dlist_mm; 215 /* Memory manager for the LBM memory used by HVS scaling. */ 216 struct drm_mm lbm_mm; 217 spinlock_t mm_lock; 218 219 struct drm_mm_node mitchell_netravali_filter; 220 }; 221 222 struct vc4_plane { 223 struct drm_plane base; 224 }; 225 226 static inline struct vc4_plane * 227 to_vc4_plane(struct drm_plane *plane) 228 { 229 return (struct vc4_plane *)plane; 230 } 231 232 enum vc4_encoder_type { 233 VC4_ENCODER_TYPE_NONE, 234 VC4_ENCODER_TYPE_HDMI, 235 VC4_ENCODER_TYPE_VEC, 236 VC4_ENCODER_TYPE_DSI0, 237 VC4_ENCODER_TYPE_DSI1, 238 VC4_ENCODER_TYPE_SMI, 239 VC4_ENCODER_TYPE_DPI, 240 }; 241 242 struct vc4_encoder { 243 struct drm_encoder base; 244 enum vc4_encoder_type type; 245 u32 clock_select; 246 }; 247 248 static inline struct vc4_encoder * 249 to_vc4_encoder(struct drm_encoder *encoder) 250 { 251 return container_of(encoder, struct vc4_encoder, base); 252 } 253 254 #define V3D_READ(offset) readl(vc4->v3d->regs + offset) 255 #define V3D_WRITE(offset, val) writel(val, vc4->v3d->regs + offset) 256 #define HVS_READ(offset) readl(vc4->hvs->regs + offset) 257 #define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset) 258 259 struct vc4_exec_info { 260 /* Sequence number for this bin/render job. */ 261 uint64_t seqno; 262 263 /* Latest write_seqno of any BO that binning depends on. */ 264 uint64_t bin_dep_seqno; 265 266 struct dma_fence *fence; 267 268 /* Last current addresses the hardware was processing when the 269 * hangcheck timer checked on us. 270 */ 271 uint32_t last_ct0ca, last_ct1ca; 272 273 /* Kernel-space copy of the ioctl arguments */ 274 struct drm_vc4_submit_cl *args; 275 276 /* This is the array of BOs that were looked up at the start of exec. 277 * Command validation will use indices into this array. 278 */ 279 struct drm_gem_cma_object **bo; 280 uint32_t bo_count; 281 282 /* List of BOs that are being written by the RCL. Other than 283 * the binner temporary storage, this is all the BOs written 284 * by the job. 285 */ 286 struct drm_gem_cma_object *rcl_write_bo[4]; 287 uint32_t rcl_write_bo_count; 288 289 /* Pointers for our position in vc4->job_list */ 290 struct list_head head; 291 292 /* List of other BOs used in the job that need to be released 293 * once the job is complete. 294 */ 295 struct list_head unref_list; 296 297 /* Current unvalidated indices into @bo loaded by the non-hardware 298 * VC4_PACKET_GEM_HANDLES. 299 */ 300 uint32_t bo_index[2]; 301 302 /* This is the BO where we store the validated command lists, shader 303 * records, and uniforms. 304 */ 305 struct drm_gem_cma_object *exec_bo; 306 307 /** 308 * This tracks the per-shader-record state (packet 64) that 309 * determines the length of the shader record and the offset 310 * it's expected to be found at. It gets read in from the 311 * command lists. 312 */ 313 struct vc4_shader_state { 314 uint32_t addr; 315 /* Maximum vertex index referenced by any primitive using this 316 * shader state. 317 */ 318 uint32_t max_index; 319 } *shader_state; 320 321 /** How many shader states the user declared they were using. */ 322 uint32_t shader_state_size; 323 /** How many shader state records the validator has seen. */ 324 uint32_t shader_state_count; 325 326 bool found_tile_binning_mode_config_packet; 327 bool found_start_tile_binning_packet; 328 bool found_increment_semaphore_packet; 329 bool found_flush; 330 uint8_t bin_tiles_x, bin_tiles_y; 331 /* Physical address of the start of the tile alloc array 332 * (where each tile's binned CL will start) 333 */ 334 uint32_t tile_alloc_offset; 335 /* Bitmask of which binner slots are freed when this job completes. */ 336 uint32_t bin_slots; 337 338 /** 339 * Computed addresses pointing into exec_bo where we start the 340 * bin thread (ct0) and render thread (ct1). 341 */ 342 uint32_t ct0ca, ct0ea; 343 uint32_t ct1ca, ct1ea; 344 345 /* Pointer to the unvalidated bin CL (if present). */ 346 void *bin_u; 347 348 /* Pointers to the shader recs. These paddr gets incremented as CL 349 * packets are relocated in validate_gl_shader_state, and the vaddrs 350 * (u and v) get incremented and size decremented as the shader recs 351 * themselves are validated. 352 */ 353 void *shader_rec_u; 354 void *shader_rec_v; 355 uint32_t shader_rec_p; 356 uint32_t shader_rec_size; 357 358 /* Pointers to the uniform data. These pointers are incremented, and 359 * size decremented, as each batch of uniforms is uploaded. 360 */ 361 void *uniforms_u; 362 void *uniforms_v; 363 uint32_t uniforms_p; 364 uint32_t uniforms_size; 365 }; 366 367 static inline struct vc4_exec_info * 368 vc4_first_bin_job(struct vc4_dev *vc4) 369 { 370 return list_first_entry_or_null(&vc4->bin_job_list, 371 struct vc4_exec_info, head); 372 } 373 374 static inline struct vc4_exec_info * 375 vc4_first_render_job(struct vc4_dev *vc4) 376 { 377 return list_first_entry_or_null(&vc4->render_job_list, 378 struct vc4_exec_info, head); 379 } 380 381 static inline struct vc4_exec_info * 382 vc4_last_render_job(struct vc4_dev *vc4) 383 { 384 if (list_empty(&vc4->render_job_list)) 385 return NULL; 386 return list_last_entry(&vc4->render_job_list, 387 struct vc4_exec_info, head); 388 } 389 390 /** 391 * struct vc4_texture_sample_info - saves the offsets into the UBO for texture 392 * setup parameters. 393 * 394 * This will be used at draw time to relocate the reference to the texture 395 * contents in p0, and validate that the offset combined with 396 * width/height/stride/etc. from p1 and p2/p3 doesn't sample outside the BO. 397 * Note that the hardware treats unprovided config parameters as 0, so not all 398 * of them need to be set up for every texure sample, and we'll store ~0 as 399 * the offset to mark the unused ones. 400 * 401 * See the VC4 3D architecture guide page 41 ("Texture and Memory Lookup Unit 402 * Setup") for definitions of the texture parameters. 403 */ 404 struct vc4_texture_sample_info { 405 bool is_direct; 406 uint32_t p_offset[4]; 407 }; 408 409 /** 410 * struct vc4_validated_shader_info - information about validated shaders that 411 * needs to be used from command list validation. 412 * 413 * For a given shader, each time a shader state record references it, we need 414 * to verify that the shader doesn't read more uniforms than the shader state 415 * record's uniform BO pointer can provide, and we need to apply relocations 416 * and validate the shader state record's uniforms that define the texture 417 * samples. 418 */ 419 struct vc4_validated_shader_info { 420 uint32_t uniforms_size; 421 uint32_t uniforms_src_size; 422 uint32_t num_texture_samples; 423 struct vc4_texture_sample_info *texture_samples; 424 425 uint32_t num_uniform_addr_offsets; 426 uint32_t *uniform_addr_offsets; 427 428 bool is_threaded; 429 }; 430 431 /** 432 * _wait_for - magic (register) wait macro 433 * 434 * Does the right thing for modeset paths when run under kdgb or similar atomic 435 * contexts. Note that it's important that we check the condition again after 436 * having timed out, since the timeout could be due to preemption or similar and 437 * we've never had a chance to check the condition before the timeout. 438 */ 439 #define _wait_for(COND, MS, W) ({ \ 440 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \ 441 int ret__ = 0; \ 442 while (!(COND)) { \ 443 if (time_after(jiffies, timeout__)) { \ 444 if (!(COND)) \ 445 ret__ = -ETIMEDOUT; \ 446 break; \ 447 } \ 448 if (W && drm_can_sleep()) { \ 449 msleep(W); \ 450 } else { \ 451 cpu_relax(); \ 452 } \ 453 } \ 454 ret__; \ 455 }) 456 457 #define wait_for(COND, MS) _wait_for(COND, MS, 1) 458 459 /* vc4_bo.c */ 460 struct drm_gem_object *vc4_create_object(struct drm_device *dev, size_t size); 461 void vc4_free_object(struct drm_gem_object *gem_obj); 462 struct vc4_bo *vc4_bo_create(struct drm_device *dev, size_t size, 463 bool from_cache); 464 int vc4_dumb_create(struct drm_file *file_priv, 465 struct drm_device *dev, 466 struct drm_mode_create_dumb *args); 467 struct dma_buf *vc4_prime_export(struct drm_device *dev, 468 struct drm_gem_object *obj, int flags); 469 int vc4_create_bo_ioctl(struct drm_device *dev, void *data, 470 struct drm_file *file_priv); 471 int vc4_create_shader_bo_ioctl(struct drm_device *dev, void *data, 472 struct drm_file *file_priv); 473 int vc4_mmap_bo_ioctl(struct drm_device *dev, void *data, 474 struct drm_file *file_priv); 475 int vc4_set_tiling_ioctl(struct drm_device *dev, void *data, 476 struct drm_file *file_priv); 477 int vc4_get_tiling_ioctl(struct drm_device *dev, void *data, 478 struct drm_file *file_priv); 479 int vc4_get_hang_state_ioctl(struct drm_device *dev, void *data, 480 struct drm_file *file_priv); 481 int vc4_mmap(struct file *filp, struct vm_area_struct *vma); 482 struct reservation_object *vc4_prime_res_obj(struct drm_gem_object *obj); 483 int vc4_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma); 484 struct drm_gem_object *vc4_prime_import_sg_table(struct drm_device *dev, 485 struct dma_buf_attachment *attach, 486 struct sg_table *sgt); 487 void *vc4_prime_vmap(struct drm_gem_object *obj); 488 void vc4_bo_cache_init(struct drm_device *dev); 489 void vc4_bo_cache_destroy(struct drm_device *dev); 490 int vc4_bo_stats_debugfs(struct seq_file *m, void *arg); 491 492 /* vc4_crtc.c */ 493 extern struct platform_driver vc4_crtc_driver; 494 bool vc4_event_pending(struct drm_crtc *crtc); 495 int vc4_crtc_debugfs_regs(struct seq_file *m, void *arg); 496 bool vc4_crtc_get_scanoutpos(struct drm_device *dev, unsigned int crtc_id, 497 bool in_vblank_irq, int *vpos, int *hpos, 498 ktime_t *stime, ktime_t *etime, 499 const struct drm_display_mode *mode); 500 501 /* vc4_debugfs.c */ 502 int vc4_debugfs_init(struct drm_minor *minor); 503 504 /* vc4_drv.c */ 505 void __iomem *vc4_ioremap_regs(struct platform_device *dev, int index); 506 507 /* vc4_dpi.c */ 508 extern struct platform_driver vc4_dpi_driver; 509 int vc4_dpi_debugfs_regs(struct seq_file *m, void *unused); 510 511 /* vc4_dsi.c */ 512 extern struct platform_driver vc4_dsi_driver; 513 int vc4_dsi_debugfs_regs(struct seq_file *m, void *unused); 514 515 /* vc4_fence.c */ 516 extern const struct dma_fence_ops vc4_fence_ops; 517 518 /* vc4_gem.c */ 519 void vc4_gem_init(struct drm_device *dev); 520 void vc4_gem_destroy(struct drm_device *dev); 521 int vc4_submit_cl_ioctl(struct drm_device *dev, void *data, 522 struct drm_file *file_priv); 523 int vc4_wait_seqno_ioctl(struct drm_device *dev, void *data, 524 struct drm_file *file_priv); 525 int vc4_wait_bo_ioctl(struct drm_device *dev, void *data, 526 struct drm_file *file_priv); 527 void vc4_submit_next_bin_job(struct drm_device *dev); 528 void vc4_submit_next_render_job(struct drm_device *dev); 529 void vc4_move_job_to_render(struct drm_device *dev, struct vc4_exec_info *exec); 530 int vc4_wait_for_seqno(struct drm_device *dev, uint64_t seqno, 531 uint64_t timeout_ns, bool interruptible); 532 void vc4_job_handle_completed(struct vc4_dev *vc4); 533 int vc4_queue_seqno_cb(struct drm_device *dev, 534 struct vc4_seqno_cb *cb, uint64_t seqno, 535 void (*func)(struct vc4_seqno_cb *cb)); 536 537 /* vc4_hdmi.c */ 538 extern struct platform_driver vc4_hdmi_driver; 539 int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused); 540 541 /* vc4_vec.c */ 542 extern struct platform_driver vc4_vec_driver; 543 int vc4_vec_debugfs_regs(struct seq_file *m, void *unused); 544 545 /* vc4_irq.c */ 546 irqreturn_t vc4_irq(int irq, void *arg); 547 void vc4_irq_preinstall(struct drm_device *dev); 548 int vc4_irq_postinstall(struct drm_device *dev); 549 void vc4_irq_uninstall(struct drm_device *dev); 550 void vc4_irq_reset(struct drm_device *dev); 551 552 /* vc4_hvs.c */ 553 extern struct platform_driver vc4_hvs_driver; 554 void vc4_hvs_dump_state(struct drm_device *dev); 555 int vc4_hvs_debugfs_regs(struct seq_file *m, void *unused); 556 557 /* vc4_kms.c */ 558 int vc4_kms_load(struct drm_device *dev); 559 560 /* vc4_plane.c */ 561 struct drm_plane *vc4_plane_init(struct drm_device *dev, 562 enum drm_plane_type type); 563 u32 vc4_plane_write_dlist(struct drm_plane *plane, u32 __iomem *dlist); 564 u32 vc4_plane_dlist_size(const struct drm_plane_state *state); 565 void vc4_plane_async_set_fb(struct drm_plane *plane, 566 struct drm_framebuffer *fb); 567 568 /* vc4_v3d.c */ 569 extern struct platform_driver vc4_v3d_driver; 570 int vc4_v3d_debugfs_ident(struct seq_file *m, void *unused); 571 int vc4_v3d_debugfs_regs(struct seq_file *m, void *unused); 572 int vc4_v3d_get_bin_slot(struct vc4_dev *vc4); 573 574 /* vc4_validate.c */ 575 int 576 vc4_validate_bin_cl(struct drm_device *dev, 577 void *validated, 578 void *unvalidated, 579 struct vc4_exec_info *exec); 580 581 int 582 vc4_validate_shader_recs(struct drm_device *dev, struct vc4_exec_info *exec); 583 584 struct drm_gem_cma_object *vc4_use_bo(struct vc4_exec_info *exec, 585 uint32_t hindex); 586 587 int vc4_get_rcl(struct drm_device *dev, struct vc4_exec_info *exec); 588 589 bool vc4_check_tex_size(struct vc4_exec_info *exec, 590 struct drm_gem_cma_object *fbo, 591 uint32_t offset, uint8_t tiling_format, 592 uint32_t width, uint32_t height, uint8_t cpp); 593 594 /* vc4_validate_shader.c */ 595 struct vc4_validated_shader_info * 596 vc4_validate_shader(struct drm_gem_cma_object *shader_obj); 597