1 /* 2 * Copyright (C) 2015 Broadcom 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 #include <linux/reservation.h> 10 #include <drm/drmP.h> 11 #include <drm/drm_encoder.h> 12 #include <drm/drm_gem_cma_helper.h> 13 14 /* Don't forget to update vc4_bo.c: bo_type_names[] when adding to 15 * this. 16 */ 17 enum vc4_kernel_bo_type { 18 /* Any kernel allocation (gem_create_object hook) before it 19 * gets another type set. 20 */ 21 VC4_BO_TYPE_KERNEL, 22 VC4_BO_TYPE_V3D, 23 VC4_BO_TYPE_V3D_SHADER, 24 VC4_BO_TYPE_DUMB, 25 VC4_BO_TYPE_BIN, 26 VC4_BO_TYPE_RCL, 27 VC4_BO_TYPE_BCL, 28 VC4_BO_TYPE_KERNEL_CACHE, 29 VC4_BO_TYPE_COUNT 30 }; 31 32 struct vc4_dev { 33 struct drm_device *dev; 34 35 struct vc4_hdmi *hdmi; 36 struct vc4_hvs *hvs; 37 struct vc4_v3d *v3d; 38 struct vc4_dpi *dpi; 39 struct vc4_dsi *dsi1; 40 struct vc4_vec *vec; 41 42 struct drm_fbdev_cma *fbdev; 43 44 struct vc4_hang_state *hang_state; 45 46 /* The kernel-space BO cache. Tracks buffers that have been 47 * unreferenced by all other users (refcounts of 0!) but not 48 * yet freed, so we can do cheap allocations. 49 */ 50 struct vc4_bo_cache { 51 /* Array of list heads for entries in the BO cache, 52 * based on number of pages, so we can do O(1) lookups 53 * in the cache when allocating. 54 */ 55 struct list_head *size_list; 56 uint32_t size_list_size; 57 58 /* List of all BOs in the cache, ordered by age, so we 59 * can do O(1) lookups when trying to free old 60 * buffers. 61 */ 62 struct list_head time_list; 63 struct work_struct time_work; 64 struct timer_list time_timer; 65 } bo_cache; 66 67 u32 num_labels; 68 struct vc4_label { 69 const char *name; 70 u32 num_allocated; 71 u32 size_allocated; 72 } *bo_labels; 73 74 /* Protects bo_cache and bo_labels. */ 75 struct mutex bo_lock; 76 77 uint64_t dma_fence_context; 78 79 /* Sequence number for the last job queued in bin_job_list. 80 * Starts at 0 (no jobs emitted). 81 */ 82 uint64_t emit_seqno; 83 84 /* Sequence number for the last completed job on the GPU. 85 * Starts at 0 (no jobs completed). 86 */ 87 uint64_t finished_seqno; 88 89 /* List of all struct vc4_exec_info for jobs to be executed in 90 * the binner. The first job in the list is the one currently 91 * programmed into ct0ca for execution. 92 */ 93 struct list_head bin_job_list; 94 95 /* List of all struct vc4_exec_info for jobs that have 96 * completed binning and are ready for rendering. The first 97 * job in the list is the one currently programmed into ct1ca 98 * for execution. 99 */ 100 struct list_head render_job_list; 101 102 /* List of the finished vc4_exec_infos waiting to be freed by 103 * job_done_work. 104 */ 105 struct list_head job_done_list; 106 /* Spinlock used to synchronize the job_list and seqno 107 * accesses between the IRQ handler and GEM ioctls. 108 */ 109 spinlock_t job_lock; 110 wait_queue_head_t job_wait_queue; 111 struct work_struct job_done_work; 112 113 /* List of struct vc4_seqno_cb for callbacks to be made from a 114 * workqueue when the given seqno is passed. 115 */ 116 struct list_head seqno_cb_list; 117 118 /* The memory used for storing binner tile alloc, tile state, 119 * and overflow memory allocations. This is freed when V3D 120 * powers down. 121 */ 122 struct vc4_bo *bin_bo; 123 124 /* Size of blocks allocated within bin_bo. */ 125 uint32_t bin_alloc_size; 126 127 /* Bitmask of the bin_alloc_size chunks in bin_bo that are 128 * used. 129 */ 130 uint32_t bin_alloc_used; 131 132 /* Bitmask of the current bin_alloc used for overflow memory. */ 133 uint32_t bin_alloc_overflow; 134 135 struct work_struct overflow_mem_work; 136 137 int power_refcount; 138 139 /* Mutex controlling the power refcount. */ 140 struct mutex power_lock; 141 142 struct { 143 struct timer_list timer; 144 struct work_struct reset_work; 145 } hangcheck; 146 147 struct semaphore async_modeset; 148 }; 149 150 static inline struct vc4_dev * 151 to_vc4_dev(struct drm_device *dev) 152 { 153 return (struct vc4_dev *)dev->dev_private; 154 } 155 156 struct vc4_bo { 157 struct drm_gem_cma_object base; 158 159 /* seqno of the last job to render using this BO. */ 160 uint64_t seqno; 161 162 /* seqno of the last job to use the RCL to write to this BO. 163 * 164 * Note that this doesn't include binner overflow memory 165 * writes. 166 */ 167 uint64_t write_seqno; 168 169 bool t_format; 170 171 /* List entry for the BO's position in either 172 * vc4_exec_info->unref_list or vc4_dev->bo_cache.time_list 173 */ 174 struct list_head unref_head; 175 176 /* Time in jiffies when the BO was put in vc4->bo_cache. */ 177 unsigned long free_time; 178 179 /* List entry for the BO's position in vc4_dev->bo_cache.size_list */ 180 struct list_head size_head; 181 182 /* Struct for shader validation state, if created by 183 * DRM_IOCTL_VC4_CREATE_SHADER_BO. 184 */ 185 struct vc4_validated_shader_info *validated_shader; 186 187 /* normally (resv == &_resv) except for imported bo's */ 188 struct reservation_object *resv; 189 struct reservation_object _resv; 190 191 /* One of enum vc4_kernel_bo_type, or VC4_BO_TYPE_COUNT + i 192 * for user-allocated labels. 193 */ 194 int label; 195 }; 196 197 static inline struct vc4_bo * 198 to_vc4_bo(struct drm_gem_object *bo) 199 { 200 return (struct vc4_bo *)bo; 201 } 202 203 struct vc4_fence { 204 struct dma_fence base; 205 struct drm_device *dev; 206 /* vc4 seqno for signaled() test */ 207 uint64_t seqno; 208 }; 209 210 static inline struct vc4_fence * 211 to_vc4_fence(struct dma_fence *fence) 212 { 213 return (struct vc4_fence *)fence; 214 } 215 216 struct vc4_seqno_cb { 217 struct work_struct work; 218 uint64_t seqno; 219 void (*func)(struct vc4_seqno_cb *cb); 220 }; 221 222 struct vc4_v3d { 223 struct vc4_dev *vc4; 224 struct platform_device *pdev; 225 void __iomem *regs; 226 struct clk *clk; 227 }; 228 229 struct vc4_hvs { 230 struct platform_device *pdev; 231 void __iomem *regs; 232 u32 __iomem *dlist; 233 234 /* Memory manager for CRTCs to allocate space in the display 235 * list. Units are dwords. 236 */ 237 struct drm_mm dlist_mm; 238 /* Memory manager for the LBM memory used by HVS scaling. */ 239 struct drm_mm lbm_mm; 240 spinlock_t mm_lock; 241 242 struct drm_mm_node mitchell_netravali_filter; 243 }; 244 245 struct vc4_plane { 246 struct drm_plane base; 247 }; 248 249 static inline struct vc4_plane * 250 to_vc4_plane(struct drm_plane *plane) 251 { 252 return (struct vc4_plane *)plane; 253 } 254 255 enum vc4_encoder_type { 256 VC4_ENCODER_TYPE_NONE, 257 VC4_ENCODER_TYPE_HDMI, 258 VC4_ENCODER_TYPE_VEC, 259 VC4_ENCODER_TYPE_DSI0, 260 VC4_ENCODER_TYPE_DSI1, 261 VC4_ENCODER_TYPE_SMI, 262 VC4_ENCODER_TYPE_DPI, 263 }; 264 265 struct vc4_encoder { 266 struct drm_encoder base; 267 enum vc4_encoder_type type; 268 u32 clock_select; 269 }; 270 271 static inline struct vc4_encoder * 272 to_vc4_encoder(struct drm_encoder *encoder) 273 { 274 return container_of(encoder, struct vc4_encoder, base); 275 } 276 277 #define V3D_READ(offset) readl(vc4->v3d->regs + offset) 278 #define V3D_WRITE(offset, val) writel(val, vc4->v3d->regs + offset) 279 #define HVS_READ(offset) readl(vc4->hvs->regs + offset) 280 #define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset) 281 282 struct vc4_exec_info { 283 /* Sequence number for this bin/render job. */ 284 uint64_t seqno; 285 286 /* Latest write_seqno of any BO that binning depends on. */ 287 uint64_t bin_dep_seqno; 288 289 struct dma_fence *fence; 290 291 /* Last current addresses the hardware was processing when the 292 * hangcheck timer checked on us. 293 */ 294 uint32_t last_ct0ca, last_ct1ca; 295 296 /* Kernel-space copy of the ioctl arguments */ 297 struct drm_vc4_submit_cl *args; 298 299 /* This is the array of BOs that were looked up at the start of exec. 300 * Command validation will use indices into this array. 301 */ 302 struct drm_gem_cma_object **bo; 303 uint32_t bo_count; 304 305 /* List of BOs that are being written by the RCL. Other than 306 * the binner temporary storage, this is all the BOs written 307 * by the job. 308 */ 309 struct drm_gem_cma_object *rcl_write_bo[4]; 310 uint32_t rcl_write_bo_count; 311 312 /* Pointers for our position in vc4->job_list */ 313 struct list_head head; 314 315 /* List of other BOs used in the job that need to be released 316 * once the job is complete. 317 */ 318 struct list_head unref_list; 319 320 /* Current unvalidated indices into @bo loaded by the non-hardware 321 * VC4_PACKET_GEM_HANDLES. 322 */ 323 uint32_t bo_index[2]; 324 325 /* This is the BO where we store the validated command lists, shader 326 * records, and uniforms. 327 */ 328 struct drm_gem_cma_object *exec_bo; 329 330 /** 331 * This tracks the per-shader-record state (packet 64) that 332 * determines the length of the shader record and the offset 333 * it's expected to be found at. It gets read in from the 334 * command lists. 335 */ 336 struct vc4_shader_state { 337 uint32_t addr; 338 /* Maximum vertex index referenced by any primitive using this 339 * shader state. 340 */ 341 uint32_t max_index; 342 } *shader_state; 343 344 /** How many shader states the user declared they were using. */ 345 uint32_t shader_state_size; 346 /** How many shader state records the validator has seen. */ 347 uint32_t shader_state_count; 348 349 bool found_tile_binning_mode_config_packet; 350 bool found_start_tile_binning_packet; 351 bool found_increment_semaphore_packet; 352 bool found_flush; 353 uint8_t bin_tiles_x, bin_tiles_y; 354 /* Physical address of the start of the tile alloc array 355 * (where each tile's binned CL will start) 356 */ 357 uint32_t tile_alloc_offset; 358 /* Bitmask of which binner slots are freed when this job completes. */ 359 uint32_t bin_slots; 360 361 /** 362 * Computed addresses pointing into exec_bo where we start the 363 * bin thread (ct0) and render thread (ct1). 364 */ 365 uint32_t ct0ca, ct0ea; 366 uint32_t ct1ca, ct1ea; 367 368 /* Pointer to the unvalidated bin CL (if present). */ 369 void *bin_u; 370 371 /* Pointers to the shader recs. These paddr gets incremented as CL 372 * packets are relocated in validate_gl_shader_state, and the vaddrs 373 * (u and v) get incremented and size decremented as the shader recs 374 * themselves are validated. 375 */ 376 void *shader_rec_u; 377 void *shader_rec_v; 378 uint32_t shader_rec_p; 379 uint32_t shader_rec_size; 380 381 /* Pointers to the uniform data. These pointers are incremented, and 382 * size decremented, as each batch of uniforms is uploaded. 383 */ 384 void *uniforms_u; 385 void *uniforms_v; 386 uint32_t uniforms_p; 387 uint32_t uniforms_size; 388 }; 389 390 static inline struct vc4_exec_info * 391 vc4_first_bin_job(struct vc4_dev *vc4) 392 { 393 return list_first_entry_or_null(&vc4->bin_job_list, 394 struct vc4_exec_info, head); 395 } 396 397 static inline struct vc4_exec_info * 398 vc4_first_render_job(struct vc4_dev *vc4) 399 { 400 return list_first_entry_or_null(&vc4->render_job_list, 401 struct vc4_exec_info, head); 402 } 403 404 static inline struct vc4_exec_info * 405 vc4_last_render_job(struct vc4_dev *vc4) 406 { 407 if (list_empty(&vc4->render_job_list)) 408 return NULL; 409 return list_last_entry(&vc4->render_job_list, 410 struct vc4_exec_info, head); 411 } 412 413 /** 414 * struct vc4_texture_sample_info - saves the offsets into the UBO for texture 415 * setup parameters. 416 * 417 * This will be used at draw time to relocate the reference to the texture 418 * contents in p0, and validate that the offset combined with 419 * width/height/stride/etc. from p1 and p2/p3 doesn't sample outside the BO. 420 * Note that the hardware treats unprovided config parameters as 0, so not all 421 * of them need to be set up for every texure sample, and we'll store ~0 as 422 * the offset to mark the unused ones. 423 * 424 * See the VC4 3D architecture guide page 41 ("Texture and Memory Lookup Unit 425 * Setup") for definitions of the texture parameters. 426 */ 427 struct vc4_texture_sample_info { 428 bool is_direct; 429 uint32_t p_offset[4]; 430 }; 431 432 /** 433 * struct vc4_validated_shader_info - information about validated shaders that 434 * needs to be used from command list validation. 435 * 436 * For a given shader, each time a shader state record references it, we need 437 * to verify that the shader doesn't read more uniforms than the shader state 438 * record's uniform BO pointer can provide, and we need to apply relocations 439 * and validate the shader state record's uniforms that define the texture 440 * samples. 441 */ 442 struct vc4_validated_shader_info { 443 uint32_t uniforms_size; 444 uint32_t uniforms_src_size; 445 uint32_t num_texture_samples; 446 struct vc4_texture_sample_info *texture_samples; 447 448 uint32_t num_uniform_addr_offsets; 449 uint32_t *uniform_addr_offsets; 450 451 bool is_threaded; 452 }; 453 454 /** 455 * _wait_for - magic (register) wait macro 456 * 457 * Does the right thing for modeset paths when run under kdgb or similar atomic 458 * contexts. Note that it's important that we check the condition again after 459 * having timed out, since the timeout could be due to preemption or similar and 460 * we've never had a chance to check the condition before the timeout. 461 */ 462 #define _wait_for(COND, MS, W) ({ \ 463 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \ 464 int ret__ = 0; \ 465 while (!(COND)) { \ 466 if (time_after(jiffies, timeout__)) { \ 467 if (!(COND)) \ 468 ret__ = -ETIMEDOUT; \ 469 break; \ 470 } \ 471 if (W && drm_can_sleep()) { \ 472 msleep(W); \ 473 } else { \ 474 cpu_relax(); \ 475 } \ 476 } \ 477 ret__; \ 478 }) 479 480 #define wait_for(COND, MS) _wait_for(COND, MS, 1) 481 482 /* vc4_bo.c */ 483 struct drm_gem_object *vc4_create_object(struct drm_device *dev, size_t size); 484 void vc4_free_object(struct drm_gem_object *gem_obj); 485 struct vc4_bo *vc4_bo_create(struct drm_device *dev, size_t size, 486 bool from_cache, enum vc4_kernel_bo_type type); 487 int vc4_dumb_create(struct drm_file *file_priv, 488 struct drm_device *dev, 489 struct drm_mode_create_dumb *args); 490 struct dma_buf *vc4_prime_export(struct drm_device *dev, 491 struct drm_gem_object *obj, int flags); 492 int vc4_create_bo_ioctl(struct drm_device *dev, void *data, 493 struct drm_file *file_priv); 494 int vc4_create_shader_bo_ioctl(struct drm_device *dev, void *data, 495 struct drm_file *file_priv); 496 int vc4_mmap_bo_ioctl(struct drm_device *dev, void *data, 497 struct drm_file *file_priv); 498 int vc4_set_tiling_ioctl(struct drm_device *dev, void *data, 499 struct drm_file *file_priv); 500 int vc4_get_tiling_ioctl(struct drm_device *dev, void *data, 501 struct drm_file *file_priv); 502 int vc4_get_hang_state_ioctl(struct drm_device *dev, void *data, 503 struct drm_file *file_priv); 504 int vc4_label_bo_ioctl(struct drm_device *dev, void *data, 505 struct drm_file *file_priv); 506 int vc4_mmap(struct file *filp, struct vm_area_struct *vma); 507 struct reservation_object *vc4_prime_res_obj(struct drm_gem_object *obj); 508 int vc4_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma); 509 struct drm_gem_object *vc4_prime_import_sg_table(struct drm_device *dev, 510 struct dma_buf_attachment *attach, 511 struct sg_table *sgt); 512 void *vc4_prime_vmap(struct drm_gem_object *obj); 513 int vc4_bo_cache_init(struct drm_device *dev); 514 void vc4_bo_cache_destroy(struct drm_device *dev); 515 int vc4_bo_stats_debugfs(struct seq_file *m, void *arg); 516 517 /* vc4_crtc.c */ 518 extern struct platform_driver vc4_crtc_driver; 519 int vc4_crtc_debugfs_regs(struct seq_file *m, void *arg); 520 bool vc4_crtc_get_scanoutpos(struct drm_device *dev, unsigned int crtc_id, 521 bool in_vblank_irq, int *vpos, int *hpos, 522 ktime_t *stime, ktime_t *etime, 523 const struct drm_display_mode *mode); 524 525 /* vc4_debugfs.c */ 526 int vc4_debugfs_init(struct drm_minor *minor); 527 528 /* vc4_drv.c */ 529 void __iomem *vc4_ioremap_regs(struct platform_device *dev, int index); 530 531 /* vc4_dpi.c */ 532 extern struct platform_driver vc4_dpi_driver; 533 int vc4_dpi_debugfs_regs(struct seq_file *m, void *unused); 534 535 /* vc4_dsi.c */ 536 extern struct platform_driver vc4_dsi_driver; 537 int vc4_dsi_debugfs_regs(struct seq_file *m, void *unused); 538 539 /* vc4_fence.c */ 540 extern const struct dma_fence_ops vc4_fence_ops; 541 542 /* vc4_gem.c */ 543 void vc4_gem_init(struct drm_device *dev); 544 void vc4_gem_destroy(struct drm_device *dev); 545 int vc4_submit_cl_ioctl(struct drm_device *dev, void *data, 546 struct drm_file *file_priv); 547 int vc4_wait_seqno_ioctl(struct drm_device *dev, void *data, 548 struct drm_file *file_priv); 549 int vc4_wait_bo_ioctl(struct drm_device *dev, void *data, 550 struct drm_file *file_priv); 551 void vc4_submit_next_bin_job(struct drm_device *dev); 552 void vc4_submit_next_render_job(struct drm_device *dev); 553 void vc4_move_job_to_render(struct drm_device *dev, struct vc4_exec_info *exec); 554 int vc4_wait_for_seqno(struct drm_device *dev, uint64_t seqno, 555 uint64_t timeout_ns, bool interruptible); 556 void vc4_job_handle_completed(struct vc4_dev *vc4); 557 int vc4_queue_seqno_cb(struct drm_device *dev, 558 struct vc4_seqno_cb *cb, uint64_t seqno, 559 void (*func)(struct vc4_seqno_cb *cb)); 560 561 /* vc4_hdmi.c */ 562 extern struct platform_driver vc4_hdmi_driver; 563 int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused); 564 565 /* vc4_vec.c */ 566 extern struct platform_driver vc4_vec_driver; 567 int vc4_vec_debugfs_regs(struct seq_file *m, void *unused); 568 569 /* vc4_irq.c */ 570 irqreturn_t vc4_irq(int irq, void *arg); 571 void vc4_irq_preinstall(struct drm_device *dev); 572 int vc4_irq_postinstall(struct drm_device *dev); 573 void vc4_irq_uninstall(struct drm_device *dev); 574 void vc4_irq_reset(struct drm_device *dev); 575 576 /* vc4_hvs.c */ 577 extern struct platform_driver vc4_hvs_driver; 578 void vc4_hvs_dump_state(struct drm_device *dev); 579 int vc4_hvs_debugfs_regs(struct seq_file *m, void *unused); 580 581 /* vc4_kms.c */ 582 int vc4_kms_load(struct drm_device *dev); 583 584 /* vc4_plane.c */ 585 struct drm_plane *vc4_plane_init(struct drm_device *dev, 586 enum drm_plane_type type); 587 u32 vc4_plane_write_dlist(struct drm_plane *plane, u32 __iomem *dlist); 588 u32 vc4_plane_dlist_size(const struct drm_plane_state *state); 589 void vc4_plane_async_set_fb(struct drm_plane *plane, 590 struct drm_framebuffer *fb); 591 592 /* vc4_v3d.c */ 593 extern struct platform_driver vc4_v3d_driver; 594 int vc4_v3d_debugfs_ident(struct seq_file *m, void *unused); 595 int vc4_v3d_debugfs_regs(struct seq_file *m, void *unused); 596 int vc4_v3d_get_bin_slot(struct vc4_dev *vc4); 597 598 /* vc4_validate.c */ 599 int 600 vc4_validate_bin_cl(struct drm_device *dev, 601 void *validated, 602 void *unvalidated, 603 struct vc4_exec_info *exec); 604 605 int 606 vc4_validate_shader_recs(struct drm_device *dev, struct vc4_exec_info *exec); 607 608 struct drm_gem_cma_object *vc4_use_bo(struct vc4_exec_info *exec, 609 uint32_t hindex); 610 611 int vc4_get_rcl(struct drm_device *dev, struct vc4_exec_info *exec); 612 613 bool vc4_check_tex_size(struct vc4_exec_info *exec, 614 struct drm_gem_cma_object *fbo, 615 uint32_t offset, uint8_t tiling_format, 616 uint32_t width, uint32_t height, uint8_t cpp); 617 618 /* vc4_validate_shader.c */ 619 struct vc4_validated_shader_info * 620 vc4_validate_shader(struct drm_gem_cma_object *shader_obj); 621