1 /* 2 * Copyright (C) 2015 Broadcom 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 #include "drmP.h" 10 #include "drm_gem_cma_helper.h" 11 12 #include <drm/drm_encoder.h> 13 14 struct vc4_dev { 15 struct drm_device *dev; 16 17 struct vc4_hdmi *hdmi; 18 struct vc4_hvs *hvs; 19 struct vc4_v3d *v3d; 20 struct vc4_dpi *dpi; 21 struct vc4_dsi *dsi1; 22 struct vc4_vec *vec; 23 24 struct drm_fbdev_cma *fbdev; 25 26 struct vc4_hang_state *hang_state; 27 28 /* The kernel-space BO cache. Tracks buffers that have been 29 * unreferenced by all other users (refcounts of 0!) but not 30 * yet freed, so we can do cheap allocations. 31 */ 32 struct vc4_bo_cache { 33 /* Array of list heads for entries in the BO cache, 34 * based on number of pages, so we can do O(1) lookups 35 * in the cache when allocating. 36 */ 37 struct list_head *size_list; 38 uint32_t size_list_size; 39 40 /* List of all BOs in the cache, ordered by age, so we 41 * can do O(1) lookups when trying to free old 42 * buffers. 43 */ 44 struct list_head time_list; 45 struct work_struct time_work; 46 struct timer_list time_timer; 47 } bo_cache; 48 49 struct vc4_bo_stats { 50 u32 num_allocated; 51 u32 size_allocated; 52 u32 num_cached; 53 u32 size_cached; 54 } bo_stats; 55 56 /* Protects bo_cache and the BO stats. */ 57 struct mutex bo_lock; 58 59 /* Sequence number for the last job queued in bin_job_list. 60 * Starts at 0 (no jobs emitted). 61 */ 62 uint64_t emit_seqno; 63 64 /* Sequence number for the last completed job on the GPU. 65 * Starts at 0 (no jobs completed). 66 */ 67 uint64_t finished_seqno; 68 69 /* List of all struct vc4_exec_info for jobs to be executed in 70 * the binner. The first job in the list is the one currently 71 * programmed into ct0ca for execution. 72 */ 73 struct list_head bin_job_list; 74 75 /* List of all struct vc4_exec_info for jobs that have 76 * completed binning and are ready for rendering. The first 77 * job in the list is the one currently programmed into ct1ca 78 * for execution. 79 */ 80 struct list_head render_job_list; 81 82 /* List of the finished vc4_exec_infos waiting to be freed by 83 * job_done_work. 84 */ 85 struct list_head job_done_list; 86 /* Spinlock used to synchronize the job_list and seqno 87 * accesses between the IRQ handler and GEM ioctls. 88 */ 89 spinlock_t job_lock; 90 wait_queue_head_t job_wait_queue; 91 struct work_struct job_done_work; 92 93 /* List of struct vc4_seqno_cb for callbacks to be made from a 94 * workqueue when the given seqno is passed. 95 */ 96 struct list_head seqno_cb_list; 97 98 /* The binner overflow memory that's currently set up in 99 * BPOA/BPOS registers. When overflow occurs and a new one is 100 * allocated, the previous one will be moved to 101 * vc4->current_exec's free list. 102 */ 103 struct vc4_bo *overflow_mem; 104 struct work_struct overflow_mem_work; 105 106 int power_refcount; 107 108 /* Mutex controlling the power refcount. */ 109 struct mutex power_lock; 110 111 struct { 112 struct timer_list timer; 113 struct work_struct reset_work; 114 } hangcheck; 115 116 struct semaphore async_modeset; 117 }; 118 119 static inline struct vc4_dev * 120 to_vc4_dev(struct drm_device *dev) 121 { 122 return (struct vc4_dev *)dev->dev_private; 123 } 124 125 struct vc4_bo { 126 struct drm_gem_cma_object base; 127 128 /* seqno of the last job to render using this BO. */ 129 uint64_t seqno; 130 131 /* seqno of the last job to use the RCL to write to this BO. 132 * 133 * Note that this doesn't include binner overflow memory 134 * writes. 135 */ 136 uint64_t write_seqno; 137 138 /* List entry for the BO's position in either 139 * vc4_exec_info->unref_list or vc4_dev->bo_cache.time_list 140 */ 141 struct list_head unref_head; 142 143 /* Time in jiffies when the BO was put in vc4->bo_cache. */ 144 unsigned long free_time; 145 146 /* List entry for the BO's position in vc4_dev->bo_cache.size_list */ 147 struct list_head size_head; 148 149 /* Struct for shader validation state, if created by 150 * DRM_IOCTL_VC4_CREATE_SHADER_BO. 151 */ 152 struct vc4_validated_shader_info *validated_shader; 153 }; 154 155 static inline struct vc4_bo * 156 to_vc4_bo(struct drm_gem_object *bo) 157 { 158 return (struct vc4_bo *)bo; 159 } 160 161 struct vc4_seqno_cb { 162 struct work_struct work; 163 uint64_t seqno; 164 void (*func)(struct vc4_seqno_cb *cb); 165 }; 166 167 struct vc4_v3d { 168 struct vc4_dev *vc4; 169 struct platform_device *pdev; 170 void __iomem *regs; 171 }; 172 173 struct vc4_hvs { 174 struct platform_device *pdev; 175 void __iomem *regs; 176 u32 __iomem *dlist; 177 178 /* Memory manager for CRTCs to allocate space in the display 179 * list. Units are dwords. 180 */ 181 struct drm_mm dlist_mm; 182 /* Memory manager for the LBM memory used by HVS scaling. */ 183 struct drm_mm lbm_mm; 184 spinlock_t mm_lock; 185 186 struct drm_mm_node mitchell_netravali_filter; 187 }; 188 189 struct vc4_plane { 190 struct drm_plane base; 191 }; 192 193 static inline struct vc4_plane * 194 to_vc4_plane(struct drm_plane *plane) 195 { 196 return (struct vc4_plane *)plane; 197 } 198 199 enum vc4_encoder_type { 200 VC4_ENCODER_TYPE_NONE, 201 VC4_ENCODER_TYPE_HDMI, 202 VC4_ENCODER_TYPE_VEC, 203 VC4_ENCODER_TYPE_DSI0, 204 VC4_ENCODER_TYPE_DSI1, 205 VC4_ENCODER_TYPE_SMI, 206 VC4_ENCODER_TYPE_DPI, 207 }; 208 209 struct vc4_encoder { 210 struct drm_encoder base; 211 enum vc4_encoder_type type; 212 u32 clock_select; 213 }; 214 215 static inline struct vc4_encoder * 216 to_vc4_encoder(struct drm_encoder *encoder) 217 { 218 return container_of(encoder, struct vc4_encoder, base); 219 } 220 221 #define V3D_READ(offset) readl(vc4->v3d->regs + offset) 222 #define V3D_WRITE(offset, val) writel(val, vc4->v3d->regs + offset) 223 #define HVS_READ(offset) readl(vc4->hvs->regs + offset) 224 #define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset) 225 226 struct vc4_exec_info { 227 /* Sequence number for this bin/render job. */ 228 uint64_t seqno; 229 230 /* Latest write_seqno of any BO that binning depends on. */ 231 uint64_t bin_dep_seqno; 232 233 /* Last current addresses the hardware was processing when the 234 * hangcheck timer checked on us. 235 */ 236 uint32_t last_ct0ca, last_ct1ca; 237 238 /* Kernel-space copy of the ioctl arguments */ 239 struct drm_vc4_submit_cl *args; 240 241 /* This is the array of BOs that were looked up at the start of exec. 242 * Command validation will use indices into this array. 243 */ 244 struct drm_gem_cma_object **bo; 245 uint32_t bo_count; 246 247 /* List of BOs that are being written by the RCL. Other than 248 * the binner temporary storage, this is all the BOs written 249 * by the job. 250 */ 251 struct drm_gem_cma_object *rcl_write_bo[4]; 252 uint32_t rcl_write_bo_count; 253 254 /* Pointers for our position in vc4->job_list */ 255 struct list_head head; 256 257 /* List of other BOs used in the job that need to be released 258 * once the job is complete. 259 */ 260 struct list_head unref_list; 261 262 /* Current unvalidated indices into @bo loaded by the non-hardware 263 * VC4_PACKET_GEM_HANDLES. 264 */ 265 uint32_t bo_index[2]; 266 267 /* This is the BO where we store the validated command lists, shader 268 * records, and uniforms. 269 */ 270 struct drm_gem_cma_object *exec_bo; 271 272 /** 273 * This tracks the per-shader-record state (packet 64) that 274 * determines the length of the shader record and the offset 275 * it's expected to be found at. It gets read in from the 276 * command lists. 277 */ 278 struct vc4_shader_state { 279 uint32_t addr; 280 /* Maximum vertex index referenced by any primitive using this 281 * shader state. 282 */ 283 uint32_t max_index; 284 } *shader_state; 285 286 /** How many shader states the user declared they were using. */ 287 uint32_t shader_state_size; 288 /** How many shader state records the validator has seen. */ 289 uint32_t shader_state_count; 290 291 bool found_tile_binning_mode_config_packet; 292 bool found_start_tile_binning_packet; 293 bool found_increment_semaphore_packet; 294 bool found_flush; 295 uint8_t bin_tiles_x, bin_tiles_y; 296 struct drm_gem_cma_object *tile_bo; 297 uint32_t tile_alloc_offset; 298 299 /** 300 * Computed addresses pointing into exec_bo where we start the 301 * bin thread (ct0) and render thread (ct1). 302 */ 303 uint32_t ct0ca, ct0ea; 304 uint32_t ct1ca, ct1ea; 305 306 /* Pointer to the unvalidated bin CL (if present). */ 307 void *bin_u; 308 309 /* Pointers to the shader recs. These paddr gets incremented as CL 310 * packets are relocated in validate_gl_shader_state, and the vaddrs 311 * (u and v) get incremented and size decremented as the shader recs 312 * themselves are validated. 313 */ 314 void *shader_rec_u; 315 void *shader_rec_v; 316 uint32_t shader_rec_p; 317 uint32_t shader_rec_size; 318 319 /* Pointers to the uniform data. These pointers are incremented, and 320 * size decremented, as each batch of uniforms is uploaded. 321 */ 322 void *uniforms_u; 323 void *uniforms_v; 324 uint32_t uniforms_p; 325 uint32_t uniforms_size; 326 }; 327 328 static inline struct vc4_exec_info * 329 vc4_first_bin_job(struct vc4_dev *vc4) 330 { 331 return list_first_entry_or_null(&vc4->bin_job_list, 332 struct vc4_exec_info, head); 333 } 334 335 static inline struct vc4_exec_info * 336 vc4_first_render_job(struct vc4_dev *vc4) 337 { 338 return list_first_entry_or_null(&vc4->render_job_list, 339 struct vc4_exec_info, head); 340 } 341 342 static inline struct vc4_exec_info * 343 vc4_last_render_job(struct vc4_dev *vc4) 344 { 345 if (list_empty(&vc4->render_job_list)) 346 return NULL; 347 return list_last_entry(&vc4->render_job_list, 348 struct vc4_exec_info, head); 349 } 350 351 /** 352 * struct vc4_texture_sample_info - saves the offsets into the UBO for texture 353 * setup parameters. 354 * 355 * This will be used at draw time to relocate the reference to the texture 356 * contents in p0, and validate that the offset combined with 357 * width/height/stride/etc. from p1 and p2/p3 doesn't sample outside the BO. 358 * Note that the hardware treats unprovided config parameters as 0, so not all 359 * of them need to be set up for every texure sample, and we'll store ~0 as 360 * the offset to mark the unused ones. 361 * 362 * See the VC4 3D architecture guide page 41 ("Texture and Memory Lookup Unit 363 * Setup") for definitions of the texture parameters. 364 */ 365 struct vc4_texture_sample_info { 366 bool is_direct; 367 uint32_t p_offset[4]; 368 }; 369 370 /** 371 * struct vc4_validated_shader_info - information about validated shaders that 372 * needs to be used from command list validation. 373 * 374 * For a given shader, each time a shader state record references it, we need 375 * to verify that the shader doesn't read more uniforms than the shader state 376 * record's uniform BO pointer can provide, and we need to apply relocations 377 * and validate the shader state record's uniforms that define the texture 378 * samples. 379 */ 380 struct vc4_validated_shader_info { 381 uint32_t uniforms_size; 382 uint32_t uniforms_src_size; 383 uint32_t num_texture_samples; 384 struct vc4_texture_sample_info *texture_samples; 385 386 uint32_t num_uniform_addr_offsets; 387 uint32_t *uniform_addr_offsets; 388 389 bool is_threaded; 390 }; 391 392 /** 393 * _wait_for - magic (register) wait macro 394 * 395 * Does the right thing for modeset paths when run under kdgb or similar atomic 396 * contexts. Note that it's important that we check the condition again after 397 * having timed out, since the timeout could be due to preemption or similar and 398 * we've never had a chance to check the condition before the timeout. 399 */ 400 #define _wait_for(COND, MS, W) ({ \ 401 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \ 402 int ret__ = 0; \ 403 while (!(COND)) { \ 404 if (time_after(jiffies, timeout__)) { \ 405 if (!(COND)) \ 406 ret__ = -ETIMEDOUT; \ 407 break; \ 408 } \ 409 if (W && drm_can_sleep()) { \ 410 msleep(W); \ 411 } else { \ 412 cpu_relax(); \ 413 } \ 414 } \ 415 ret__; \ 416 }) 417 418 #define wait_for(COND, MS) _wait_for(COND, MS, 1) 419 420 /* vc4_bo.c */ 421 struct drm_gem_object *vc4_create_object(struct drm_device *dev, size_t size); 422 void vc4_free_object(struct drm_gem_object *gem_obj); 423 struct vc4_bo *vc4_bo_create(struct drm_device *dev, size_t size, 424 bool from_cache); 425 int vc4_dumb_create(struct drm_file *file_priv, 426 struct drm_device *dev, 427 struct drm_mode_create_dumb *args); 428 struct dma_buf *vc4_prime_export(struct drm_device *dev, 429 struct drm_gem_object *obj, int flags); 430 int vc4_create_bo_ioctl(struct drm_device *dev, void *data, 431 struct drm_file *file_priv); 432 int vc4_create_shader_bo_ioctl(struct drm_device *dev, void *data, 433 struct drm_file *file_priv); 434 int vc4_mmap_bo_ioctl(struct drm_device *dev, void *data, 435 struct drm_file *file_priv); 436 int vc4_get_hang_state_ioctl(struct drm_device *dev, void *data, 437 struct drm_file *file_priv); 438 int vc4_mmap(struct file *filp, struct vm_area_struct *vma); 439 int vc4_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma); 440 void *vc4_prime_vmap(struct drm_gem_object *obj); 441 void vc4_bo_cache_init(struct drm_device *dev); 442 void vc4_bo_cache_destroy(struct drm_device *dev); 443 int vc4_bo_stats_debugfs(struct seq_file *m, void *arg); 444 445 /* vc4_crtc.c */ 446 extern struct platform_driver vc4_crtc_driver; 447 int vc4_enable_vblank(struct drm_device *dev, unsigned int crtc_id); 448 void vc4_disable_vblank(struct drm_device *dev, unsigned int crtc_id); 449 bool vc4_event_pending(struct drm_crtc *crtc); 450 int vc4_crtc_debugfs_regs(struct seq_file *m, void *arg); 451 int vc4_crtc_get_scanoutpos(struct drm_device *dev, unsigned int crtc_id, 452 unsigned int flags, int *vpos, int *hpos, 453 ktime_t *stime, ktime_t *etime, 454 const struct drm_display_mode *mode); 455 int vc4_crtc_get_vblank_timestamp(struct drm_device *dev, unsigned int crtc_id, 456 int *max_error, struct timeval *vblank_time, 457 unsigned flags); 458 459 /* vc4_debugfs.c */ 460 int vc4_debugfs_init(struct drm_minor *minor); 461 462 /* vc4_drv.c */ 463 void __iomem *vc4_ioremap_regs(struct platform_device *dev, int index); 464 465 /* vc4_dpi.c */ 466 extern struct platform_driver vc4_dpi_driver; 467 int vc4_dpi_debugfs_regs(struct seq_file *m, void *unused); 468 469 /* vc4_dsi.c */ 470 extern struct platform_driver vc4_dsi_driver; 471 int vc4_dsi_debugfs_regs(struct seq_file *m, void *unused); 472 473 /* vc4_gem.c */ 474 void vc4_gem_init(struct drm_device *dev); 475 void vc4_gem_destroy(struct drm_device *dev); 476 int vc4_submit_cl_ioctl(struct drm_device *dev, void *data, 477 struct drm_file *file_priv); 478 int vc4_wait_seqno_ioctl(struct drm_device *dev, void *data, 479 struct drm_file *file_priv); 480 int vc4_wait_bo_ioctl(struct drm_device *dev, void *data, 481 struct drm_file *file_priv); 482 void vc4_submit_next_bin_job(struct drm_device *dev); 483 void vc4_submit_next_render_job(struct drm_device *dev); 484 void vc4_move_job_to_render(struct drm_device *dev, struct vc4_exec_info *exec); 485 int vc4_wait_for_seqno(struct drm_device *dev, uint64_t seqno, 486 uint64_t timeout_ns, bool interruptible); 487 void vc4_job_handle_completed(struct vc4_dev *vc4); 488 int vc4_queue_seqno_cb(struct drm_device *dev, 489 struct vc4_seqno_cb *cb, uint64_t seqno, 490 void (*func)(struct vc4_seqno_cb *cb)); 491 492 /* vc4_hdmi.c */ 493 extern struct platform_driver vc4_hdmi_driver; 494 int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused); 495 496 /* vc4_hdmi.c */ 497 extern struct platform_driver vc4_vec_driver; 498 int vc4_vec_debugfs_regs(struct seq_file *m, void *unused); 499 500 /* vc4_irq.c */ 501 irqreturn_t vc4_irq(int irq, void *arg); 502 void vc4_irq_preinstall(struct drm_device *dev); 503 int vc4_irq_postinstall(struct drm_device *dev); 504 void vc4_irq_uninstall(struct drm_device *dev); 505 void vc4_irq_reset(struct drm_device *dev); 506 507 /* vc4_hvs.c */ 508 extern struct platform_driver vc4_hvs_driver; 509 void vc4_hvs_dump_state(struct drm_device *dev); 510 int vc4_hvs_debugfs_regs(struct seq_file *m, void *unused); 511 512 /* vc4_kms.c */ 513 int vc4_kms_load(struct drm_device *dev); 514 515 /* vc4_plane.c */ 516 struct drm_plane *vc4_plane_init(struct drm_device *dev, 517 enum drm_plane_type type); 518 u32 vc4_plane_write_dlist(struct drm_plane *plane, u32 __iomem *dlist); 519 u32 vc4_plane_dlist_size(const struct drm_plane_state *state); 520 void vc4_plane_async_set_fb(struct drm_plane *plane, 521 struct drm_framebuffer *fb); 522 523 /* vc4_v3d.c */ 524 extern struct platform_driver vc4_v3d_driver; 525 int vc4_v3d_debugfs_ident(struct seq_file *m, void *unused); 526 int vc4_v3d_debugfs_regs(struct seq_file *m, void *unused); 527 528 /* vc4_validate.c */ 529 int 530 vc4_validate_bin_cl(struct drm_device *dev, 531 void *validated, 532 void *unvalidated, 533 struct vc4_exec_info *exec); 534 535 int 536 vc4_validate_shader_recs(struct drm_device *dev, struct vc4_exec_info *exec); 537 538 struct drm_gem_cma_object *vc4_use_bo(struct vc4_exec_info *exec, 539 uint32_t hindex); 540 541 int vc4_get_rcl(struct drm_device *dev, struct vc4_exec_info *exec); 542 543 bool vc4_check_tex_size(struct vc4_exec_info *exec, 544 struct drm_gem_cma_object *fbo, 545 uint32_t offset, uint8_t tiling_format, 546 uint32_t width, uint32_t height, uint8_t cpp); 547 548 /* vc4_validate_shader.c */ 549 struct vc4_validated_shader_info * 550 vc4_validate_shader(struct drm_gem_cma_object *shader_obj); 551