1 /* 2 * Copyright (C) 2015 Broadcom 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 #include "drmP.h" 10 #include "drm_gem_cma_helper.h" 11 12 struct vc4_dev { 13 struct drm_device *dev; 14 15 struct vc4_hdmi *hdmi; 16 struct vc4_hvs *hvs; 17 struct vc4_crtc *crtc[3]; 18 struct vc4_v3d *v3d; 19 20 struct drm_fbdev_cma *fbdev; 21 22 struct vc4_hang_state *hang_state; 23 24 /* The kernel-space BO cache. Tracks buffers that have been 25 * unreferenced by all other users (refcounts of 0!) but not 26 * yet freed, so we can do cheap allocations. 27 */ 28 struct vc4_bo_cache { 29 /* Array of list heads for entries in the BO cache, 30 * based on number of pages, so we can do O(1) lookups 31 * in the cache when allocating. 32 */ 33 struct list_head *size_list; 34 uint32_t size_list_size; 35 36 /* List of all BOs in the cache, ordered by age, so we 37 * can do O(1) lookups when trying to free old 38 * buffers. 39 */ 40 struct list_head time_list; 41 struct work_struct time_work; 42 struct timer_list time_timer; 43 } bo_cache; 44 45 struct vc4_bo_stats { 46 u32 num_allocated; 47 u32 size_allocated; 48 u32 num_cached; 49 u32 size_cached; 50 } bo_stats; 51 52 /* Protects bo_cache and the BO stats. */ 53 struct mutex bo_lock; 54 55 /* Sequence number for the last job queued in job_list. 56 * Starts at 0 (no jobs emitted). 57 */ 58 uint64_t emit_seqno; 59 60 /* Sequence number for the last completed job on the GPU. 61 * Starts at 0 (no jobs completed). 62 */ 63 uint64_t finished_seqno; 64 65 /* List of all struct vc4_exec_info for jobs to be executed. 66 * The first job in the list is the one currently programmed 67 * into ct0ca/ct1ca for execution. 68 */ 69 struct list_head job_list; 70 /* List of the finished vc4_exec_infos waiting to be freed by 71 * job_done_work. 72 */ 73 struct list_head job_done_list; 74 /* Spinlock used to synchronize the job_list and seqno 75 * accesses between the IRQ handler and GEM ioctls. 76 */ 77 spinlock_t job_lock; 78 wait_queue_head_t job_wait_queue; 79 struct work_struct job_done_work; 80 81 /* List of struct vc4_seqno_cb for callbacks to be made from a 82 * workqueue when the given seqno is passed. 83 */ 84 struct list_head seqno_cb_list; 85 86 /* The binner overflow memory that's currently set up in 87 * BPOA/BPOS registers. When overflow occurs and a new one is 88 * allocated, the previous one will be moved to 89 * vc4->current_exec's free list. 90 */ 91 struct vc4_bo *overflow_mem; 92 struct work_struct overflow_mem_work; 93 94 int power_refcount; 95 96 /* Mutex controlling the power refcount. */ 97 struct mutex power_lock; 98 99 struct { 100 struct timer_list timer; 101 struct work_struct reset_work; 102 } hangcheck; 103 104 struct semaphore async_modeset; 105 }; 106 107 static inline struct vc4_dev * 108 to_vc4_dev(struct drm_device *dev) 109 { 110 return (struct vc4_dev *)dev->dev_private; 111 } 112 113 struct vc4_bo { 114 struct drm_gem_cma_object base; 115 116 /* seqno of the last job to render to this BO. */ 117 uint64_t seqno; 118 119 /* List entry for the BO's position in either 120 * vc4_exec_info->unref_list or vc4_dev->bo_cache.time_list 121 */ 122 struct list_head unref_head; 123 124 /* Time in jiffies when the BO was put in vc4->bo_cache. */ 125 unsigned long free_time; 126 127 /* List entry for the BO's position in vc4_dev->bo_cache.size_list */ 128 struct list_head size_head; 129 130 /* Struct for shader validation state, if created by 131 * DRM_IOCTL_VC4_CREATE_SHADER_BO. 132 */ 133 struct vc4_validated_shader_info *validated_shader; 134 }; 135 136 static inline struct vc4_bo * 137 to_vc4_bo(struct drm_gem_object *bo) 138 { 139 return (struct vc4_bo *)bo; 140 } 141 142 struct vc4_seqno_cb { 143 struct work_struct work; 144 uint64_t seqno; 145 void (*func)(struct vc4_seqno_cb *cb); 146 }; 147 148 struct vc4_v3d { 149 struct vc4_dev *vc4; 150 struct platform_device *pdev; 151 void __iomem *regs; 152 }; 153 154 struct vc4_hvs { 155 struct platform_device *pdev; 156 void __iomem *regs; 157 void __iomem *dlist; 158 }; 159 160 struct vc4_plane { 161 struct drm_plane base; 162 }; 163 164 static inline struct vc4_plane * 165 to_vc4_plane(struct drm_plane *plane) 166 { 167 return (struct vc4_plane *)plane; 168 } 169 170 enum vc4_encoder_type { 171 VC4_ENCODER_TYPE_HDMI, 172 VC4_ENCODER_TYPE_VEC, 173 VC4_ENCODER_TYPE_DSI0, 174 VC4_ENCODER_TYPE_DSI1, 175 VC4_ENCODER_TYPE_SMI, 176 VC4_ENCODER_TYPE_DPI, 177 }; 178 179 struct vc4_encoder { 180 struct drm_encoder base; 181 enum vc4_encoder_type type; 182 u32 clock_select; 183 }; 184 185 static inline struct vc4_encoder * 186 to_vc4_encoder(struct drm_encoder *encoder) 187 { 188 return container_of(encoder, struct vc4_encoder, base); 189 } 190 191 #define V3D_READ(offset) readl(vc4->v3d->regs + offset) 192 #define V3D_WRITE(offset, val) writel(val, vc4->v3d->regs + offset) 193 #define HVS_READ(offset) readl(vc4->hvs->regs + offset) 194 #define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset) 195 196 struct vc4_exec_info { 197 /* Sequence number for this bin/render job. */ 198 uint64_t seqno; 199 200 /* Last current addresses the hardware was processing when the 201 * hangcheck timer checked on us. 202 */ 203 uint32_t last_ct0ca, last_ct1ca; 204 205 /* Kernel-space copy of the ioctl arguments */ 206 struct drm_vc4_submit_cl *args; 207 208 /* This is the array of BOs that were looked up at the start of exec. 209 * Command validation will use indices into this array. 210 */ 211 struct drm_gem_cma_object **bo; 212 uint32_t bo_count; 213 214 /* Pointers for our position in vc4->job_list */ 215 struct list_head head; 216 217 /* List of other BOs used in the job that need to be released 218 * once the job is complete. 219 */ 220 struct list_head unref_list; 221 222 /* Current unvalidated indices into @bo loaded by the non-hardware 223 * VC4_PACKET_GEM_HANDLES. 224 */ 225 uint32_t bo_index[2]; 226 227 /* This is the BO where we store the validated command lists, shader 228 * records, and uniforms. 229 */ 230 struct drm_gem_cma_object *exec_bo; 231 232 /** 233 * This tracks the per-shader-record state (packet 64) that 234 * determines the length of the shader record and the offset 235 * it's expected to be found at. It gets read in from the 236 * command lists. 237 */ 238 struct vc4_shader_state { 239 uint32_t addr; 240 /* Maximum vertex index referenced by any primitive using this 241 * shader state. 242 */ 243 uint32_t max_index; 244 } *shader_state; 245 246 /** How many shader states the user declared they were using. */ 247 uint32_t shader_state_size; 248 /** How many shader state records the validator has seen. */ 249 uint32_t shader_state_count; 250 251 bool found_tile_binning_mode_config_packet; 252 bool found_start_tile_binning_packet; 253 bool found_increment_semaphore_packet; 254 bool found_flush; 255 uint8_t bin_tiles_x, bin_tiles_y; 256 struct drm_gem_cma_object *tile_bo; 257 uint32_t tile_alloc_offset; 258 259 /** 260 * Computed addresses pointing into exec_bo where we start the 261 * bin thread (ct0) and render thread (ct1). 262 */ 263 uint32_t ct0ca, ct0ea; 264 uint32_t ct1ca, ct1ea; 265 266 /* Pointer to the unvalidated bin CL (if present). */ 267 void *bin_u; 268 269 /* Pointers to the shader recs. These paddr gets incremented as CL 270 * packets are relocated in validate_gl_shader_state, and the vaddrs 271 * (u and v) get incremented and size decremented as the shader recs 272 * themselves are validated. 273 */ 274 void *shader_rec_u; 275 void *shader_rec_v; 276 uint32_t shader_rec_p; 277 uint32_t shader_rec_size; 278 279 /* Pointers to the uniform data. These pointers are incremented, and 280 * size decremented, as each batch of uniforms is uploaded. 281 */ 282 void *uniforms_u; 283 void *uniforms_v; 284 uint32_t uniforms_p; 285 uint32_t uniforms_size; 286 }; 287 288 static inline struct vc4_exec_info * 289 vc4_first_job(struct vc4_dev *vc4) 290 { 291 if (list_empty(&vc4->job_list)) 292 return NULL; 293 return list_first_entry(&vc4->job_list, struct vc4_exec_info, head); 294 } 295 296 /** 297 * struct vc4_texture_sample_info - saves the offsets into the UBO for texture 298 * setup parameters. 299 * 300 * This will be used at draw time to relocate the reference to the texture 301 * contents in p0, and validate that the offset combined with 302 * width/height/stride/etc. from p1 and p2/p3 doesn't sample outside the BO. 303 * Note that the hardware treats unprovided config parameters as 0, so not all 304 * of them need to be set up for every texure sample, and we'll store ~0 as 305 * the offset to mark the unused ones. 306 * 307 * See the VC4 3D architecture guide page 41 ("Texture and Memory Lookup Unit 308 * Setup") for definitions of the texture parameters. 309 */ 310 struct vc4_texture_sample_info { 311 bool is_direct; 312 uint32_t p_offset[4]; 313 }; 314 315 /** 316 * struct vc4_validated_shader_info - information about validated shaders that 317 * needs to be used from command list validation. 318 * 319 * For a given shader, each time a shader state record references it, we need 320 * to verify that the shader doesn't read more uniforms than the shader state 321 * record's uniform BO pointer can provide, and we need to apply relocations 322 * and validate the shader state record's uniforms that define the texture 323 * samples. 324 */ 325 struct vc4_validated_shader_info { 326 uint32_t uniforms_size; 327 uint32_t uniforms_src_size; 328 uint32_t num_texture_samples; 329 struct vc4_texture_sample_info *texture_samples; 330 }; 331 332 /** 333 * _wait_for - magic (register) wait macro 334 * 335 * Does the right thing for modeset paths when run under kdgb or similar atomic 336 * contexts. Note that it's important that we check the condition again after 337 * having timed out, since the timeout could be due to preemption or similar and 338 * we've never had a chance to check the condition before the timeout. 339 */ 340 #define _wait_for(COND, MS, W) ({ \ 341 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \ 342 int ret__ = 0; \ 343 while (!(COND)) { \ 344 if (time_after(jiffies, timeout__)) { \ 345 if (!(COND)) \ 346 ret__ = -ETIMEDOUT; \ 347 break; \ 348 } \ 349 if (W && drm_can_sleep()) { \ 350 msleep(W); \ 351 } else { \ 352 cpu_relax(); \ 353 } \ 354 } \ 355 ret__; \ 356 }) 357 358 #define wait_for(COND, MS) _wait_for(COND, MS, 1) 359 360 /* vc4_bo.c */ 361 struct drm_gem_object *vc4_create_object(struct drm_device *dev, size_t size); 362 void vc4_free_object(struct drm_gem_object *gem_obj); 363 struct vc4_bo *vc4_bo_create(struct drm_device *dev, size_t size, 364 bool from_cache); 365 int vc4_dumb_create(struct drm_file *file_priv, 366 struct drm_device *dev, 367 struct drm_mode_create_dumb *args); 368 struct dma_buf *vc4_prime_export(struct drm_device *dev, 369 struct drm_gem_object *obj, int flags); 370 int vc4_create_bo_ioctl(struct drm_device *dev, void *data, 371 struct drm_file *file_priv); 372 int vc4_create_shader_bo_ioctl(struct drm_device *dev, void *data, 373 struct drm_file *file_priv); 374 int vc4_mmap_bo_ioctl(struct drm_device *dev, void *data, 375 struct drm_file *file_priv); 376 int vc4_get_hang_state_ioctl(struct drm_device *dev, void *data, 377 struct drm_file *file_priv); 378 int vc4_mmap(struct file *filp, struct vm_area_struct *vma); 379 int vc4_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma); 380 void *vc4_prime_vmap(struct drm_gem_object *obj); 381 void vc4_bo_cache_init(struct drm_device *dev); 382 void vc4_bo_cache_destroy(struct drm_device *dev); 383 int vc4_bo_stats_debugfs(struct seq_file *m, void *arg); 384 385 /* vc4_crtc.c */ 386 extern struct platform_driver vc4_crtc_driver; 387 int vc4_enable_vblank(struct drm_device *dev, unsigned int crtc_id); 388 void vc4_disable_vblank(struct drm_device *dev, unsigned int crtc_id); 389 void vc4_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file); 390 int vc4_crtc_debugfs_regs(struct seq_file *m, void *arg); 391 392 /* vc4_debugfs.c */ 393 int vc4_debugfs_init(struct drm_minor *minor); 394 void vc4_debugfs_cleanup(struct drm_minor *minor); 395 396 /* vc4_drv.c */ 397 void __iomem *vc4_ioremap_regs(struct platform_device *dev, int index); 398 399 /* vc4_gem.c */ 400 void vc4_gem_init(struct drm_device *dev); 401 void vc4_gem_destroy(struct drm_device *dev); 402 int vc4_submit_cl_ioctl(struct drm_device *dev, void *data, 403 struct drm_file *file_priv); 404 int vc4_wait_seqno_ioctl(struct drm_device *dev, void *data, 405 struct drm_file *file_priv); 406 int vc4_wait_bo_ioctl(struct drm_device *dev, void *data, 407 struct drm_file *file_priv); 408 void vc4_submit_next_job(struct drm_device *dev); 409 int vc4_wait_for_seqno(struct drm_device *dev, uint64_t seqno, 410 uint64_t timeout_ns, bool interruptible); 411 void vc4_job_handle_completed(struct vc4_dev *vc4); 412 int vc4_queue_seqno_cb(struct drm_device *dev, 413 struct vc4_seqno_cb *cb, uint64_t seqno, 414 void (*func)(struct vc4_seqno_cb *cb)); 415 416 /* vc4_hdmi.c */ 417 extern struct platform_driver vc4_hdmi_driver; 418 int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused); 419 420 /* vc4_irq.c */ 421 irqreturn_t vc4_irq(int irq, void *arg); 422 void vc4_irq_preinstall(struct drm_device *dev); 423 int vc4_irq_postinstall(struct drm_device *dev); 424 void vc4_irq_uninstall(struct drm_device *dev); 425 void vc4_irq_reset(struct drm_device *dev); 426 427 /* vc4_hvs.c */ 428 extern struct platform_driver vc4_hvs_driver; 429 void vc4_hvs_dump_state(struct drm_device *dev); 430 int vc4_hvs_debugfs_regs(struct seq_file *m, void *unused); 431 432 /* vc4_kms.c */ 433 int vc4_kms_load(struct drm_device *dev); 434 435 /* vc4_plane.c */ 436 struct drm_plane *vc4_plane_init(struct drm_device *dev, 437 enum drm_plane_type type); 438 u32 vc4_plane_write_dlist(struct drm_plane *plane, u32 __iomem *dlist); 439 u32 vc4_plane_dlist_size(struct drm_plane_state *state); 440 void vc4_plane_async_set_fb(struct drm_plane *plane, 441 struct drm_framebuffer *fb); 442 443 /* vc4_v3d.c */ 444 extern struct platform_driver vc4_v3d_driver; 445 int vc4_v3d_debugfs_ident(struct seq_file *m, void *unused); 446 int vc4_v3d_debugfs_regs(struct seq_file *m, void *unused); 447 448 /* vc4_validate.c */ 449 int 450 vc4_validate_bin_cl(struct drm_device *dev, 451 void *validated, 452 void *unvalidated, 453 struct vc4_exec_info *exec); 454 455 int 456 vc4_validate_shader_recs(struct drm_device *dev, struct vc4_exec_info *exec); 457 458 struct drm_gem_cma_object *vc4_use_bo(struct vc4_exec_info *exec, 459 uint32_t hindex); 460 461 int vc4_get_rcl(struct drm_device *dev, struct vc4_exec_info *exec); 462 463 bool vc4_check_tex_size(struct vc4_exec_info *exec, 464 struct drm_gem_cma_object *fbo, 465 uint32_t offset, uint8_t tiling_format, 466 uint32_t width, uint32_t height, uint8_t cpp); 467 468 /* vc4_validate_shader.c */ 469 struct vc4_validated_shader_info * 470 vc4_validate_shader(struct drm_gem_cma_object *shader_obj); 471