1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2015 Broadcom 4 */ 5 #ifndef _VC4_DRV_H_ 6 #define _VC4_DRV_H_ 7 8 #include <linux/delay.h> 9 #include <linux/refcount.h> 10 #include <linux/uaccess.h> 11 12 #include <drm/drm_atomic.h> 13 #include <drm/drm_debugfs.h> 14 #include <drm/drm_device.h> 15 #include <drm/drm_encoder.h> 16 #include <drm/drm_gem_cma_helper.h> 17 #include <drm/drm_managed.h> 18 #include <drm/drm_mm.h> 19 #include <drm/drm_modeset_lock.h> 20 21 #include "uapi/drm/vc4_drm.h" 22 23 struct drm_device; 24 struct drm_gem_object; 25 26 /* Don't forget to update vc4_bo.c: bo_type_names[] when adding to 27 * this. 28 */ 29 enum vc4_kernel_bo_type { 30 /* Any kernel allocation (gem_create_object hook) before it 31 * gets another type set. 32 */ 33 VC4_BO_TYPE_KERNEL, 34 VC4_BO_TYPE_V3D, 35 VC4_BO_TYPE_V3D_SHADER, 36 VC4_BO_TYPE_DUMB, 37 VC4_BO_TYPE_BIN, 38 VC4_BO_TYPE_RCL, 39 VC4_BO_TYPE_BCL, 40 VC4_BO_TYPE_KERNEL_CACHE, 41 VC4_BO_TYPE_COUNT 42 }; 43 44 /* Performance monitor object. The perform lifetime is controlled by userspace 45 * using perfmon related ioctls. A perfmon can be attached to a submit_cl 46 * request, and when this is the case, HW perf counters will be activated just 47 * before the submit_cl is submitted to the GPU and disabled when the job is 48 * done. This way, only events related to a specific job will be counted. 49 */ 50 struct vc4_perfmon { 51 /* Tracks the number of users of the perfmon, when this counter reaches 52 * zero the perfmon is destroyed. 53 */ 54 refcount_t refcnt; 55 56 /* Number of counters activated in this perfmon instance 57 * (should be less than DRM_VC4_MAX_PERF_COUNTERS). 58 */ 59 u8 ncounters; 60 61 /* Events counted by the HW perf counters. */ 62 u8 events[DRM_VC4_MAX_PERF_COUNTERS]; 63 64 /* Storage for counter values. Counters are incremented by the HW 65 * perf counter values every time the perfmon is attached to a GPU job. 66 * This way, perfmon users don't have to retrieve the results after 67 * each job if they want to track events covering several submissions. 68 * Note that counter values can't be reset, but you can fake a reset by 69 * destroying the perfmon and creating a new one. 70 */ 71 u64 counters[]; 72 }; 73 74 struct vc4_dev { 75 struct drm_device base; 76 77 struct vc4_hvs *hvs; 78 struct vc4_v3d *v3d; 79 struct vc4_dpi *dpi; 80 struct vc4_dsi *dsi1; 81 struct vc4_vec *vec; 82 struct vc4_txp *txp; 83 84 struct vc4_hang_state *hang_state; 85 86 /* The kernel-space BO cache. Tracks buffers that have been 87 * unreferenced by all other users (refcounts of 0!) but not 88 * yet freed, so we can do cheap allocations. 89 */ 90 struct vc4_bo_cache { 91 /* Array of list heads for entries in the BO cache, 92 * based on number of pages, so we can do O(1) lookups 93 * in the cache when allocating. 94 */ 95 struct list_head *size_list; 96 uint32_t size_list_size; 97 98 /* List of all BOs in the cache, ordered by age, so we 99 * can do O(1) lookups when trying to free old 100 * buffers. 101 */ 102 struct list_head time_list; 103 struct work_struct time_work; 104 struct timer_list time_timer; 105 } bo_cache; 106 107 u32 num_labels; 108 struct vc4_label { 109 const char *name; 110 u32 num_allocated; 111 u32 size_allocated; 112 } *bo_labels; 113 114 /* Protects bo_cache and bo_labels. */ 115 struct mutex bo_lock; 116 117 /* Purgeable BO pool. All BOs in this pool can have their memory 118 * reclaimed if the driver is unable to allocate new BOs. We also 119 * keep stats related to the purge mechanism here. 120 */ 121 struct { 122 struct list_head list; 123 unsigned int num; 124 size_t size; 125 unsigned int purged_num; 126 size_t purged_size; 127 struct mutex lock; 128 } purgeable; 129 130 uint64_t dma_fence_context; 131 132 /* Sequence number for the last job queued in bin_job_list. 133 * Starts at 0 (no jobs emitted). 134 */ 135 uint64_t emit_seqno; 136 137 /* Sequence number for the last completed job on the GPU. 138 * Starts at 0 (no jobs completed). 139 */ 140 uint64_t finished_seqno; 141 142 /* List of all struct vc4_exec_info for jobs to be executed in 143 * the binner. The first job in the list is the one currently 144 * programmed into ct0ca for execution. 145 */ 146 struct list_head bin_job_list; 147 148 /* List of all struct vc4_exec_info for jobs that have 149 * completed binning and are ready for rendering. The first 150 * job in the list is the one currently programmed into ct1ca 151 * for execution. 152 */ 153 struct list_head render_job_list; 154 155 /* List of the finished vc4_exec_infos waiting to be freed by 156 * job_done_work. 157 */ 158 struct list_head job_done_list; 159 /* Spinlock used to synchronize the job_list and seqno 160 * accesses between the IRQ handler and GEM ioctls. 161 */ 162 spinlock_t job_lock; 163 wait_queue_head_t job_wait_queue; 164 struct work_struct job_done_work; 165 166 /* Used to track the active perfmon if any. Access to this field is 167 * protected by job_lock. 168 */ 169 struct vc4_perfmon *active_perfmon; 170 171 /* List of struct vc4_seqno_cb for callbacks to be made from a 172 * workqueue when the given seqno is passed. 173 */ 174 struct list_head seqno_cb_list; 175 176 /* The memory used for storing binner tile alloc, tile state, 177 * and overflow memory allocations. This is freed when V3D 178 * powers down. 179 */ 180 struct vc4_bo *bin_bo; 181 182 /* Size of blocks allocated within bin_bo. */ 183 uint32_t bin_alloc_size; 184 185 /* Bitmask of the bin_alloc_size chunks in bin_bo that are 186 * used. 187 */ 188 uint32_t bin_alloc_used; 189 190 /* Bitmask of the current bin_alloc used for overflow memory. */ 191 uint32_t bin_alloc_overflow; 192 193 /* Incremented when an underrun error happened after an atomic commit. 194 * This is particularly useful to detect when a specific modeset is too 195 * demanding in term of memory or HVS bandwidth which is hard to guess 196 * at atomic check time. 197 */ 198 atomic_t underrun; 199 200 struct work_struct overflow_mem_work; 201 202 int power_refcount; 203 204 /* Set to true when the load tracker is supported. */ 205 bool load_tracker_available; 206 207 /* Set to true when the load tracker is active. */ 208 bool load_tracker_enabled; 209 210 /* Mutex controlling the power refcount. */ 211 struct mutex power_lock; 212 213 struct { 214 struct timer_list timer; 215 struct work_struct reset_work; 216 } hangcheck; 217 218 struct semaphore async_modeset; 219 220 struct drm_modeset_lock ctm_state_lock; 221 struct drm_private_obj ctm_manager; 222 struct drm_private_obj hvs_channels; 223 struct drm_private_obj load_tracker; 224 225 /* List of vc4_debugfs_info_entry for adding to debugfs once 226 * the minor is available (after drm_dev_register()). 227 */ 228 struct list_head debugfs_list; 229 230 /* Mutex for binner bo allocation. */ 231 struct mutex bin_bo_lock; 232 /* Reference count for our binner bo. */ 233 struct kref bin_bo_kref; 234 }; 235 236 static inline struct vc4_dev * 237 to_vc4_dev(struct drm_device *dev) 238 { 239 return container_of(dev, struct vc4_dev, base); 240 } 241 242 struct vc4_bo { 243 struct drm_gem_cma_object base; 244 245 /* seqno of the last job to render using this BO. */ 246 uint64_t seqno; 247 248 /* seqno of the last job to use the RCL to write to this BO. 249 * 250 * Note that this doesn't include binner overflow memory 251 * writes. 252 */ 253 uint64_t write_seqno; 254 255 bool t_format; 256 257 /* List entry for the BO's position in either 258 * vc4_exec_info->unref_list or vc4_dev->bo_cache.time_list 259 */ 260 struct list_head unref_head; 261 262 /* Time in jiffies when the BO was put in vc4->bo_cache. */ 263 unsigned long free_time; 264 265 /* List entry for the BO's position in vc4_dev->bo_cache.size_list */ 266 struct list_head size_head; 267 268 /* Struct for shader validation state, if created by 269 * DRM_IOCTL_VC4_CREATE_SHADER_BO. 270 */ 271 struct vc4_validated_shader_info *validated_shader; 272 273 /* One of enum vc4_kernel_bo_type, or VC4_BO_TYPE_COUNT + i 274 * for user-allocated labels. 275 */ 276 int label; 277 278 /* Count the number of active users. This is needed to determine 279 * whether we can move the BO to the purgeable list or not (when the BO 280 * is used by the GPU or the display engine we can't purge it). 281 */ 282 refcount_t usecnt; 283 284 /* Store purgeable/purged state here */ 285 u32 madv; 286 struct mutex madv_lock; 287 }; 288 289 static inline struct vc4_bo * 290 to_vc4_bo(struct drm_gem_object *bo) 291 { 292 return container_of(to_drm_gem_cma_obj(bo), struct vc4_bo, base); 293 } 294 295 struct vc4_fence { 296 struct dma_fence base; 297 struct drm_device *dev; 298 /* vc4 seqno for signaled() test */ 299 uint64_t seqno; 300 }; 301 302 static inline struct vc4_fence * 303 to_vc4_fence(struct dma_fence *fence) 304 { 305 return container_of(fence, struct vc4_fence, base); 306 } 307 308 struct vc4_seqno_cb { 309 struct work_struct work; 310 uint64_t seqno; 311 void (*func)(struct vc4_seqno_cb *cb); 312 }; 313 314 struct vc4_v3d { 315 struct vc4_dev *vc4; 316 struct platform_device *pdev; 317 void __iomem *regs; 318 struct clk *clk; 319 struct debugfs_regset32 regset; 320 }; 321 322 struct vc4_hvs { 323 struct platform_device *pdev; 324 void __iomem *regs; 325 u32 __iomem *dlist; 326 327 struct clk *core_clk; 328 329 /* Memory manager for CRTCs to allocate space in the display 330 * list. Units are dwords. 331 */ 332 struct drm_mm dlist_mm; 333 /* Memory manager for the LBM memory used by HVS scaling. */ 334 struct drm_mm lbm_mm; 335 spinlock_t mm_lock; 336 337 struct drm_mm_node mitchell_netravali_filter; 338 339 struct debugfs_regset32 regset; 340 341 /* HVS version 5 flag, therefore requires updated dlist structures */ 342 bool hvs5; 343 }; 344 345 struct vc4_plane { 346 struct drm_plane base; 347 }; 348 349 static inline struct vc4_plane * 350 to_vc4_plane(struct drm_plane *plane) 351 { 352 return container_of(plane, struct vc4_plane, base); 353 } 354 355 enum vc4_scaling_mode { 356 VC4_SCALING_NONE, 357 VC4_SCALING_TPZ, 358 VC4_SCALING_PPF, 359 }; 360 361 struct vc4_plane_state { 362 struct drm_plane_state base; 363 /* System memory copy of the display list for this element, computed 364 * at atomic_check time. 365 */ 366 u32 *dlist; 367 u32 dlist_size; /* Number of dwords allocated for the display list */ 368 u32 dlist_count; /* Number of used dwords in the display list. */ 369 370 /* Offset in the dlist to various words, for pageflip or 371 * cursor updates. 372 */ 373 u32 pos0_offset; 374 u32 pos2_offset; 375 u32 ptr0_offset; 376 u32 lbm_offset; 377 378 /* Offset where the plane's dlist was last stored in the 379 * hardware at vc4_crtc_atomic_flush() time. 380 */ 381 u32 __iomem *hw_dlist; 382 383 /* Clipped coordinates of the plane on the display. */ 384 int crtc_x, crtc_y, crtc_w, crtc_h; 385 /* Clipped area being scanned from in the FB. */ 386 u32 src_x, src_y; 387 388 u32 src_w[2], src_h[2]; 389 390 /* Scaling selection for the RGB/Y plane and the Cb/Cr planes. */ 391 enum vc4_scaling_mode x_scaling[2], y_scaling[2]; 392 bool is_unity; 393 bool is_yuv; 394 395 /* Offset to start scanning out from the start of the plane's 396 * BO. 397 */ 398 u32 offsets[3]; 399 400 /* Our allocation in LBM for temporary storage during scaling. */ 401 struct drm_mm_node lbm; 402 403 /* Set when the plane has per-pixel alpha content or does not cover 404 * the entire screen. This is a hint to the CRTC that it might need 405 * to enable background color fill. 406 */ 407 bool needs_bg_fill; 408 409 /* Mark the dlist as initialized. Useful to avoid initializing it twice 410 * when async update is not possible. 411 */ 412 bool dlist_initialized; 413 414 /* Load of this plane on the HVS block. The load is expressed in HVS 415 * cycles/sec. 416 */ 417 u64 hvs_load; 418 419 /* Memory bandwidth needed for this plane. This is expressed in 420 * bytes/sec. 421 */ 422 u64 membus_load; 423 }; 424 425 static inline struct vc4_plane_state * 426 to_vc4_plane_state(struct drm_plane_state *state) 427 { 428 return container_of(state, struct vc4_plane_state, base); 429 } 430 431 enum vc4_encoder_type { 432 VC4_ENCODER_TYPE_NONE, 433 VC4_ENCODER_TYPE_HDMI0, 434 VC4_ENCODER_TYPE_HDMI1, 435 VC4_ENCODER_TYPE_VEC, 436 VC4_ENCODER_TYPE_DSI0, 437 VC4_ENCODER_TYPE_DSI1, 438 VC4_ENCODER_TYPE_SMI, 439 VC4_ENCODER_TYPE_DPI, 440 }; 441 442 struct vc4_encoder { 443 struct drm_encoder base; 444 enum vc4_encoder_type type; 445 u32 clock_select; 446 447 void (*pre_crtc_configure)(struct drm_encoder *encoder); 448 void (*pre_crtc_enable)(struct drm_encoder *encoder); 449 void (*post_crtc_enable)(struct drm_encoder *encoder); 450 451 void (*post_crtc_disable)(struct drm_encoder *encoder); 452 void (*post_crtc_powerdown)(struct drm_encoder *encoder); 453 }; 454 455 static inline struct vc4_encoder * 456 to_vc4_encoder(struct drm_encoder *encoder) 457 { 458 return container_of(encoder, struct vc4_encoder, base); 459 } 460 461 struct vc4_crtc_data { 462 /* Bitmask of channels (FIFOs) of the HVS that the output can source from */ 463 unsigned int hvs_available_channels; 464 465 /* Which output of the HVS this pixelvalve sources from. */ 466 int hvs_output; 467 }; 468 469 struct vc4_pv_data { 470 struct vc4_crtc_data base; 471 472 /* Depth of the PixelValve FIFO in bytes */ 473 unsigned int fifo_depth; 474 475 /* Number of pixels output per clock period */ 476 u8 pixels_per_clock; 477 478 enum vc4_encoder_type encoder_types[4]; 479 const char *debugfs_name; 480 481 }; 482 483 struct vc4_crtc { 484 struct drm_crtc base; 485 struct platform_device *pdev; 486 const struct vc4_crtc_data *data; 487 void __iomem *regs; 488 489 /* Timestamp at start of vblank irq - unaffected by lock delays. */ 490 ktime_t t_vblank; 491 492 u8 lut_r[256]; 493 u8 lut_g[256]; 494 u8 lut_b[256]; 495 496 struct drm_pending_vblank_event *event; 497 498 struct debugfs_regset32 regset; 499 }; 500 501 static inline struct vc4_crtc * 502 to_vc4_crtc(struct drm_crtc *crtc) 503 { 504 return container_of(crtc, struct vc4_crtc, base); 505 } 506 507 static inline const struct vc4_crtc_data * 508 vc4_crtc_to_vc4_crtc_data(const struct vc4_crtc *crtc) 509 { 510 return crtc->data; 511 } 512 513 static inline const struct vc4_pv_data * 514 vc4_crtc_to_vc4_pv_data(const struct vc4_crtc *crtc) 515 { 516 const struct vc4_crtc_data *data = vc4_crtc_to_vc4_crtc_data(crtc); 517 518 return container_of(data, struct vc4_pv_data, base); 519 } 520 521 struct vc4_crtc_state { 522 struct drm_crtc_state base; 523 /* Dlist area for this CRTC configuration. */ 524 struct drm_mm_node mm; 525 bool feed_txp; 526 bool txp_armed; 527 unsigned int assigned_channel; 528 529 struct { 530 unsigned int left; 531 unsigned int right; 532 unsigned int top; 533 unsigned int bottom; 534 } margins; 535 536 /* Transitional state below, only valid during atomic commits */ 537 bool update_muxing; 538 }; 539 540 #define VC4_HVS_CHANNEL_DISABLED ((unsigned int)-1) 541 542 static inline struct vc4_crtc_state * 543 to_vc4_crtc_state(struct drm_crtc_state *crtc_state) 544 { 545 return container_of(crtc_state, struct vc4_crtc_state, base); 546 } 547 548 #define V3D_READ(offset) readl(vc4->v3d->regs + offset) 549 #define V3D_WRITE(offset, val) writel(val, vc4->v3d->regs + offset) 550 #define HVS_READ(offset) readl(vc4->hvs->regs + offset) 551 #define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset) 552 553 #define VC4_REG32(reg) { .name = #reg, .offset = reg } 554 555 struct vc4_exec_info { 556 /* Sequence number for this bin/render job. */ 557 uint64_t seqno; 558 559 /* Latest write_seqno of any BO that binning depends on. */ 560 uint64_t bin_dep_seqno; 561 562 struct dma_fence *fence; 563 564 /* Last current addresses the hardware was processing when the 565 * hangcheck timer checked on us. 566 */ 567 uint32_t last_ct0ca, last_ct1ca; 568 569 /* Kernel-space copy of the ioctl arguments */ 570 struct drm_vc4_submit_cl *args; 571 572 /* This is the array of BOs that were looked up at the start of exec. 573 * Command validation will use indices into this array. 574 */ 575 struct drm_gem_cma_object **bo; 576 uint32_t bo_count; 577 578 /* List of BOs that are being written by the RCL. Other than 579 * the binner temporary storage, this is all the BOs written 580 * by the job. 581 */ 582 struct drm_gem_cma_object *rcl_write_bo[4]; 583 uint32_t rcl_write_bo_count; 584 585 /* Pointers for our position in vc4->job_list */ 586 struct list_head head; 587 588 /* List of other BOs used in the job that need to be released 589 * once the job is complete. 590 */ 591 struct list_head unref_list; 592 593 /* Current unvalidated indices into @bo loaded by the non-hardware 594 * VC4_PACKET_GEM_HANDLES. 595 */ 596 uint32_t bo_index[2]; 597 598 /* This is the BO where we store the validated command lists, shader 599 * records, and uniforms. 600 */ 601 struct drm_gem_cma_object *exec_bo; 602 603 /** 604 * This tracks the per-shader-record state (packet 64) that 605 * determines the length of the shader record and the offset 606 * it's expected to be found at. It gets read in from the 607 * command lists. 608 */ 609 struct vc4_shader_state { 610 uint32_t addr; 611 /* Maximum vertex index referenced by any primitive using this 612 * shader state. 613 */ 614 uint32_t max_index; 615 } *shader_state; 616 617 /** How many shader states the user declared they were using. */ 618 uint32_t shader_state_size; 619 /** How many shader state records the validator has seen. */ 620 uint32_t shader_state_count; 621 622 bool found_tile_binning_mode_config_packet; 623 bool found_start_tile_binning_packet; 624 bool found_increment_semaphore_packet; 625 bool found_flush; 626 uint8_t bin_tiles_x, bin_tiles_y; 627 /* Physical address of the start of the tile alloc array 628 * (where each tile's binned CL will start) 629 */ 630 uint32_t tile_alloc_offset; 631 /* Bitmask of which binner slots are freed when this job completes. */ 632 uint32_t bin_slots; 633 634 /** 635 * Computed addresses pointing into exec_bo where we start the 636 * bin thread (ct0) and render thread (ct1). 637 */ 638 uint32_t ct0ca, ct0ea; 639 uint32_t ct1ca, ct1ea; 640 641 /* Pointer to the unvalidated bin CL (if present). */ 642 void *bin_u; 643 644 /* Pointers to the shader recs. These paddr gets incremented as CL 645 * packets are relocated in validate_gl_shader_state, and the vaddrs 646 * (u and v) get incremented and size decremented as the shader recs 647 * themselves are validated. 648 */ 649 void *shader_rec_u; 650 void *shader_rec_v; 651 uint32_t shader_rec_p; 652 uint32_t shader_rec_size; 653 654 /* Pointers to the uniform data. These pointers are incremented, and 655 * size decremented, as each batch of uniforms is uploaded. 656 */ 657 void *uniforms_u; 658 void *uniforms_v; 659 uint32_t uniforms_p; 660 uint32_t uniforms_size; 661 662 /* Pointer to a performance monitor object if the user requested it, 663 * NULL otherwise. 664 */ 665 struct vc4_perfmon *perfmon; 666 667 /* Whether the exec has taken a reference to the binner BO, which should 668 * happen with a VC4_PACKET_TILE_BINNING_MODE_CONFIG packet. 669 */ 670 bool bin_bo_used; 671 }; 672 673 /* Per-open file private data. Any driver-specific resource that has to be 674 * released when the DRM file is closed should be placed here. 675 */ 676 struct vc4_file { 677 struct { 678 struct idr idr; 679 struct mutex lock; 680 } perfmon; 681 682 bool bin_bo_used; 683 }; 684 685 static inline struct vc4_exec_info * 686 vc4_first_bin_job(struct vc4_dev *vc4) 687 { 688 return list_first_entry_or_null(&vc4->bin_job_list, 689 struct vc4_exec_info, head); 690 } 691 692 static inline struct vc4_exec_info * 693 vc4_first_render_job(struct vc4_dev *vc4) 694 { 695 return list_first_entry_or_null(&vc4->render_job_list, 696 struct vc4_exec_info, head); 697 } 698 699 static inline struct vc4_exec_info * 700 vc4_last_render_job(struct vc4_dev *vc4) 701 { 702 if (list_empty(&vc4->render_job_list)) 703 return NULL; 704 return list_last_entry(&vc4->render_job_list, 705 struct vc4_exec_info, head); 706 } 707 708 /** 709 * struct vc4_texture_sample_info - saves the offsets into the UBO for texture 710 * setup parameters. 711 * 712 * This will be used at draw time to relocate the reference to the texture 713 * contents in p0, and validate that the offset combined with 714 * width/height/stride/etc. from p1 and p2/p3 doesn't sample outside the BO. 715 * Note that the hardware treats unprovided config parameters as 0, so not all 716 * of them need to be set up for every texure sample, and we'll store ~0 as 717 * the offset to mark the unused ones. 718 * 719 * See the VC4 3D architecture guide page 41 ("Texture and Memory Lookup Unit 720 * Setup") for definitions of the texture parameters. 721 */ 722 struct vc4_texture_sample_info { 723 bool is_direct; 724 uint32_t p_offset[4]; 725 }; 726 727 /** 728 * struct vc4_validated_shader_info - information about validated shaders that 729 * needs to be used from command list validation. 730 * 731 * For a given shader, each time a shader state record references it, we need 732 * to verify that the shader doesn't read more uniforms than the shader state 733 * record's uniform BO pointer can provide, and we need to apply relocations 734 * and validate the shader state record's uniforms that define the texture 735 * samples. 736 */ 737 struct vc4_validated_shader_info { 738 uint32_t uniforms_size; 739 uint32_t uniforms_src_size; 740 uint32_t num_texture_samples; 741 struct vc4_texture_sample_info *texture_samples; 742 743 uint32_t num_uniform_addr_offsets; 744 uint32_t *uniform_addr_offsets; 745 746 bool is_threaded; 747 }; 748 749 /** 750 * __wait_for - magic wait macro 751 * 752 * Macro to help avoid open coding check/wait/timeout patterns. Note that it's 753 * important that we check the condition again after having timed out, since the 754 * timeout could be due to preemption or similar and we've never had a chance to 755 * check the condition before the timeout. 756 */ 757 #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \ 758 const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (US)); \ 759 long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \ 760 int ret__; \ 761 might_sleep(); \ 762 for (;;) { \ 763 const bool expired__ = ktime_after(ktime_get_raw(), end__); \ 764 OP; \ 765 /* Guarantee COND check prior to timeout */ \ 766 barrier(); \ 767 if (COND) { \ 768 ret__ = 0; \ 769 break; \ 770 } \ 771 if (expired__) { \ 772 ret__ = -ETIMEDOUT; \ 773 break; \ 774 } \ 775 usleep_range(wait__, wait__ * 2); \ 776 if (wait__ < (Wmax)) \ 777 wait__ <<= 1; \ 778 } \ 779 ret__; \ 780 }) 781 782 #define _wait_for(COND, US, Wmin, Wmax) __wait_for(, (COND), (US), (Wmin), \ 783 (Wmax)) 784 #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 10, 1000) 785 786 /* vc4_bo.c */ 787 struct drm_gem_object *vc4_create_object(struct drm_device *dev, size_t size); 788 void vc4_free_object(struct drm_gem_object *gem_obj); 789 struct vc4_bo *vc4_bo_create(struct drm_device *dev, size_t size, 790 bool from_cache, enum vc4_kernel_bo_type type); 791 int vc4_dumb_create(struct drm_file *file_priv, 792 struct drm_device *dev, 793 struct drm_mode_create_dumb *args); 794 struct dma_buf *vc4_prime_export(struct drm_gem_object *obj, int flags); 795 int vc4_create_bo_ioctl(struct drm_device *dev, void *data, 796 struct drm_file *file_priv); 797 int vc4_create_shader_bo_ioctl(struct drm_device *dev, void *data, 798 struct drm_file *file_priv); 799 int vc4_mmap_bo_ioctl(struct drm_device *dev, void *data, 800 struct drm_file *file_priv); 801 int vc4_set_tiling_ioctl(struct drm_device *dev, void *data, 802 struct drm_file *file_priv); 803 int vc4_get_tiling_ioctl(struct drm_device *dev, void *data, 804 struct drm_file *file_priv); 805 int vc4_get_hang_state_ioctl(struct drm_device *dev, void *data, 806 struct drm_file *file_priv); 807 int vc4_label_bo_ioctl(struct drm_device *dev, void *data, 808 struct drm_file *file_priv); 809 int vc4_mmap(struct file *filp, struct vm_area_struct *vma); 810 int vc4_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma); 811 struct drm_gem_object *vc4_prime_import_sg_table(struct drm_device *dev, 812 struct dma_buf_attachment *attach, 813 struct sg_table *sgt); 814 int vc4_prime_vmap(struct drm_gem_object *obj, struct dma_buf_map *map); 815 int vc4_bo_cache_init(struct drm_device *dev); 816 int vc4_bo_inc_usecnt(struct vc4_bo *bo); 817 void vc4_bo_dec_usecnt(struct vc4_bo *bo); 818 void vc4_bo_add_to_purgeable_pool(struct vc4_bo *bo); 819 void vc4_bo_remove_from_purgeable_pool(struct vc4_bo *bo); 820 821 /* vc4_crtc.c */ 822 extern struct platform_driver vc4_crtc_driver; 823 int vc4_crtc_disable_at_boot(struct drm_crtc *crtc); 824 int vc4_crtc_init(struct drm_device *drm, struct vc4_crtc *vc4_crtc, 825 const struct drm_crtc_funcs *crtc_funcs, 826 const struct drm_crtc_helper_funcs *crtc_helper_funcs); 827 void vc4_crtc_destroy(struct drm_crtc *crtc); 828 int vc4_page_flip(struct drm_crtc *crtc, 829 struct drm_framebuffer *fb, 830 struct drm_pending_vblank_event *event, 831 uint32_t flags, 832 struct drm_modeset_acquire_ctx *ctx); 833 struct drm_crtc_state *vc4_crtc_duplicate_state(struct drm_crtc *crtc); 834 void vc4_crtc_destroy_state(struct drm_crtc *crtc, 835 struct drm_crtc_state *state); 836 void vc4_crtc_reset(struct drm_crtc *crtc); 837 void vc4_crtc_handle_vblank(struct vc4_crtc *crtc); 838 void vc4_crtc_get_margins(struct drm_crtc_state *state, 839 unsigned int *right, unsigned int *left, 840 unsigned int *top, unsigned int *bottom); 841 842 /* vc4_debugfs.c */ 843 void vc4_debugfs_init(struct drm_minor *minor); 844 #ifdef CONFIG_DEBUG_FS 845 void vc4_debugfs_add_file(struct drm_device *drm, 846 const char *filename, 847 int (*show)(struct seq_file*, void*), 848 void *data); 849 void vc4_debugfs_add_regset32(struct drm_device *drm, 850 const char *filename, 851 struct debugfs_regset32 *regset); 852 #else 853 static inline void vc4_debugfs_add_file(struct drm_device *drm, 854 const char *filename, 855 int (*show)(struct seq_file*, void*), 856 void *data) 857 { 858 } 859 860 static inline void vc4_debugfs_add_regset32(struct drm_device *drm, 861 const char *filename, 862 struct debugfs_regset32 *regset) 863 { 864 } 865 #endif 866 867 /* vc4_drv.c */ 868 void __iomem *vc4_ioremap_regs(struct platform_device *dev, int index); 869 870 /* vc4_dpi.c */ 871 extern struct platform_driver vc4_dpi_driver; 872 873 /* vc4_dsi.c */ 874 extern struct platform_driver vc4_dsi_driver; 875 876 /* vc4_fence.c */ 877 extern const struct dma_fence_ops vc4_fence_ops; 878 879 /* vc4_gem.c */ 880 int vc4_gem_init(struct drm_device *dev); 881 int vc4_submit_cl_ioctl(struct drm_device *dev, void *data, 882 struct drm_file *file_priv); 883 int vc4_wait_seqno_ioctl(struct drm_device *dev, void *data, 884 struct drm_file *file_priv); 885 int vc4_wait_bo_ioctl(struct drm_device *dev, void *data, 886 struct drm_file *file_priv); 887 void vc4_submit_next_bin_job(struct drm_device *dev); 888 void vc4_submit_next_render_job(struct drm_device *dev); 889 void vc4_move_job_to_render(struct drm_device *dev, struct vc4_exec_info *exec); 890 int vc4_wait_for_seqno(struct drm_device *dev, uint64_t seqno, 891 uint64_t timeout_ns, bool interruptible); 892 void vc4_job_handle_completed(struct vc4_dev *vc4); 893 int vc4_queue_seqno_cb(struct drm_device *dev, 894 struct vc4_seqno_cb *cb, uint64_t seqno, 895 void (*func)(struct vc4_seqno_cb *cb)); 896 int vc4_gem_madvise_ioctl(struct drm_device *dev, void *data, 897 struct drm_file *file_priv); 898 899 /* vc4_hdmi.c */ 900 extern struct platform_driver vc4_hdmi_driver; 901 902 /* vc4_vec.c */ 903 extern struct platform_driver vc4_vec_driver; 904 905 /* vc4_txp.c */ 906 extern struct platform_driver vc4_txp_driver; 907 908 /* vc4_irq.c */ 909 irqreturn_t vc4_irq(int irq, void *arg); 910 void vc4_irq_preinstall(struct drm_device *dev); 911 int vc4_irq_postinstall(struct drm_device *dev); 912 void vc4_irq_uninstall(struct drm_device *dev); 913 void vc4_irq_reset(struct drm_device *dev); 914 915 /* vc4_hvs.c */ 916 extern struct platform_driver vc4_hvs_driver; 917 void vc4_hvs_stop_channel(struct drm_device *dev, unsigned int output); 918 int vc4_hvs_get_fifo_from_output(struct drm_device *dev, unsigned int output); 919 int vc4_hvs_atomic_check(struct drm_crtc *crtc, struct drm_crtc_state *state); 920 void vc4_hvs_atomic_enable(struct drm_crtc *crtc, struct drm_crtc_state *old_state); 921 void vc4_hvs_atomic_disable(struct drm_crtc *crtc, struct drm_crtc_state *old_state); 922 void vc4_hvs_atomic_flush(struct drm_crtc *crtc, 923 struct drm_atomic_state *state); 924 void vc4_hvs_dump_state(struct drm_device *dev); 925 void vc4_hvs_unmask_underrun(struct drm_device *dev, int channel); 926 void vc4_hvs_mask_underrun(struct drm_device *dev, int channel); 927 928 /* vc4_kms.c */ 929 int vc4_kms_load(struct drm_device *dev); 930 931 /* vc4_plane.c */ 932 struct drm_plane *vc4_plane_init(struct drm_device *dev, 933 enum drm_plane_type type); 934 int vc4_plane_create_additional_planes(struct drm_device *dev); 935 u32 vc4_plane_write_dlist(struct drm_plane *plane, u32 __iomem *dlist); 936 u32 vc4_plane_dlist_size(const struct drm_plane_state *state); 937 void vc4_plane_async_set_fb(struct drm_plane *plane, 938 struct drm_framebuffer *fb); 939 940 /* vc4_v3d.c */ 941 extern struct platform_driver vc4_v3d_driver; 942 extern const struct of_device_id vc4_v3d_dt_match[]; 943 int vc4_v3d_get_bin_slot(struct vc4_dev *vc4); 944 int vc4_v3d_bin_bo_get(struct vc4_dev *vc4, bool *used); 945 void vc4_v3d_bin_bo_put(struct vc4_dev *vc4); 946 int vc4_v3d_pm_get(struct vc4_dev *vc4); 947 void vc4_v3d_pm_put(struct vc4_dev *vc4); 948 949 /* vc4_validate.c */ 950 int 951 vc4_validate_bin_cl(struct drm_device *dev, 952 void *validated, 953 void *unvalidated, 954 struct vc4_exec_info *exec); 955 956 int 957 vc4_validate_shader_recs(struct drm_device *dev, struct vc4_exec_info *exec); 958 959 struct drm_gem_cma_object *vc4_use_bo(struct vc4_exec_info *exec, 960 uint32_t hindex); 961 962 int vc4_get_rcl(struct drm_device *dev, struct vc4_exec_info *exec); 963 964 bool vc4_check_tex_size(struct vc4_exec_info *exec, 965 struct drm_gem_cma_object *fbo, 966 uint32_t offset, uint8_t tiling_format, 967 uint32_t width, uint32_t height, uint8_t cpp); 968 969 /* vc4_validate_shader.c */ 970 struct vc4_validated_shader_info * 971 vc4_validate_shader(struct drm_gem_cma_object *shader_obj); 972 973 /* vc4_perfmon.c */ 974 void vc4_perfmon_get(struct vc4_perfmon *perfmon); 975 void vc4_perfmon_put(struct vc4_perfmon *perfmon); 976 void vc4_perfmon_start(struct vc4_dev *vc4, struct vc4_perfmon *perfmon); 977 void vc4_perfmon_stop(struct vc4_dev *vc4, struct vc4_perfmon *perfmon, 978 bool capture); 979 struct vc4_perfmon *vc4_perfmon_find(struct vc4_file *vc4file, int id); 980 void vc4_perfmon_open_file(struct vc4_file *vc4file); 981 void vc4_perfmon_close_file(struct vc4_file *vc4file); 982 int vc4_perfmon_create_ioctl(struct drm_device *dev, void *data, 983 struct drm_file *file_priv); 984 int vc4_perfmon_destroy_ioctl(struct drm_device *dev, void *data, 985 struct drm_file *file_priv); 986 int vc4_perfmon_get_values_ioctl(struct drm_device *dev, void *data, 987 struct drm_file *file_priv); 988 989 #endif /* _VC4_DRV_H_ */ 990