1d2912cb1SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 2c8b75bcaSEric Anholt /* 3c8b75bcaSEric Anholt * Copyright (C) 2015 Broadcom 4c8b75bcaSEric Anholt */ 56a88752cSMaxime Ripard #ifndef _VC4_DRV_H_ 66a88752cSMaxime Ripard #define _VC4_DRV_H_ 7c8b75bcaSEric Anholt 8fd6d6d80SSam Ravnborg #include <linux/delay.h> 9fd6d6d80SSam Ravnborg #include <linux/refcount.h> 10fd6d6d80SSam Ravnborg #include <linux/uaccess.h> 11fd6d6d80SSam Ravnborg 12fd6d6d80SSam Ravnborg #include <drm/drm_atomic.h> 13fd6d6d80SSam Ravnborg #include <drm/drm_debugfs.h> 14fd6d6d80SSam Ravnborg #include <drm/drm_device.h> 159338203cSLaurent Pinchart #include <drm/drm_encoder.h> 16b7e8e25bSMasahiro Yamada #include <drm/drm_gem_cma_helper.h> 17fd6d6d80SSam Ravnborg #include <drm/drm_mm.h> 18fd6d6d80SSam Ravnborg #include <drm/drm_modeset_lock.h> 199338203cSLaurent Pinchart 2065101d8cSBoris Brezillon #include "uapi/drm/vc4_drm.h" 2165101d8cSBoris Brezillon 22fd6d6d80SSam Ravnborg struct drm_device; 23fd6d6d80SSam Ravnborg struct drm_gem_object; 24fd6d6d80SSam Ravnborg 25f3099462SEric Anholt /* Don't forget to update vc4_bo.c: bo_type_names[] when adding to 26f3099462SEric Anholt * this. 27f3099462SEric Anholt */ 28f3099462SEric Anholt enum vc4_kernel_bo_type { 29f3099462SEric Anholt /* Any kernel allocation (gem_create_object hook) before it 30f3099462SEric Anholt * gets another type set. 31f3099462SEric Anholt */ 32f3099462SEric Anholt VC4_BO_TYPE_KERNEL, 33f3099462SEric Anholt VC4_BO_TYPE_V3D, 34f3099462SEric Anholt VC4_BO_TYPE_V3D_SHADER, 35f3099462SEric Anholt VC4_BO_TYPE_DUMB, 36f3099462SEric Anholt VC4_BO_TYPE_BIN, 37f3099462SEric Anholt VC4_BO_TYPE_RCL, 38f3099462SEric Anholt VC4_BO_TYPE_BCL, 39f3099462SEric Anholt VC4_BO_TYPE_KERNEL_CACHE, 40f3099462SEric Anholt VC4_BO_TYPE_COUNT 41f3099462SEric Anholt }; 42f3099462SEric Anholt 4365101d8cSBoris Brezillon /* Performance monitor object. The perform lifetime is controlled by userspace 4465101d8cSBoris Brezillon * using perfmon related ioctls. A perfmon can be attached to a submit_cl 4565101d8cSBoris Brezillon * request, and when this is the case, HW perf counters will be activated just 4665101d8cSBoris Brezillon * before the submit_cl is submitted to the GPU and disabled when the job is 4765101d8cSBoris Brezillon * done. This way, only events related to a specific job will be counted. 4865101d8cSBoris Brezillon */ 4965101d8cSBoris Brezillon struct vc4_perfmon { 5065101d8cSBoris Brezillon /* Tracks the number of users of the perfmon, when this counter reaches 5165101d8cSBoris Brezillon * zero the perfmon is destroyed. 5265101d8cSBoris Brezillon */ 5365101d8cSBoris Brezillon refcount_t refcnt; 5465101d8cSBoris Brezillon 5565101d8cSBoris Brezillon /* Number of counters activated in this perfmon instance 5665101d8cSBoris Brezillon * (should be less than DRM_VC4_MAX_PERF_COUNTERS). 5765101d8cSBoris Brezillon */ 5865101d8cSBoris Brezillon u8 ncounters; 5965101d8cSBoris Brezillon 6065101d8cSBoris Brezillon /* Events counted by the HW perf counters. */ 6165101d8cSBoris Brezillon u8 events[DRM_VC4_MAX_PERF_COUNTERS]; 6265101d8cSBoris Brezillon 6365101d8cSBoris Brezillon /* Storage for counter values. Counters are incremented by the HW 6465101d8cSBoris Brezillon * perf counter values every time the perfmon is attached to a GPU job. 6565101d8cSBoris Brezillon * This way, perfmon users don't have to retrieve the results after 6665101d8cSBoris Brezillon * each job if they want to track events covering several submissions. 6765101d8cSBoris Brezillon * Note that counter values can't be reset, but you can fake a reset by 6865101d8cSBoris Brezillon * destroying the perfmon and creating a new one. 6965101d8cSBoris Brezillon */ 705b2adbddSGustavo A. R. Silva u64 counters[]; 7165101d8cSBoris Brezillon }; 7265101d8cSBoris Brezillon 73c8b75bcaSEric Anholt struct vc4_dev { 74c8b75bcaSEric Anholt struct drm_device *dev; 75c8b75bcaSEric Anholt 76c8b75bcaSEric Anholt struct vc4_hvs *hvs; 77d3f5168aSEric Anholt struct vc4_v3d *v3d; 7808302c35SEric Anholt struct vc4_dpi *dpi; 794078f575SEric Anholt struct vc4_dsi *dsi1; 80e4b81f8cSBoris Brezillon struct vc4_vec *vec; 81008095e0SBoris Brezillon struct vc4_txp *txp; 8248666d56SDerek Foreman 8321461365SEric Anholt struct vc4_hang_state *hang_state; 8421461365SEric Anholt 85c826a6e1SEric Anholt /* The kernel-space BO cache. Tracks buffers that have been 86c826a6e1SEric Anholt * unreferenced by all other users (refcounts of 0!) but not 87c826a6e1SEric Anholt * yet freed, so we can do cheap allocations. 88c826a6e1SEric Anholt */ 89c826a6e1SEric Anholt struct vc4_bo_cache { 90c826a6e1SEric Anholt /* Array of list heads for entries in the BO cache, 91c826a6e1SEric Anholt * based on number of pages, so we can do O(1) lookups 92c826a6e1SEric Anholt * in the cache when allocating. 93c826a6e1SEric Anholt */ 94c826a6e1SEric Anholt struct list_head *size_list; 95c826a6e1SEric Anholt uint32_t size_list_size; 96c826a6e1SEric Anholt 97c826a6e1SEric Anholt /* List of all BOs in the cache, ordered by age, so we 98c826a6e1SEric Anholt * can do O(1) lookups when trying to free old 99c826a6e1SEric Anholt * buffers. 100c826a6e1SEric Anholt */ 101c826a6e1SEric Anholt struct list_head time_list; 102c826a6e1SEric Anholt struct work_struct time_work; 103c826a6e1SEric Anholt struct timer_list time_timer; 104c826a6e1SEric Anholt } bo_cache; 105c826a6e1SEric Anholt 106f3099462SEric Anholt u32 num_labels; 107f3099462SEric Anholt struct vc4_label { 108f3099462SEric Anholt const char *name; 109c826a6e1SEric Anholt u32 num_allocated; 110c826a6e1SEric Anholt u32 size_allocated; 111f3099462SEric Anholt } *bo_labels; 112c826a6e1SEric Anholt 113f3099462SEric Anholt /* Protects bo_cache and bo_labels. */ 114c826a6e1SEric Anholt struct mutex bo_lock; 115d5b1a78aSEric Anholt 116b9f19259SBoris Brezillon /* Purgeable BO pool. All BOs in this pool can have their memory 117b9f19259SBoris Brezillon * reclaimed if the driver is unable to allocate new BOs. We also 118b9f19259SBoris Brezillon * keep stats related to the purge mechanism here. 119b9f19259SBoris Brezillon */ 120b9f19259SBoris Brezillon struct { 121b9f19259SBoris Brezillon struct list_head list; 122b9f19259SBoris Brezillon unsigned int num; 123b9f19259SBoris Brezillon size_t size; 124b9f19259SBoris Brezillon unsigned int purged_num; 125b9f19259SBoris Brezillon size_t purged_size; 126b9f19259SBoris Brezillon struct mutex lock; 127b9f19259SBoris Brezillon } purgeable; 128b9f19259SBoris Brezillon 129cdec4d36SEric Anholt uint64_t dma_fence_context; 130cdec4d36SEric Anholt 131ca26d28bSVarad Gautam /* Sequence number for the last job queued in bin_job_list. 132d5b1a78aSEric Anholt * Starts at 0 (no jobs emitted). 133d5b1a78aSEric Anholt */ 134d5b1a78aSEric Anholt uint64_t emit_seqno; 135d5b1a78aSEric Anholt 136d5b1a78aSEric Anholt /* Sequence number for the last completed job on the GPU. 137d5b1a78aSEric Anholt * Starts at 0 (no jobs completed). 138d5b1a78aSEric Anholt */ 139d5b1a78aSEric Anholt uint64_t finished_seqno; 140d5b1a78aSEric Anholt 141ca26d28bSVarad Gautam /* List of all struct vc4_exec_info for jobs to be executed in 142ca26d28bSVarad Gautam * the binner. The first job in the list is the one currently 143ca26d28bSVarad Gautam * programmed into ct0ca for execution. 144d5b1a78aSEric Anholt */ 145ca26d28bSVarad Gautam struct list_head bin_job_list; 146ca26d28bSVarad Gautam 147ca26d28bSVarad Gautam /* List of all struct vc4_exec_info for jobs that have 148ca26d28bSVarad Gautam * completed binning and are ready for rendering. The first 149ca26d28bSVarad Gautam * job in the list is the one currently programmed into ct1ca 150ca26d28bSVarad Gautam * for execution. 151ca26d28bSVarad Gautam */ 152ca26d28bSVarad Gautam struct list_head render_job_list; 153ca26d28bSVarad Gautam 154d5b1a78aSEric Anholt /* List of the finished vc4_exec_infos waiting to be freed by 155d5b1a78aSEric Anholt * job_done_work. 156d5b1a78aSEric Anholt */ 157d5b1a78aSEric Anholt struct list_head job_done_list; 158d5b1a78aSEric Anholt /* Spinlock used to synchronize the job_list and seqno 159d5b1a78aSEric Anholt * accesses between the IRQ handler and GEM ioctls. 160d5b1a78aSEric Anholt */ 161d5b1a78aSEric Anholt spinlock_t job_lock; 162d5b1a78aSEric Anholt wait_queue_head_t job_wait_queue; 163d5b1a78aSEric Anholt struct work_struct job_done_work; 164d5b1a78aSEric Anholt 16565101d8cSBoris Brezillon /* Used to track the active perfmon if any. Access to this field is 16665101d8cSBoris Brezillon * protected by job_lock. 16765101d8cSBoris Brezillon */ 16865101d8cSBoris Brezillon struct vc4_perfmon *active_perfmon; 16965101d8cSBoris Brezillon 170b501baccSEric Anholt /* List of struct vc4_seqno_cb for callbacks to be made from a 171b501baccSEric Anholt * workqueue when the given seqno is passed. 172b501baccSEric Anholt */ 173b501baccSEric Anholt struct list_head seqno_cb_list; 174b501baccSEric Anholt 175553c942fSEric Anholt /* The memory used for storing binner tile alloc, tile state, 176553c942fSEric Anholt * and overflow memory allocations. This is freed when V3D 177553c942fSEric Anholt * powers down. 178d5b1a78aSEric Anholt */ 179553c942fSEric Anholt struct vc4_bo *bin_bo; 180553c942fSEric Anholt 181553c942fSEric Anholt /* Size of blocks allocated within bin_bo. */ 182553c942fSEric Anholt uint32_t bin_alloc_size; 183553c942fSEric Anholt 184553c942fSEric Anholt /* Bitmask of the bin_alloc_size chunks in bin_bo that are 185553c942fSEric Anholt * used. 186553c942fSEric Anholt */ 187553c942fSEric Anholt uint32_t bin_alloc_used; 188553c942fSEric Anholt 189553c942fSEric Anholt /* Bitmask of the current bin_alloc used for overflow memory. */ 190553c942fSEric Anholt uint32_t bin_alloc_overflow; 191553c942fSEric Anholt 192531a1b62SBoris Brezillon /* Incremented when an underrun error happened after an atomic commit. 193531a1b62SBoris Brezillon * This is particularly useful to detect when a specific modeset is too 194531a1b62SBoris Brezillon * demanding in term of memory or HVS bandwidth which is hard to guess 195531a1b62SBoris Brezillon * at atomic check time. 196531a1b62SBoris Brezillon */ 197531a1b62SBoris Brezillon atomic_t underrun; 198531a1b62SBoris Brezillon 199d5b1a78aSEric Anholt struct work_struct overflow_mem_work; 200d5b1a78aSEric Anholt 20136cb6253SEric Anholt int power_refcount; 20236cb6253SEric Anholt 203f437bc1eSMaxime Ripard /* Set to true when the load tracker is supported. */ 204f437bc1eSMaxime Ripard bool load_tracker_available; 205f437bc1eSMaxime Ripard 2066b5c029dSPaul Kocialkowski /* Set to true when the load tracker is active. */ 2076b5c029dSPaul Kocialkowski bool load_tracker_enabled; 2086b5c029dSPaul Kocialkowski 20936cb6253SEric Anholt /* Mutex controlling the power refcount. */ 21036cb6253SEric Anholt struct mutex power_lock; 21136cb6253SEric Anholt 212d5b1a78aSEric Anholt struct { 213d5b1a78aSEric Anholt struct timer_list timer; 214d5b1a78aSEric Anholt struct work_struct reset_work; 215d5b1a78aSEric Anholt } hangcheck; 216d5b1a78aSEric Anholt 217d5b1a78aSEric Anholt struct semaphore async_modeset; 218766cc6b1SStefan Schake 219766cc6b1SStefan Schake struct drm_modeset_lock ctm_state_lock; 220766cc6b1SStefan Schake struct drm_private_obj ctm_manager; 2214686da83SBoris Brezillon struct drm_private_obj load_tracker; 222c9be804cSEric Anholt 223c9be804cSEric Anholt /* List of vc4_debugfs_info_entry for adding to debugfs once 224c9be804cSEric Anholt * the minor is available (after drm_dev_register()). 225c9be804cSEric Anholt */ 226c9be804cSEric Anholt struct list_head debugfs_list; 22735c8b4b2SPaul Kocialkowski 22835c8b4b2SPaul Kocialkowski /* Mutex for binner bo allocation. */ 22935c8b4b2SPaul Kocialkowski struct mutex bin_bo_lock; 23035c8b4b2SPaul Kocialkowski /* Reference count for our binner bo. */ 23135c8b4b2SPaul Kocialkowski struct kref bin_bo_kref; 232c8b75bcaSEric Anholt }; 233c8b75bcaSEric Anholt 234c8b75bcaSEric Anholt static inline struct vc4_dev * 235c8b75bcaSEric Anholt to_vc4_dev(struct drm_device *dev) 236c8b75bcaSEric Anholt { 237c8b75bcaSEric Anholt return (struct vc4_dev *)dev->dev_private; 238c8b75bcaSEric Anholt } 239c8b75bcaSEric Anholt 240c8b75bcaSEric Anholt struct vc4_bo { 241c8b75bcaSEric Anholt struct drm_gem_cma_object base; 242c826a6e1SEric Anholt 2437edabee0SEric Anholt /* seqno of the last job to render using this BO. */ 244d5b1a78aSEric Anholt uint64_t seqno; 245d5b1a78aSEric Anholt 2467edabee0SEric Anholt /* seqno of the last job to use the RCL to write to this BO. 2477edabee0SEric Anholt * 2487edabee0SEric Anholt * Note that this doesn't include binner overflow memory 2497edabee0SEric Anholt * writes. 2507edabee0SEric Anholt */ 2517edabee0SEric Anholt uint64_t write_seqno; 2527edabee0SEric Anholt 25383753117SEric Anholt bool t_format; 25483753117SEric Anholt 255c826a6e1SEric Anholt /* List entry for the BO's position in either 256c826a6e1SEric Anholt * vc4_exec_info->unref_list or vc4_dev->bo_cache.time_list 257c826a6e1SEric Anholt */ 258c826a6e1SEric Anholt struct list_head unref_head; 259c826a6e1SEric Anholt 260c826a6e1SEric Anholt /* Time in jiffies when the BO was put in vc4->bo_cache. */ 261c826a6e1SEric Anholt unsigned long free_time; 262c826a6e1SEric Anholt 263c826a6e1SEric Anholt /* List entry for the BO's position in vc4_dev->bo_cache.size_list */ 264c826a6e1SEric Anholt struct list_head size_head; 265463873d5SEric Anholt 266463873d5SEric Anholt /* Struct for shader validation state, if created by 267463873d5SEric Anholt * DRM_IOCTL_VC4_CREATE_SHADER_BO. 268463873d5SEric Anholt */ 269463873d5SEric Anholt struct vc4_validated_shader_info *validated_shader; 270cdec4d36SEric Anholt 271f3099462SEric Anholt /* One of enum vc4_kernel_bo_type, or VC4_BO_TYPE_COUNT + i 272f3099462SEric Anholt * for user-allocated labels. 273f3099462SEric Anholt */ 274f3099462SEric Anholt int label; 275b9f19259SBoris Brezillon 276b9f19259SBoris Brezillon /* Count the number of active users. This is needed to determine 277b9f19259SBoris Brezillon * whether we can move the BO to the purgeable list or not (when the BO 278b9f19259SBoris Brezillon * is used by the GPU or the display engine we can't purge it). 279b9f19259SBoris Brezillon */ 280b9f19259SBoris Brezillon refcount_t usecnt; 281b9f19259SBoris Brezillon 282b9f19259SBoris Brezillon /* Store purgeable/purged state here */ 283b9f19259SBoris Brezillon u32 madv; 284b9f19259SBoris Brezillon struct mutex madv_lock; 285c8b75bcaSEric Anholt }; 286c8b75bcaSEric Anholt 287c8b75bcaSEric Anholt static inline struct vc4_bo * 288c8b75bcaSEric Anholt to_vc4_bo(struct drm_gem_object *bo) 289c8b75bcaSEric Anholt { 290c8b75bcaSEric Anholt return (struct vc4_bo *)bo; 291c8b75bcaSEric Anholt } 292c8b75bcaSEric Anholt 293cdec4d36SEric Anholt struct vc4_fence { 294cdec4d36SEric Anholt struct dma_fence base; 295cdec4d36SEric Anholt struct drm_device *dev; 296cdec4d36SEric Anholt /* vc4 seqno for signaled() test */ 297cdec4d36SEric Anholt uint64_t seqno; 298cdec4d36SEric Anholt }; 299cdec4d36SEric Anholt 300cdec4d36SEric Anholt static inline struct vc4_fence * 301cdec4d36SEric Anholt to_vc4_fence(struct dma_fence *fence) 302cdec4d36SEric Anholt { 303cdec4d36SEric Anholt return (struct vc4_fence *)fence; 304cdec4d36SEric Anholt } 305cdec4d36SEric Anholt 306b501baccSEric Anholt struct vc4_seqno_cb { 307b501baccSEric Anholt struct work_struct work; 308b501baccSEric Anholt uint64_t seqno; 309b501baccSEric Anholt void (*func)(struct vc4_seqno_cb *cb); 310b501baccSEric Anholt }; 311b501baccSEric Anholt 312d3f5168aSEric Anholt struct vc4_v3d { 313001bdb55SEric Anholt struct vc4_dev *vc4; 314d3f5168aSEric Anholt struct platform_device *pdev; 315d3f5168aSEric Anholt void __iomem *regs; 316b72a2816SEric Anholt struct clk *clk; 3173051719aSEric Anholt struct debugfs_regset32 regset; 318d3f5168aSEric Anholt }; 319d3f5168aSEric Anholt 320c8b75bcaSEric Anholt struct vc4_hvs { 321c8b75bcaSEric Anholt struct platform_device *pdev; 322c8b75bcaSEric Anholt void __iomem *regs; 323d8dbf44fSEric Anholt u32 __iomem *dlist; 324d8dbf44fSEric Anholt 325d7d96c00SMaxime Ripard struct clk *core_clk; 326d7d96c00SMaxime Ripard 327d8dbf44fSEric Anholt /* Memory manager for CRTCs to allocate space in the display 328d8dbf44fSEric Anholt * list. Units are dwords. 329d8dbf44fSEric Anholt */ 330d8dbf44fSEric Anholt struct drm_mm dlist_mm; 33121af94cfSEric Anholt /* Memory manager for the LBM memory used by HVS scaling. */ 33221af94cfSEric Anholt struct drm_mm lbm_mm; 333d8dbf44fSEric Anholt spinlock_t mm_lock; 33421af94cfSEric Anholt 33521af94cfSEric Anholt struct drm_mm_node mitchell_netravali_filter; 336c54619b0SDave Stevenson 3373051719aSEric Anholt struct debugfs_regset32 regset; 338c54619b0SDave Stevenson 339c54619b0SDave Stevenson /* HVS version 5 flag, therefore requires updated dlist structures */ 340c54619b0SDave Stevenson bool hvs5; 341c8b75bcaSEric Anholt }; 342c8b75bcaSEric Anholt 343c8b75bcaSEric Anholt struct vc4_plane { 344c8b75bcaSEric Anholt struct drm_plane base; 345c8b75bcaSEric Anholt }; 346c8b75bcaSEric Anholt 347c8b75bcaSEric Anholt static inline struct vc4_plane * 348c8b75bcaSEric Anholt to_vc4_plane(struct drm_plane *plane) 349c8b75bcaSEric Anholt { 350c8b75bcaSEric Anholt return (struct vc4_plane *)plane; 351c8b75bcaSEric Anholt } 352c8b75bcaSEric Anholt 35382364698SStefan Schake enum vc4_scaling_mode { 35482364698SStefan Schake VC4_SCALING_NONE, 35582364698SStefan Schake VC4_SCALING_TPZ, 35682364698SStefan Schake VC4_SCALING_PPF, 35782364698SStefan Schake }; 35882364698SStefan Schake 35982364698SStefan Schake struct vc4_plane_state { 36082364698SStefan Schake struct drm_plane_state base; 36182364698SStefan Schake /* System memory copy of the display list for this element, computed 36282364698SStefan Schake * at atomic_check time. 36382364698SStefan Schake */ 36482364698SStefan Schake u32 *dlist; 36582364698SStefan Schake u32 dlist_size; /* Number of dwords allocated for the display list */ 36682364698SStefan Schake u32 dlist_count; /* Number of used dwords in the display list. */ 36782364698SStefan Schake 36882364698SStefan Schake /* Offset in the dlist to various words, for pageflip or 36982364698SStefan Schake * cursor updates. 37082364698SStefan Schake */ 37182364698SStefan Schake u32 pos0_offset; 37282364698SStefan Schake u32 pos2_offset; 37382364698SStefan Schake u32 ptr0_offset; 3740a038c1cSBoris Brezillon u32 lbm_offset; 37582364698SStefan Schake 37682364698SStefan Schake /* Offset where the plane's dlist was last stored in the 37782364698SStefan Schake * hardware at vc4_crtc_atomic_flush() time. 37882364698SStefan Schake */ 37982364698SStefan Schake u32 __iomem *hw_dlist; 38082364698SStefan Schake 38182364698SStefan Schake /* Clipped coordinates of the plane on the display. */ 38282364698SStefan Schake int crtc_x, crtc_y, crtc_w, crtc_h; 38382364698SStefan Schake /* Clipped area being scanned from in the FB. */ 38482364698SStefan Schake u32 src_x, src_y; 38582364698SStefan Schake 38682364698SStefan Schake u32 src_w[2], src_h[2]; 38782364698SStefan Schake 38882364698SStefan Schake /* Scaling selection for the RGB/Y plane and the Cb/Cr planes. */ 38982364698SStefan Schake enum vc4_scaling_mode x_scaling[2], y_scaling[2]; 39082364698SStefan Schake bool is_unity; 39182364698SStefan Schake bool is_yuv; 39282364698SStefan Schake 39382364698SStefan Schake /* Offset to start scanning out from the start of the plane's 39482364698SStefan Schake * BO. 39582364698SStefan Schake */ 39682364698SStefan Schake u32 offsets[3]; 39782364698SStefan Schake 39882364698SStefan Schake /* Our allocation in LBM for temporary storage during scaling. */ 39982364698SStefan Schake struct drm_mm_node lbm; 40082364698SStefan Schake 40182364698SStefan Schake /* Set when the plane has per-pixel alpha content or does not cover 40282364698SStefan Schake * the entire screen. This is a hint to the CRTC that it might need 40382364698SStefan Schake * to enable background color fill. 40482364698SStefan Schake */ 40582364698SStefan Schake bool needs_bg_fill; 4068d938449SBoris Brezillon 4078d938449SBoris Brezillon /* Mark the dlist as initialized. Useful to avoid initializing it twice 4088d938449SBoris Brezillon * when async update is not possible. 4098d938449SBoris Brezillon */ 4108d938449SBoris Brezillon bool dlist_initialized; 4114686da83SBoris Brezillon 4124686da83SBoris Brezillon /* Load of this plane on the HVS block. The load is expressed in HVS 4134686da83SBoris Brezillon * cycles/sec. 4144686da83SBoris Brezillon */ 4154686da83SBoris Brezillon u64 hvs_load; 4164686da83SBoris Brezillon 4174686da83SBoris Brezillon /* Memory bandwidth needed for this plane. This is expressed in 4184686da83SBoris Brezillon * bytes/sec. 4194686da83SBoris Brezillon */ 4204686da83SBoris Brezillon u64 membus_load; 42182364698SStefan Schake }; 42282364698SStefan Schake 42382364698SStefan Schake static inline struct vc4_plane_state * 42482364698SStefan Schake to_vc4_plane_state(struct drm_plane_state *state) 42582364698SStefan Schake { 42682364698SStefan Schake return (struct vc4_plane_state *)state; 42782364698SStefan Schake } 42882364698SStefan Schake 429c8b75bcaSEric Anholt enum vc4_encoder_type { 430ab8df60eSBoris Brezillon VC4_ENCODER_TYPE_NONE, 431ed024b22SMaxime Ripard VC4_ENCODER_TYPE_HDMI0, 432aa2fd1caSMaxime Ripard VC4_ENCODER_TYPE_HDMI1, 433c8b75bcaSEric Anholt VC4_ENCODER_TYPE_VEC, 434c8b75bcaSEric Anholt VC4_ENCODER_TYPE_DSI0, 435c8b75bcaSEric Anholt VC4_ENCODER_TYPE_DSI1, 436c8b75bcaSEric Anholt VC4_ENCODER_TYPE_SMI, 437c8b75bcaSEric Anholt VC4_ENCODER_TYPE_DPI, 438c8b75bcaSEric Anholt }; 439c8b75bcaSEric Anholt 440c8b75bcaSEric Anholt struct vc4_encoder { 441c8b75bcaSEric Anholt struct drm_encoder base; 442c8b75bcaSEric Anholt enum vc4_encoder_type type; 443c8b75bcaSEric Anholt u32 clock_select; 444792c3132SMaxime Ripard 445792c3132SMaxime Ripard void (*pre_crtc_configure)(struct drm_encoder *encoder); 446792c3132SMaxime Ripard void (*pre_crtc_enable)(struct drm_encoder *encoder); 447792c3132SMaxime Ripard void (*post_crtc_enable)(struct drm_encoder *encoder); 448792c3132SMaxime Ripard 449792c3132SMaxime Ripard void (*post_crtc_disable)(struct drm_encoder *encoder); 450792c3132SMaxime Ripard void (*post_crtc_powerdown)(struct drm_encoder *encoder); 451c8b75bcaSEric Anholt }; 452c8b75bcaSEric Anholt 453c8b75bcaSEric Anholt static inline struct vc4_encoder * 454c8b75bcaSEric Anholt to_vc4_encoder(struct drm_encoder *encoder) 455c8b75bcaSEric Anholt { 456c8b75bcaSEric Anholt return container_of(encoder, struct vc4_encoder, base); 457c8b75bcaSEric Anholt } 458c8b75bcaSEric Anholt 45979271807SStefan Schake struct vc4_crtc_data { 46087ebcd42SMaxime Ripard /* Bitmask of channels (FIFOs) of the HVS that the output can source from */ 46187ebcd42SMaxime Ripard unsigned int hvs_available_channels; 46287ebcd42SMaxime Ripard 4638ebb2cf0SMaxime Ripard /* Which output of the HVS this pixelvalve sources from. */ 4648ebb2cf0SMaxime Ripard int hvs_output; 4655a20ff8bSMaxime Ripard }; 4665a20ff8bSMaxime Ripard 4675a20ff8bSMaxime Ripard struct vc4_pv_data { 4685a20ff8bSMaxime Ripard struct vc4_crtc_data base; 46979271807SStefan Schake 470649abf2fSMaxime Ripard /* Depth of the PixelValve FIFO in bytes */ 471649abf2fSMaxime Ripard unsigned int fifo_depth; 472649abf2fSMaxime Ripard 473644df22fSMaxime Ripard /* Number of pixels output per clock period */ 474644df22fSMaxime Ripard u8 pixels_per_clock; 475644df22fSMaxime Ripard 47679271807SStefan Schake enum vc4_encoder_type encoder_types[4]; 477c9be804cSEric Anholt const char *debugfs_name; 4785a20ff8bSMaxime Ripard 47979271807SStefan Schake }; 48079271807SStefan Schake 48179271807SStefan Schake struct vc4_crtc { 48279271807SStefan Schake struct drm_crtc base; 4833051719aSEric Anholt struct platform_device *pdev; 48479271807SStefan Schake const struct vc4_crtc_data *data; 48579271807SStefan Schake void __iomem *regs; 48679271807SStefan Schake 48779271807SStefan Schake /* Timestamp at start of vblank irq - unaffected by lock delays. */ 48879271807SStefan Schake ktime_t t_vblank; 48979271807SStefan Schake 49079271807SStefan Schake u8 lut_r[256]; 49179271807SStefan Schake u8 lut_g[256]; 49279271807SStefan Schake u8 lut_b[256]; 49379271807SStefan Schake 49479271807SStefan Schake struct drm_pending_vblank_event *event; 4953051719aSEric Anholt 4963051719aSEric Anholt struct debugfs_regset32 regset; 49779271807SStefan Schake }; 49879271807SStefan Schake 49979271807SStefan Schake static inline struct vc4_crtc * 50079271807SStefan Schake to_vc4_crtc(struct drm_crtc *crtc) 50179271807SStefan Schake { 50279271807SStefan Schake return (struct vc4_crtc *)crtc; 50379271807SStefan Schake } 50479271807SStefan Schake 5055a20ff8bSMaxime Ripard static inline const struct vc4_crtc_data * 5065a20ff8bSMaxime Ripard vc4_crtc_to_vc4_crtc_data(const struct vc4_crtc *crtc) 5075a20ff8bSMaxime Ripard { 5085a20ff8bSMaxime Ripard return crtc->data; 5095a20ff8bSMaxime Ripard } 5105a20ff8bSMaxime Ripard 5115a20ff8bSMaxime Ripard static inline const struct vc4_pv_data * 5125a20ff8bSMaxime Ripard vc4_crtc_to_vc4_pv_data(const struct vc4_crtc *crtc) 5135a20ff8bSMaxime Ripard { 5145a20ff8bSMaxime Ripard const struct vc4_crtc_data *data = vc4_crtc_to_vc4_crtc_data(crtc); 5155a20ff8bSMaxime Ripard 5165a20ff8bSMaxime Ripard return container_of(data, struct vc4_pv_data, base); 5175a20ff8bSMaxime Ripard } 5185a20ff8bSMaxime Ripard 519ae44a527SMaxime Ripard struct vc4_crtc_state { 520ae44a527SMaxime Ripard struct drm_crtc_state base; 521ae44a527SMaxime Ripard /* Dlist area for this CRTC configuration. */ 522ae44a527SMaxime Ripard struct drm_mm_node mm; 523ae44a527SMaxime Ripard bool feed_txp; 524ae44a527SMaxime Ripard bool txp_armed; 52587ebcd42SMaxime Ripard unsigned int assigned_channel; 526ae44a527SMaxime Ripard 527ae44a527SMaxime Ripard struct { 528ae44a527SMaxime Ripard unsigned int left; 529ae44a527SMaxime Ripard unsigned int right; 530ae44a527SMaxime Ripard unsigned int top; 531ae44a527SMaxime Ripard unsigned int bottom; 532ae44a527SMaxime Ripard } margins; 533ae44a527SMaxime Ripard }; 534ae44a527SMaxime Ripard 535ae44a527SMaxime Ripard static inline struct vc4_crtc_state * 536ae44a527SMaxime Ripard to_vc4_crtc_state(struct drm_crtc_state *crtc_state) 537ae44a527SMaxime Ripard { 538ae44a527SMaxime Ripard return (struct vc4_crtc_state *)crtc_state; 539ae44a527SMaxime Ripard } 540ae44a527SMaxime Ripard 541d3f5168aSEric Anholt #define V3D_READ(offset) readl(vc4->v3d->regs + offset) 542d3f5168aSEric Anholt #define V3D_WRITE(offset, val) writel(val, vc4->v3d->regs + offset) 543c8b75bcaSEric Anholt #define HVS_READ(offset) readl(vc4->hvs->regs + offset) 544c8b75bcaSEric Anholt #define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset) 545c8b75bcaSEric Anholt 5463051719aSEric Anholt #define VC4_REG32(reg) { .name = #reg, .offset = reg } 5473051719aSEric Anholt 548d5b1a78aSEric Anholt struct vc4_exec_info { 549d5b1a78aSEric Anholt /* Sequence number for this bin/render job. */ 550d5b1a78aSEric Anholt uint64_t seqno; 551d5b1a78aSEric Anholt 5527edabee0SEric Anholt /* Latest write_seqno of any BO that binning depends on. */ 5537edabee0SEric Anholt uint64_t bin_dep_seqno; 5547edabee0SEric Anholt 555cdec4d36SEric Anholt struct dma_fence *fence; 556cdec4d36SEric Anholt 557c4ce60dcSEric Anholt /* Last current addresses the hardware was processing when the 558c4ce60dcSEric Anholt * hangcheck timer checked on us. 559c4ce60dcSEric Anholt */ 560c4ce60dcSEric Anholt uint32_t last_ct0ca, last_ct1ca; 561c4ce60dcSEric Anholt 562d5b1a78aSEric Anholt /* Kernel-space copy of the ioctl arguments */ 563d5b1a78aSEric Anholt struct drm_vc4_submit_cl *args; 564d5b1a78aSEric Anholt 565d5b1a78aSEric Anholt /* This is the array of BOs that were looked up at the start of exec. 566d5b1a78aSEric Anholt * Command validation will use indices into this array. 567d5b1a78aSEric Anholt */ 568d5b1a78aSEric Anholt struct drm_gem_cma_object **bo; 569d5b1a78aSEric Anholt uint32_t bo_count; 570d5b1a78aSEric Anholt 5717edabee0SEric Anholt /* List of BOs that are being written by the RCL. Other than 5727edabee0SEric Anholt * the binner temporary storage, this is all the BOs written 5737edabee0SEric Anholt * by the job. 5747edabee0SEric Anholt */ 5757edabee0SEric Anholt struct drm_gem_cma_object *rcl_write_bo[4]; 5767edabee0SEric Anholt uint32_t rcl_write_bo_count; 5777edabee0SEric Anholt 578d5b1a78aSEric Anholt /* Pointers for our position in vc4->job_list */ 579d5b1a78aSEric Anholt struct list_head head; 580d5b1a78aSEric Anholt 581d5b1a78aSEric Anholt /* List of other BOs used in the job that need to be released 582d5b1a78aSEric Anholt * once the job is complete. 583d5b1a78aSEric Anholt */ 584d5b1a78aSEric Anholt struct list_head unref_list; 585d5b1a78aSEric Anholt 586d5b1a78aSEric Anholt /* Current unvalidated indices into @bo loaded by the non-hardware 587d5b1a78aSEric Anholt * VC4_PACKET_GEM_HANDLES. 588d5b1a78aSEric Anholt */ 589d5b1a78aSEric Anholt uint32_t bo_index[2]; 590d5b1a78aSEric Anholt 591d5b1a78aSEric Anholt /* This is the BO where we store the validated command lists, shader 592d5b1a78aSEric Anholt * records, and uniforms. 593d5b1a78aSEric Anholt */ 594d5b1a78aSEric Anholt struct drm_gem_cma_object *exec_bo; 595d5b1a78aSEric Anholt 596d5b1a78aSEric Anholt /** 597d5b1a78aSEric Anholt * This tracks the per-shader-record state (packet 64) that 598d5b1a78aSEric Anholt * determines the length of the shader record and the offset 599d5b1a78aSEric Anholt * it's expected to be found at. It gets read in from the 600d5b1a78aSEric Anholt * command lists. 601d5b1a78aSEric Anholt */ 602d5b1a78aSEric Anholt struct vc4_shader_state { 603d5b1a78aSEric Anholt uint32_t addr; 604d5b1a78aSEric Anholt /* Maximum vertex index referenced by any primitive using this 605d5b1a78aSEric Anholt * shader state. 606d5b1a78aSEric Anholt */ 607d5b1a78aSEric Anholt uint32_t max_index; 608d5b1a78aSEric Anholt } *shader_state; 609d5b1a78aSEric Anholt 610d5b1a78aSEric Anholt /** How many shader states the user declared they were using. */ 611d5b1a78aSEric Anholt uint32_t shader_state_size; 612d5b1a78aSEric Anholt /** How many shader state records the validator has seen. */ 613d5b1a78aSEric Anholt uint32_t shader_state_count; 614d5b1a78aSEric Anholt 615d5b1a78aSEric Anholt bool found_tile_binning_mode_config_packet; 616d5b1a78aSEric Anholt bool found_start_tile_binning_packet; 617d5b1a78aSEric Anholt bool found_increment_semaphore_packet; 618d5b1a78aSEric Anholt bool found_flush; 619d5b1a78aSEric Anholt uint8_t bin_tiles_x, bin_tiles_y; 620553c942fSEric Anholt /* Physical address of the start of the tile alloc array 621553c942fSEric Anholt * (where each tile's binned CL will start) 622553c942fSEric Anholt */ 623d5b1a78aSEric Anholt uint32_t tile_alloc_offset; 624553c942fSEric Anholt /* Bitmask of which binner slots are freed when this job completes. */ 625553c942fSEric Anholt uint32_t bin_slots; 626d5b1a78aSEric Anholt 627d5b1a78aSEric Anholt /** 628d5b1a78aSEric Anholt * Computed addresses pointing into exec_bo where we start the 629d5b1a78aSEric Anholt * bin thread (ct0) and render thread (ct1). 630d5b1a78aSEric Anholt */ 631d5b1a78aSEric Anholt uint32_t ct0ca, ct0ea; 632d5b1a78aSEric Anholt uint32_t ct1ca, ct1ea; 633d5b1a78aSEric Anholt 634d5b1a78aSEric Anholt /* Pointer to the unvalidated bin CL (if present). */ 635d5b1a78aSEric Anholt void *bin_u; 636d5b1a78aSEric Anholt 637d5b1a78aSEric Anholt /* Pointers to the shader recs. These paddr gets incremented as CL 638d5b1a78aSEric Anholt * packets are relocated in validate_gl_shader_state, and the vaddrs 639d5b1a78aSEric Anholt * (u and v) get incremented and size decremented as the shader recs 640d5b1a78aSEric Anholt * themselves are validated. 641d5b1a78aSEric Anholt */ 642d5b1a78aSEric Anholt void *shader_rec_u; 643d5b1a78aSEric Anholt void *shader_rec_v; 644d5b1a78aSEric Anholt uint32_t shader_rec_p; 645d5b1a78aSEric Anholt uint32_t shader_rec_size; 646d5b1a78aSEric Anholt 647d5b1a78aSEric Anholt /* Pointers to the uniform data. These pointers are incremented, and 648d5b1a78aSEric Anholt * size decremented, as each batch of uniforms is uploaded. 649d5b1a78aSEric Anholt */ 650d5b1a78aSEric Anholt void *uniforms_u; 651d5b1a78aSEric Anholt void *uniforms_v; 652d5b1a78aSEric Anholt uint32_t uniforms_p; 653d5b1a78aSEric Anholt uint32_t uniforms_size; 65465101d8cSBoris Brezillon 65565101d8cSBoris Brezillon /* Pointer to a performance monitor object if the user requested it, 65665101d8cSBoris Brezillon * NULL otherwise. 65765101d8cSBoris Brezillon */ 65865101d8cSBoris Brezillon struct vc4_perfmon *perfmon; 65935c8b4b2SPaul Kocialkowski 66035c8b4b2SPaul Kocialkowski /* Whether the exec has taken a reference to the binner BO, which should 66135c8b4b2SPaul Kocialkowski * happen with a VC4_PACKET_TILE_BINNING_MODE_CONFIG packet. 66235c8b4b2SPaul Kocialkowski */ 66335c8b4b2SPaul Kocialkowski bool bin_bo_used; 66465101d8cSBoris Brezillon }; 66565101d8cSBoris Brezillon 66665101d8cSBoris Brezillon /* Per-open file private data. Any driver-specific resource that has to be 66765101d8cSBoris Brezillon * released when the DRM file is closed should be placed here. 66865101d8cSBoris Brezillon */ 66965101d8cSBoris Brezillon struct vc4_file { 67065101d8cSBoris Brezillon struct { 67165101d8cSBoris Brezillon struct idr idr; 67265101d8cSBoris Brezillon struct mutex lock; 67365101d8cSBoris Brezillon } perfmon; 67435c8b4b2SPaul Kocialkowski 67535c8b4b2SPaul Kocialkowski bool bin_bo_used; 676d5b1a78aSEric Anholt }; 677d5b1a78aSEric Anholt 678d5b1a78aSEric Anholt static inline struct vc4_exec_info * 679ca26d28bSVarad Gautam vc4_first_bin_job(struct vc4_dev *vc4) 680d5b1a78aSEric Anholt { 68157b9f569SMasahiro Yamada return list_first_entry_or_null(&vc4->bin_job_list, 68257b9f569SMasahiro Yamada struct vc4_exec_info, head); 683ca26d28bSVarad Gautam } 684ca26d28bSVarad Gautam 685ca26d28bSVarad Gautam static inline struct vc4_exec_info * 686ca26d28bSVarad Gautam vc4_first_render_job(struct vc4_dev *vc4) 687ca26d28bSVarad Gautam { 68857b9f569SMasahiro Yamada return list_first_entry_or_null(&vc4->render_job_list, 689ca26d28bSVarad Gautam struct vc4_exec_info, head); 690d5b1a78aSEric Anholt } 691d5b1a78aSEric Anholt 6929326e6f2SEric Anholt static inline struct vc4_exec_info * 6939326e6f2SEric Anholt vc4_last_render_job(struct vc4_dev *vc4) 6949326e6f2SEric Anholt { 6959326e6f2SEric Anholt if (list_empty(&vc4->render_job_list)) 6969326e6f2SEric Anholt return NULL; 6979326e6f2SEric Anholt return list_last_entry(&vc4->render_job_list, 6989326e6f2SEric Anholt struct vc4_exec_info, head); 6999326e6f2SEric Anholt } 7009326e6f2SEric Anholt 701c8b75bcaSEric Anholt /** 702463873d5SEric Anholt * struct vc4_texture_sample_info - saves the offsets into the UBO for texture 703463873d5SEric Anholt * setup parameters. 704463873d5SEric Anholt * 705463873d5SEric Anholt * This will be used at draw time to relocate the reference to the texture 706463873d5SEric Anholt * contents in p0, and validate that the offset combined with 707463873d5SEric Anholt * width/height/stride/etc. from p1 and p2/p3 doesn't sample outside the BO. 708463873d5SEric Anholt * Note that the hardware treats unprovided config parameters as 0, so not all 709463873d5SEric Anholt * of them need to be set up for every texure sample, and we'll store ~0 as 710463873d5SEric Anholt * the offset to mark the unused ones. 711463873d5SEric Anholt * 712463873d5SEric Anholt * See the VC4 3D architecture guide page 41 ("Texture and Memory Lookup Unit 713463873d5SEric Anholt * Setup") for definitions of the texture parameters. 714463873d5SEric Anholt */ 715463873d5SEric Anholt struct vc4_texture_sample_info { 716463873d5SEric Anholt bool is_direct; 717463873d5SEric Anholt uint32_t p_offset[4]; 718463873d5SEric Anholt }; 719463873d5SEric Anholt 720463873d5SEric Anholt /** 721463873d5SEric Anholt * struct vc4_validated_shader_info - information about validated shaders that 722463873d5SEric Anholt * needs to be used from command list validation. 723463873d5SEric Anholt * 724463873d5SEric Anholt * For a given shader, each time a shader state record references it, we need 725463873d5SEric Anholt * to verify that the shader doesn't read more uniforms than the shader state 726463873d5SEric Anholt * record's uniform BO pointer can provide, and we need to apply relocations 727463873d5SEric Anholt * and validate the shader state record's uniforms that define the texture 728463873d5SEric Anholt * samples. 729463873d5SEric Anholt */ 730463873d5SEric Anholt struct vc4_validated_shader_info { 731463873d5SEric Anholt uint32_t uniforms_size; 732463873d5SEric Anholt uint32_t uniforms_src_size; 733463873d5SEric Anholt uint32_t num_texture_samples; 734463873d5SEric Anholt struct vc4_texture_sample_info *texture_samples; 7356d45c81dSEric Anholt 7366d45c81dSEric Anholt uint32_t num_uniform_addr_offsets; 7376d45c81dSEric Anholt uint32_t *uniform_addr_offsets; 738c778cc5dSJonas Pfeil 739c778cc5dSJonas Pfeil bool is_threaded; 740463873d5SEric Anholt }; 741463873d5SEric Anholt 742463873d5SEric Anholt /** 7437f2a09ecSJames Hughes * __wait_for - magic wait macro 744c8b75bcaSEric Anholt * 7457f2a09ecSJames Hughes * Macro to help avoid open coding check/wait/timeout patterns. Note that it's 7467f2a09ecSJames Hughes * important that we check the condition again after having timed out, since the 7477f2a09ecSJames Hughes * timeout could be due to preemption or similar and we've never had a chance to 7487f2a09ecSJames Hughes * check the condition before the timeout. 749c8b75bcaSEric Anholt */ 7507f2a09ecSJames Hughes #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \ 7517f2a09ecSJames Hughes const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (US)); \ 7527f2a09ecSJames Hughes long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \ 7537f2a09ecSJames Hughes int ret__; \ 7547f2a09ecSJames Hughes might_sleep(); \ 7557f2a09ecSJames Hughes for (;;) { \ 7567f2a09ecSJames Hughes const bool expired__ = ktime_after(ktime_get_raw(), end__); \ 7577f2a09ecSJames Hughes OP; \ 7587f2a09ecSJames Hughes /* Guarantee COND check prior to timeout */ \ 7597f2a09ecSJames Hughes barrier(); \ 7607f2a09ecSJames Hughes if (COND) { \ 7617f2a09ecSJames Hughes ret__ = 0; \ 7627f2a09ecSJames Hughes break; \ 7637f2a09ecSJames Hughes } \ 7647f2a09ecSJames Hughes if (expired__) { \ 765c8b75bcaSEric Anholt ret__ = -ETIMEDOUT; \ 766c8b75bcaSEric Anholt break; \ 767c8b75bcaSEric Anholt } \ 7687f2a09ecSJames Hughes usleep_range(wait__, wait__ * 2); \ 7697f2a09ecSJames Hughes if (wait__ < (Wmax)) \ 7707f2a09ecSJames Hughes wait__ <<= 1; \ 771c8b75bcaSEric Anholt } \ 772c8b75bcaSEric Anholt ret__; \ 773c8b75bcaSEric Anholt }) 774c8b75bcaSEric Anholt 7757f2a09ecSJames Hughes #define _wait_for(COND, US, Wmin, Wmax) __wait_for(, (COND), (US), (Wmin), \ 7767f2a09ecSJames Hughes (Wmax)) 7777f2a09ecSJames Hughes #define wait_for(COND, MS) _wait_for((COND), (MS) * 1000, 10, 1000) 778c8b75bcaSEric Anholt 779c8b75bcaSEric Anholt /* vc4_bo.c */ 780c826a6e1SEric Anholt struct drm_gem_object *vc4_create_object(struct drm_device *dev, size_t size); 781c8b75bcaSEric Anholt void vc4_free_object(struct drm_gem_object *gem_obj); 782c826a6e1SEric Anholt struct vc4_bo *vc4_bo_create(struct drm_device *dev, size_t size, 783f3099462SEric Anholt bool from_cache, enum vc4_kernel_bo_type type); 784c8b75bcaSEric Anholt int vc4_dumb_create(struct drm_file *file_priv, 785c8b75bcaSEric Anholt struct drm_device *dev, 786c8b75bcaSEric Anholt struct drm_mode_create_dumb *args); 787e4fa8457SDaniel Vetter struct dma_buf *vc4_prime_export(struct drm_gem_object *obj, int flags); 788d5bc60f6SEric Anholt int vc4_create_bo_ioctl(struct drm_device *dev, void *data, 789d5bc60f6SEric Anholt struct drm_file *file_priv); 790463873d5SEric Anholt int vc4_create_shader_bo_ioctl(struct drm_device *dev, void *data, 791463873d5SEric Anholt struct drm_file *file_priv); 792d5bc60f6SEric Anholt int vc4_mmap_bo_ioctl(struct drm_device *dev, void *data, 793d5bc60f6SEric Anholt struct drm_file *file_priv); 79483753117SEric Anholt int vc4_set_tiling_ioctl(struct drm_device *dev, void *data, 79583753117SEric Anholt struct drm_file *file_priv); 79683753117SEric Anholt int vc4_get_tiling_ioctl(struct drm_device *dev, void *data, 79783753117SEric Anholt struct drm_file *file_priv); 79821461365SEric Anholt int vc4_get_hang_state_ioctl(struct drm_device *dev, void *data, 79921461365SEric Anholt struct drm_file *file_priv); 800f3099462SEric Anholt int vc4_label_bo_ioctl(struct drm_device *dev, void *data, 801f3099462SEric Anholt struct drm_file *file_priv); 802abd7dbe9SSouptick Joarder vm_fault_t vc4_fault(struct vm_fault *vmf); 803463873d5SEric Anholt int vc4_mmap(struct file *filp, struct vm_area_struct *vma); 804463873d5SEric Anholt int vc4_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma); 805cdec4d36SEric Anholt struct drm_gem_object *vc4_prime_import_sg_table(struct drm_device *dev, 806cdec4d36SEric Anholt struct dma_buf_attachment *attach, 807cdec4d36SEric Anholt struct sg_table *sgt); 808463873d5SEric Anholt void *vc4_prime_vmap(struct drm_gem_object *obj); 809f3099462SEric Anholt int vc4_bo_cache_init(struct drm_device *dev); 810c826a6e1SEric Anholt void vc4_bo_cache_destroy(struct drm_device *dev); 811b9f19259SBoris Brezillon int vc4_bo_inc_usecnt(struct vc4_bo *bo); 812b9f19259SBoris Brezillon void vc4_bo_dec_usecnt(struct vc4_bo *bo); 813b9f19259SBoris Brezillon void vc4_bo_add_to_purgeable_pool(struct vc4_bo *bo); 814b9f19259SBoris Brezillon void vc4_bo_remove_from_purgeable_pool(struct vc4_bo *bo); 815c8b75bcaSEric Anholt 816c8b75bcaSEric Anholt /* vc4_crtc.c */ 817c8b75bcaSEric Anholt extern struct platform_driver vc4_crtc_driver; 818875a4d53SMaxime Ripard int vc4_crtc_disable_at_boot(struct drm_crtc *crtc); 8195fefc601SMaxime Ripard int vc4_crtc_init(struct drm_device *drm, struct vc4_crtc *vc4_crtc, 8205fefc601SMaxime Ripard const struct drm_crtc_funcs *crtc_funcs, 8215fefc601SMaxime Ripard const struct drm_crtc_helper_funcs *crtc_helper_funcs); 822bdd96472SMaxime Ripard void vc4_crtc_destroy(struct drm_crtc *crtc); 823bdd96472SMaxime Ripard int vc4_page_flip(struct drm_crtc *crtc, 824bdd96472SMaxime Ripard struct drm_framebuffer *fb, 825bdd96472SMaxime Ripard struct drm_pending_vblank_event *event, 826bdd96472SMaxime Ripard uint32_t flags, 827bdd96472SMaxime Ripard struct drm_modeset_acquire_ctx *ctx); 828bdd96472SMaxime Ripard struct drm_crtc_state *vc4_crtc_duplicate_state(struct drm_crtc *crtc); 829bdd96472SMaxime Ripard void vc4_crtc_destroy_state(struct drm_crtc *crtc, 830bdd96472SMaxime Ripard struct drm_crtc_state *state); 831bdd96472SMaxime Ripard void vc4_crtc_reset(struct drm_crtc *crtc); 832008095e0SBoris Brezillon void vc4_crtc_handle_vblank(struct vc4_crtc *crtc); 833666e7358SBoris Brezillon void vc4_crtc_get_margins(struct drm_crtc_state *state, 834666e7358SBoris Brezillon unsigned int *right, unsigned int *left, 835666e7358SBoris Brezillon unsigned int *top, unsigned int *bottom); 836c8b75bcaSEric Anholt 837c8b75bcaSEric Anholt /* vc4_debugfs.c */ 8387ce84471SWambui Karuga void vc4_debugfs_init(struct drm_minor *minor); 839c9be804cSEric Anholt #ifdef CONFIG_DEBUG_FS 840c9be804cSEric Anholt void vc4_debugfs_add_file(struct drm_device *drm, 841c9be804cSEric Anholt const char *filename, 842c9be804cSEric Anholt int (*show)(struct seq_file*, void*), 843c9be804cSEric Anholt void *data); 844c9be804cSEric Anholt void vc4_debugfs_add_regset32(struct drm_device *drm, 845c9be804cSEric Anholt const char *filename, 846c9be804cSEric Anholt struct debugfs_regset32 *regset); 847c9be804cSEric Anholt #else 848c9be804cSEric Anholt static inline void vc4_debugfs_add_file(struct drm_device *drm, 849c9be804cSEric Anholt const char *filename, 850c9be804cSEric Anholt int (*show)(struct seq_file*, void*), 851c9be804cSEric Anholt void *data) 852c9be804cSEric Anholt { 853c9be804cSEric Anholt } 854c9be804cSEric Anholt 855c9be804cSEric Anholt static inline void vc4_debugfs_add_regset32(struct drm_device *drm, 856c9be804cSEric Anholt const char *filename, 857c9be804cSEric Anholt struct debugfs_regset32 *regset) 858c9be804cSEric Anholt { 859c9be804cSEric Anholt } 860c9be804cSEric Anholt #endif 861c8b75bcaSEric Anholt 862c8b75bcaSEric Anholt /* vc4_drv.c */ 863c8b75bcaSEric Anholt void __iomem *vc4_ioremap_regs(struct platform_device *dev, int index); 864c8b75bcaSEric Anholt 86508302c35SEric Anholt /* vc4_dpi.c */ 86608302c35SEric Anholt extern struct platform_driver vc4_dpi_driver; 86708302c35SEric Anholt 8684078f575SEric Anholt /* vc4_dsi.c */ 8694078f575SEric Anholt extern struct platform_driver vc4_dsi_driver; 8704078f575SEric Anholt 871cdec4d36SEric Anholt /* vc4_fence.c */ 872cdec4d36SEric Anholt extern const struct dma_fence_ops vc4_fence_ops; 873cdec4d36SEric Anholt 874d5b1a78aSEric Anholt /* vc4_gem.c */ 875d5b1a78aSEric Anholt void vc4_gem_init(struct drm_device *dev); 876d5b1a78aSEric Anholt void vc4_gem_destroy(struct drm_device *dev); 877d5b1a78aSEric Anholt int vc4_submit_cl_ioctl(struct drm_device *dev, void *data, 878d5b1a78aSEric Anholt struct drm_file *file_priv); 879d5b1a78aSEric Anholt int vc4_wait_seqno_ioctl(struct drm_device *dev, void *data, 880d5b1a78aSEric Anholt struct drm_file *file_priv); 881d5b1a78aSEric Anholt int vc4_wait_bo_ioctl(struct drm_device *dev, void *data, 882d5b1a78aSEric Anholt struct drm_file *file_priv); 883ca26d28bSVarad Gautam void vc4_submit_next_bin_job(struct drm_device *dev); 884ca26d28bSVarad Gautam void vc4_submit_next_render_job(struct drm_device *dev); 885ca26d28bSVarad Gautam void vc4_move_job_to_render(struct drm_device *dev, struct vc4_exec_info *exec); 886d5b1a78aSEric Anholt int vc4_wait_for_seqno(struct drm_device *dev, uint64_t seqno, 887d5b1a78aSEric Anholt uint64_t timeout_ns, bool interruptible); 888d5b1a78aSEric Anholt void vc4_job_handle_completed(struct vc4_dev *vc4); 889b501baccSEric Anholt int vc4_queue_seqno_cb(struct drm_device *dev, 890b501baccSEric Anholt struct vc4_seqno_cb *cb, uint64_t seqno, 891b501baccSEric Anholt void (*func)(struct vc4_seqno_cb *cb)); 892b9f19259SBoris Brezillon int vc4_gem_madvise_ioctl(struct drm_device *dev, void *data, 893b9f19259SBoris Brezillon struct drm_file *file_priv); 894d5b1a78aSEric Anholt 895c8b75bcaSEric Anholt /* vc4_hdmi.c */ 896c8b75bcaSEric Anholt extern struct platform_driver vc4_hdmi_driver; 897c8b75bcaSEric Anholt 8989a8d5e4aSBoris Brezillon /* vc4_vec.c */ 899e4b81f8cSBoris Brezillon extern struct platform_driver vc4_vec_driver; 900e4b81f8cSBoris Brezillon 901008095e0SBoris Brezillon /* vc4_txp.c */ 902008095e0SBoris Brezillon extern struct platform_driver vc4_txp_driver; 903008095e0SBoris Brezillon 904d5b1a78aSEric Anholt /* vc4_irq.c */ 905d5b1a78aSEric Anholt irqreturn_t vc4_irq(int irq, void *arg); 906d5b1a78aSEric Anholt void vc4_irq_preinstall(struct drm_device *dev); 907d5b1a78aSEric Anholt int vc4_irq_postinstall(struct drm_device *dev); 908d5b1a78aSEric Anholt void vc4_irq_uninstall(struct drm_device *dev); 909d5b1a78aSEric Anholt void vc4_irq_reset(struct drm_device *dev); 910d5b1a78aSEric Anholt 911c8b75bcaSEric Anholt /* vc4_hvs.c */ 912c8b75bcaSEric Anholt extern struct platform_driver vc4_hvs_driver; 91350e9d6cbSMaxime Ripard void vc4_hvs_stop_channel(struct drm_device *dev, unsigned int output); 91429bbb930SMaxime Ripard int vc4_hvs_get_fifo_from_output(struct drm_device *dev, unsigned int output); 9158175287bSMaxime Ripard int vc4_hvs_atomic_check(struct drm_crtc *crtc, struct drm_crtc_state *state); 9168175287bSMaxime Ripard void vc4_hvs_atomic_enable(struct drm_crtc *crtc, struct drm_crtc_state *old_state); 9178175287bSMaxime Ripard void vc4_hvs_atomic_disable(struct drm_crtc *crtc, struct drm_crtc_state *old_state); 9188175287bSMaxime Ripard void vc4_hvs_atomic_flush(struct drm_crtc *crtc, struct drm_crtc_state *state); 919c8b75bcaSEric Anholt void vc4_hvs_dump_state(struct drm_device *dev); 920531a1b62SBoris Brezillon void vc4_hvs_unmask_underrun(struct drm_device *dev, int channel); 921531a1b62SBoris Brezillon void vc4_hvs_mask_underrun(struct drm_device *dev, int channel); 922c8b75bcaSEric Anholt 923c8b75bcaSEric Anholt /* vc4_kms.c */ 924c8b75bcaSEric Anholt int vc4_kms_load(struct drm_device *dev); 925c8b75bcaSEric Anholt 926c8b75bcaSEric Anholt /* vc4_plane.c */ 927c8b75bcaSEric Anholt struct drm_plane *vc4_plane_init(struct drm_device *dev, 928c8b75bcaSEric Anholt enum drm_plane_type type); 9290c2a50f1SMaxime Ripard int vc4_plane_create_additional_planes(struct drm_device *dev); 930c8b75bcaSEric Anholt u32 vc4_plane_write_dlist(struct drm_plane *plane, u32 __iomem *dlist); 9312f196b7cSDaniel Vetter u32 vc4_plane_dlist_size(const struct drm_plane_state *state); 932b501baccSEric Anholt void vc4_plane_async_set_fb(struct drm_plane *plane, 933b501baccSEric Anholt struct drm_framebuffer *fb); 934463873d5SEric Anholt 935d3f5168aSEric Anholt /* vc4_v3d.c */ 936d3f5168aSEric Anholt extern struct platform_driver vc4_v3d_driver; 937ffc26740SEric Anholt extern const struct of_device_id vc4_v3d_dt_match[]; 938553c942fSEric Anholt int vc4_v3d_get_bin_slot(struct vc4_dev *vc4); 93935c8b4b2SPaul Kocialkowski int vc4_v3d_bin_bo_get(struct vc4_dev *vc4, bool *used); 94035c8b4b2SPaul Kocialkowski void vc4_v3d_bin_bo_put(struct vc4_dev *vc4); 941cb74f6eeSEric Anholt int vc4_v3d_pm_get(struct vc4_dev *vc4); 942cb74f6eeSEric Anholt void vc4_v3d_pm_put(struct vc4_dev *vc4); 943d5b1a78aSEric Anholt 944d5b1a78aSEric Anholt /* vc4_validate.c */ 945d5b1a78aSEric Anholt int 946d5b1a78aSEric Anholt vc4_validate_bin_cl(struct drm_device *dev, 947d5b1a78aSEric Anholt void *validated, 948d5b1a78aSEric Anholt void *unvalidated, 949d5b1a78aSEric Anholt struct vc4_exec_info *exec); 950d5b1a78aSEric Anholt 951d5b1a78aSEric Anholt int 952d5b1a78aSEric Anholt vc4_validate_shader_recs(struct drm_device *dev, struct vc4_exec_info *exec); 953d5b1a78aSEric Anholt 954d5b1a78aSEric Anholt struct drm_gem_cma_object *vc4_use_bo(struct vc4_exec_info *exec, 955d5b1a78aSEric Anholt uint32_t hindex); 956d5b1a78aSEric Anholt 957d5b1a78aSEric Anholt int vc4_get_rcl(struct drm_device *dev, struct vc4_exec_info *exec); 958d5b1a78aSEric Anholt 959d5b1a78aSEric Anholt bool vc4_check_tex_size(struct vc4_exec_info *exec, 960d5b1a78aSEric Anholt struct drm_gem_cma_object *fbo, 961d5b1a78aSEric Anholt uint32_t offset, uint8_t tiling_format, 962d5b1a78aSEric Anholt uint32_t width, uint32_t height, uint8_t cpp); 963d3f5168aSEric Anholt 964463873d5SEric Anholt /* vc4_validate_shader.c */ 965463873d5SEric Anholt struct vc4_validated_shader_info * 966463873d5SEric Anholt vc4_validate_shader(struct drm_gem_cma_object *shader_obj); 96765101d8cSBoris Brezillon 96865101d8cSBoris Brezillon /* vc4_perfmon.c */ 96965101d8cSBoris Brezillon void vc4_perfmon_get(struct vc4_perfmon *perfmon); 97065101d8cSBoris Brezillon void vc4_perfmon_put(struct vc4_perfmon *perfmon); 97165101d8cSBoris Brezillon void vc4_perfmon_start(struct vc4_dev *vc4, struct vc4_perfmon *perfmon); 97265101d8cSBoris Brezillon void vc4_perfmon_stop(struct vc4_dev *vc4, struct vc4_perfmon *perfmon, 97365101d8cSBoris Brezillon bool capture); 97465101d8cSBoris Brezillon struct vc4_perfmon *vc4_perfmon_find(struct vc4_file *vc4file, int id); 97565101d8cSBoris Brezillon void vc4_perfmon_open_file(struct vc4_file *vc4file); 97665101d8cSBoris Brezillon void vc4_perfmon_close_file(struct vc4_file *vc4file); 97765101d8cSBoris Brezillon int vc4_perfmon_create_ioctl(struct drm_device *dev, void *data, 97865101d8cSBoris Brezillon struct drm_file *file_priv); 97965101d8cSBoris Brezillon int vc4_perfmon_destroy_ioctl(struct drm_device *dev, void *data, 98065101d8cSBoris Brezillon struct drm_file *file_priv); 98165101d8cSBoris Brezillon int vc4_perfmon_get_values_ioctl(struct drm_device *dev, void *data, 98265101d8cSBoris Brezillon struct drm_file *file_priv); 9836a88752cSMaxime Ripard 9846a88752cSMaxime Ripard #endif /* _VC4_DRV_H_ */ 985