1c8b75bcaSEric Anholt /* 2c8b75bcaSEric Anholt * Copyright (C) 2015 Broadcom 3c8b75bcaSEric Anholt * 4c8b75bcaSEric Anholt * This program is free software; you can redistribute it and/or modify 5c8b75bcaSEric Anholt * it under the terms of the GNU General Public License version 2 as 6c8b75bcaSEric Anholt * published by the Free Software Foundation. 7c8b75bcaSEric Anholt */ 8c8b75bcaSEric Anholt 9c8b75bcaSEric Anholt #include "drmP.h" 10c8b75bcaSEric Anholt #include "drm_gem_cma_helper.h" 11c8b75bcaSEric Anholt 12c8b75bcaSEric Anholt struct vc4_dev { 13c8b75bcaSEric Anholt struct drm_device *dev; 14c8b75bcaSEric Anholt 15c8b75bcaSEric Anholt struct vc4_hdmi *hdmi; 16c8b75bcaSEric Anholt struct vc4_hvs *hvs; 17c8b75bcaSEric Anholt struct vc4_crtc *crtc[3]; 18d3f5168aSEric Anholt struct vc4_v3d *v3d; 1948666d56SDerek Foreman 2048666d56SDerek Foreman struct drm_fbdev_cma *fbdev; 21c826a6e1SEric Anholt 22c826a6e1SEric Anholt /* The kernel-space BO cache. Tracks buffers that have been 23c826a6e1SEric Anholt * unreferenced by all other users (refcounts of 0!) but not 24c826a6e1SEric Anholt * yet freed, so we can do cheap allocations. 25c826a6e1SEric Anholt */ 26c826a6e1SEric Anholt struct vc4_bo_cache { 27c826a6e1SEric Anholt /* Array of list heads for entries in the BO cache, 28c826a6e1SEric Anholt * based on number of pages, so we can do O(1) lookups 29c826a6e1SEric Anholt * in the cache when allocating. 30c826a6e1SEric Anholt */ 31c826a6e1SEric Anholt struct list_head *size_list; 32c826a6e1SEric Anholt uint32_t size_list_size; 33c826a6e1SEric Anholt 34c826a6e1SEric Anholt /* List of all BOs in the cache, ordered by age, so we 35c826a6e1SEric Anholt * can do O(1) lookups when trying to free old 36c826a6e1SEric Anholt * buffers. 37c826a6e1SEric Anholt */ 38c826a6e1SEric Anholt struct list_head time_list; 39c826a6e1SEric Anholt struct work_struct time_work; 40c826a6e1SEric Anholt struct timer_list time_timer; 41c826a6e1SEric Anholt } bo_cache; 42c826a6e1SEric Anholt 43c826a6e1SEric Anholt struct vc4_bo_stats { 44c826a6e1SEric Anholt u32 num_allocated; 45c826a6e1SEric Anholt u32 size_allocated; 46c826a6e1SEric Anholt u32 num_cached; 47c826a6e1SEric Anholt u32 size_cached; 48c826a6e1SEric Anholt } bo_stats; 49c826a6e1SEric Anholt 50c826a6e1SEric Anholt /* Protects bo_cache and the BO stats. */ 51c826a6e1SEric Anholt struct mutex bo_lock; 52d5b1a78aSEric Anholt 53d5b1a78aSEric Anholt /* Sequence number for the last job queued in job_list. 54d5b1a78aSEric Anholt * Starts at 0 (no jobs emitted). 55d5b1a78aSEric Anholt */ 56d5b1a78aSEric Anholt uint64_t emit_seqno; 57d5b1a78aSEric Anholt 58d5b1a78aSEric Anholt /* Sequence number for the last completed job on the GPU. 59d5b1a78aSEric Anholt * Starts at 0 (no jobs completed). 60d5b1a78aSEric Anholt */ 61d5b1a78aSEric Anholt uint64_t finished_seqno; 62d5b1a78aSEric Anholt 63d5b1a78aSEric Anholt /* List of all struct vc4_exec_info for jobs to be executed. 64d5b1a78aSEric Anholt * The first job in the list is the one currently programmed 65d5b1a78aSEric Anholt * into ct0ca/ct1ca for execution. 66d5b1a78aSEric Anholt */ 67d5b1a78aSEric Anholt struct list_head job_list; 68d5b1a78aSEric Anholt /* List of the finished vc4_exec_infos waiting to be freed by 69d5b1a78aSEric Anholt * job_done_work. 70d5b1a78aSEric Anholt */ 71d5b1a78aSEric Anholt struct list_head job_done_list; 72d5b1a78aSEric Anholt /* Spinlock used to synchronize the job_list and seqno 73d5b1a78aSEric Anholt * accesses between the IRQ handler and GEM ioctls. 74d5b1a78aSEric Anholt */ 75d5b1a78aSEric Anholt spinlock_t job_lock; 76d5b1a78aSEric Anholt wait_queue_head_t job_wait_queue; 77d5b1a78aSEric Anholt struct work_struct job_done_work; 78d5b1a78aSEric Anholt 79d5b1a78aSEric Anholt /* The binner overflow memory that's currently set up in 80d5b1a78aSEric Anholt * BPOA/BPOS registers. When overflow occurs and a new one is 81d5b1a78aSEric Anholt * allocated, the previous one will be moved to 82d5b1a78aSEric Anholt * vc4->current_exec's free list. 83d5b1a78aSEric Anholt */ 84d5b1a78aSEric Anholt struct vc4_bo *overflow_mem; 85d5b1a78aSEric Anholt struct work_struct overflow_mem_work; 86d5b1a78aSEric Anholt 87d5b1a78aSEric Anholt struct { 88d5b1a78aSEric Anholt uint32_t last_ct0ca, last_ct1ca; 89d5b1a78aSEric Anholt struct timer_list timer; 90d5b1a78aSEric Anholt struct work_struct reset_work; 91d5b1a78aSEric Anholt } hangcheck; 92d5b1a78aSEric Anholt 93d5b1a78aSEric Anholt struct semaphore async_modeset; 94c8b75bcaSEric Anholt }; 95c8b75bcaSEric Anholt 96c8b75bcaSEric Anholt static inline struct vc4_dev * 97c8b75bcaSEric Anholt to_vc4_dev(struct drm_device *dev) 98c8b75bcaSEric Anholt { 99c8b75bcaSEric Anholt return (struct vc4_dev *)dev->dev_private; 100c8b75bcaSEric Anholt } 101c8b75bcaSEric Anholt 102c8b75bcaSEric Anholt struct vc4_bo { 103c8b75bcaSEric Anholt struct drm_gem_cma_object base; 104c826a6e1SEric Anholt 105d5b1a78aSEric Anholt /* seqno of the last job to render to this BO. */ 106d5b1a78aSEric Anholt uint64_t seqno; 107d5b1a78aSEric Anholt 108c826a6e1SEric Anholt /* List entry for the BO's position in either 109c826a6e1SEric Anholt * vc4_exec_info->unref_list or vc4_dev->bo_cache.time_list 110c826a6e1SEric Anholt */ 111c826a6e1SEric Anholt struct list_head unref_head; 112c826a6e1SEric Anholt 113c826a6e1SEric Anholt /* Time in jiffies when the BO was put in vc4->bo_cache. */ 114c826a6e1SEric Anholt unsigned long free_time; 115c826a6e1SEric Anholt 116c826a6e1SEric Anholt /* List entry for the BO's position in vc4_dev->bo_cache.size_list */ 117c826a6e1SEric Anholt struct list_head size_head; 118463873d5SEric Anholt 119463873d5SEric Anholt /* Struct for shader validation state, if created by 120463873d5SEric Anholt * DRM_IOCTL_VC4_CREATE_SHADER_BO. 121463873d5SEric Anholt */ 122463873d5SEric Anholt struct vc4_validated_shader_info *validated_shader; 123c8b75bcaSEric Anholt }; 124c8b75bcaSEric Anholt 125c8b75bcaSEric Anholt static inline struct vc4_bo * 126c8b75bcaSEric Anholt to_vc4_bo(struct drm_gem_object *bo) 127c8b75bcaSEric Anholt { 128c8b75bcaSEric Anholt return (struct vc4_bo *)bo; 129c8b75bcaSEric Anholt } 130c8b75bcaSEric Anholt 131d3f5168aSEric Anholt struct vc4_v3d { 132d3f5168aSEric Anholt struct platform_device *pdev; 133d3f5168aSEric Anholt void __iomem *regs; 134d3f5168aSEric Anholt }; 135d3f5168aSEric Anholt 136c8b75bcaSEric Anholt struct vc4_hvs { 137c8b75bcaSEric Anholt struct platform_device *pdev; 138c8b75bcaSEric Anholt void __iomem *regs; 139c8b75bcaSEric Anholt void __iomem *dlist; 140c8b75bcaSEric Anholt }; 141c8b75bcaSEric Anholt 142c8b75bcaSEric Anholt struct vc4_plane { 143c8b75bcaSEric Anholt struct drm_plane base; 144c8b75bcaSEric Anholt }; 145c8b75bcaSEric Anholt 146c8b75bcaSEric Anholt static inline struct vc4_plane * 147c8b75bcaSEric Anholt to_vc4_plane(struct drm_plane *plane) 148c8b75bcaSEric Anholt { 149c8b75bcaSEric Anholt return (struct vc4_plane *)plane; 150c8b75bcaSEric Anholt } 151c8b75bcaSEric Anholt 152c8b75bcaSEric Anholt enum vc4_encoder_type { 153c8b75bcaSEric Anholt VC4_ENCODER_TYPE_HDMI, 154c8b75bcaSEric Anholt VC4_ENCODER_TYPE_VEC, 155c8b75bcaSEric Anholt VC4_ENCODER_TYPE_DSI0, 156c8b75bcaSEric Anholt VC4_ENCODER_TYPE_DSI1, 157c8b75bcaSEric Anholt VC4_ENCODER_TYPE_SMI, 158c8b75bcaSEric Anholt VC4_ENCODER_TYPE_DPI, 159c8b75bcaSEric Anholt }; 160c8b75bcaSEric Anholt 161c8b75bcaSEric Anholt struct vc4_encoder { 162c8b75bcaSEric Anholt struct drm_encoder base; 163c8b75bcaSEric Anholt enum vc4_encoder_type type; 164c8b75bcaSEric Anholt u32 clock_select; 165c8b75bcaSEric Anholt }; 166c8b75bcaSEric Anholt 167c8b75bcaSEric Anholt static inline struct vc4_encoder * 168c8b75bcaSEric Anholt to_vc4_encoder(struct drm_encoder *encoder) 169c8b75bcaSEric Anholt { 170c8b75bcaSEric Anholt return container_of(encoder, struct vc4_encoder, base); 171c8b75bcaSEric Anholt } 172c8b75bcaSEric Anholt 173d3f5168aSEric Anholt #define V3D_READ(offset) readl(vc4->v3d->regs + offset) 174d3f5168aSEric Anholt #define V3D_WRITE(offset, val) writel(val, vc4->v3d->regs + offset) 175c8b75bcaSEric Anholt #define HVS_READ(offset) readl(vc4->hvs->regs + offset) 176c8b75bcaSEric Anholt #define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset) 177c8b75bcaSEric Anholt 178d5b1a78aSEric Anholt struct vc4_exec_info { 179d5b1a78aSEric Anholt /* Sequence number for this bin/render job. */ 180d5b1a78aSEric Anholt uint64_t seqno; 181d5b1a78aSEric Anholt 182d5b1a78aSEric Anholt /* Kernel-space copy of the ioctl arguments */ 183d5b1a78aSEric Anholt struct drm_vc4_submit_cl *args; 184d5b1a78aSEric Anholt 185d5b1a78aSEric Anholt /* This is the array of BOs that were looked up at the start of exec. 186d5b1a78aSEric Anholt * Command validation will use indices into this array. 187d5b1a78aSEric Anholt */ 188d5b1a78aSEric Anholt struct drm_gem_cma_object **bo; 189d5b1a78aSEric Anholt uint32_t bo_count; 190d5b1a78aSEric Anholt 191d5b1a78aSEric Anholt /* Pointers for our position in vc4->job_list */ 192d5b1a78aSEric Anholt struct list_head head; 193d5b1a78aSEric Anholt 194d5b1a78aSEric Anholt /* List of other BOs used in the job that need to be released 195d5b1a78aSEric Anholt * once the job is complete. 196d5b1a78aSEric Anholt */ 197d5b1a78aSEric Anholt struct list_head unref_list; 198d5b1a78aSEric Anholt 199d5b1a78aSEric Anholt /* Current unvalidated indices into @bo loaded by the non-hardware 200d5b1a78aSEric Anholt * VC4_PACKET_GEM_HANDLES. 201d5b1a78aSEric Anholt */ 202d5b1a78aSEric Anholt uint32_t bo_index[2]; 203d5b1a78aSEric Anholt 204d5b1a78aSEric Anholt /* This is the BO where we store the validated command lists, shader 205d5b1a78aSEric Anholt * records, and uniforms. 206d5b1a78aSEric Anholt */ 207d5b1a78aSEric Anholt struct drm_gem_cma_object *exec_bo; 208d5b1a78aSEric Anholt 209d5b1a78aSEric Anholt /** 210d5b1a78aSEric Anholt * This tracks the per-shader-record state (packet 64) that 211d5b1a78aSEric Anholt * determines the length of the shader record and the offset 212d5b1a78aSEric Anholt * it's expected to be found at. It gets read in from the 213d5b1a78aSEric Anholt * command lists. 214d5b1a78aSEric Anholt */ 215d5b1a78aSEric Anholt struct vc4_shader_state { 216d5b1a78aSEric Anholt uint32_t addr; 217d5b1a78aSEric Anholt /* Maximum vertex index referenced by any primitive using this 218d5b1a78aSEric Anholt * shader state. 219d5b1a78aSEric Anholt */ 220d5b1a78aSEric Anholt uint32_t max_index; 221d5b1a78aSEric Anholt } *shader_state; 222d5b1a78aSEric Anholt 223d5b1a78aSEric Anholt /** How many shader states the user declared they were using. */ 224d5b1a78aSEric Anholt uint32_t shader_state_size; 225d5b1a78aSEric Anholt /** How many shader state records the validator has seen. */ 226d5b1a78aSEric Anholt uint32_t shader_state_count; 227d5b1a78aSEric Anholt 228d5b1a78aSEric Anholt bool found_tile_binning_mode_config_packet; 229d5b1a78aSEric Anholt bool found_start_tile_binning_packet; 230d5b1a78aSEric Anholt bool found_increment_semaphore_packet; 231d5b1a78aSEric Anholt bool found_flush; 232d5b1a78aSEric Anholt uint8_t bin_tiles_x, bin_tiles_y; 233d5b1a78aSEric Anholt struct drm_gem_cma_object *tile_bo; 234d5b1a78aSEric Anholt uint32_t tile_alloc_offset; 235d5b1a78aSEric Anholt 236d5b1a78aSEric Anholt /** 237d5b1a78aSEric Anholt * Computed addresses pointing into exec_bo where we start the 238d5b1a78aSEric Anholt * bin thread (ct0) and render thread (ct1). 239d5b1a78aSEric Anholt */ 240d5b1a78aSEric Anholt uint32_t ct0ca, ct0ea; 241d5b1a78aSEric Anholt uint32_t ct1ca, ct1ea; 242d5b1a78aSEric Anholt 243d5b1a78aSEric Anholt /* Pointer to the unvalidated bin CL (if present). */ 244d5b1a78aSEric Anholt void *bin_u; 245d5b1a78aSEric Anholt 246d5b1a78aSEric Anholt /* Pointers to the shader recs. These paddr gets incremented as CL 247d5b1a78aSEric Anholt * packets are relocated in validate_gl_shader_state, and the vaddrs 248d5b1a78aSEric Anholt * (u and v) get incremented and size decremented as the shader recs 249d5b1a78aSEric Anholt * themselves are validated. 250d5b1a78aSEric Anholt */ 251d5b1a78aSEric Anholt void *shader_rec_u; 252d5b1a78aSEric Anholt void *shader_rec_v; 253d5b1a78aSEric Anholt uint32_t shader_rec_p; 254d5b1a78aSEric Anholt uint32_t shader_rec_size; 255d5b1a78aSEric Anholt 256d5b1a78aSEric Anholt /* Pointers to the uniform data. These pointers are incremented, and 257d5b1a78aSEric Anholt * size decremented, as each batch of uniforms is uploaded. 258d5b1a78aSEric Anholt */ 259d5b1a78aSEric Anholt void *uniforms_u; 260d5b1a78aSEric Anholt void *uniforms_v; 261d5b1a78aSEric Anholt uint32_t uniforms_p; 262d5b1a78aSEric Anholt uint32_t uniforms_size; 263d5b1a78aSEric Anholt }; 264d5b1a78aSEric Anholt 265d5b1a78aSEric Anholt static inline struct vc4_exec_info * 266d5b1a78aSEric Anholt vc4_first_job(struct vc4_dev *vc4) 267d5b1a78aSEric Anholt { 268d5b1a78aSEric Anholt if (list_empty(&vc4->job_list)) 269d5b1a78aSEric Anholt return NULL; 270d5b1a78aSEric Anholt return list_first_entry(&vc4->job_list, struct vc4_exec_info, head); 271d5b1a78aSEric Anholt } 272d5b1a78aSEric Anholt 273c8b75bcaSEric Anholt /** 274463873d5SEric Anholt * struct vc4_texture_sample_info - saves the offsets into the UBO for texture 275463873d5SEric Anholt * setup parameters. 276463873d5SEric Anholt * 277463873d5SEric Anholt * This will be used at draw time to relocate the reference to the texture 278463873d5SEric Anholt * contents in p0, and validate that the offset combined with 279463873d5SEric Anholt * width/height/stride/etc. from p1 and p2/p3 doesn't sample outside the BO. 280463873d5SEric Anholt * Note that the hardware treats unprovided config parameters as 0, so not all 281463873d5SEric Anholt * of them need to be set up for every texure sample, and we'll store ~0 as 282463873d5SEric Anholt * the offset to mark the unused ones. 283463873d5SEric Anholt * 284463873d5SEric Anholt * See the VC4 3D architecture guide page 41 ("Texture and Memory Lookup Unit 285463873d5SEric Anholt * Setup") for definitions of the texture parameters. 286463873d5SEric Anholt */ 287463873d5SEric Anholt struct vc4_texture_sample_info { 288463873d5SEric Anholt bool is_direct; 289463873d5SEric Anholt uint32_t p_offset[4]; 290463873d5SEric Anholt }; 291463873d5SEric Anholt 292463873d5SEric Anholt /** 293463873d5SEric Anholt * struct vc4_validated_shader_info - information about validated shaders that 294463873d5SEric Anholt * needs to be used from command list validation. 295463873d5SEric Anholt * 296463873d5SEric Anholt * For a given shader, each time a shader state record references it, we need 297463873d5SEric Anholt * to verify that the shader doesn't read more uniforms than the shader state 298463873d5SEric Anholt * record's uniform BO pointer can provide, and we need to apply relocations 299463873d5SEric Anholt * and validate the shader state record's uniforms that define the texture 300463873d5SEric Anholt * samples. 301463873d5SEric Anholt */ 302463873d5SEric Anholt struct vc4_validated_shader_info { 303463873d5SEric Anholt uint32_t uniforms_size; 304463873d5SEric Anholt uint32_t uniforms_src_size; 305463873d5SEric Anholt uint32_t num_texture_samples; 306463873d5SEric Anholt struct vc4_texture_sample_info *texture_samples; 307463873d5SEric Anholt }; 308463873d5SEric Anholt 309463873d5SEric Anholt /** 310c8b75bcaSEric Anholt * _wait_for - magic (register) wait macro 311c8b75bcaSEric Anholt * 312c8b75bcaSEric Anholt * Does the right thing for modeset paths when run under kdgb or similar atomic 313c8b75bcaSEric Anholt * contexts. Note that it's important that we check the condition again after 314c8b75bcaSEric Anholt * having timed out, since the timeout could be due to preemption or similar and 315c8b75bcaSEric Anholt * we've never had a chance to check the condition before the timeout. 316c8b75bcaSEric Anholt */ 317c8b75bcaSEric Anholt #define _wait_for(COND, MS, W) ({ \ 318c8b75bcaSEric Anholt unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \ 319c8b75bcaSEric Anholt int ret__ = 0; \ 320c8b75bcaSEric Anholt while (!(COND)) { \ 321c8b75bcaSEric Anholt if (time_after(jiffies, timeout__)) { \ 322c8b75bcaSEric Anholt if (!(COND)) \ 323c8b75bcaSEric Anholt ret__ = -ETIMEDOUT; \ 324c8b75bcaSEric Anholt break; \ 325c8b75bcaSEric Anholt } \ 326c8b75bcaSEric Anholt if (W && drm_can_sleep()) { \ 327c8b75bcaSEric Anholt msleep(W); \ 328c8b75bcaSEric Anholt } else { \ 329c8b75bcaSEric Anholt cpu_relax(); \ 330c8b75bcaSEric Anholt } \ 331c8b75bcaSEric Anholt } \ 332c8b75bcaSEric Anholt ret__; \ 333c8b75bcaSEric Anholt }) 334c8b75bcaSEric Anholt 335c8b75bcaSEric Anholt #define wait_for(COND, MS) _wait_for(COND, MS, 1) 336c8b75bcaSEric Anholt 337c8b75bcaSEric Anholt /* vc4_bo.c */ 338c826a6e1SEric Anholt struct drm_gem_object *vc4_create_object(struct drm_device *dev, size_t size); 339c8b75bcaSEric Anholt void vc4_free_object(struct drm_gem_object *gem_obj); 340c826a6e1SEric Anholt struct vc4_bo *vc4_bo_create(struct drm_device *dev, size_t size, 341c826a6e1SEric Anholt bool from_cache); 342c8b75bcaSEric Anholt int vc4_dumb_create(struct drm_file *file_priv, 343c8b75bcaSEric Anholt struct drm_device *dev, 344c8b75bcaSEric Anholt struct drm_mode_create_dumb *args); 345c8b75bcaSEric Anholt struct dma_buf *vc4_prime_export(struct drm_device *dev, 346c8b75bcaSEric Anholt struct drm_gem_object *obj, int flags); 347d5bc60f6SEric Anholt int vc4_create_bo_ioctl(struct drm_device *dev, void *data, 348d5bc60f6SEric Anholt struct drm_file *file_priv); 349463873d5SEric Anholt int vc4_create_shader_bo_ioctl(struct drm_device *dev, void *data, 350463873d5SEric Anholt struct drm_file *file_priv); 351d5bc60f6SEric Anholt int vc4_mmap_bo_ioctl(struct drm_device *dev, void *data, 352d5bc60f6SEric Anholt struct drm_file *file_priv); 353463873d5SEric Anholt int vc4_mmap(struct file *filp, struct vm_area_struct *vma); 354463873d5SEric Anholt int vc4_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma); 355463873d5SEric Anholt void *vc4_prime_vmap(struct drm_gem_object *obj); 356c826a6e1SEric Anholt void vc4_bo_cache_init(struct drm_device *dev); 357c826a6e1SEric Anholt void vc4_bo_cache_destroy(struct drm_device *dev); 358c826a6e1SEric Anholt int vc4_bo_stats_debugfs(struct seq_file *m, void *arg); 359c8b75bcaSEric Anholt 360c8b75bcaSEric Anholt /* vc4_crtc.c */ 361c8b75bcaSEric Anholt extern struct platform_driver vc4_crtc_driver; 3621f43710aSDave Airlie int vc4_enable_vblank(struct drm_device *dev, unsigned int crtc_id); 3631f43710aSDave Airlie void vc4_disable_vblank(struct drm_device *dev, unsigned int crtc_id); 364c8b75bcaSEric Anholt void vc4_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file); 365c8b75bcaSEric Anholt int vc4_crtc_debugfs_regs(struct seq_file *m, void *arg); 366c8b75bcaSEric Anholt 367c8b75bcaSEric Anholt /* vc4_debugfs.c */ 368c8b75bcaSEric Anholt int vc4_debugfs_init(struct drm_minor *minor); 369c8b75bcaSEric Anholt void vc4_debugfs_cleanup(struct drm_minor *minor); 370c8b75bcaSEric Anholt 371c8b75bcaSEric Anholt /* vc4_drv.c */ 372c8b75bcaSEric Anholt void __iomem *vc4_ioremap_regs(struct platform_device *dev, int index); 373c8b75bcaSEric Anholt 374d5b1a78aSEric Anholt /* vc4_gem.c */ 375d5b1a78aSEric Anholt void vc4_gem_init(struct drm_device *dev); 376d5b1a78aSEric Anholt void vc4_gem_destroy(struct drm_device *dev); 377d5b1a78aSEric Anholt int vc4_submit_cl_ioctl(struct drm_device *dev, void *data, 378d5b1a78aSEric Anholt struct drm_file *file_priv); 379d5b1a78aSEric Anholt int vc4_wait_seqno_ioctl(struct drm_device *dev, void *data, 380d5b1a78aSEric Anholt struct drm_file *file_priv); 381d5b1a78aSEric Anholt int vc4_wait_bo_ioctl(struct drm_device *dev, void *data, 382d5b1a78aSEric Anholt struct drm_file *file_priv); 383d5b1a78aSEric Anholt void vc4_submit_next_job(struct drm_device *dev); 384d5b1a78aSEric Anholt int vc4_wait_for_seqno(struct drm_device *dev, uint64_t seqno, 385d5b1a78aSEric Anholt uint64_t timeout_ns, bool interruptible); 386d5b1a78aSEric Anholt void vc4_job_handle_completed(struct vc4_dev *vc4); 387d5b1a78aSEric Anholt 388c8b75bcaSEric Anholt /* vc4_hdmi.c */ 389c8b75bcaSEric Anholt extern struct platform_driver vc4_hdmi_driver; 390c8b75bcaSEric Anholt int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused); 391c8b75bcaSEric Anholt 392d5b1a78aSEric Anholt /* vc4_irq.c */ 393d5b1a78aSEric Anholt irqreturn_t vc4_irq(int irq, void *arg); 394d5b1a78aSEric Anholt void vc4_irq_preinstall(struct drm_device *dev); 395d5b1a78aSEric Anholt int vc4_irq_postinstall(struct drm_device *dev); 396d5b1a78aSEric Anholt void vc4_irq_uninstall(struct drm_device *dev); 397d5b1a78aSEric Anholt void vc4_irq_reset(struct drm_device *dev); 398d5b1a78aSEric Anholt 399c8b75bcaSEric Anholt /* vc4_hvs.c */ 400c8b75bcaSEric Anholt extern struct platform_driver vc4_hvs_driver; 401c8b75bcaSEric Anholt void vc4_hvs_dump_state(struct drm_device *dev); 402c8b75bcaSEric Anholt int vc4_hvs_debugfs_regs(struct seq_file *m, void *unused); 403c8b75bcaSEric Anholt 404c8b75bcaSEric Anholt /* vc4_kms.c */ 405c8b75bcaSEric Anholt int vc4_kms_load(struct drm_device *dev); 406c8b75bcaSEric Anholt 407c8b75bcaSEric Anholt /* vc4_plane.c */ 408c8b75bcaSEric Anholt struct drm_plane *vc4_plane_init(struct drm_device *dev, 409c8b75bcaSEric Anholt enum drm_plane_type type); 410c8b75bcaSEric Anholt u32 vc4_plane_write_dlist(struct drm_plane *plane, u32 __iomem *dlist); 411c8b75bcaSEric Anholt u32 vc4_plane_dlist_size(struct drm_plane_state *state); 412463873d5SEric Anholt 413d3f5168aSEric Anholt /* vc4_v3d.c */ 414d3f5168aSEric Anholt extern struct platform_driver vc4_v3d_driver; 415d3f5168aSEric Anholt int vc4_v3d_debugfs_ident(struct seq_file *m, void *unused); 416d3f5168aSEric Anholt int vc4_v3d_debugfs_regs(struct seq_file *m, void *unused); 417d5b1a78aSEric Anholt int vc4_v3d_set_power(struct vc4_dev *vc4, bool on); 418d5b1a78aSEric Anholt 419d5b1a78aSEric Anholt /* vc4_validate.c */ 420d5b1a78aSEric Anholt int 421d5b1a78aSEric Anholt vc4_validate_bin_cl(struct drm_device *dev, 422d5b1a78aSEric Anholt void *validated, 423d5b1a78aSEric Anholt void *unvalidated, 424d5b1a78aSEric Anholt struct vc4_exec_info *exec); 425d5b1a78aSEric Anholt 426d5b1a78aSEric Anholt int 427d5b1a78aSEric Anholt vc4_validate_shader_recs(struct drm_device *dev, struct vc4_exec_info *exec); 428d5b1a78aSEric Anholt 429d5b1a78aSEric Anholt struct drm_gem_cma_object *vc4_use_bo(struct vc4_exec_info *exec, 430d5b1a78aSEric Anholt uint32_t hindex); 431d5b1a78aSEric Anholt 432d5b1a78aSEric Anholt int vc4_get_rcl(struct drm_device *dev, struct vc4_exec_info *exec); 433d5b1a78aSEric Anholt 434d5b1a78aSEric Anholt bool vc4_check_tex_size(struct vc4_exec_info *exec, 435d5b1a78aSEric Anholt struct drm_gem_cma_object *fbo, 436d5b1a78aSEric Anholt uint32_t offset, uint8_t tiling_format, 437d5b1a78aSEric Anholt uint32_t width, uint32_t height, uint8_t cpp); 438d3f5168aSEric Anholt 439463873d5SEric Anholt /* vc4_validate_shader.c */ 440463873d5SEric Anholt struct vc4_validated_shader_info * 441463873d5SEric Anholt vc4_validate_shader(struct drm_gem_cma_object *shader_obj); 442