1c8b75bcaSEric Anholt /* 2c8b75bcaSEric Anholt * Copyright (C) 2015 Broadcom 3c8b75bcaSEric Anholt * 4c8b75bcaSEric Anholt * This program is free software; you can redistribute it and/or modify 5c8b75bcaSEric Anholt * it under the terms of the GNU General Public License version 2 as 6c8b75bcaSEric Anholt * published by the Free Software Foundation. 7c8b75bcaSEric Anholt */ 8c8b75bcaSEric Anholt 9c8b75bcaSEric Anholt #include "drmP.h" 10c8b75bcaSEric Anholt #include "drm_gem_cma_helper.h" 11c8b75bcaSEric Anholt 12c8b75bcaSEric Anholt struct vc4_dev { 13c8b75bcaSEric Anholt struct drm_device *dev; 14c8b75bcaSEric Anholt 15c8b75bcaSEric Anholt struct vc4_hdmi *hdmi; 16c8b75bcaSEric Anholt struct vc4_hvs *hvs; 17c8b75bcaSEric Anholt struct vc4_crtc *crtc[3]; 18d3f5168aSEric Anholt struct vc4_v3d *v3d; 1948666d56SDerek Foreman 2048666d56SDerek Foreman struct drm_fbdev_cma *fbdev; 21c826a6e1SEric Anholt 2221461365SEric Anholt struct vc4_hang_state *hang_state; 2321461365SEric Anholt 24c826a6e1SEric Anholt /* The kernel-space BO cache. Tracks buffers that have been 25c826a6e1SEric Anholt * unreferenced by all other users (refcounts of 0!) but not 26c826a6e1SEric Anholt * yet freed, so we can do cheap allocations. 27c826a6e1SEric Anholt */ 28c826a6e1SEric Anholt struct vc4_bo_cache { 29c826a6e1SEric Anholt /* Array of list heads for entries in the BO cache, 30c826a6e1SEric Anholt * based on number of pages, so we can do O(1) lookups 31c826a6e1SEric Anholt * in the cache when allocating. 32c826a6e1SEric Anholt */ 33c826a6e1SEric Anholt struct list_head *size_list; 34c826a6e1SEric Anholt uint32_t size_list_size; 35c826a6e1SEric Anholt 36c826a6e1SEric Anholt /* List of all BOs in the cache, ordered by age, so we 37c826a6e1SEric Anholt * can do O(1) lookups when trying to free old 38c826a6e1SEric Anholt * buffers. 39c826a6e1SEric Anholt */ 40c826a6e1SEric Anholt struct list_head time_list; 41c826a6e1SEric Anholt struct work_struct time_work; 42c826a6e1SEric Anholt struct timer_list time_timer; 43c826a6e1SEric Anholt } bo_cache; 44c826a6e1SEric Anholt 45c826a6e1SEric Anholt struct vc4_bo_stats { 46c826a6e1SEric Anholt u32 num_allocated; 47c826a6e1SEric Anholt u32 size_allocated; 48c826a6e1SEric Anholt u32 num_cached; 49c826a6e1SEric Anholt u32 size_cached; 50c826a6e1SEric Anholt } bo_stats; 51c826a6e1SEric Anholt 52c826a6e1SEric Anholt /* Protects bo_cache and the BO stats. */ 53c826a6e1SEric Anholt struct mutex bo_lock; 54d5b1a78aSEric Anholt 55ca26d28bSVarad Gautam /* Sequence number for the last job queued in bin_job_list. 56d5b1a78aSEric Anholt * Starts at 0 (no jobs emitted). 57d5b1a78aSEric Anholt */ 58d5b1a78aSEric Anholt uint64_t emit_seqno; 59d5b1a78aSEric Anholt 60d5b1a78aSEric Anholt /* Sequence number for the last completed job on the GPU. 61d5b1a78aSEric Anholt * Starts at 0 (no jobs completed). 62d5b1a78aSEric Anholt */ 63d5b1a78aSEric Anholt uint64_t finished_seqno; 64d5b1a78aSEric Anholt 65ca26d28bSVarad Gautam /* List of all struct vc4_exec_info for jobs to be executed in 66ca26d28bSVarad Gautam * the binner. The first job in the list is the one currently 67ca26d28bSVarad Gautam * programmed into ct0ca for execution. 68d5b1a78aSEric Anholt */ 69ca26d28bSVarad Gautam struct list_head bin_job_list; 70ca26d28bSVarad Gautam 71ca26d28bSVarad Gautam /* List of all struct vc4_exec_info for jobs that have 72ca26d28bSVarad Gautam * completed binning and are ready for rendering. The first 73ca26d28bSVarad Gautam * job in the list is the one currently programmed into ct1ca 74ca26d28bSVarad Gautam * for execution. 75ca26d28bSVarad Gautam */ 76ca26d28bSVarad Gautam struct list_head render_job_list; 77ca26d28bSVarad Gautam 78d5b1a78aSEric Anholt /* List of the finished vc4_exec_infos waiting to be freed by 79d5b1a78aSEric Anholt * job_done_work. 80d5b1a78aSEric Anholt */ 81d5b1a78aSEric Anholt struct list_head job_done_list; 82d5b1a78aSEric Anholt /* Spinlock used to synchronize the job_list and seqno 83d5b1a78aSEric Anholt * accesses between the IRQ handler and GEM ioctls. 84d5b1a78aSEric Anholt */ 85d5b1a78aSEric Anholt spinlock_t job_lock; 86d5b1a78aSEric Anholt wait_queue_head_t job_wait_queue; 87d5b1a78aSEric Anholt struct work_struct job_done_work; 88d5b1a78aSEric Anholt 89b501baccSEric Anholt /* List of struct vc4_seqno_cb for callbacks to be made from a 90b501baccSEric Anholt * workqueue when the given seqno is passed. 91b501baccSEric Anholt */ 92b501baccSEric Anholt struct list_head seqno_cb_list; 93b501baccSEric Anholt 94d5b1a78aSEric Anholt /* The binner overflow memory that's currently set up in 95d5b1a78aSEric Anholt * BPOA/BPOS registers. When overflow occurs and a new one is 96d5b1a78aSEric Anholt * allocated, the previous one will be moved to 97d5b1a78aSEric Anholt * vc4->current_exec's free list. 98d5b1a78aSEric Anholt */ 99d5b1a78aSEric Anholt struct vc4_bo *overflow_mem; 100d5b1a78aSEric Anholt struct work_struct overflow_mem_work; 101d5b1a78aSEric Anholt 10236cb6253SEric Anholt int power_refcount; 10336cb6253SEric Anholt 10436cb6253SEric Anholt /* Mutex controlling the power refcount. */ 10536cb6253SEric Anholt struct mutex power_lock; 10636cb6253SEric Anholt 107d5b1a78aSEric Anholt struct { 108d5b1a78aSEric Anholt struct timer_list timer; 109d5b1a78aSEric Anholt struct work_struct reset_work; 110d5b1a78aSEric Anholt } hangcheck; 111d5b1a78aSEric Anholt 112d5b1a78aSEric Anholt struct semaphore async_modeset; 113c8b75bcaSEric Anholt }; 114c8b75bcaSEric Anholt 115c8b75bcaSEric Anholt static inline struct vc4_dev * 116c8b75bcaSEric Anholt to_vc4_dev(struct drm_device *dev) 117c8b75bcaSEric Anholt { 118c8b75bcaSEric Anholt return (struct vc4_dev *)dev->dev_private; 119c8b75bcaSEric Anholt } 120c8b75bcaSEric Anholt 121c8b75bcaSEric Anholt struct vc4_bo { 122c8b75bcaSEric Anholt struct drm_gem_cma_object base; 123c826a6e1SEric Anholt 124d5b1a78aSEric Anholt /* seqno of the last job to render to this BO. */ 125d5b1a78aSEric Anholt uint64_t seqno; 126d5b1a78aSEric Anholt 127c826a6e1SEric Anholt /* List entry for the BO's position in either 128c826a6e1SEric Anholt * vc4_exec_info->unref_list or vc4_dev->bo_cache.time_list 129c826a6e1SEric Anholt */ 130c826a6e1SEric Anholt struct list_head unref_head; 131c826a6e1SEric Anholt 132c826a6e1SEric Anholt /* Time in jiffies when the BO was put in vc4->bo_cache. */ 133c826a6e1SEric Anholt unsigned long free_time; 134c826a6e1SEric Anholt 135c826a6e1SEric Anholt /* List entry for the BO's position in vc4_dev->bo_cache.size_list */ 136c826a6e1SEric Anholt struct list_head size_head; 137463873d5SEric Anholt 138463873d5SEric Anholt /* Struct for shader validation state, if created by 139463873d5SEric Anholt * DRM_IOCTL_VC4_CREATE_SHADER_BO. 140463873d5SEric Anholt */ 141463873d5SEric Anholt struct vc4_validated_shader_info *validated_shader; 142c8b75bcaSEric Anholt }; 143c8b75bcaSEric Anholt 144c8b75bcaSEric Anholt static inline struct vc4_bo * 145c8b75bcaSEric Anholt to_vc4_bo(struct drm_gem_object *bo) 146c8b75bcaSEric Anholt { 147c8b75bcaSEric Anholt return (struct vc4_bo *)bo; 148c8b75bcaSEric Anholt } 149c8b75bcaSEric Anholt 150b501baccSEric Anholt struct vc4_seqno_cb { 151b501baccSEric Anholt struct work_struct work; 152b501baccSEric Anholt uint64_t seqno; 153b501baccSEric Anholt void (*func)(struct vc4_seqno_cb *cb); 154b501baccSEric Anholt }; 155b501baccSEric Anholt 156d3f5168aSEric Anholt struct vc4_v3d { 157001bdb55SEric Anholt struct vc4_dev *vc4; 158d3f5168aSEric Anholt struct platform_device *pdev; 159d3f5168aSEric Anholt void __iomem *regs; 160d3f5168aSEric Anholt }; 161d3f5168aSEric Anholt 162c8b75bcaSEric Anholt struct vc4_hvs { 163c8b75bcaSEric Anholt struct platform_device *pdev; 164c8b75bcaSEric Anholt void __iomem *regs; 165d8dbf44fSEric Anholt u32 __iomem *dlist; 166d8dbf44fSEric Anholt 167d8dbf44fSEric Anholt /* Memory manager for CRTCs to allocate space in the display 168d8dbf44fSEric Anholt * list. Units are dwords. 169d8dbf44fSEric Anholt */ 170d8dbf44fSEric Anholt struct drm_mm dlist_mm; 17121af94cfSEric Anholt /* Memory manager for the LBM memory used by HVS scaling. */ 17221af94cfSEric Anholt struct drm_mm lbm_mm; 173d8dbf44fSEric Anholt spinlock_t mm_lock; 17421af94cfSEric Anholt 17521af94cfSEric Anholt struct drm_mm_node mitchell_netravali_filter; 176c8b75bcaSEric Anholt }; 177c8b75bcaSEric Anholt 178c8b75bcaSEric Anholt struct vc4_plane { 179c8b75bcaSEric Anholt struct drm_plane base; 180c8b75bcaSEric Anholt }; 181c8b75bcaSEric Anholt 182c8b75bcaSEric Anholt static inline struct vc4_plane * 183c8b75bcaSEric Anholt to_vc4_plane(struct drm_plane *plane) 184c8b75bcaSEric Anholt { 185c8b75bcaSEric Anholt return (struct vc4_plane *)plane; 186c8b75bcaSEric Anholt } 187c8b75bcaSEric Anholt 188c8b75bcaSEric Anholt enum vc4_encoder_type { 189c8b75bcaSEric Anholt VC4_ENCODER_TYPE_HDMI, 190c8b75bcaSEric Anholt VC4_ENCODER_TYPE_VEC, 191c8b75bcaSEric Anholt VC4_ENCODER_TYPE_DSI0, 192c8b75bcaSEric Anholt VC4_ENCODER_TYPE_DSI1, 193c8b75bcaSEric Anholt VC4_ENCODER_TYPE_SMI, 194c8b75bcaSEric Anholt VC4_ENCODER_TYPE_DPI, 195c8b75bcaSEric Anholt }; 196c8b75bcaSEric Anholt 197c8b75bcaSEric Anholt struct vc4_encoder { 198c8b75bcaSEric Anholt struct drm_encoder base; 199c8b75bcaSEric Anholt enum vc4_encoder_type type; 200c8b75bcaSEric Anholt u32 clock_select; 201c8b75bcaSEric Anholt }; 202c8b75bcaSEric Anholt 203c8b75bcaSEric Anholt static inline struct vc4_encoder * 204c8b75bcaSEric Anholt to_vc4_encoder(struct drm_encoder *encoder) 205c8b75bcaSEric Anholt { 206c8b75bcaSEric Anholt return container_of(encoder, struct vc4_encoder, base); 207c8b75bcaSEric Anholt } 208c8b75bcaSEric Anholt 209d3f5168aSEric Anholt #define V3D_READ(offset) readl(vc4->v3d->regs + offset) 210d3f5168aSEric Anholt #define V3D_WRITE(offset, val) writel(val, vc4->v3d->regs + offset) 211c8b75bcaSEric Anholt #define HVS_READ(offset) readl(vc4->hvs->regs + offset) 212c8b75bcaSEric Anholt #define HVS_WRITE(offset, val) writel(val, vc4->hvs->regs + offset) 213c8b75bcaSEric Anholt 214d5b1a78aSEric Anholt struct vc4_exec_info { 215d5b1a78aSEric Anholt /* Sequence number for this bin/render job. */ 216d5b1a78aSEric Anholt uint64_t seqno; 217d5b1a78aSEric Anholt 218c4ce60dcSEric Anholt /* Last current addresses the hardware was processing when the 219c4ce60dcSEric Anholt * hangcheck timer checked on us. 220c4ce60dcSEric Anholt */ 221c4ce60dcSEric Anholt uint32_t last_ct0ca, last_ct1ca; 222c4ce60dcSEric Anholt 223d5b1a78aSEric Anholt /* Kernel-space copy of the ioctl arguments */ 224d5b1a78aSEric Anholt struct drm_vc4_submit_cl *args; 225d5b1a78aSEric Anholt 226d5b1a78aSEric Anholt /* This is the array of BOs that were looked up at the start of exec. 227d5b1a78aSEric Anholt * Command validation will use indices into this array. 228d5b1a78aSEric Anholt */ 229d5b1a78aSEric Anholt struct drm_gem_cma_object **bo; 230d5b1a78aSEric Anholt uint32_t bo_count; 231d5b1a78aSEric Anholt 232d5b1a78aSEric Anholt /* Pointers for our position in vc4->job_list */ 233d5b1a78aSEric Anholt struct list_head head; 234d5b1a78aSEric Anholt 235d5b1a78aSEric Anholt /* List of other BOs used in the job that need to be released 236d5b1a78aSEric Anholt * once the job is complete. 237d5b1a78aSEric Anholt */ 238d5b1a78aSEric Anholt struct list_head unref_list; 239d5b1a78aSEric Anholt 240d5b1a78aSEric Anholt /* Current unvalidated indices into @bo loaded by the non-hardware 241d5b1a78aSEric Anholt * VC4_PACKET_GEM_HANDLES. 242d5b1a78aSEric Anholt */ 243d5b1a78aSEric Anholt uint32_t bo_index[2]; 244d5b1a78aSEric Anholt 245d5b1a78aSEric Anholt /* This is the BO where we store the validated command lists, shader 246d5b1a78aSEric Anholt * records, and uniforms. 247d5b1a78aSEric Anholt */ 248d5b1a78aSEric Anholt struct drm_gem_cma_object *exec_bo; 249d5b1a78aSEric Anholt 250d5b1a78aSEric Anholt /** 251d5b1a78aSEric Anholt * This tracks the per-shader-record state (packet 64) that 252d5b1a78aSEric Anholt * determines the length of the shader record and the offset 253d5b1a78aSEric Anholt * it's expected to be found at. It gets read in from the 254d5b1a78aSEric Anholt * command lists. 255d5b1a78aSEric Anholt */ 256d5b1a78aSEric Anholt struct vc4_shader_state { 257d5b1a78aSEric Anholt uint32_t addr; 258d5b1a78aSEric Anholt /* Maximum vertex index referenced by any primitive using this 259d5b1a78aSEric Anholt * shader state. 260d5b1a78aSEric Anholt */ 261d5b1a78aSEric Anholt uint32_t max_index; 262d5b1a78aSEric Anholt } *shader_state; 263d5b1a78aSEric Anholt 264d5b1a78aSEric Anholt /** How many shader states the user declared they were using. */ 265d5b1a78aSEric Anholt uint32_t shader_state_size; 266d5b1a78aSEric Anholt /** How many shader state records the validator has seen. */ 267d5b1a78aSEric Anholt uint32_t shader_state_count; 268d5b1a78aSEric Anholt 269d5b1a78aSEric Anholt bool found_tile_binning_mode_config_packet; 270d5b1a78aSEric Anholt bool found_start_tile_binning_packet; 271d5b1a78aSEric Anholt bool found_increment_semaphore_packet; 272d5b1a78aSEric Anholt bool found_flush; 273d5b1a78aSEric Anholt uint8_t bin_tiles_x, bin_tiles_y; 274d5b1a78aSEric Anholt struct drm_gem_cma_object *tile_bo; 275d5b1a78aSEric Anholt uint32_t tile_alloc_offset; 276d5b1a78aSEric Anholt 277d5b1a78aSEric Anholt /** 278d5b1a78aSEric Anholt * Computed addresses pointing into exec_bo where we start the 279d5b1a78aSEric Anholt * bin thread (ct0) and render thread (ct1). 280d5b1a78aSEric Anholt */ 281d5b1a78aSEric Anholt uint32_t ct0ca, ct0ea; 282d5b1a78aSEric Anholt uint32_t ct1ca, ct1ea; 283d5b1a78aSEric Anholt 284d5b1a78aSEric Anholt /* Pointer to the unvalidated bin CL (if present). */ 285d5b1a78aSEric Anholt void *bin_u; 286d5b1a78aSEric Anholt 287d5b1a78aSEric Anholt /* Pointers to the shader recs. These paddr gets incremented as CL 288d5b1a78aSEric Anholt * packets are relocated in validate_gl_shader_state, and the vaddrs 289d5b1a78aSEric Anholt * (u and v) get incremented and size decremented as the shader recs 290d5b1a78aSEric Anholt * themselves are validated. 291d5b1a78aSEric Anholt */ 292d5b1a78aSEric Anholt void *shader_rec_u; 293d5b1a78aSEric Anholt void *shader_rec_v; 294d5b1a78aSEric Anholt uint32_t shader_rec_p; 295d5b1a78aSEric Anholt uint32_t shader_rec_size; 296d5b1a78aSEric Anholt 297d5b1a78aSEric Anholt /* Pointers to the uniform data. These pointers are incremented, and 298d5b1a78aSEric Anholt * size decremented, as each batch of uniforms is uploaded. 299d5b1a78aSEric Anholt */ 300d5b1a78aSEric Anholt void *uniforms_u; 301d5b1a78aSEric Anholt void *uniforms_v; 302d5b1a78aSEric Anholt uint32_t uniforms_p; 303d5b1a78aSEric Anholt uint32_t uniforms_size; 304d5b1a78aSEric Anholt }; 305d5b1a78aSEric Anholt 306d5b1a78aSEric Anholt static inline struct vc4_exec_info * 307ca26d28bSVarad Gautam vc4_first_bin_job(struct vc4_dev *vc4) 308d5b1a78aSEric Anholt { 309ca26d28bSVarad Gautam if (list_empty(&vc4->bin_job_list)) 310d5b1a78aSEric Anholt return NULL; 311ca26d28bSVarad Gautam return list_first_entry(&vc4->bin_job_list, struct vc4_exec_info, head); 312ca26d28bSVarad Gautam } 313ca26d28bSVarad Gautam 314ca26d28bSVarad Gautam static inline struct vc4_exec_info * 315ca26d28bSVarad Gautam vc4_first_render_job(struct vc4_dev *vc4) 316ca26d28bSVarad Gautam { 317ca26d28bSVarad Gautam if (list_empty(&vc4->render_job_list)) 318ca26d28bSVarad Gautam return NULL; 319ca26d28bSVarad Gautam return list_first_entry(&vc4->render_job_list, 320ca26d28bSVarad Gautam struct vc4_exec_info, head); 321d5b1a78aSEric Anholt } 322d5b1a78aSEric Anholt 323c8b75bcaSEric Anholt /** 324463873d5SEric Anholt * struct vc4_texture_sample_info - saves the offsets into the UBO for texture 325463873d5SEric Anholt * setup parameters. 326463873d5SEric Anholt * 327463873d5SEric Anholt * This will be used at draw time to relocate the reference to the texture 328463873d5SEric Anholt * contents in p0, and validate that the offset combined with 329463873d5SEric Anholt * width/height/stride/etc. from p1 and p2/p3 doesn't sample outside the BO. 330463873d5SEric Anholt * Note that the hardware treats unprovided config parameters as 0, so not all 331463873d5SEric Anholt * of them need to be set up for every texure sample, and we'll store ~0 as 332463873d5SEric Anholt * the offset to mark the unused ones. 333463873d5SEric Anholt * 334463873d5SEric Anholt * See the VC4 3D architecture guide page 41 ("Texture and Memory Lookup Unit 335463873d5SEric Anholt * Setup") for definitions of the texture parameters. 336463873d5SEric Anholt */ 337463873d5SEric Anholt struct vc4_texture_sample_info { 338463873d5SEric Anholt bool is_direct; 339463873d5SEric Anholt uint32_t p_offset[4]; 340463873d5SEric Anholt }; 341463873d5SEric Anholt 342463873d5SEric Anholt /** 343463873d5SEric Anholt * struct vc4_validated_shader_info - information about validated shaders that 344463873d5SEric Anholt * needs to be used from command list validation. 345463873d5SEric Anholt * 346463873d5SEric Anholt * For a given shader, each time a shader state record references it, we need 347463873d5SEric Anholt * to verify that the shader doesn't read more uniforms than the shader state 348463873d5SEric Anholt * record's uniform BO pointer can provide, and we need to apply relocations 349463873d5SEric Anholt * and validate the shader state record's uniforms that define the texture 350463873d5SEric Anholt * samples. 351463873d5SEric Anholt */ 352463873d5SEric Anholt struct vc4_validated_shader_info { 353463873d5SEric Anholt uint32_t uniforms_size; 354463873d5SEric Anholt uint32_t uniforms_src_size; 355463873d5SEric Anholt uint32_t num_texture_samples; 356463873d5SEric Anholt struct vc4_texture_sample_info *texture_samples; 357463873d5SEric Anholt }; 358463873d5SEric Anholt 359463873d5SEric Anholt /** 360c8b75bcaSEric Anholt * _wait_for - magic (register) wait macro 361c8b75bcaSEric Anholt * 362c8b75bcaSEric Anholt * Does the right thing for modeset paths when run under kdgb or similar atomic 363c8b75bcaSEric Anholt * contexts. Note that it's important that we check the condition again after 364c8b75bcaSEric Anholt * having timed out, since the timeout could be due to preemption or similar and 365c8b75bcaSEric Anholt * we've never had a chance to check the condition before the timeout. 366c8b75bcaSEric Anholt */ 367c8b75bcaSEric Anholt #define _wait_for(COND, MS, W) ({ \ 368c8b75bcaSEric Anholt unsigned long timeout__ = jiffies + msecs_to_jiffies(MS) + 1; \ 369c8b75bcaSEric Anholt int ret__ = 0; \ 370c8b75bcaSEric Anholt while (!(COND)) { \ 371c8b75bcaSEric Anholt if (time_after(jiffies, timeout__)) { \ 372c8b75bcaSEric Anholt if (!(COND)) \ 373c8b75bcaSEric Anholt ret__ = -ETIMEDOUT; \ 374c8b75bcaSEric Anholt break; \ 375c8b75bcaSEric Anholt } \ 376c8b75bcaSEric Anholt if (W && drm_can_sleep()) { \ 377c8b75bcaSEric Anholt msleep(W); \ 378c8b75bcaSEric Anholt } else { \ 379c8b75bcaSEric Anholt cpu_relax(); \ 380c8b75bcaSEric Anholt } \ 381c8b75bcaSEric Anholt } \ 382c8b75bcaSEric Anholt ret__; \ 383c8b75bcaSEric Anholt }) 384c8b75bcaSEric Anholt 385c8b75bcaSEric Anholt #define wait_for(COND, MS) _wait_for(COND, MS, 1) 386c8b75bcaSEric Anholt 387c8b75bcaSEric Anholt /* vc4_bo.c */ 388c826a6e1SEric Anholt struct drm_gem_object *vc4_create_object(struct drm_device *dev, size_t size); 389c8b75bcaSEric Anholt void vc4_free_object(struct drm_gem_object *gem_obj); 390c826a6e1SEric Anholt struct vc4_bo *vc4_bo_create(struct drm_device *dev, size_t size, 391c826a6e1SEric Anholt bool from_cache); 392c8b75bcaSEric Anholt int vc4_dumb_create(struct drm_file *file_priv, 393c8b75bcaSEric Anholt struct drm_device *dev, 394c8b75bcaSEric Anholt struct drm_mode_create_dumb *args); 395c8b75bcaSEric Anholt struct dma_buf *vc4_prime_export(struct drm_device *dev, 396c8b75bcaSEric Anholt struct drm_gem_object *obj, int flags); 397d5bc60f6SEric Anholt int vc4_create_bo_ioctl(struct drm_device *dev, void *data, 398d5bc60f6SEric Anholt struct drm_file *file_priv); 399463873d5SEric Anholt int vc4_create_shader_bo_ioctl(struct drm_device *dev, void *data, 400463873d5SEric Anholt struct drm_file *file_priv); 401d5bc60f6SEric Anholt int vc4_mmap_bo_ioctl(struct drm_device *dev, void *data, 402d5bc60f6SEric Anholt struct drm_file *file_priv); 40321461365SEric Anholt int vc4_get_hang_state_ioctl(struct drm_device *dev, void *data, 40421461365SEric Anholt struct drm_file *file_priv); 405463873d5SEric Anholt int vc4_mmap(struct file *filp, struct vm_area_struct *vma); 406463873d5SEric Anholt int vc4_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma); 407463873d5SEric Anholt void *vc4_prime_vmap(struct drm_gem_object *obj); 408c826a6e1SEric Anholt void vc4_bo_cache_init(struct drm_device *dev); 409c826a6e1SEric Anholt void vc4_bo_cache_destroy(struct drm_device *dev); 410c826a6e1SEric Anholt int vc4_bo_stats_debugfs(struct seq_file *m, void *arg); 411c8b75bcaSEric Anholt 412c8b75bcaSEric Anholt /* vc4_crtc.c */ 413c8b75bcaSEric Anholt extern struct platform_driver vc4_crtc_driver; 4141f43710aSDave Airlie int vc4_enable_vblank(struct drm_device *dev, unsigned int crtc_id); 4151f43710aSDave Airlie void vc4_disable_vblank(struct drm_device *dev, unsigned int crtc_id); 416c8b75bcaSEric Anholt int vc4_crtc_debugfs_regs(struct seq_file *m, void *arg); 417c8b75bcaSEric Anholt 418c8b75bcaSEric Anholt /* vc4_debugfs.c */ 419c8b75bcaSEric Anholt int vc4_debugfs_init(struct drm_minor *minor); 420c8b75bcaSEric Anholt void vc4_debugfs_cleanup(struct drm_minor *minor); 421c8b75bcaSEric Anholt 422c8b75bcaSEric Anholt /* vc4_drv.c */ 423c8b75bcaSEric Anholt void __iomem *vc4_ioremap_regs(struct platform_device *dev, int index); 424c8b75bcaSEric Anholt 425d5b1a78aSEric Anholt /* vc4_gem.c */ 426d5b1a78aSEric Anholt void vc4_gem_init(struct drm_device *dev); 427d5b1a78aSEric Anholt void vc4_gem_destroy(struct drm_device *dev); 428d5b1a78aSEric Anholt int vc4_submit_cl_ioctl(struct drm_device *dev, void *data, 429d5b1a78aSEric Anholt struct drm_file *file_priv); 430d5b1a78aSEric Anholt int vc4_wait_seqno_ioctl(struct drm_device *dev, void *data, 431d5b1a78aSEric Anholt struct drm_file *file_priv); 432d5b1a78aSEric Anholt int vc4_wait_bo_ioctl(struct drm_device *dev, void *data, 433d5b1a78aSEric Anholt struct drm_file *file_priv); 434ca26d28bSVarad Gautam void vc4_submit_next_bin_job(struct drm_device *dev); 435ca26d28bSVarad Gautam void vc4_submit_next_render_job(struct drm_device *dev); 436ca26d28bSVarad Gautam void vc4_move_job_to_render(struct drm_device *dev, struct vc4_exec_info *exec); 437d5b1a78aSEric Anholt int vc4_wait_for_seqno(struct drm_device *dev, uint64_t seqno, 438d5b1a78aSEric Anholt uint64_t timeout_ns, bool interruptible); 439d5b1a78aSEric Anholt void vc4_job_handle_completed(struct vc4_dev *vc4); 440b501baccSEric Anholt int vc4_queue_seqno_cb(struct drm_device *dev, 441b501baccSEric Anholt struct vc4_seqno_cb *cb, uint64_t seqno, 442b501baccSEric Anholt void (*func)(struct vc4_seqno_cb *cb)); 443d5b1a78aSEric Anholt 444c8b75bcaSEric Anholt /* vc4_hdmi.c */ 445c8b75bcaSEric Anholt extern struct platform_driver vc4_hdmi_driver; 446c8b75bcaSEric Anholt int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused); 447c8b75bcaSEric Anholt 448d5b1a78aSEric Anholt /* vc4_irq.c */ 449d5b1a78aSEric Anholt irqreturn_t vc4_irq(int irq, void *arg); 450d5b1a78aSEric Anholt void vc4_irq_preinstall(struct drm_device *dev); 451d5b1a78aSEric Anholt int vc4_irq_postinstall(struct drm_device *dev); 452d5b1a78aSEric Anholt void vc4_irq_uninstall(struct drm_device *dev); 453d5b1a78aSEric Anholt void vc4_irq_reset(struct drm_device *dev); 454d5b1a78aSEric Anholt 455c8b75bcaSEric Anholt /* vc4_hvs.c */ 456c8b75bcaSEric Anholt extern struct platform_driver vc4_hvs_driver; 457c8b75bcaSEric Anholt void vc4_hvs_dump_state(struct drm_device *dev); 458c8b75bcaSEric Anholt int vc4_hvs_debugfs_regs(struct seq_file *m, void *unused); 459c8b75bcaSEric Anholt 460c8b75bcaSEric Anholt /* vc4_kms.c */ 461c8b75bcaSEric Anholt int vc4_kms_load(struct drm_device *dev); 462c8b75bcaSEric Anholt 463c8b75bcaSEric Anholt /* vc4_plane.c */ 464c8b75bcaSEric Anholt struct drm_plane *vc4_plane_init(struct drm_device *dev, 465c8b75bcaSEric Anholt enum drm_plane_type type); 466c8b75bcaSEric Anholt u32 vc4_plane_write_dlist(struct drm_plane *plane, u32 __iomem *dlist); 467c8b75bcaSEric Anholt u32 vc4_plane_dlist_size(struct drm_plane_state *state); 468b501baccSEric Anholt void vc4_plane_async_set_fb(struct drm_plane *plane, 469b501baccSEric Anholt struct drm_framebuffer *fb); 470463873d5SEric Anholt 471d3f5168aSEric Anholt /* vc4_v3d.c */ 472d3f5168aSEric Anholt extern struct platform_driver vc4_v3d_driver; 473d3f5168aSEric Anholt int vc4_v3d_debugfs_ident(struct seq_file *m, void *unused); 474d3f5168aSEric Anholt int vc4_v3d_debugfs_regs(struct seq_file *m, void *unused); 475d5b1a78aSEric Anholt 476d5b1a78aSEric Anholt /* vc4_validate.c */ 477d5b1a78aSEric Anholt int 478d5b1a78aSEric Anholt vc4_validate_bin_cl(struct drm_device *dev, 479d5b1a78aSEric Anholt void *validated, 480d5b1a78aSEric Anholt void *unvalidated, 481d5b1a78aSEric Anholt struct vc4_exec_info *exec); 482d5b1a78aSEric Anholt 483d5b1a78aSEric Anholt int 484d5b1a78aSEric Anholt vc4_validate_shader_recs(struct drm_device *dev, struct vc4_exec_info *exec); 485d5b1a78aSEric Anholt 486d5b1a78aSEric Anholt struct drm_gem_cma_object *vc4_use_bo(struct vc4_exec_info *exec, 487d5b1a78aSEric Anholt uint32_t hindex); 488d5b1a78aSEric Anholt 489d5b1a78aSEric Anholt int vc4_get_rcl(struct drm_device *dev, struct vc4_exec_info *exec); 490d5b1a78aSEric Anholt 491d5b1a78aSEric Anholt bool vc4_check_tex_size(struct vc4_exec_info *exec, 492d5b1a78aSEric Anholt struct drm_gem_cma_object *fbo, 493d5b1a78aSEric Anholt uint32_t offset, uint8_t tiling_format, 494d5b1a78aSEric Anholt uint32_t width, uint32_t height, uint8_t cpp); 495d3f5168aSEric Anholt 496463873d5SEric Anholt /* vc4_validate_shader.c */ 497463873d5SEric Anholt struct vc4_validated_shader_info * 498463873d5SEric Anholt vc4_validate_shader(struct drm_gem_cma_object *shader_obj); 499