1 /* 2 * Copyright (C) 2015 Broadcom 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 /** 10 * DOC: VC4 CRTC module 11 * 12 * In VC4, the Pixel Valve is what most closely corresponds to the 13 * DRM's concept of a CRTC. The PV generates video timings from the 14 * encoder's clock plus its configuration. It pulls scaled pixels from 15 * the HVS at that timing, and feeds it to the encoder. 16 * 17 * However, the DRM CRTC also collects the configuration of all the 18 * DRM planes attached to it. As a result, the CRTC is also 19 * responsible for writing the display list for the HVS channel that 20 * the CRTC will use. 21 * 22 * The 2835 has 3 different pixel valves. pv0 in the audio power 23 * domain feeds DSI0 or DPI, while pv1 feeds DS1 or SMI. pv2 in the 24 * image domain can feed either HDMI or the SDTV controller. The 25 * pixel valve chooses from the CPRMAN clocks (HSM for HDMI, VEC for 26 * SDTV, etc.) according to which output type is chosen in the mux. 27 * 28 * For power management, the pixel valve's registers are all clocked 29 * by the AXI clock, while the timings and FIFOs make use of the 30 * output-specific clock. Since the encoders also directly consume 31 * the CPRMAN clocks, and know what timings they need, they are the 32 * ones that set the clock. 33 */ 34 35 #include <drm/drm_atomic.h> 36 #include <drm/drm_atomic_helper.h> 37 #include <drm/drm_crtc_helper.h> 38 #include <linux/clk.h> 39 #include <drm/drm_fb_cma_helper.h> 40 #include <linux/component.h> 41 #include <linux/of_device.h> 42 #include "vc4_drv.h" 43 #include "vc4_regs.h" 44 45 struct vc4_crtc_state { 46 struct drm_crtc_state base; 47 /* Dlist area for this CRTC configuration. */ 48 struct drm_mm_node mm; 49 }; 50 51 static inline struct vc4_crtc_state * 52 to_vc4_crtc_state(struct drm_crtc_state *crtc_state) 53 { 54 return (struct vc4_crtc_state *)crtc_state; 55 } 56 57 #define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset)) 58 #define CRTC_READ(offset) readl(vc4_crtc->regs + (offset)) 59 60 #define CRTC_REG(reg) { reg, #reg } 61 static const struct { 62 u32 reg; 63 const char *name; 64 } crtc_regs[] = { 65 CRTC_REG(PV_CONTROL), 66 CRTC_REG(PV_V_CONTROL), 67 CRTC_REG(PV_VSYNCD_EVEN), 68 CRTC_REG(PV_HORZA), 69 CRTC_REG(PV_HORZB), 70 CRTC_REG(PV_VERTA), 71 CRTC_REG(PV_VERTB), 72 CRTC_REG(PV_VERTA_EVEN), 73 CRTC_REG(PV_VERTB_EVEN), 74 CRTC_REG(PV_INTEN), 75 CRTC_REG(PV_INTSTAT), 76 CRTC_REG(PV_STAT), 77 CRTC_REG(PV_HACT_ACT), 78 }; 79 80 static void vc4_crtc_dump_regs(struct vc4_crtc *vc4_crtc) 81 { 82 int i; 83 84 for (i = 0; i < ARRAY_SIZE(crtc_regs); i++) { 85 DRM_INFO("0x%04x (%s): 0x%08x\n", 86 crtc_regs[i].reg, crtc_regs[i].name, 87 CRTC_READ(crtc_regs[i].reg)); 88 } 89 } 90 91 #ifdef CONFIG_DEBUG_FS 92 int vc4_crtc_debugfs_regs(struct seq_file *m, void *unused) 93 { 94 struct drm_info_node *node = (struct drm_info_node *)m->private; 95 struct drm_device *dev = node->minor->dev; 96 int crtc_index = (uintptr_t)node->info_ent->data; 97 struct drm_crtc *crtc; 98 struct vc4_crtc *vc4_crtc; 99 int i; 100 101 i = 0; 102 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 103 if (i == crtc_index) 104 break; 105 i++; 106 } 107 if (!crtc) 108 return 0; 109 vc4_crtc = to_vc4_crtc(crtc); 110 111 for (i = 0; i < ARRAY_SIZE(crtc_regs); i++) { 112 seq_printf(m, "%s (0x%04x): 0x%08x\n", 113 crtc_regs[i].name, crtc_regs[i].reg, 114 CRTC_READ(crtc_regs[i].reg)); 115 } 116 117 return 0; 118 } 119 #endif 120 121 bool vc4_crtc_get_scanoutpos(struct drm_device *dev, unsigned int crtc_id, 122 bool in_vblank_irq, int *vpos, int *hpos, 123 ktime_t *stime, ktime_t *etime, 124 const struct drm_display_mode *mode) 125 { 126 struct vc4_dev *vc4 = to_vc4_dev(dev); 127 struct drm_crtc *crtc = drm_crtc_from_index(dev, crtc_id); 128 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 129 u32 val; 130 int fifo_lines; 131 int vblank_lines; 132 bool ret = false; 133 134 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */ 135 136 /* Get optional system timestamp before query. */ 137 if (stime) 138 *stime = ktime_get(); 139 140 /* 141 * Read vertical scanline which is currently composed for our 142 * pixelvalve by the HVS, and also the scaler status. 143 */ 144 val = HVS_READ(SCALER_DISPSTATX(vc4_crtc->channel)); 145 146 /* Get optional system timestamp after query. */ 147 if (etime) 148 *etime = ktime_get(); 149 150 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */ 151 152 /* Vertical position of hvs composed scanline. */ 153 *vpos = VC4_GET_FIELD(val, SCALER_DISPSTATX_LINE); 154 *hpos = 0; 155 156 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 157 *vpos /= 2; 158 159 /* Use hpos to correct for field offset in interlaced mode. */ 160 if (VC4_GET_FIELD(val, SCALER_DISPSTATX_FRAME_COUNT) % 2) 161 *hpos += mode->crtc_htotal / 2; 162 } 163 164 /* This is the offset we need for translating hvs -> pv scanout pos. */ 165 fifo_lines = vc4_crtc->cob_size / mode->crtc_hdisplay; 166 167 if (fifo_lines > 0) 168 ret = true; 169 170 /* HVS more than fifo_lines into frame for compositing? */ 171 if (*vpos > fifo_lines) { 172 /* 173 * We are in active scanout and can get some meaningful results 174 * from HVS. The actual PV scanout can not trail behind more 175 * than fifo_lines as that is the fifo's capacity. Assume that 176 * in active scanout the HVS and PV work in lockstep wrt. HVS 177 * refilling the fifo and PV consuming from the fifo, ie. 178 * whenever the PV consumes and frees up a scanline in the 179 * fifo, the HVS will immediately refill it, therefore 180 * incrementing vpos. Therefore we choose HVS read position - 181 * fifo size in scanlines as a estimate of the real scanout 182 * position of the PV. 183 */ 184 *vpos -= fifo_lines + 1; 185 186 return ret; 187 } 188 189 /* 190 * Less: This happens when we are in vblank and the HVS, after getting 191 * the VSTART restart signal from the PV, just started refilling its 192 * fifo with new lines from the top-most lines of the new framebuffers. 193 * The PV does not scan out in vblank, so does not remove lines from 194 * the fifo, so the fifo will be full quickly and the HVS has to pause. 195 * We can't get meaningful readings wrt. scanline position of the PV 196 * and need to make things up in a approximative but consistent way. 197 */ 198 vblank_lines = mode->vtotal - mode->vdisplay; 199 200 if (in_vblank_irq) { 201 /* 202 * Assume the irq handler got called close to first 203 * line of vblank, so PV has about a full vblank 204 * scanlines to go, and as a base timestamp use the 205 * one taken at entry into vblank irq handler, so it 206 * is not affected by random delays due to lock 207 * contention on event_lock or vblank_time lock in 208 * the core. 209 */ 210 *vpos = -vblank_lines; 211 212 if (stime) 213 *stime = vc4_crtc->t_vblank; 214 if (etime) 215 *etime = vc4_crtc->t_vblank; 216 217 /* 218 * If the HVS fifo is not yet full then we know for certain 219 * we are at the very beginning of vblank, as the hvs just 220 * started refilling, and the stime and etime timestamps 221 * truly correspond to start of vblank. 222 * 223 * Unfortunately there's no way to report this to upper levels 224 * and make it more useful. 225 */ 226 } else { 227 /* 228 * No clue where we are inside vblank. Return a vpos of zero, 229 * which will cause calling code to just return the etime 230 * timestamp uncorrected. At least this is no worse than the 231 * standard fallback. 232 */ 233 *vpos = 0; 234 } 235 236 return ret; 237 } 238 239 static void vc4_crtc_destroy(struct drm_crtc *crtc) 240 { 241 drm_crtc_cleanup(crtc); 242 } 243 244 static void 245 vc4_crtc_lut_load(struct drm_crtc *crtc) 246 { 247 struct drm_device *dev = crtc->dev; 248 struct vc4_dev *vc4 = to_vc4_dev(dev); 249 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 250 u32 i; 251 252 /* The LUT memory is laid out with each HVS channel in order, 253 * each of which takes 256 writes for R, 256 for G, then 256 254 * for B. 255 */ 256 HVS_WRITE(SCALER_GAMADDR, 257 SCALER_GAMADDR_AUTOINC | 258 (vc4_crtc->channel * 3 * crtc->gamma_size)); 259 260 for (i = 0; i < crtc->gamma_size; i++) 261 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_r[i]); 262 for (i = 0; i < crtc->gamma_size; i++) 263 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_g[i]); 264 for (i = 0; i < crtc->gamma_size; i++) 265 HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_b[i]); 266 } 267 268 static void 269 vc4_crtc_update_gamma_lut(struct drm_crtc *crtc) 270 { 271 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 272 struct drm_color_lut *lut = crtc->state->gamma_lut->data; 273 u32 length = drm_color_lut_size(crtc->state->gamma_lut); 274 u32 i; 275 276 for (i = 0; i < length; i++) { 277 vc4_crtc->lut_r[i] = drm_color_lut_extract(lut[i].red, 8); 278 vc4_crtc->lut_g[i] = drm_color_lut_extract(lut[i].green, 8); 279 vc4_crtc->lut_b[i] = drm_color_lut_extract(lut[i].blue, 8); 280 } 281 282 vc4_crtc_lut_load(crtc); 283 } 284 285 static u32 vc4_get_fifo_full_level(u32 format) 286 { 287 static const u32 fifo_len_bytes = 64; 288 static const u32 hvs_latency_pix = 6; 289 290 switch (format) { 291 case PV_CONTROL_FORMAT_DSIV_16: 292 case PV_CONTROL_FORMAT_DSIC_16: 293 return fifo_len_bytes - 2 * hvs_latency_pix; 294 case PV_CONTROL_FORMAT_DSIV_18: 295 return fifo_len_bytes - 14; 296 case PV_CONTROL_FORMAT_24: 297 case PV_CONTROL_FORMAT_DSIV_24: 298 default: 299 return fifo_len_bytes - 3 * hvs_latency_pix; 300 } 301 } 302 303 /* 304 * Returns the encoder attached to the CRTC. 305 * 306 * VC4 can only scan out to one encoder at a time, while the DRM core 307 * allows drivers to push pixels to more than one encoder from the 308 * same CRTC. 309 */ 310 static struct drm_encoder *vc4_get_crtc_encoder(struct drm_crtc *crtc) 311 { 312 struct drm_connector *connector; 313 struct drm_connector_list_iter conn_iter; 314 315 drm_connector_list_iter_begin(crtc->dev, &conn_iter); 316 drm_for_each_connector_iter(connector, &conn_iter) { 317 if (connector->state->crtc == crtc) { 318 drm_connector_list_iter_end(&conn_iter); 319 return connector->encoder; 320 } 321 } 322 drm_connector_list_iter_end(&conn_iter); 323 324 return NULL; 325 } 326 327 static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc) 328 { 329 struct drm_device *dev = crtc->dev; 330 struct vc4_dev *vc4 = to_vc4_dev(dev); 331 struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc); 332 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder); 333 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 334 struct drm_crtc_state *state = crtc->state; 335 struct drm_display_mode *mode = &state->adjusted_mode; 336 bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE; 337 u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1; 338 bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 || 339 vc4_encoder->type == VC4_ENCODER_TYPE_DSI1); 340 u32 format = is_dsi ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24; 341 bool debug_dump_regs = false; 342 343 if (debug_dump_regs) { 344 DRM_INFO("CRTC %d regs before:\n", drm_crtc_index(crtc)); 345 vc4_crtc_dump_regs(vc4_crtc); 346 } 347 348 /* Reset the PV fifo. */ 349 CRTC_WRITE(PV_CONTROL, 0); 350 CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR | PV_CONTROL_EN); 351 CRTC_WRITE(PV_CONTROL, 0); 352 353 CRTC_WRITE(PV_HORZA, 354 VC4_SET_FIELD((mode->htotal - 355 mode->hsync_end) * pixel_rep, 356 PV_HORZA_HBP) | 357 VC4_SET_FIELD((mode->hsync_end - 358 mode->hsync_start) * pixel_rep, 359 PV_HORZA_HSYNC)); 360 CRTC_WRITE(PV_HORZB, 361 VC4_SET_FIELD((mode->hsync_start - 362 mode->hdisplay) * pixel_rep, 363 PV_HORZB_HFP) | 364 VC4_SET_FIELD(mode->hdisplay * pixel_rep, PV_HORZB_HACTIVE)); 365 366 CRTC_WRITE(PV_VERTA, 367 VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end, 368 PV_VERTA_VBP) | 369 VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start, 370 PV_VERTA_VSYNC)); 371 CRTC_WRITE(PV_VERTB, 372 VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay, 373 PV_VERTB_VFP) | 374 VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE)); 375 376 if (interlace) { 377 CRTC_WRITE(PV_VERTA_EVEN, 378 VC4_SET_FIELD(mode->crtc_vtotal - 379 mode->crtc_vsync_end - 1, 380 PV_VERTA_VBP) | 381 VC4_SET_FIELD(mode->crtc_vsync_end - 382 mode->crtc_vsync_start, 383 PV_VERTA_VSYNC)); 384 CRTC_WRITE(PV_VERTB_EVEN, 385 VC4_SET_FIELD(mode->crtc_vsync_start - 386 mode->crtc_vdisplay, 387 PV_VERTB_VFP) | 388 VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE)); 389 390 /* We set up first field even mode for HDMI. VEC's 391 * NTSC mode would want first field odd instead, once 392 * we support it (to do so, set ODD_FIRST and put the 393 * delay in VSYNCD_EVEN instead). 394 */ 395 CRTC_WRITE(PV_V_CONTROL, 396 PV_VCONTROL_CONTINUOUS | 397 (is_dsi ? PV_VCONTROL_DSI : 0) | 398 PV_VCONTROL_INTERLACE | 399 VC4_SET_FIELD(mode->htotal * pixel_rep / 2, 400 PV_VCONTROL_ODD_DELAY)); 401 CRTC_WRITE(PV_VSYNCD_EVEN, 0); 402 } else { 403 CRTC_WRITE(PV_V_CONTROL, 404 PV_VCONTROL_CONTINUOUS | 405 (is_dsi ? PV_VCONTROL_DSI : 0)); 406 } 407 408 CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep); 409 410 CRTC_WRITE(PV_CONTROL, 411 VC4_SET_FIELD(format, PV_CONTROL_FORMAT) | 412 VC4_SET_FIELD(vc4_get_fifo_full_level(format), 413 PV_CONTROL_FIFO_LEVEL) | 414 VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) | 415 PV_CONTROL_CLR_AT_START | 416 PV_CONTROL_TRIGGER_UNDERFLOW | 417 PV_CONTROL_WAIT_HSTART | 418 VC4_SET_FIELD(vc4_encoder->clock_select, 419 PV_CONTROL_CLK_SELECT) | 420 PV_CONTROL_FIFO_CLR | 421 PV_CONTROL_EN); 422 423 HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel), 424 SCALER_DISPBKGND_AUTOHS | 425 SCALER_DISPBKGND_GAMMA | 426 (interlace ? SCALER_DISPBKGND_INTERLACE : 0)); 427 428 /* Reload the LUT, since the SRAMs would have been disabled if 429 * all CRTCs had SCALER_DISPBKGND_GAMMA unset at once. 430 */ 431 vc4_crtc_lut_load(crtc); 432 433 if (debug_dump_regs) { 434 DRM_INFO("CRTC %d regs after:\n", drm_crtc_index(crtc)); 435 vc4_crtc_dump_regs(vc4_crtc); 436 } 437 } 438 439 static void require_hvs_enabled(struct drm_device *dev) 440 { 441 struct vc4_dev *vc4 = to_vc4_dev(dev); 442 443 WARN_ON_ONCE((HVS_READ(SCALER_DISPCTRL) & SCALER_DISPCTRL_ENABLE) != 444 SCALER_DISPCTRL_ENABLE); 445 } 446 447 static void vc4_crtc_atomic_disable(struct drm_crtc *crtc, 448 struct drm_crtc_state *old_state) 449 { 450 struct drm_device *dev = crtc->dev; 451 struct vc4_dev *vc4 = to_vc4_dev(dev); 452 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 453 u32 chan = vc4_crtc->channel; 454 int ret; 455 require_hvs_enabled(dev); 456 457 /* Disable vblank irq handling before crtc is disabled. */ 458 drm_crtc_vblank_off(crtc); 459 460 CRTC_WRITE(PV_V_CONTROL, 461 CRTC_READ(PV_V_CONTROL) & ~PV_VCONTROL_VIDEN); 462 ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1); 463 WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n"); 464 465 if (HVS_READ(SCALER_DISPCTRLX(chan)) & 466 SCALER_DISPCTRLX_ENABLE) { 467 HVS_WRITE(SCALER_DISPCTRLX(chan), 468 SCALER_DISPCTRLX_RESET); 469 470 /* While the docs say that reset is self-clearing, it 471 * seems it doesn't actually. 472 */ 473 HVS_WRITE(SCALER_DISPCTRLX(chan), 0); 474 } 475 476 /* Once we leave, the scaler should be disabled and its fifo empty. */ 477 478 WARN_ON_ONCE(HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_RESET); 479 480 WARN_ON_ONCE(VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(chan)), 481 SCALER_DISPSTATX_MODE) != 482 SCALER_DISPSTATX_MODE_DISABLED); 483 484 WARN_ON_ONCE((HVS_READ(SCALER_DISPSTATX(chan)) & 485 (SCALER_DISPSTATX_FULL | SCALER_DISPSTATX_EMPTY)) != 486 SCALER_DISPSTATX_EMPTY); 487 488 /* 489 * Make sure we issue a vblank event after disabling the CRTC if 490 * someone was waiting it. 491 */ 492 if (crtc->state->event) { 493 unsigned long flags; 494 495 spin_lock_irqsave(&dev->event_lock, flags); 496 drm_crtc_send_vblank_event(crtc, crtc->state->event); 497 crtc->state->event = NULL; 498 spin_unlock_irqrestore(&dev->event_lock, flags); 499 } 500 } 501 502 static void vc4_crtc_update_dlist(struct drm_crtc *crtc) 503 { 504 struct drm_device *dev = crtc->dev; 505 struct vc4_dev *vc4 = to_vc4_dev(dev); 506 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 507 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state); 508 509 if (crtc->state->event) { 510 unsigned long flags; 511 512 crtc->state->event->pipe = drm_crtc_index(crtc); 513 514 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 515 516 spin_lock_irqsave(&dev->event_lock, flags); 517 vc4_crtc->event = crtc->state->event; 518 crtc->state->event = NULL; 519 520 HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel), 521 vc4_state->mm.start); 522 523 spin_unlock_irqrestore(&dev->event_lock, flags); 524 } else { 525 HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel), 526 vc4_state->mm.start); 527 } 528 } 529 530 static void vc4_crtc_atomic_enable(struct drm_crtc *crtc, 531 struct drm_crtc_state *old_state) 532 { 533 struct drm_device *dev = crtc->dev; 534 struct vc4_dev *vc4 = to_vc4_dev(dev); 535 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 536 struct drm_crtc_state *state = crtc->state; 537 struct drm_display_mode *mode = &state->adjusted_mode; 538 539 require_hvs_enabled(dev); 540 541 /* Enable vblank irq handling before crtc is started otherwise 542 * drm_crtc_get_vblank() fails in vc4_crtc_update_dlist(). 543 */ 544 drm_crtc_vblank_on(crtc); 545 vc4_crtc_update_dlist(crtc); 546 547 /* Turn on the scaler, which will wait for vstart to start 548 * compositing. 549 */ 550 HVS_WRITE(SCALER_DISPCTRLX(vc4_crtc->channel), 551 VC4_SET_FIELD(mode->hdisplay, SCALER_DISPCTRLX_WIDTH) | 552 VC4_SET_FIELD(mode->vdisplay, SCALER_DISPCTRLX_HEIGHT) | 553 SCALER_DISPCTRLX_ENABLE); 554 555 /* Turn on the pixel valve, which will emit the vstart signal. */ 556 CRTC_WRITE(PV_V_CONTROL, 557 CRTC_READ(PV_V_CONTROL) | PV_VCONTROL_VIDEN); 558 } 559 560 static enum drm_mode_status vc4_crtc_mode_valid(struct drm_crtc *crtc, 561 const struct drm_display_mode *mode) 562 { 563 /* Do not allow doublescan modes from user space */ 564 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) { 565 DRM_DEBUG_KMS("[CRTC:%d] Doublescan mode rejected.\n", 566 crtc->base.id); 567 return MODE_NO_DBLESCAN; 568 } 569 570 return MODE_OK; 571 } 572 573 static int vc4_crtc_atomic_check(struct drm_crtc *crtc, 574 struct drm_crtc_state *state) 575 { 576 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state); 577 struct drm_device *dev = crtc->dev; 578 struct vc4_dev *vc4 = to_vc4_dev(dev); 579 struct drm_plane *plane; 580 unsigned long flags; 581 const struct drm_plane_state *plane_state; 582 u32 dlist_count = 0; 583 int ret; 584 585 /* The pixelvalve can only feed one encoder (and encoders are 586 * 1:1 with connectors.) 587 */ 588 if (hweight32(state->connector_mask) > 1) 589 return -EINVAL; 590 591 drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, state) 592 dlist_count += vc4_plane_dlist_size(plane_state); 593 594 dlist_count++; /* Account for SCALER_CTL0_END. */ 595 596 spin_lock_irqsave(&vc4->hvs->mm_lock, flags); 597 ret = drm_mm_insert_node(&vc4->hvs->dlist_mm, &vc4_state->mm, 598 dlist_count); 599 spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags); 600 if (ret) 601 return ret; 602 603 return 0; 604 } 605 606 static void vc4_crtc_atomic_flush(struct drm_crtc *crtc, 607 struct drm_crtc_state *old_state) 608 { 609 struct drm_device *dev = crtc->dev; 610 struct vc4_dev *vc4 = to_vc4_dev(dev); 611 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 612 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state); 613 struct drm_plane *plane; 614 struct vc4_plane_state *vc4_plane_state; 615 bool debug_dump_regs = false; 616 bool enable_bg_fill = false; 617 u32 __iomem *dlist_start = vc4->hvs->dlist + vc4_state->mm.start; 618 u32 __iomem *dlist_next = dlist_start; 619 620 if (debug_dump_regs) { 621 DRM_INFO("CRTC %d HVS before:\n", drm_crtc_index(crtc)); 622 vc4_hvs_dump_state(dev); 623 } 624 625 /* Copy all the active planes' dlist contents to the hardware dlist. */ 626 drm_atomic_crtc_for_each_plane(plane, crtc) { 627 /* Is this the first active plane? */ 628 if (dlist_next == dlist_start) { 629 /* We need to enable background fill when a plane 630 * could be alpha blending from the background, i.e. 631 * where no other plane is underneath. It suffices to 632 * consider the first active plane here since we set 633 * needs_bg_fill such that either the first plane 634 * already needs it or all planes on top blend from 635 * the first or a lower plane. 636 */ 637 vc4_plane_state = to_vc4_plane_state(plane->state); 638 enable_bg_fill = vc4_plane_state->needs_bg_fill; 639 } 640 641 dlist_next += vc4_plane_write_dlist(plane, dlist_next); 642 } 643 644 writel(SCALER_CTL0_END, dlist_next); 645 dlist_next++; 646 647 WARN_ON_ONCE(dlist_next - dlist_start != vc4_state->mm.size); 648 649 if (enable_bg_fill) 650 /* This sets a black background color fill, as is the case 651 * with other DRM drivers. 652 */ 653 HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel), 654 HVS_READ(SCALER_DISPBKGNDX(vc4_crtc->channel)) | 655 SCALER_DISPBKGND_FILL); 656 657 /* Only update DISPLIST if the CRTC was already running and is not 658 * being disabled. 659 * vc4_crtc_enable() takes care of updating the dlist just after 660 * re-enabling VBLANK interrupts and before enabling the engine. 661 * If the CRTC is being disabled, there's no point in updating this 662 * information. 663 */ 664 if (crtc->state->active && old_state->active) 665 vc4_crtc_update_dlist(crtc); 666 667 if (crtc->state->color_mgmt_changed) { 668 u32 dispbkgndx = HVS_READ(SCALER_DISPBKGNDX(vc4_crtc->channel)); 669 670 if (crtc->state->gamma_lut) { 671 vc4_crtc_update_gamma_lut(crtc); 672 dispbkgndx |= SCALER_DISPBKGND_GAMMA; 673 } else { 674 /* Unsetting DISPBKGND_GAMMA skips the gamma lut step 675 * in hardware, which is the same as a linear lut that 676 * DRM expects us to use in absence of a user lut. 677 */ 678 dispbkgndx &= ~SCALER_DISPBKGND_GAMMA; 679 } 680 HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel), dispbkgndx); 681 } 682 683 if (debug_dump_regs) { 684 DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc)); 685 vc4_hvs_dump_state(dev); 686 } 687 } 688 689 static int vc4_enable_vblank(struct drm_crtc *crtc) 690 { 691 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 692 693 CRTC_WRITE(PV_INTEN, PV_INT_VFP_START); 694 695 return 0; 696 } 697 698 static void vc4_disable_vblank(struct drm_crtc *crtc) 699 { 700 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 701 702 CRTC_WRITE(PV_INTEN, 0); 703 } 704 705 static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc) 706 { 707 struct drm_crtc *crtc = &vc4_crtc->base; 708 struct drm_device *dev = crtc->dev; 709 struct vc4_dev *vc4 = to_vc4_dev(dev); 710 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state); 711 u32 chan = vc4_crtc->channel; 712 unsigned long flags; 713 714 spin_lock_irqsave(&dev->event_lock, flags); 715 if (vc4_crtc->event && 716 (vc4_state->mm.start == HVS_READ(SCALER_DISPLACTX(chan)))) { 717 drm_crtc_send_vblank_event(crtc, vc4_crtc->event); 718 vc4_crtc->event = NULL; 719 drm_crtc_vblank_put(crtc); 720 } 721 spin_unlock_irqrestore(&dev->event_lock, flags); 722 } 723 724 static irqreturn_t vc4_crtc_irq_handler(int irq, void *data) 725 { 726 struct vc4_crtc *vc4_crtc = data; 727 u32 stat = CRTC_READ(PV_INTSTAT); 728 irqreturn_t ret = IRQ_NONE; 729 730 if (stat & PV_INT_VFP_START) { 731 vc4_crtc->t_vblank = ktime_get(); 732 CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START); 733 drm_crtc_handle_vblank(&vc4_crtc->base); 734 vc4_crtc_handle_page_flip(vc4_crtc); 735 ret = IRQ_HANDLED; 736 } 737 738 return ret; 739 } 740 741 struct vc4_async_flip_state { 742 struct drm_crtc *crtc; 743 struct drm_framebuffer *fb; 744 struct drm_framebuffer *old_fb; 745 struct drm_pending_vblank_event *event; 746 747 struct vc4_seqno_cb cb; 748 }; 749 750 /* Called when the V3D execution for the BO being flipped to is done, so that 751 * we can actually update the plane's address to point to it. 752 */ 753 static void 754 vc4_async_page_flip_complete(struct vc4_seqno_cb *cb) 755 { 756 struct vc4_async_flip_state *flip_state = 757 container_of(cb, struct vc4_async_flip_state, cb); 758 struct drm_crtc *crtc = flip_state->crtc; 759 struct drm_device *dev = crtc->dev; 760 struct vc4_dev *vc4 = to_vc4_dev(dev); 761 struct drm_plane *plane = crtc->primary; 762 763 vc4_plane_async_set_fb(plane, flip_state->fb); 764 if (flip_state->event) { 765 unsigned long flags; 766 767 spin_lock_irqsave(&dev->event_lock, flags); 768 drm_crtc_send_vblank_event(crtc, flip_state->event); 769 spin_unlock_irqrestore(&dev->event_lock, flags); 770 } 771 772 drm_crtc_vblank_put(crtc); 773 drm_framebuffer_put(flip_state->fb); 774 775 /* Decrement the BO usecnt in order to keep the inc/dec calls balanced 776 * when the planes are updated through the async update path. 777 * FIXME: we should move to generic async-page-flip when it's 778 * available, so that we can get rid of this hand-made cleanup_fb() 779 * logic. 780 */ 781 if (flip_state->old_fb) { 782 struct drm_gem_cma_object *cma_bo; 783 struct vc4_bo *bo; 784 785 cma_bo = drm_fb_cma_get_gem_obj(flip_state->old_fb, 0); 786 bo = to_vc4_bo(&cma_bo->base); 787 vc4_bo_dec_usecnt(bo); 788 drm_framebuffer_put(flip_state->old_fb); 789 } 790 791 kfree(flip_state); 792 793 up(&vc4->async_modeset); 794 } 795 796 /* Implements async (non-vblank-synced) page flips. 797 * 798 * The page flip ioctl needs to return immediately, so we grab the 799 * modeset semaphore on the pipe, and queue the address update for 800 * when V3D is done with the BO being flipped to. 801 */ 802 static int vc4_async_page_flip(struct drm_crtc *crtc, 803 struct drm_framebuffer *fb, 804 struct drm_pending_vblank_event *event, 805 uint32_t flags) 806 { 807 struct drm_device *dev = crtc->dev; 808 struct vc4_dev *vc4 = to_vc4_dev(dev); 809 struct drm_plane *plane = crtc->primary; 810 int ret = 0; 811 struct vc4_async_flip_state *flip_state; 812 struct drm_gem_cma_object *cma_bo = drm_fb_cma_get_gem_obj(fb, 0); 813 struct vc4_bo *bo = to_vc4_bo(&cma_bo->base); 814 815 /* Increment the BO usecnt here, so that we never end up with an 816 * unbalanced number of vc4_bo_{dec,inc}_usecnt() calls when the 817 * plane is later updated through the non-async path. 818 * FIXME: we should move to generic async-page-flip when it's 819 * available, so that we can get rid of this hand-made prepare_fb() 820 * logic. 821 */ 822 ret = vc4_bo_inc_usecnt(bo); 823 if (ret) 824 return ret; 825 826 flip_state = kzalloc(sizeof(*flip_state), GFP_KERNEL); 827 if (!flip_state) { 828 vc4_bo_dec_usecnt(bo); 829 return -ENOMEM; 830 } 831 832 drm_framebuffer_get(fb); 833 flip_state->fb = fb; 834 flip_state->crtc = crtc; 835 flip_state->event = event; 836 837 /* Make sure all other async modesetes have landed. */ 838 ret = down_interruptible(&vc4->async_modeset); 839 if (ret) { 840 drm_framebuffer_put(fb); 841 vc4_bo_dec_usecnt(bo); 842 kfree(flip_state); 843 return ret; 844 } 845 846 /* Save the current FB before it's replaced by the new one in 847 * drm_atomic_set_fb_for_plane(). We'll need the old FB in 848 * vc4_async_page_flip_complete() to decrement the BO usecnt and keep 849 * it consistent. 850 * FIXME: we should move to generic async-page-flip when it's 851 * available, so that we can get rid of this hand-made cleanup_fb() 852 * logic. 853 */ 854 flip_state->old_fb = plane->state->fb; 855 if (flip_state->old_fb) 856 drm_framebuffer_get(flip_state->old_fb); 857 858 WARN_ON(drm_crtc_vblank_get(crtc) != 0); 859 860 /* Immediately update the plane's legacy fb pointer, so that later 861 * modeset prep sees the state that will be present when the semaphore 862 * is released. 863 */ 864 drm_atomic_set_fb_for_plane(plane->state, fb); 865 866 vc4_queue_seqno_cb(dev, &flip_state->cb, bo->seqno, 867 vc4_async_page_flip_complete); 868 869 /* Driver takes ownership of state on successful async commit. */ 870 return 0; 871 } 872 873 static int vc4_page_flip(struct drm_crtc *crtc, 874 struct drm_framebuffer *fb, 875 struct drm_pending_vblank_event *event, 876 uint32_t flags, 877 struct drm_modeset_acquire_ctx *ctx) 878 { 879 if (flags & DRM_MODE_PAGE_FLIP_ASYNC) 880 return vc4_async_page_flip(crtc, fb, event, flags); 881 else 882 return drm_atomic_helper_page_flip(crtc, fb, event, flags, ctx); 883 } 884 885 static struct drm_crtc_state *vc4_crtc_duplicate_state(struct drm_crtc *crtc) 886 { 887 struct vc4_crtc_state *vc4_state; 888 889 vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL); 890 if (!vc4_state) 891 return NULL; 892 893 __drm_atomic_helper_crtc_duplicate_state(crtc, &vc4_state->base); 894 return &vc4_state->base; 895 } 896 897 static void vc4_crtc_destroy_state(struct drm_crtc *crtc, 898 struct drm_crtc_state *state) 899 { 900 struct vc4_dev *vc4 = to_vc4_dev(crtc->dev); 901 struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state); 902 903 if (vc4_state->mm.allocated) { 904 unsigned long flags; 905 906 spin_lock_irqsave(&vc4->hvs->mm_lock, flags); 907 drm_mm_remove_node(&vc4_state->mm); 908 spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags); 909 910 } 911 912 drm_atomic_helper_crtc_destroy_state(crtc, state); 913 } 914 915 static void 916 vc4_crtc_reset(struct drm_crtc *crtc) 917 { 918 if (crtc->state) 919 __drm_atomic_helper_crtc_destroy_state(crtc->state); 920 921 crtc->state = kzalloc(sizeof(struct vc4_crtc_state), GFP_KERNEL); 922 if (crtc->state) 923 crtc->state->crtc = crtc; 924 } 925 926 static const struct drm_crtc_funcs vc4_crtc_funcs = { 927 .set_config = drm_atomic_helper_set_config, 928 .destroy = vc4_crtc_destroy, 929 .page_flip = vc4_page_flip, 930 .set_property = NULL, 931 .cursor_set = NULL, /* handled by drm_mode_cursor_universal */ 932 .cursor_move = NULL, /* handled by drm_mode_cursor_universal */ 933 .reset = vc4_crtc_reset, 934 .atomic_duplicate_state = vc4_crtc_duplicate_state, 935 .atomic_destroy_state = vc4_crtc_destroy_state, 936 .gamma_set = drm_atomic_helper_legacy_gamma_set, 937 .enable_vblank = vc4_enable_vblank, 938 .disable_vblank = vc4_disable_vblank, 939 }; 940 941 static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = { 942 .mode_set_nofb = vc4_crtc_mode_set_nofb, 943 .mode_valid = vc4_crtc_mode_valid, 944 .atomic_check = vc4_crtc_atomic_check, 945 .atomic_flush = vc4_crtc_atomic_flush, 946 .atomic_enable = vc4_crtc_atomic_enable, 947 .atomic_disable = vc4_crtc_atomic_disable, 948 }; 949 950 static const struct vc4_crtc_data pv0_data = { 951 .hvs_channel = 0, 952 .encoder_types = { 953 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI0, 954 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_DPI, 955 }, 956 }; 957 958 static const struct vc4_crtc_data pv1_data = { 959 .hvs_channel = 2, 960 .encoder_types = { 961 [PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI1, 962 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_SMI, 963 }, 964 }; 965 966 static const struct vc4_crtc_data pv2_data = { 967 .hvs_channel = 1, 968 .encoder_types = { 969 [PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_HDMI, 970 [PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC, 971 }, 972 }; 973 974 static const struct of_device_id vc4_crtc_dt_match[] = { 975 { .compatible = "brcm,bcm2835-pixelvalve0", .data = &pv0_data }, 976 { .compatible = "brcm,bcm2835-pixelvalve1", .data = &pv1_data }, 977 { .compatible = "brcm,bcm2835-pixelvalve2", .data = &pv2_data }, 978 {} 979 }; 980 981 static void vc4_set_crtc_possible_masks(struct drm_device *drm, 982 struct drm_crtc *crtc) 983 { 984 struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc); 985 const struct vc4_crtc_data *crtc_data = vc4_crtc->data; 986 const enum vc4_encoder_type *encoder_types = crtc_data->encoder_types; 987 struct drm_encoder *encoder; 988 989 drm_for_each_encoder(encoder, drm) { 990 struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder); 991 int i; 992 993 for (i = 0; i < ARRAY_SIZE(crtc_data->encoder_types); i++) { 994 if (vc4_encoder->type == encoder_types[i]) { 995 vc4_encoder->clock_select = i; 996 encoder->possible_crtcs |= drm_crtc_mask(crtc); 997 break; 998 } 999 } 1000 } 1001 } 1002 1003 static void 1004 vc4_crtc_get_cob_allocation(struct vc4_crtc *vc4_crtc) 1005 { 1006 struct drm_device *drm = vc4_crtc->base.dev; 1007 struct vc4_dev *vc4 = to_vc4_dev(drm); 1008 u32 dispbase = HVS_READ(SCALER_DISPBASEX(vc4_crtc->channel)); 1009 /* Top/base are supposed to be 4-pixel aligned, but the 1010 * Raspberry Pi firmware fills the low bits (which are 1011 * presumably ignored). 1012 */ 1013 u32 top = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_TOP) & ~3; 1014 u32 base = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_BASE) & ~3; 1015 1016 vc4_crtc->cob_size = top - base + 4; 1017 } 1018 1019 static int vc4_crtc_bind(struct device *dev, struct device *master, void *data) 1020 { 1021 struct platform_device *pdev = to_platform_device(dev); 1022 struct drm_device *drm = dev_get_drvdata(master); 1023 struct vc4_crtc *vc4_crtc; 1024 struct drm_crtc *crtc; 1025 struct drm_plane *primary_plane, *cursor_plane, *destroy_plane, *temp; 1026 const struct of_device_id *match; 1027 int ret, i; 1028 1029 vc4_crtc = devm_kzalloc(dev, sizeof(*vc4_crtc), GFP_KERNEL); 1030 if (!vc4_crtc) 1031 return -ENOMEM; 1032 crtc = &vc4_crtc->base; 1033 1034 match = of_match_device(vc4_crtc_dt_match, dev); 1035 if (!match) 1036 return -ENODEV; 1037 vc4_crtc->data = match->data; 1038 1039 vc4_crtc->regs = vc4_ioremap_regs(pdev, 0); 1040 if (IS_ERR(vc4_crtc->regs)) 1041 return PTR_ERR(vc4_crtc->regs); 1042 1043 /* For now, we create just the primary and the legacy cursor 1044 * planes. We should be able to stack more planes on easily, 1045 * but to do that we would need to compute the bandwidth 1046 * requirement of the plane configuration, and reject ones 1047 * that will take too much. 1048 */ 1049 primary_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_PRIMARY); 1050 if (IS_ERR(primary_plane)) { 1051 dev_err(dev, "failed to construct primary plane\n"); 1052 ret = PTR_ERR(primary_plane); 1053 goto err; 1054 } 1055 1056 drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL, 1057 &vc4_crtc_funcs, NULL); 1058 drm_crtc_helper_add(crtc, &vc4_crtc_helper_funcs); 1059 vc4_crtc->channel = vc4_crtc->data->hvs_channel; 1060 drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r)); 1061 drm_crtc_enable_color_mgmt(crtc, 0, false, crtc->gamma_size); 1062 1063 /* We support CTM, but only for one CRTC at a time. It's therefore 1064 * implemented as private driver state in vc4_kms, not here. 1065 */ 1066 drm_crtc_enable_color_mgmt(crtc, 0, true, crtc->gamma_size); 1067 1068 /* Set up some arbitrary number of planes. We're not limited 1069 * by a set number of physical registers, just the space in 1070 * the HVS (16k) and how small an plane can be (28 bytes). 1071 * However, each plane we set up takes up some memory, and 1072 * increases the cost of looping over planes, which atomic 1073 * modesetting does quite a bit. As a result, we pick a 1074 * modest number of planes to expose, that should hopefully 1075 * still cover any sane usecase. 1076 */ 1077 for (i = 0; i < 8; i++) { 1078 struct drm_plane *plane = 1079 vc4_plane_init(drm, DRM_PLANE_TYPE_OVERLAY); 1080 1081 if (IS_ERR(plane)) 1082 continue; 1083 1084 plane->possible_crtcs = drm_crtc_mask(crtc); 1085 } 1086 1087 /* Set up the legacy cursor after overlay initialization, 1088 * since we overlay planes on the CRTC in the order they were 1089 * initialized. 1090 */ 1091 cursor_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_CURSOR); 1092 if (!IS_ERR(cursor_plane)) { 1093 cursor_plane->possible_crtcs = drm_crtc_mask(crtc); 1094 crtc->cursor = cursor_plane; 1095 } 1096 1097 vc4_crtc_get_cob_allocation(vc4_crtc); 1098 1099 CRTC_WRITE(PV_INTEN, 0); 1100 CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START); 1101 ret = devm_request_irq(dev, platform_get_irq(pdev, 0), 1102 vc4_crtc_irq_handler, 0, "vc4 crtc", vc4_crtc); 1103 if (ret) 1104 goto err_destroy_planes; 1105 1106 vc4_set_crtc_possible_masks(drm, crtc); 1107 1108 for (i = 0; i < crtc->gamma_size; i++) { 1109 vc4_crtc->lut_r[i] = i; 1110 vc4_crtc->lut_g[i] = i; 1111 vc4_crtc->lut_b[i] = i; 1112 } 1113 1114 platform_set_drvdata(pdev, vc4_crtc); 1115 1116 return 0; 1117 1118 err_destroy_planes: 1119 list_for_each_entry_safe(destroy_plane, temp, 1120 &drm->mode_config.plane_list, head) { 1121 if (destroy_plane->possible_crtcs == drm_crtc_mask(crtc)) 1122 destroy_plane->funcs->destroy(destroy_plane); 1123 } 1124 err: 1125 return ret; 1126 } 1127 1128 static void vc4_crtc_unbind(struct device *dev, struct device *master, 1129 void *data) 1130 { 1131 struct platform_device *pdev = to_platform_device(dev); 1132 struct vc4_crtc *vc4_crtc = dev_get_drvdata(dev); 1133 1134 vc4_crtc_destroy(&vc4_crtc->base); 1135 1136 CRTC_WRITE(PV_INTEN, 0); 1137 1138 platform_set_drvdata(pdev, NULL); 1139 } 1140 1141 static const struct component_ops vc4_crtc_ops = { 1142 .bind = vc4_crtc_bind, 1143 .unbind = vc4_crtc_unbind, 1144 }; 1145 1146 static int vc4_crtc_dev_probe(struct platform_device *pdev) 1147 { 1148 return component_add(&pdev->dev, &vc4_crtc_ops); 1149 } 1150 1151 static int vc4_crtc_dev_remove(struct platform_device *pdev) 1152 { 1153 component_del(&pdev->dev, &vc4_crtc_ops); 1154 return 0; 1155 } 1156 1157 struct platform_driver vc4_crtc_driver = { 1158 .probe = vc4_crtc_dev_probe, 1159 .remove = vc4_crtc_dev_remove, 1160 .driver = { 1161 .name = "vc4_crtc", 1162 .of_match_table = vc4_crtc_dt_match, 1163 }, 1164 }; 1165