xref: /openbmc/linux/drivers/gpu/drm/vc4/vc4_crtc.c (revision a6ca5ac746d104019e76c29e69c2a1fc6dd2b29f)
1 /*
2  * Copyright (C) 2015 Broadcom
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License version 2 as
6  * published by the Free Software Foundation.
7  */
8 
9 /**
10  * DOC: VC4 CRTC module
11  *
12  * In VC4, the Pixel Valve is what most closely corresponds to the
13  * DRM's concept of a CRTC.  The PV generates video timings from the
14  * encoder's clock plus its configuration.  It pulls scaled pixels from
15  * the HVS at that timing, and feeds it to the encoder.
16  *
17  * However, the DRM CRTC also collects the configuration of all the
18  * DRM planes attached to it.  As a result, the CRTC is also
19  * responsible for writing the display list for the HVS channel that
20  * the CRTC will use.
21  *
22  * The 2835 has 3 different pixel valves.  pv0 in the audio power
23  * domain feeds DSI0 or DPI, while pv1 feeds DS1 or SMI.  pv2 in the
24  * image domain can feed either HDMI or the SDTV controller.  The
25  * pixel valve chooses from the CPRMAN clocks (HSM for HDMI, VEC for
26  * SDTV, etc.) according to which output type is chosen in the mux.
27  *
28  * For power management, the pixel valve's registers are all clocked
29  * by the AXI clock, while the timings and FIFOs make use of the
30  * output-specific clock.  Since the encoders also directly consume
31  * the CPRMAN clocks, and know what timings they need, they are the
32  * ones that set the clock.
33  */
34 
35 #include "drm_atomic.h"
36 #include "drm_atomic_helper.h"
37 #include "drm_crtc_helper.h"
38 #include "linux/clk.h"
39 #include "drm_fb_cma_helper.h"
40 #include "linux/component.h"
41 #include "linux/of_device.h"
42 #include "vc4_drv.h"
43 #include "vc4_regs.h"
44 
45 struct vc4_crtc {
46 	struct drm_crtc base;
47 	const struct vc4_crtc_data *data;
48 	void __iomem *regs;
49 
50 	/* Timestamp at start of vblank irq - unaffected by lock delays. */
51 	ktime_t t_vblank;
52 
53 	/* Which HVS channel we're using for our CRTC. */
54 	int channel;
55 
56 	u8 lut_r[256];
57 	u8 lut_g[256];
58 	u8 lut_b[256];
59 	/* Size in pixels of the COB memory allocated to this CRTC. */
60 	u32 cob_size;
61 
62 	struct drm_pending_vblank_event *event;
63 };
64 
65 struct vc4_crtc_state {
66 	struct drm_crtc_state base;
67 	/* Dlist area for this CRTC configuration. */
68 	struct drm_mm_node mm;
69 };
70 
71 static inline struct vc4_crtc *
72 to_vc4_crtc(struct drm_crtc *crtc)
73 {
74 	return (struct vc4_crtc *)crtc;
75 }
76 
77 static inline struct vc4_crtc_state *
78 to_vc4_crtc_state(struct drm_crtc_state *crtc_state)
79 {
80 	return (struct vc4_crtc_state *)crtc_state;
81 }
82 
83 struct vc4_crtc_data {
84 	/* Which channel of the HVS this pixelvalve sources from. */
85 	int hvs_channel;
86 
87 	enum vc4_encoder_type encoder_types[4];
88 };
89 
90 #define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset))
91 #define CRTC_READ(offset) readl(vc4_crtc->regs + (offset))
92 
93 #define CRTC_REG(reg) { reg, #reg }
94 static const struct {
95 	u32 reg;
96 	const char *name;
97 } crtc_regs[] = {
98 	CRTC_REG(PV_CONTROL),
99 	CRTC_REG(PV_V_CONTROL),
100 	CRTC_REG(PV_VSYNCD_EVEN),
101 	CRTC_REG(PV_HORZA),
102 	CRTC_REG(PV_HORZB),
103 	CRTC_REG(PV_VERTA),
104 	CRTC_REG(PV_VERTB),
105 	CRTC_REG(PV_VERTA_EVEN),
106 	CRTC_REG(PV_VERTB_EVEN),
107 	CRTC_REG(PV_INTEN),
108 	CRTC_REG(PV_INTSTAT),
109 	CRTC_REG(PV_STAT),
110 	CRTC_REG(PV_HACT_ACT),
111 };
112 
113 static void vc4_crtc_dump_regs(struct vc4_crtc *vc4_crtc)
114 {
115 	int i;
116 
117 	for (i = 0; i < ARRAY_SIZE(crtc_regs); i++) {
118 		DRM_INFO("0x%04x (%s): 0x%08x\n",
119 			 crtc_regs[i].reg, crtc_regs[i].name,
120 			 CRTC_READ(crtc_regs[i].reg));
121 	}
122 }
123 
124 #ifdef CONFIG_DEBUG_FS
125 int vc4_crtc_debugfs_regs(struct seq_file *m, void *unused)
126 {
127 	struct drm_info_node *node = (struct drm_info_node *)m->private;
128 	struct drm_device *dev = node->minor->dev;
129 	int crtc_index = (uintptr_t)node->info_ent->data;
130 	struct drm_crtc *crtc;
131 	struct vc4_crtc *vc4_crtc;
132 	int i;
133 
134 	i = 0;
135 	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
136 		if (i == crtc_index)
137 			break;
138 		i++;
139 	}
140 	if (!crtc)
141 		return 0;
142 	vc4_crtc = to_vc4_crtc(crtc);
143 
144 	for (i = 0; i < ARRAY_SIZE(crtc_regs); i++) {
145 		seq_printf(m, "%s (0x%04x): 0x%08x\n",
146 			   crtc_regs[i].name, crtc_regs[i].reg,
147 			   CRTC_READ(crtc_regs[i].reg));
148 	}
149 
150 	return 0;
151 }
152 #endif
153 
154 bool vc4_crtc_get_scanoutpos(struct drm_device *dev, unsigned int crtc_id,
155 			     bool in_vblank_irq, int *vpos, int *hpos,
156 			     ktime_t *stime, ktime_t *etime,
157 			     const struct drm_display_mode *mode)
158 {
159 	struct vc4_dev *vc4 = to_vc4_dev(dev);
160 	struct drm_crtc *crtc = drm_crtc_from_index(dev, crtc_id);
161 	struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
162 	u32 val;
163 	int fifo_lines;
164 	int vblank_lines;
165 	bool ret = false;
166 
167 	/* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
168 
169 	/* Get optional system timestamp before query. */
170 	if (stime)
171 		*stime = ktime_get();
172 
173 	/*
174 	 * Read vertical scanline which is currently composed for our
175 	 * pixelvalve by the HVS, and also the scaler status.
176 	 */
177 	val = HVS_READ(SCALER_DISPSTATX(vc4_crtc->channel));
178 
179 	/* Get optional system timestamp after query. */
180 	if (etime)
181 		*etime = ktime_get();
182 
183 	/* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
184 
185 	/* Vertical position of hvs composed scanline. */
186 	*vpos = VC4_GET_FIELD(val, SCALER_DISPSTATX_LINE);
187 	*hpos = 0;
188 
189 	if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
190 		*vpos /= 2;
191 
192 		/* Use hpos to correct for field offset in interlaced mode. */
193 		if (VC4_GET_FIELD(val, SCALER_DISPSTATX_FRAME_COUNT) % 2)
194 			*hpos += mode->crtc_htotal / 2;
195 	}
196 
197 	/* This is the offset we need for translating hvs -> pv scanout pos. */
198 	fifo_lines = vc4_crtc->cob_size / mode->crtc_hdisplay;
199 
200 	if (fifo_lines > 0)
201 		ret = true;
202 
203 	/* HVS more than fifo_lines into frame for compositing? */
204 	if (*vpos > fifo_lines) {
205 		/*
206 		 * We are in active scanout and can get some meaningful results
207 		 * from HVS. The actual PV scanout can not trail behind more
208 		 * than fifo_lines as that is the fifo's capacity. Assume that
209 		 * in active scanout the HVS and PV work in lockstep wrt. HVS
210 		 * refilling the fifo and PV consuming from the fifo, ie.
211 		 * whenever the PV consumes and frees up a scanline in the
212 		 * fifo, the HVS will immediately refill it, therefore
213 		 * incrementing vpos. Therefore we choose HVS read position -
214 		 * fifo size in scanlines as a estimate of the real scanout
215 		 * position of the PV.
216 		 */
217 		*vpos -= fifo_lines + 1;
218 
219 		return ret;
220 	}
221 
222 	/*
223 	 * Less: This happens when we are in vblank and the HVS, after getting
224 	 * the VSTART restart signal from the PV, just started refilling its
225 	 * fifo with new lines from the top-most lines of the new framebuffers.
226 	 * The PV does not scan out in vblank, so does not remove lines from
227 	 * the fifo, so the fifo will be full quickly and the HVS has to pause.
228 	 * We can't get meaningful readings wrt. scanline position of the PV
229 	 * and need to make things up in a approximative but consistent way.
230 	 */
231 	vblank_lines = mode->vtotal - mode->vdisplay;
232 
233 	if (in_vblank_irq) {
234 		/*
235 		 * Assume the irq handler got called close to first
236 		 * line of vblank, so PV has about a full vblank
237 		 * scanlines to go, and as a base timestamp use the
238 		 * one taken at entry into vblank irq handler, so it
239 		 * is not affected by random delays due to lock
240 		 * contention on event_lock or vblank_time lock in
241 		 * the core.
242 		 */
243 		*vpos = -vblank_lines;
244 
245 		if (stime)
246 			*stime = vc4_crtc->t_vblank;
247 		if (etime)
248 			*etime = vc4_crtc->t_vblank;
249 
250 		/*
251 		 * If the HVS fifo is not yet full then we know for certain
252 		 * we are at the very beginning of vblank, as the hvs just
253 		 * started refilling, and the stime and etime timestamps
254 		 * truly correspond to start of vblank.
255 		 *
256 		 * Unfortunately there's no way to report this to upper levels
257 		 * and make it more useful.
258 		 */
259 	} else {
260 		/*
261 		 * No clue where we are inside vblank. Return a vpos of zero,
262 		 * which will cause calling code to just return the etime
263 		 * timestamp uncorrected. At least this is no worse than the
264 		 * standard fallback.
265 		 */
266 		*vpos = 0;
267 	}
268 
269 	return ret;
270 }
271 
272 static void vc4_crtc_destroy(struct drm_crtc *crtc)
273 {
274 	drm_crtc_cleanup(crtc);
275 }
276 
277 static void
278 vc4_crtc_lut_load(struct drm_crtc *crtc)
279 {
280 	struct drm_device *dev = crtc->dev;
281 	struct vc4_dev *vc4 = to_vc4_dev(dev);
282 	struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
283 	u32 i;
284 
285 	/* The LUT memory is laid out with each HVS channel in order,
286 	 * each of which takes 256 writes for R, 256 for G, then 256
287 	 * for B.
288 	 */
289 	HVS_WRITE(SCALER_GAMADDR,
290 		  SCALER_GAMADDR_AUTOINC |
291 		  (vc4_crtc->channel * 3 * crtc->gamma_size));
292 
293 	for (i = 0; i < crtc->gamma_size; i++)
294 		HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_r[i]);
295 	for (i = 0; i < crtc->gamma_size; i++)
296 		HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_g[i]);
297 	for (i = 0; i < crtc->gamma_size; i++)
298 		HVS_WRITE(SCALER_GAMDATA, vc4_crtc->lut_b[i]);
299 }
300 
301 static int
302 vc4_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b,
303 		   uint32_t size,
304 		   struct drm_modeset_acquire_ctx *ctx)
305 {
306 	struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
307 	u32 i;
308 
309 	for (i = 0; i < size; i++) {
310 		vc4_crtc->lut_r[i] = r[i] >> 8;
311 		vc4_crtc->lut_g[i] = g[i] >> 8;
312 		vc4_crtc->lut_b[i] = b[i] >> 8;
313 	}
314 
315 	vc4_crtc_lut_load(crtc);
316 
317 	return 0;
318 }
319 
320 static u32 vc4_get_fifo_full_level(u32 format)
321 {
322 	static const u32 fifo_len_bytes = 64;
323 	static const u32 hvs_latency_pix = 6;
324 
325 	switch (format) {
326 	case PV_CONTROL_FORMAT_DSIV_16:
327 	case PV_CONTROL_FORMAT_DSIC_16:
328 		return fifo_len_bytes - 2 * hvs_latency_pix;
329 	case PV_CONTROL_FORMAT_DSIV_18:
330 		return fifo_len_bytes - 14;
331 	case PV_CONTROL_FORMAT_24:
332 	case PV_CONTROL_FORMAT_DSIV_24:
333 	default:
334 		return fifo_len_bytes - 3 * hvs_latency_pix;
335 	}
336 }
337 
338 /*
339  * Returns the encoder attached to the CRTC.
340  *
341  * VC4 can only scan out to one encoder at a time, while the DRM core
342  * allows drivers to push pixels to more than one encoder from the
343  * same CRTC.
344  */
345 static struct drm_encoder *vc4_get_crtc_encoder(struct drm_crtc *crtc)
346 {
347 	struct drm_connector *connector;
348 
349 	drm_for_each_connector(connector, crtc->dev) {
350 		if (connector->state->crtc == crtc) {
351 			return connector->encoder;
352 		}
353 	}
354 
355 	return NULL;
356 }
357 
358 static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
359 {
360 	struct drm_device *dev = crtc->dev;
361 	struct vc4_dev *vc4 = to_vc4_dev(dev);
362 	struct drm_encoder *encoder = vc4_get_crtc_encoder(crtc);
363 	struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
364 	struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
365 	struct drm_crtc_state *state = crtc->state;
366 	struct drm_display_mode *mode = &state->adjusted_mode;
367 	bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
368 	u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
369 	bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 ||
370 		       vc4_encoder->type == VC4_ENCODER_TYPE_DSI1);
371 	u32 format = is_dsi ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24;
372 	bool debug_dump_regs = false;
373 
374 	if (debug_dump_regs) {
375 		DRM_INFO("CRTC %d regs before:\n", drm_crtc_index(crtc));
376 		vc4_crtc_dump_regs(vc4_crtc);
377 	}
378 
379 	/* Reset the PV fifo. */
380 	CRTC_WRITE(PV_CONTROL, 0);
381 	CRTC_WRITE(PV_CONTROL, PV_CONTROL_FIFO_CLR | PV_CONTROL_EN);
382 	CRTC_WRITE(PV_CONTROL, 0);
383 
384 	CRTC_WRITE(PV_HORZA,
385 		   VC4_SET_FIELD((mode->htotal -
386 				  mode->hsync_end) * pixel_rep,
387 				 PV_HORZA_HBP) |
388 		   VC4_SET_FIELD((mode->hsync_end -
389 				  mode->hsync_start) * pixel_rep,
390 				 PV_HORZA_HSYNC));
391 	CRTC_WRITE(PV_HORZB,
392 		   VC4_SET_FIELD((mode->hsync_start -
393 				  mode->hdisplay) * pixel_rep,
394 				 PV_HORZB_HFP) |
395 		   VC4_SET_FIELD(mode->hdisplay * pixel_rep, PV_HORZB_HACTIVE));
396 
397 	CRTC_WRITE(PV_VERTA,
398 		   VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
399 				 PV_VERTA_VBP) |
400 		   VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
401 				 PV_VERTA_VSYNC));
402 	CRTC_WRITE(PV_VERTB,
403 		   VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
404 				 PV_VERTB_VFP) |
405 		   VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
406 
407 	if (interlace) {
408 		CRTC_WRITE(PV_VERTA_EVEN,
409 			   VC4_SET_FIELD(mode->crtc_vtotal -
410 					 mode->crtc_vsync_end - 1,
411 					 PV_VERTA_VBP) |
412 			   VC4_SET_FIELD(mode->crtc_vsync_end -
413 					 mode->crtc_vsync_start,
414 					 PV_VERTA_VSYNC));
415 		CRTC_WRITE(PV_VERTB_EVEN,
416 			   VC4_SET_FIELD(mode->crtc_vsync_start -
417 					 mode->crtc_vdisplay,
418 					 PV_VERTB_VFP) |
419 			   VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
420 
421 		/* We set up first field even mode for HDMI.  VEC's
422 		 * NTSC mode would want first field odd instead, once
423 		 * we support it (to do so, set ODD_FIRST and put the
424 		 * delay in VSYNCD_EVEN instead).
425 		 */
426 		CRTC_WRITE(PV_V_CONTROL,
427 			   PV_VCONTROL_CONTINUOUS |
428 			   (is_dsi ? PV_VCONTROL_DSI : 0) |
429 			   PV_VCONTROL_INTERLACE |
430 			   VC4_SET_FIELD(mode->htotal * pixel_rep / 2,
431 					 PV_VCONTROL_ODD_DELAY));
432 		CRTC_WRITE(PV_VSYNCD_EVEN, 0);
433 	} else {
434 		CRTC_WRITE(PV_V_CONTROL,
435 			   PV_VCONTROL_CONTINUOUS |
436 			   (is_dsi ? PV_VCONTROL_DSI : 0));
437 	}
438 
439 	CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep);
440 
441 	CRTC_WRITE(PV_CONTROL,
442 		   VC4_SET_FIELD(format, PV_CONTROL_FORMAT) |
443 		   VC4_SET_FIELD(vc4_get_fifo_full_level(format),
444 				 PV_CONTROL_FIFO_LEVEL) |
445 		   VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) |
446 		   PV_CONTROL_CLR_AT_START |
447 		   PV_CONTROL_TRIGGER_UNDERFLOW |
448 		   PV_CONTROL_WAIT_HSTART |
449 		   VC4_SET_FIELD(vc4_encoder->clock_select,
450 				 PV_CONTROL_CLK_SELECT) |
451 		   PV_CONTROL_FIFO_CLR |
452 		   PV_CONTROL_EN);
453 
454 	HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel),
455 		  SCALER_DISPBKGND_AUTOHS |
456 		  SCALER_DISPBKGND_GAMMA |
457 		  (interlace ? SCALER_DISPBKGND_INTERLACE : 0));
458 
459 	/* Reload the LUT, since the SRAMs would have been disabled if
460 	 * all CRTCs had SCALER_DISPBKGND_GAMMA unset at once.
461 	 */
462 	vc4_crtc_lut_load(crtc);
463 
464 	if (debug_dump_regs) {
465 		DRM_INFO("CRTC %d regs after:\n", drm_crtc_index(crtc));
466 		vc4_crtc_dump_regs(vc4_crtc);
467 	}
468 }
469 
470 static void require_hvs_enabled(struct drm_device *dev)
471 {
472 	struct vc4_dev *vc4 = to_vc4_dev(dev);
473 
474 	WARN_ON_ONCE((HVS_READ(SCALER_DISPCTRL) & SCALER_DISPCTRL_ENABLE) !=
475 		     SCALER_DISPCTRL_ENABLE);
476 }
477 
478 static void vc4_crtc_disable(struct drm_crtc *crtc)
479 {
480 	struct drm_device *dev = crtc->dev;
481 	struct vc4_dev *vc4 = to_vc4_dev(dev);
482 	struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
483 	u32 chan = vc4_crtc->channel;
484 	int ret;
485 	require_hvs_enabled(dev);
486 
487 	/* Disable vblank irq handling before crtc is disabled. */
488 	drm_crtc_vblank_off(crtc);
489 
490 	CRTC_WRITE(PV_V_CONTROL,
491 		   CRTC_READ(PV_V_CONTROL) & ~PV_VCONTROL_VIDEN);
492 	ret = wait_for(!(CRTC_READ(PV_V_CONTROL) & PV_VCONTROL_VIDEN), 1);
493 	WARN_ONCE(ret, "Timeout waiting for !PV_VCONTROL_VIDEN\n");
494 
495 	if (HVS_READ(SCALER_DISPCTRLX(chan)) &
496 	    SCALER_DISPCTRLX_ENABLE) {
497 		HVS_WRITE(SCALER_DISPCTRLX(chan),
498 			  SCALER_DISPCTRLX_RESET);
499 
500 		/* While the docs say that reset is self-clearing, it
501 		 * seems it doesn't actually.
502 		 */
503 		HVS_WRITE(SCALER_DISPCTRLX(chan), 0);
504 	}
505 
506 	/* Once we leave, the scaler should be disabled and its fifo empty. */
507 
508 	WARN_ON_ONCE(HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_RESET);
509 
510 	WARN_ON_ONCE(VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(chan)),
511 				   SCALER_DISPSTATX_MODE) !=
512 		     SCALER_DISPSTATX_MODE_DISABLED);
513 
514 	WARN_ON_ONCE((HVS_READ(SCALER_DISPSTATX(chan)) &
515 		      (SCALER_DISPSTATX_FULL | SCALER_DISPSTATX_EMPTY)) !=
516 		     SCALER_DISPSTATX_EMPTY);
517 }
518 
519 static void vc4_crtc_enable(struct drm_crtc *crtc)
520 {
521 	struct drm_device *dev = crtc->dev;
522 	struct vc4_dev *vc4 = to_vc4_dev(dev);
523 	struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
524 	struct drm_crtc_state *state = crtc->state;
525 	struct drm_display_mode *mode = &state->adjusted_mode;
526 
527 	require_hvs_enabled(dev);
528 
529 	/* Turn on the scaler, which will wait for vstart to start
530 	 * compositing.
531 	 */
532 	HVS_WRITE(SCALER_DISPCTRLX(vc4_crtc->channel),
533 		  VC4_SET_FIELD(mode->hdisplay, SCALER_DISPCTRLX_WIDTH) |
534 		  VC4_SET_FIELD(mode->vdisplay, SCALER_DISPCTRLX_HEIGHT) |
535 		  SCALER_DISPCTRLX_ENABLE);
536 
537 	/* Turn on the pixel valve, which will emit the vstart signal. */
538 	CRTC_WRITE(PV_V_CONTROL,
539 		   CRTC_READ(PV_V_CONTROL) | PV_VCONTROL_VIDEN);
540 
541 	/* Enable vblank irq handling after crtc is started. */
542 	drm_crtc_vblank_on(crtc);
543 }
544 
545 static bool vc4_crtc_mode_fixup(struct drm_crtc *crtc,
546 				const struct drm_display_mode *mode,
547 				struct drm_display_mode *adjusted_mode)
548 {
549 	/* Do not allow doublescan modes from user space */
550 	if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) {
551 		DRM_DEBUG_KMS("[CRTC:%d] Doublescan mode rejected.\n",
552 			      crtc->base.id);
553 		return false;
554 	}
555 
556 	return true;
557 }
558 
559 static int vc4_crtc_atomic_check(struct drm_crtc *crtc,
560 				 struct drm_crtc_state *state)
561 {
562 	struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
563 	struct drm_device *dev = crtc->dev;
564 	struct vc4_dev *vc4 = to_vc4_dev(dev);
565 	struct drm_plane *plane;
566 	unsigned long flags;
567 	const struct drm_plane_state *plane_state;
568 	u32 dlist_count = 0;
569 	int ret;
570 
571 	/* The pixelvalve can only feed one encoder (and encoders are
572 	 * 1:1 with connectors.)
573 	 */
574 	if (hweight32(state->connector_mask) > 1)
575 		return -EINVAL;
576 
577 	drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, state)
578 		dlist_count += vc4_plane_dlist_size(plane_state);
579 
580 	dlist_count++; /* Account for SCALER_CTL0_END. */
581 
582 	spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
583 	ret = drm_mm_insert_node(&vc4->hvs->dlist_mm, &vc4_state->mm,
584 				 dlist_count);
585 	spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
586 	if (ret)
587 		return ret;
588 
589 	return 0;
590 }
591 
592 static void vc4_crtc_atomic_flush(struct drm_crtc *crtc,
593 				  struct drm_crtc_state *old_state)
594 {
595 	struct drm_device *dev = crtc->dev;
596 	struct vc4_dev *vc4 = to_vc4_dev(dev);
597 	struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
598 	struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
599 	struct drm_plane *plane;
600 	bool debug_dump_regs = false;
601 	u32 __iomem *dlist_start = vc4->hvs->dlist + vc4_state->mm.start;
602 	u32 __iomem *dlist_next = dlist_start;
603 
604 	if (debug_dump_regs) {
605 		DRM_INFO("CRTC %d HVS before:\n", drm_crtc_index(crtc));
606 		vc4_hvs_dump_state(dev);
607 	}
608 
609 	/* Copy all the active planes' dlist contents to the hardware dlist. */
610 	drm_atomic_crtc_for_each_plane(plane, crtc) {
611 		dlist_next += vc4_plane_write_dlist(plane, dlist_next);
612 	}
613 
614 	writel(SCALER_CTL0_END, dlist_next);
615 	dlist_next++;
616 
617 	WARN_ON_ONCE(dlist_next - dlist_start != vc4_state->mm.size);
618 
619 	if (crtc->state->event) {
620 		unsigned long flags;
621 
622 		crtc->state->event->pipe = drm_crtc_index(crtc);
623 
624 		WARN_ON(drm_crtc_vblank_get(crtc) != 0);
625 
626 		spin_lock_irqsave(&dev->event_lock, flags);
627 		vc4_crtc->event = crtc->state->event;
628 		crtc->state->event = NULL;
629 
630 		HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
631 			  vc4_state->mm.start);
632 
633 		spin_unlock_irqrestore(&dev->event_lock, flags);
634 	} else {
635 		HVS_WRITE(SCALER_DISPLISTX(vc4_crtc->channel),
636 			  vc4_state->mm.start);
637 	}
638 
639 	if (debug_dump_regs) {
640 		DRM_INFO("CRTC %d HVS after:\n", drm_crtc_index(crtc));
641 		vc4_hvs_dump_state(dev);
642 	}
643 }
644 
645 static int vc4_enable_vblank(struct drm_crtc *crtc)
646 {
647 	struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
648 
649 	CRTC_WRITE(PV_INTEN, PV_INT_VFP_START);
650 
651 	return 0;
652 }
653 
654 static void vc4_disable_vblank(struct drm_crtc *crtc)
655 {
656 	struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
657 
658 	CRTC_WRITE(PV_INTEN, 0);
659 }
660 
661 /* Must be called with the event lock held */
662 bool vc4_event_pending(struct drm_crtc *crtc)
663 {
664 	struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
665 
666 	return !!vc4_crtc->event;
667 }
668 
669 static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc)
670 {
671 	struct drm_crtc *crtc = &vc4_crtc->base;
672 	struct drm_device *dev = crtc->dev;
673 	struct vc4_dev *vc4 = to_vc4_dev(dev);
674 	struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(crtc->state);
675 	u32 chan = vc4_crtc->channel;
676 	unsigned long flags;
677 
678 	spin_lock_irqsave(&dev->event_lock, flags);
679 	if (vc4_crtc->event &&
680 	    (vc4_state->mm.start == HVS_READ(SCALER_DISPLACTX(chan)))) {
681 		drm_crtc_send_vblank_event(crtc, vc4_crtc->event);
682 		vc4_crtc->event = NULL;
683 		drm_crtc_vblank_put(crtc);
684 	}
685 	spin_unlock_irqrestore(&dev->event_lock, flags);
686 }
687 
688 static irqreturn_t vc4_crtc_irq_handler(int irq, void *data)
689 {
690 	struct vc4_crtc *vc4_crtc = data;
691 	u32 stat = CRTC_READ(PV_INTSTAT);
692 	irqreturn_t ret = IRQ_NONE;
693 
694 	if (stat & PV_INT_VFP_START) {
695 		vc4_crtc->t_vblank = ktime_get();
696 		CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
697 		drm_crtc_handle_vblank(&vc4_crtc->base);
698 		vc4_crtc_handle_page_flip(vc4_crtc);
699 		ret = IRQ_HANDLED;
700 	}
701 
702 	return ret;
703 }
704 
705 struct vc4_async_flip_state {
706 	struct drm_crtc *crtc;
707 	struct drm_framebuffer *fb;
708 	struct drm_pending_vblank_event *event;
709 
710 	struct vc4_seqno_cb cb;
711 };
712 
713 /* Called when the V3D execution for the BO being flipped to is done, so that
714  * we can actually update the plane's address to point to it.
715  */
716 static void
717 vc4_async_page_flip_complete(struct vc4_seqno_cb *cb)
718 {
719 	struct vc4_async_flip_state *flip_state =
720 		container_of(cb, struct vc4_async_flip_state, cb);
721 	struct drm_crtc *crtc = flip_state->crtc;
722 	struct drm_device *dev = crtc->dev;
723 	struct vc4_dev *vc4 = to_vc4_dev(dev);
724 	struct drm_plane *plane = crtc->primary;
725 
726 	vc4_plane_async_set_fb(plane, flip_state->fb);
727 	if (flip_state->event) {
728 		unsigned long flags;
729 
730 		spin_lock_irqsave(&dev->event_lock, flags);
731 		drm_crtc_send_vblank_event(crtc, flip_state->event);
732 		spin_unlock_irqrestore(&dev->event_lock, flags);
733 	}
734 
735 	drm_crtc_vblank_put(crtc);
736 	drm_framebuffer_unreference(flip_state->fb);
737 	kfree(flip_state);
738 
739 	up(&vc4->async_modeset);
740 }
741 
742 /* Implements async (non-vblank-synced) page flips.
743  *
744  * The page flip ioctl needs to return immediately, so we grab the
745  * modeset semaphore on the pipe, and queue the address update for
746  * when V3D is done with the BO being flipped to.
747  */
748 static int vc4_async_page_flip(struct drm_crtc *crtc,
749 			       struct drm_framebuffer *fb,
750 			       struct drm_pending_vblank_event *event,
751 			       uint32_t flags)
752 {
753 	struct drm_device *dev = crtc->dev;
754 	struct vc4_dev *vc4 = to_vc4_dev(dev);
755 	struct drm_plane *plane = crtc->primary;
756 	int ret = 0;
757 	struct vc4_async_flip_state *flip_state;
758 	struct drm_gem_cma_object *cma_bo = drm_fb_cma_get_gem_obj(fb, 0);
759 	struct vc4_bo *bo = to_vc4_bo(&cma_bo->base);
760 
761 	flip_state = kzalloc(sizeof(*flip_state), GFP_KERNEL);
762 	if (!flip_state)
763 		return -ENOMEM;
764 
765 	drm_framebuffer_reference(fb);
766 	flip_state->fb = fb;
767 	flip_state->crtc = crtc;
768 	flip_state->event = event;
769 
770 	/* Make sure all other async modesetes have landed. */
771 	ret = down_interruptible(&vc4->async_modeset);
772 	if (ret) {
773 		drm_framebuffer_unreference(fb);
774 		kfree(flip_state);
775 		return ret;
776 	}
777 
778 	WARN_ON(drm_crtc_vblank_get(crtc) != 0);
779 
780 	/* Immediately update the plane's legacy fb pointer, so that later
781 	 * modeset prep sees the state that will be present when the semaphore
782 	 * is released.
783 	 */
784 	drm_atomic_set_fb_for_plane(plane->state, fb);
785 	plane->fb = fb;
786 
787 	vc4_queue_seqno_cb(dev, &flip_state->cb, bo->seqno,
788 			   vc4_async_page_flip_complete);
789 
790 	/* Driver takes ownership of state on successful async commit. */
791 	return 0;
792 }
793 
794 static int vc4_page_flip(struct drm_crtc *crtc,
795 			 struct drm_framebuffer *fb,
796 			 struct drm_pending_vblank_event *event,
797 			 uint32_t flags,
798 			 struct drm_modeset_acquire_ctx *ctx)
799 {
800 	if (flags & DRM_MODE_PAGE_FLIP_ASYNC)
801 		return vc4_async_page_flip(crtc, fb, event, flags);
802 	else
803 		return drm_atomic_helper_page_flip(crtc, fb, event, flags, ctx);
804 }
805 
806 static struct drm_crtc_state *vc4_crtc_duplicate_state(struct drm_crtc *crtc)
807 {
808 	struct vc4_crtc_state *vc4_state;
809 
810 	vc4_state = kzalloc(sizeof(*vc4_state), GFP_KERNEL);
811 	if (!vc4_state)
812 		return NULL;
813 
814 	__drm_atomic_helper_crtc_duplicate_state(crtc, &vc4_state->base);
815 	return &vc4_state->base;
816 }
817 
818 static void vc4_crtc_destroy_state(struct drm_crtc *crtc,
819 				   struct drm_crtc_state *state)
820 {
821 	struct vc4_dev *vc4 = to_vc4_dev(crtc->dev);
822 	struct vc4_crtc_state *vc4_state = to_vc4_crtc_state(state);
823 
824 	if (vc4_state->mm.allocated) {
825 		unsigned long flags;
826 
827 		spin_lock_irqsave(&vc4->hvs->mm_lock, flags);
828 		drm_mm_remove_node(&vc4_state->mm);
829 		spin_unlock_irqrestore(&vc4->hvs->mm_lock, flags);
830 
831 	}
832 
833 	drm_atomic_helper_crtc_destroy_state(crtc, state);
834 }
835 
836 static void
837 vc4_crtc_reset(struct drm_crtc *crtc)
838 {
839 	if (crtc->state)
840 		__drm_atomic_helper_crtc_destroy_state(crtc->state);
841 
842 	crtc->state = kzalloc(sizeof(struct vc4_crtc_state), GFP_KERNEL);
843 	if (crtc->state)
844 		crtc->state->crtc = crtc;
845 }
846 
847 static const struct drm_crtc_funcs vc4_crtc_funcs = {
848 	.set_config = drm_atomic_helper_set_config,
849 	.destroy = vc4_crtc_destroy,
850 	.page_flip = vc4_page_flip,
851 	.set_property = NULL,
852 	.cursor_set = NULL, /* handled by drm_mode_cursor_universal */
853 	.cursor_move = NULL, /* handled by drm_mode_cursor_universal */
854 	.reset = vc4_crtc_reset,
855 	.atomic_duplicate_state = vc4_crtc_duplicate_state,
856 	.atomic_destroy_state = vc4_crtc_destroy_state,
857 	.gamma_set = vc4_crtc_gamma_set,
858 	.enable_vblank = vc4_enable_vblank,
859 	.disable_vblank = vc4_disable_vblank,
860 };
861 
862 static const struct drm_crtc_helper_funcs vc4_crtc_helper_funcs = {
863 	.mode_set_nofb = vc4_crtc_mode_set_nofb,
864 	.disable = vc4_crtc_disable,
865 	.enable = vc4_crtc_enable,
866 	.mode_fixup = vc4_crtc_mode_fixup,
867 	.atomic_check = vc4_crtc_atomic_check,
868 	.atomic_flush = vc4_crtc_atomic_flush,
869 };
870 
871 static const struct vc4_crtc_data pv0_data = {
872 	.hvs_channel = 0,
873 	.encoder_types = {
874 		[PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI0,
875 		[PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_DPI,
876 	},
877 };
878 
879 static const struct vc4_crtc_data pv1_data = {
880 	.hvs_channel = 2,
881 	.encoder_types = {
882 		[PV_CONTROL_CLK_SELECT_DSI] = VC4_ENCODER_TYPE_DSI1,
883 		[PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_SMI,
884 	},
885 };
886 
887 static const struct vc4_crtc_data pv2_data = {
888 	.hvs_channel = 1,
889 	.encoder_types = {
890 		[PV_CONTROL_CLK_SELECT_DPI_SMI_HDMI] = VC4_ENCODER_TYPE_HDMI,
891 		[PV_CONTROL_CLK_SELECT_VEC] = VC4_ENCODER_TYPE_VEC,
892 	},
893 };
894 
895 static const struct of_device_id vc4_crtc_dt_match[] = {
896 	{ .compatible = "brcm,bcm2835-pixelvalve0", .data = &pv0_data },
897 	{ .compatible = "brcm,bcm2835-pixelvalve1", .data = &pv1_data },
898 	{ .compatible = "brcm,bcm2835-pixelvalve2", .data = &pv2_data },
899 	{}
900 };
901 
902 static void vc4_set_crtc_possible_masks(struct drm_device *drm,
903 					struct drm_crtc *crtc)
904 {
905 	struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
906 	const struct vc4_crtc_data *crtc_data = vc4_crtc->data;
907 	const enum vc4_encoder_type *encoder_types = crtc_data->encoder_types;
908 	struct drm_encoder *encoder;
909 
910 	drm_for_each_encoder(encoder, drm) {
911 		struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
912 		int i;
913 
914 		for (i = 0; i < ARRAY_SIZE(crtc_data->encoder_types); i++) {
915 			if (vc4_encoder->type == encoder_types[i]) {
916 				vc4_encoder->clock_select = i;
917 				encoder->possible_crtcs |= drm_crtc_mask(crtc);
918 				break;
919 			}
920 		}
921 	}
922 }
923 
924 static void
925 vc4_crtc_get_cob_allocation(struct vc4_crtc *vc4_crtc)
926 {
927 	struct drm_device *drm = vc4_crtc->base.dev;
928 	struct vc4_dev *vc4 = to_vc4_dev(drm);
929 	u32 dispbase = HVS_READ(SCALER_DISPBASEX(vc4_crtc->channel));
930 	/* Top/base are supposed to be 4-pixel aligned, but the
931 	 * Raspberry Pi firmware fills the low bits (which are
932 	 * presumably ignored).
933 	 */
934 	u32 top = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_TOP) & ~3;
935 	u32 base = VC4_GET_FIELD(dispbase, SCALER_DISPBASEX_BASE) & ~3;
936 
937 	vc4_crtc->cob_size = top - base + 4;
938 }
939 
940 static int vc4_crtc_bind(struct device *dev, struct device *master, void *data)
941 {
942 	struct platform_device *pdev = to_platform_device(dev);
943 	struct drm_device *drm = dev_get_drvdata(master);
944 	struct vc4_crtc *vc4_crtc;
945 	struct drm_crtc *crtc;
946 	struct drm_plane *primary_plane, *cursor_plane, *destroy_plane, *temp;
947 	const struct of_device_id *match;
948 	int ret, i;
949 
950 	vc4_crtc = devm_kzalloc(dev, sizeof(*vc4_crtc), GFP_KERNEL);
951 	if (!vc4_crtc)
952 		return -ENOMEM;
953 	crtc = &vc4_crtc->base;
954 
955 	match = of_match_device(vc4_crtc_dt_match, dev);
956 	if (!match)
957 		return -ENODEV;
958 	vc4_crtc->data = match->data;
959 
960 	vc4_crtc->regs = vc4_ioremap_regs(pdev, 0);
961 	if (IS_ERR(vc4_crtc->regs))
962 		return PTR_ERR(vc4_crtc->regs);
963 
964 	/* For now, we create just the primary and the legacy cursor
965 	 * planes.  We should be able to stack more planes on easily,
966 	 * but to do that we would need to compute the bandwidth
967 	 * requirement of the plane configuration, and reject ones
968 	 * that will take too much.
969 	 */
970 	primary_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_PRIMARY);
971 	if (IS_ERR(primary_plane)) {
972 		dev_err(dev, "failed to construct primary plane\n");
973 		ret = PTR_ERR(primary_plane);
974 		goto err;
975 	}
976 
977 	drm_crtc_init_with_planes(drm, crtc, primary_plane, NULL,
978 				  &vc4_crtc_funcs, NULL);
979 	drm_crtc_helper_add(crtc, &vc4_crtc_helper_funcs);
980 	primary_plane->crtc = crtc;
981 	vc4_crtc->channel = vc4_crtc->data->hvs_channel;
982 	drm_mode_crtc_set_gamma_size(crtc, ARRAY_SIZE(vc4_crtc->lut_r));
983 
984 	/* Set up some arbitrary number of planes.  We're not limited
985 	 * by a set number of physical registers, just the space in
986 	 * the HVS (16k) and how small an plane can be (28 bytes).
987 	 * However, each plane we set up takes up some memory, and
988 	 * increases the cost of looping over planes, which atomic
989 	 * modesetting does quite a bit.  As a result, we pick a
990 	 * modest number of planes to expose, that should hopefully
991 	 * still cover any sane usecase.
992 	 */
993 	for (i = 0; i < 8; i++) {
994 		struct drm_plane *plane =
995 			vc4_plane_init(drm, DRM_PLANE_TYPE_OVERLAY);
996 
997 		if (IS_ERR(plane))
998 			continue;
999 
1000 		plane->possible_crtcs = 1 << drm_crtc_index(crtc);
1001 	}
1002 
1003 	/* Set up the legacy cursor after overlay initialization,
1004 	 * since we overlay planes on the CRTC in the order they were
1005 	 * initialized.
1006 	 */
1007 	cursor_plane = vc4_plane_init(drm, DRM_PLANE_TYPE_CURSOR);
1008 	if (!IS_ERR(cursor_plane)) {
1009 		cursor_plane->possible_crtcs = 1 << drm_crtc_index(crtc);
1010 		cursor_plane->crtc = crtc;
1011 		crtc->cursor = cursor_plane;
1012 	}
1013 
1014 	vc4_crtc_get_cob_allocation(vc4_crtc);
1015 
1016 	CRTC_WRITE(PV_INTEN, 0);
1017 	CRTC_WRITE(PV_INTSTAT, PV_INT_VFP_START);
1018 	ret = devm_request_irq(dev, platform_get_irq(pdev, 0),
1019 			       vc4_crtc_irq_handler, 0, "vc4 crtc", vc4_crtc);
1020 	if (ret)
1021 		goto err_destroy_planes;
1022 
1023 	vc4_set_crtc_possible_masks(drm, crtc);
1024 
1025 	for (i = 0; i < crtc->gamma_size; i++) {
1026 		vc4_crtc->lut_r[i] = i;
1027 		vc4_crtc->lut_g[i] = i;
1028 		vc4_crtc->lut_b[i] = i;
1029 	}
1030 
1031 	platform_set_drvdata(pdev, vc4_crtc);
1032 
1033 	return 0;
1034 
1035 err_destroy_planes:
1036 	list_for_each_entry_safe(destroy_plane, temp,
1037 				 &drm->mode_config.plane_list, head) {
1038 		if (destroy_plane->possible_crtcs == 1 << drm_crtc_index(crtc))
1039 		    destroy_plane->funcs->destroy(destroy_plane);
1040 	}
1041 err:
1042 	return ret;
1043 }
1044 
1045 static void vc4_crtc_unbind(struct device *dev, struct device *master,
1046 			    void *data)
1047 {
1048 	struct platform_device *pdev = to_platform_device(dev);
1049 	struct vc4_crtc *vc4_crtc = dev_get_drvdata(dev);
1050 
1051 	vc4_crtc_destroy(&vc4_crtc->base);
1052 
1053 	CRTC_WRITE(PV_INTEN, 0);
1054 
1055 	platform_set_drvdata(pdev, NULL);
1056 }
1057 
1058 static const struct component_ops vc4_crtc_ops = {
1059 	.bind   = vc4_crtc_bind,
1060 	.unbind = vc4_crtc_unbind,
1061 };
1062 
1063 static int vc4_crtc_dev_probe(struct platform_device *pdev)
1064 {
1065 	return component_add(&pdev->dev, &vc4_crtc_ops);
1066 }
1067 
1068 static int vc4_crtc_dev_remove(struct platform_device *pdev)
1069 {
1070 	component_del(&pdev->dev, &vc4_crtc_ops);
1071 	return 0;
1072 }
1073 
1074 struct platform_driver vc4_crtc_driver = {
1075 	.probe = vc4_crtc_dev_probe,
1076 	.remove = vc4_crtc_dev_remove,
1077 	.driver = {
1078 		.name = "vc4_crtc",
1079 		.of_match_table = vc4_crtc_dt_match,
1080 	},
1081 };
1082